USRE40147E1 - Memory card device including a clock generator - Google Patents

Abstract

Disclosed herein is a card having a controller and a clock control circuit. The controller incorporates a core logic, and the clock control circuit incorporates a PLL. When a card becomes idle to wait for commands, the clock control circuit stops the supply of a clock signal to the core logic. The clock control circuit can operate in two clock control modes. In the first clock control mode, the circuit stops the PLL. In the second clock control mode, the circuit shuts off the clock signal to be supplied from the PLL to the controller.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on Japanese Patent Application No. 2000-300466, filed Sep. 29, 2000, the contents of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a memory card device that can be used in various types of electronic apparatuses. More particularly, the invention relates to a memory card device that includes a clock generator.

2. Description of the Related Art

In recent years, various portable electronic apparatuses have been developed. Among them are personal computers, PDAs, digital cameras, mobile telephones. Memory cards, which are removable memory devices, are used in these portable electronic apparatuses. Two types of memory cards are known. The first is a PCMCIA card (generally known as “PC card”). The second is a SD (Secure Digital) card that is smaller than the PCMCIA card.

The SD card incorporates a flash memory. It is small and can yet store as much data as desired and operate at as high a speed as desired. The SD card has an improved 9-pin interface. Of the nine pins, four serve to transfer data to the host apparatus. Despite a few interface pins it has, the SD card can transfer data in sufficient performance.

Recently it is demanded that power consumption be reduced in small memory cards typified by SD cards. To reduce power consumption in an electronic device, the supply of clock signals to the internal core logic units of the electronic device may be stopped as is known in the art. In a device including a PLL (Phase Locked Loop), more power consumption can be reduced by stopping the PLL operation itself than by stopping the supply of clock signals from the PLL to the internal core logic units.

Once the PLL operation is stopped to set the device into power-saving mode, however, it will take much time to set the device return into the normal operating mode. This is because the PLL cannot generate stable clock signals for some time after it starts operating again. In other words, the internal core logic units cannot operate until the clock signals become sufficiently stable.

Particularly, a memory card that incorporates a nonvolatile memory such as a flash EEPROM cannot respond fast, because it takes a relatively long time to access the nonvolatile memory. To make the matter worse, the internal core logic units will need a long time to restart their operations once the PLL provided in the device is stopped to save power. The memory card inevitably responds even more slowly.

BRIEF SUMMARY OF THE INVENTION

An object of the present invention is to provide a memory card device that can operate fast and can yet save power sufficiently.

To achieve the object, a memory card device is designed to be removably inserted in a host apparatus, the memory card device comprises: a nonvolatile memory device; a controller configured to execute commands supplied from the host apparatus, thereby to write data into, and read data from, the nonvolatile memory; a clock signal generator that includes a PLL configured to generate a clock signal to be supplied to the controller; and a clock control unit configured to operate in a first clock control mode, wherein the clock control unit stops the operation of the PLL, if the controller becomes idle while the memory card device is in a first state in which the memory card device receives a command concerning an access to the nonvolatile memory device from the host apparatus, and configured to operate in a second clock control mode, wherein the clock control unit shuts off the clock signal outputted from the PLL, if the controller becomes idle while the memory card device is in a second state in which the memory card device needs not to receive the command concerning an access to the nonvolatile memory device from the host apparatus.

In the memory card device, the clock control unit stops supplying the clock signal to the controller when the controller becomes idle to wait for commands. The supply of the clock signal can be stopped in two modes, i.e., the first clock control mode for stopping the operation of the PLL, and the second clock control mode for shutting off the clock signal outputted from the PLL. The clock control mode is switched, from the first to the second, or vice versa, in accordance with whether the current state of the card is a state in which the card device receives a command concerning an access to the nonvolatile memory device from the host apparatus.

Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiment of the invention, and together with the general description given above and the detailed description of the embodiment given below, serve to explain the principles of the invention.

FIG. 1 is a block diagram showing a memory card device according to the embodiment of the present invention;

FIG. 2 is a diagram explaining the clock control operation performed in the memory card device shown inFIG. 1;

FIG. 3 is a diagram illustrating the relation between the clock control mode and the status of the memory card device ofFIG. 1;

FIG. 4 is a flowchart explaining how the clock control circuit stops generating the clock signal in the memory card device ofFIG. 1;

FIG. 5 is a block diagram of the clock control circuit provided in the memory card device ofFIG. 1;

FIG. 6 is a timing chart explaining how the clock control circuit operates while the memory card device remains in S_state;

FIG. 7 is a timing chart explaining how the clock control circuit operates while the memory card device stays in Q_state; and

FIG. 8 is a timing chart showing how the controller incorporated in the memory card device is repeatedly started and stopped.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of the present invention will be described, with reference to the accompanying drawings.

FIG. 1 shows amemory card device11 and an electronic apparatus (host apparatus)12. Thememory card device11 is an embodiment of the invention and used in theelectronic apparatus12. More specifically, thedevice11 is an SD (Secure Digital) memory card. Nonetheless, it may be any other type of a memory card device.

TheSD memory card11 can be inserted into, and removed from, a card slot made in thehost apparatus12. Note that thehost apparatus12 may be a personal computer, a PDA, a digital camera, a mobile telephone, or the like. Thehost apparatus12 generates commands, which control the data communication between theSD memory card11 and thehost apparatus12.

AsFIG. 1 shows, theSD memory card11 incorporates acontroller111 and amemory core112. Thememory core112 is a non-volatile memory such as a flash EEPROM. Thecontroller111 performs various command processes, in response to commands supplied from thehost apparatus12. For example, it writes data into thememory core112, reads data from thememory core12 and performs other operations directed by commands.

Thecontroller111 comprises an input/output interface201,MPU202,memory interface203,buffer memory204,ROM205,control logic units206 and207, andclock control circuit208. Theunit206 is provided to control thebuffer memory204, and theunit207 to control theROM205.

The input/output interface201 receives commands and data from thehost apparatus12 and transmits data to thehost apparatus12. The data communication with thehost apparatus12 is performed through a clock line CLK, a command pin CMD and four data pins DAT3 to DAT0 DAT0, DAT1, DAT2, and CD/DAT3. The transfer of commands from thehost apparatus12 to theSD memory card11 and the transfer of data between thehost apparatus12 and theSD memory card11 are effected in synchronization with the clock signal CLK supplied from thehost apparatus12 to theSD memory card11.

Thehost apparatus12 need not always supply the clock signal CLK to theSD memory card11. It may not supply the clock signal to theSD memory card11 while data communication is not need between it and theSD memory card11.

The input/output interface201 operates in synchronization with the clock signal CLK supplied from thehost apparatus12. Theinterface201 incorporates astate machine register311, which holds the data representing the state theSD memory card11 takes at present. (More correctly, the data represents the current state of thecontroller111.) TheSD memory card11 may take various states. The state of thecard11 transits from one state to another states as its operation proceeds.

The state and operating modes of theSD memory card11 will be described. Thecard11 can operate in the following two modes.

(1) Card Identification Mode

While theSD memory card11 is operating in this mode, thehost apparatus12 can identify the attributes of thecard11.

(2) Data Transfer Mode

While theSD memory card11 is operating in this mode, data can be transferred between thememory card11 and thehost apparatus12. The following states are defined for the data transfer mode:

• • Stand-by State
  • Transfer State
  • Sending-data state
  • Receive-data state
  • Programming State
  • Disconnect State

The stand-by state is the first state theSD memory card11 takes when the operating mode is switched from the card identification mode to the data transfer mode. As long as thememory card11 remains in the stand-by state, thehost apparatus12 can transmit no memory-access commands.

Once theSD memory card11 takes the transfer state, it can receive memory-access commands from thehost apparatus12. In other words, thecard11 waits for memory-access commands. When thecard11 receives a memory-access command while staying in the transfer state, it transits to the sending-data state or the receive-data state, depending on the type of the memory-access command.

A specific command supplied from thehost apparatus12 can achieve the transition of state, from the stand-by state to the transfer state or vice versa. To make a memory access, thehost apparatus12 must transit theSD memory card11 from the stand-by state to the transfer state in order to accomplish a memory access. Thecard11 can receive the command for indicating transition to the transfer state, while staying in the stand-by state.

Two ground pins GND are used as ground signal terminals. Thehost apparatus12 supplies ground potential to theSD memory card11 through the ground pins GND. A power signal pin VDD is used as a power signal terminal. Thehost apparatus12 supplies power voltage to theSD memory card11 through the ground pins VDD.

When theSD memory card11 receives a data-read command in the transfer state, it transits to the sending-data state. While thecard11 remains in the sending-data state, data is read from thememory core112 and transmitted from thecard11 to thehost apparatus12. Upon transmitting all data to thehost apparatus12, thecard11 returns to the transfer state.

When theSD memory card11 receives a data-write command in the transfer state, it transits to the receive-data state. While thecard11 is staying in the receive-data state, the data is transferred from thehost apparatus12 is accumulated in thebuffer memory204. When the data is completely accumulated in thebuffer memory204, the state of theSD memory card11 changes, from the receive-data state to the programming state.

In the programming state, the data stored in thebuffer memory204 is written into thememory core112. When all the data is written into thememory core112, theSD memory card11 transits return to the transfer state.

TheSD memory card11 may wait for commands supplied from thehost apparatus12 in the stand-by state and the transfer state. In the present embodiment, the transfer state and the stand-by state will be referred to as “Q_state” and “S_state,” respectively. Thecard11 must respond fast to thehost apparatus12 in the Q_state (transfer state), and need not respond fast thereto in the S_state (stand-by state). The Q_state and the S_state will be explained with reference to FIG.3.

When the SD memory card11 (more correctly, the controller111) becomes idle to wait for commands, it may be stayed in the stand-by state (or STBY in FIG.3), or the transfer state (or TRN in FIG.3). In the present embodiment, if theSD memory card11 becomes idle while it is the stand-by state (STBY), a first clock control operation is performed in order to achieve lower power consumption, if theSD memory card11 becomes idle while it is the transfer state (TRN), a second clock stop control operation is performed in order to achieve faster clock restart, but at high power consumption.

Referring back toFIG. 1, the components of thecontroller111 will be described.

TheMPU202 is a processor that controls the other components of theSD memory card11. TheMPU202 executes various commands in accordance with the program stored in theROM202. Thememory interface203 controls accesses to thememory core112. In other words, theinterface203 writes data into, read data from, and erase data in, thememory core112 under the control of theMPU202. Thebuffer memory204 is used mainly as a posted buffer for storing the write data supplied from thehost apparatus12, which is to be written into thememory core112.

To program most nonvolatile memories, a representative of which is a flash EEPROM, data must be erased in units of blocks, and new data must be written in units of blocks. Inevitably it takes a long time to rewrite data in nonvolatile memories. TheSD memory card11 of this embodiment supplies a signal to thehost apparatus12 when thebuffer memory204 finishes storing the data supplied from thehost apparatus12, thus informing theapparatus12 that the data-write command has been executed. Then, thecontroller111 erases data in, and writes data into, the memory core112 (i.e., flash EEPROM).

Thehost apparatus12 may stop supplying the clock signal CLK to theSD memory card11, upon receiving the signal informing the completion of command execution. Nonetheless, thecard111 keeps operating, because theclock control circuit208 generates an internal clock signal CLK1.

As indicated earlier, the input/output interface201 operates in synchronization with the clock signal CLK supplied from thehost apparatus12. On the other hand, the core logic units provided in the controller111 (i.e., theMPU202,memory interface203 and control logic units (I/F)206 and207) operates in synchronization with the internal clock signal CLK1 generated by theclock control circuit208.

Theclock control circuit208 is a clock-generating circuit having a PLL (phase locked loop). The PLL multiplies the frequency of the source clock signal generated by the internal oscillator. The multiplied source clock signal is the internal clock signal CLK1. Theclock control signal208 is controlled by the clock control signals Q_OFF, S_OFF, CLK_ON, all generated in thecontroller111.

The clock control signal Q_OFF causes theclock control circuit208 to stop outputting the internal clock signal CLK1. The clock control signal Q_OFF is used in Q_state. When theclock control circuit208 receives the signal Q_OFF, it stops outputting the internal clock signal CLK1, though the PLL keeps operating. The clock control signal S_OFF causes theclock control circuit208 to stop PLL operation. The clock control signal S_OFF is used in S_state. When theclock control circuit208 receives the signal S_OFF, it stops PLL operation; thereby the internal clock signal CLK1 is stopped. The clock control signal CLK_ON causes theclock control circuit208 to start supplying the internal clock signal CLK1 again.

The scheme of clock control will be described, with reference to FIG.2.

AsFIG. 2 shows, theclock control circuit208 comprises an oscillator (OSC)401, aPLL402 and anoutput circuit403. ThePLL402 comprises a phase comparator, a low-pass filter, a VCO (Voltage-Controlled Oscillator) and a frequency demultiplier. When theclock control circuit208 receives the clock control signal Q_OFF, theoutput circuit403 is turned off, whereby theclock control circuit208 stops outputting the clock signal CLK1. In this case, neither theoscillator401 nor thePLL402 is stopped. When theclock control circuit208 receives the clock control signal S_OFF, theoscillator401, thePLL402 and theoutput circuit403 are stopped.

The signal Q_OFF is input to theclock control circuit208 through a two-input AND gate G1. The AND gate G1 receives at its first input terminal the transfer bit (TRAN) of thestate machine register311. The transfer bit (TRAN), which is used as Q-state signal, remains at value “1” while theSD memory card11 stays in the transfer state. The AND gate G1 receives at its second input terminal an output signal of a clock-stopinstruction generating circuit314. Theinstruction generating circuit314 generates a pulse signal that remains at “1” while the clock-stop instruction bit CLK_STP having logic value “1” is set at a prescribed position in theregister312 that is provided in theMPU202.

TheMPU202 sets the clock-stop instruction bit CLK_STP at logic value “1” when theMPU202 becomes idle to wait for commands. TheMPU202 assumes the idling state upon executing all commands (including internal operations). That is, as shown inFIG. 4, theMPU202 gets a command CMD from the input/output interface201 when it receives an interruption signal INT from the host apparatus12 (Step S101). This is because interruption signal INT shows that thehost apparatus12 has supplied the command CMD to theSD memory card11. Then, theMPU202 performs the operation designated by the command CMD it has acquired (Step S102). Upon finishing the operation, theMPU202 set the clock-stop instruction bit CLK_STP having logic value “1” in theregister312 unless it has received any new command (Step S103).

The signal S_OFF is input to theclock control circuit208 through a two-input AND gate G2. The AND gate G2 receives at its first input terminal the stand-by state bit (STBY) of thestate machine register311. The stand-by state bit (STBY) is set at “1” while theSD memory card11 remains in the stand-by state. The AND gate G2 receives at its second input terminal an output signal CLK_STP of the clock-stopinstruction generating circuit314.

The signal CLK_ON is generated by a CLK_ON-generatingcircuit313. Thecircuit313 generates the signal CLK_ON when it is triggered by the interruption signal INT the input/output interface201 has generated upon receipt of a command from thehost apparatus12. The signal CLK_ON cause theclock control circuit208 to start generating the clock signal CLK1.

FIG. 5 shows theclock control circuit208 in detail.

As shown inFIG. 5, theclock control circuit208 comprises an RS flip-flop501, anoscillator502, aPLL503, adriver504, an inverter (INV)505, acounter506, an ANDgate507, and an RS flip-flop508. Theoscillator502,PLL503 anddriver504 correspond to theoscillator401,PLL402 andoutput circuit403, respectively, which are shown in FIG.2. Thesystem core601 shown inFIG. 5 represents all circuits that are driven by the clock signal CLK1.

How theclock control circuit208 shown inFIG. 5 performs its function will be explained, with reference to the timing charts ofFIGS. 6 and 7.

FIG. 6 illustrates how the clock control is effected while theSD memory card11 remains in the S_state. The Q output of the RS flip-flop501 stay at “1” until the signal S_OFF is input to theclock control circuit208. The Q output of the RS flip-flop508 stay at “1” until the signal S_OFF is input to theclock control circuit208. Hence, theoscillator502 and thePLL503 are on. Theoscillator502 outputs a source clock signal S_CLK, which is supplied to thePLL503. ThePLL502 multiplies the clock signal S_CLK, thereby generating a clock signal PLL_CLK. Thecounter506 counts the pulses of the clock signal S_CLK for a predetermined time (WAIT TIME inFIG. 6) thePLL504 requires until it starts a stable operation. Thecounter506 outputs a signal “1” upon counting a prescribed number of the pulses after it has been reset. Hence, the driver-on signal DR_ON output from the ANDgate507 remains at “1” until the signal S_OFF is input to theclock control circuit208. Thus, before the signal S_OFF is input, thedriver504 supplies the clock signal PLL_CLK, or the clock signal CLK1, to thesystem core601.

When theMPU202 become idle to wait for commands in the S_state (STBY), the signal S_OFF is generated in thecontroller111. Therefore, the Q output of the RS flip-flop501 becomes “0,” stopping both theoscillator502 and thePLL503. Theclock control circuit208 no longer outputs a clock signal PLL_CLK, or the clock signal CLK1. Theinverter503 inverts the Q output, resetting thecounter506. Thecounter506 outputs a signal “0”. Thedriver504 is therefore stopped.

Thehost apparatus12 may generates a command in this condition. If so, a signal CLK_ON is generated and supplied to theclock control circuit208. In thecircuit208, the Q output of the RS flip-flop501 is set at “1.” Then, theoscillator502 and thePLL503 start operating, whereby thecircuit208 begins to output the clock signal PLL_CLK. Upon lapse of a predetermined time from the start of theoscillator502 andPLL503, thecounter506 outputs “1,” setting the driver-on signal DR_ON at “1.” Thus, the clock signal CLK1 would not be output before the operation of thePLL503 comes stable.

FIG. 7 illustrates how the clock control is effected while theSD memory card11 remains in the Q state. The Q output of the RS flip-flop501 and the Q output of the RS flip-flop508 remain at “1” until the Q_OFF is input to theclock control circuit208. Theoscillator502 and thePLL503 therefore remain on. Theoscillator502 outputs a clock signal S_CLK, and thePLL503 outputs a clock signal PLL_CLK obtained by multiplying the clock signal S_CLK. The driver-on signal DR_ON is held at “1,” too. Thedriver504 therefore supplies the signal PLL_CLK, as clock signal CLK1, to thesystem core601.

When theMPU202 become idle to wait for commands in the Q_state (TRAN), the signal Q_OFF is generated in thecontroller111. Therefore, the Q output of the RS flip-flop508 becomes “0,” and the driver-on signal DR_ON supplied from the ANDgate504 becomes “0.” Hence, thedriver504 shuts off the signal PLL_CLK. Theclock control circuit208 no longer outputs the clock signal CLK1. Both theoscillator502 and thePLL503 keep operating.

Thehost apparatus12 may generates a command in this condition. If so, a signal CLK_ON is generated and supplied to theclock control signal208. In thecircuit208, the Q output of the RS flip-flop508 is set at “1.” The driver-on signal DR_ON is thereby set at “1.” Thus, theclock control circuit208 immediately outputs the clock signal CLK1 again.

In the present embodiment, two clock control schemes are interchangeably used, depending on the internal state of theSD memory card11. In the first control scheme, thePLL503 is stopped. In the second control scheme, thePLL503 keeps operating and the clock signal CLK1 is not supplied to the core logic units.

FIG. 8 illustrates how thecontroller111 is repeatedly started and stopped.

HOST COMMAND shows a transition of a signal supplied from thehost apparatus12 to theSD memory card11 through the command pin CMD. COMMAND indicates the command itself. COMMAND EXECUTED shows the time when thecontroller111 executes the command COMMAND.

In the Q state, the supply of the clock signal CLK1 is stopped every time thecontroller111 finishes executing a command, as is illustrated in FIG.8. When thecontroller111 receives another command, the supply of the clock signal CLK1 is immediately started again and thecontroller111 immediately starts executing the received command.

In the S state, thePLL503 is stopped every time thecontroller111 finishes executing a command. ThePLL503 starts operating when thecontroller111 receives another command. When the operation of thePLL503 comes stable thereafter, the supply of the clock signal CLK1 is started again and thecontroller111 starts executing the received command.

Of the commands supplied from thehost apparatus12, some commands are need not to be executed by the MPU302. Upon receipt of these commands, the input/output interface201 only needs to make a response to thehost apparatus12. When the input/output interface201 receives such a command, theinterface201 generates no interruption signals INT. In this case, thecontrol circuit208 remains to stop the clock signal CLK1.

The clock control circuit according to the present embodiment effectively works in any type of a card device, such as an I/O card, which incorporates a clock-signal generating circuit.

As described above, the transfer state is Q_state in which the card device must respond fast to the host apparatus, and the stand-by state is S_state in which the card device need not respond fast to the apparatus. The present invention is not limited to an SD memory card. Rather, it may be applied to a card device of any other type. If so, the card device of any other type must respond fast to the host apparatus, while remaining in the Q_state, and need not respond fast to the host apparatus, while staying in the S_state. In this case, too, power can be saved, without decreasing the operating efficiency of the circuits incorporated in the card device.

The circuits incorporated in the card device may operate as efficiently as desired even if an event takes place to release the card device from the idling state. If this is the case, it suffices to operate the clock control circuit in accordance with the clock-stop instruction signal S_OFF. Conversely, the circuits in the card device may fail to operate as efficiently as desired, when an event takes place to release the card device from the idling state. In this case, it suffices to operate the clock control circuit in accordance with the clock-stop instruction signal Q_OFF.

As has been described above, two clock control schemes are automatically switched from one to the other, in accordance with the state in which the card device has become idle. The power consumption in the card device can be much reduced, without decreasing the operating efficiency of the circuits incorporated in the card device.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

Claims (22)

1. A memory card device capable of being removably inserted in a host apparatus, said memory card device comprising:

a nonvolatile memory device;

a controller configured to execute commands supplied from the host apparatus, thereby to write data into, and read data from, the nonvolatile memory device;

a clock signal generator including a PLL configured to generate a clock signal to be supplied to the controller; and

a clock control unit configured to operate in a first clock control mode, wherein the clock control unit stops the operation of shuts off the clock signal outputted from the PLL, if the controller becomes idle while the memory card device is in a state in which the memory card device receives waits to receive a command concerning an access to the nonvolatile memory device from the host apparatus, and configured to operate in a second clock control mode, wherein the clock control unit shuts off the clock signal outputted from stops the operation of the PLL, if the controller becomes idle while the memory card device is in a state in which the memory card device needs does not wait to receive the command concerning an access to the nonvolatile memory device.

2. The memory card device according toclaim 1, further comprising a clock supply control unit configured to start the operation of the PLL, when a command is supplied from the host apparatus to the memory card device while the operation of the PLL is stopped, and to supply the clock signal to the controller, upon lapse of a predetermined time from starting of the operation of the PLL, said predetermined time being required time by the PLL to operate stably.

3. The memory card device according toclaim 1, wherein the clock signal generator includes an oscillator configured to generate a source clock signal which is inputted to the PLL, and the clock control unit stops both the PLL and the oscillator in the first clock control mode.

4. A memory card device capable of being removably inserted in a host apparatus, said memory card device comprising:

a nonvolatile memory device;

a controller configured to be set in a transfer state to receive a command concerning an access to the nonvolatile memory device and to be set in a stand-by state to receive a command for transition to the transfer state, and configure to access to the nonvolatile memory device in accordance with a command concerning an access to the nonvolatile memory device;

a clock signal generator including a PLL configured to generate a clock signal to be supplied to the controller; and

a clock control unit configured to operate in a first clock control mode to stop the operation of the PLL if the controller starts waiting for commands in the stand-by state, and configured to operate in a second clock control mode to shut off the clock signal outputted from the PLL if the controller starts waiting for commands in the transfer state.

5. The memory card device according toclaim 4, further comprising a clock supply control unit configured to start the operation of the PLL, when a command is supplied from the host apparatus to the memory card device while the operation of the PLL is stopped, and configured to supply the clock signal to the controller, upon lapse of a predetermined time from starting of the operation of the PLL, said predetermined time being time required by the PLL to operate stably.

6. The memory card device according toclaim 4, wherein the clock signal generator includes an oscillator configured to generate a source clock signal which is inputted to the PLL, and the clock control unit stops both the PLL and the oscillator in the first clock control mode.

7. A memory card device capable of being removably inserted in a host apparatus, said memory card device comprising:

a nonvolatile memory device;

a controller configured to execute commands supplied from the host apparatus, thereby to write data into, and read data from, the nonvolatile memory;

a clock signal generator including a PLL configured to generate a clock signal to be supplied to the controller;

a first clock stop unit configured to stop the operation of the PLL, in order to stop supplying the clock signal to the controller;

a second clock stop unit configured to shut off the clock signal outputted from the PLL, in order to stop supplying the clock signal to the controller; and

a control unit configured to activate the first clock stop unit or the second clock stop unit when the controller becomes idle to wait for commands, in accordance with a current state of the memory card device.

8. The memory card device according toclaim 7, further comprising a clock supply control unit configured to start the operation of the PLL, when a command is supplied from the host apparatus to the memory card device while the operation of the PLL is stopped, and to supply the clock signal to the controller, upon lapse of a predetermined time from starting of the operation of the PLL, said predetermined time being time required by the PLL to operate stably.

9. The memory card device according toclaim 7, wherein the control unit activates the second clock stop unit if the controller becomes idle while the memory card device is in a state in which the memory card device receives a command concerning an access to the nonvolatile memory device from the host apparatus, and activates the first clock stop unit if the controller becomes idle while the memory card device is in a state in which the memory card device needs not to receive the command concerning an access to the nonvolatile memory device from the host apparatus.

10. A card device capable of being removably inserted in a host apparatus, said card device comprising:

a core logic configured to operate in accordance with a command supplied from the host apparatus;

a clock signal generator including a PLL configured to generate a clock signal to be supplied to the core logic;

a first clock stop unit configured to stop the operation of the PLL, in order to stop supplying the clock signal to the core logic;

a second clock stop unit configured to shut off the clock signal outputted from the PLL, in order to stop supplying the clock signal to the core logic; and

a control unit configured to activate the first clock stop unit or the second clock stop unit when the core logic becomes idle to wait for commands, in accordance with a current state of the card device.

11. The card device according toclaim 10, further comprising a clock supply control unit configured to start the operation of the PLL, when a command is supplied from the host apparatus to the card device while the operation of the PLL is stopped, and to supply the clock signal to the core logic, upon lapse of a predetermined time from starting of the operation of the PLL, said predetermined time being time required by the PLL to operate stably.

12. A memory card device capable of being removably inserted in a host apparatus, the memory card device comprising:

a nonvolatile semiconductor memory device;

a controller configured to control access to the nonvolatile semiconductor memory device and including a functional block; and

a clock circuit including a PLL circuit to generate a clock signal to be supplied to the functional block, wherein the clock circuit can assume: a) a first state in which the PLL circuit is not operating while the controller is idle; and b) a second state in which the clock signal is not supplied to the functional block while the controller is idle and the PLL circuit is operating.

13. The memory card device according toclaim 12, wherein the clock circuit includes an output circuit to supply the clock signal to the functional block and, in the second state, the output circuit does not output the clock signal to the functional block.

14. The memory card device according toclaim 12, wherein the clock circuit further includes an oscillator to generate a source clock signal to be supplied to the PLL circuit, and in the first state, the oscillator does generate the source clock signal.

15. The memory card device according toclaim 12, wherein the functional block is an MPU to execute a command supplied from the host apparatus.

16. The memory card device according toclaim 12, wherein the functional block is a memory interface circuit coupled to the nonvolatile semiconductor memory device.

17. The memory card device according toclaim 12, wherein the memory card device assumes a card identification mode and a data transfer mode.

18. The memory card device according toclaim 17, wherein the memory card device has nine signal terminals provided along an edge of the memory card device.

19. The memory card device according toclaim 18, wherein the signal terminals include a clock signal terminal and a plurality of data terminals.

20. The memory card device according toclaim 19, wherein the memory card device is an SD card.

21. The memory card device according toclaim 20, wherein one of the signal terminals is not aligned with other ones of the signal terminals, and the one of the signal terminals is for receiving data from the host.

22. The memory card device according toclaim 21, wherein the nonvolatile memory device is a flash EEPROM.

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