USRE39501E1 - Multiple network protocol encoder/decoder and data processor - Google Patents

Abstract

A multiple network protocol encoder/decoder comprising a network protocol layer, data handler, O.S. State machine, and memory manager state machines implemented at a hardware gate level. Network packets are received from a physical transport level mechanism by the network protocol layer state machine which decodes network protocols such as TCP, IP, User Datagram Protocol (UDP), PPP, and Raw Socket concurrently as each byte is received. Each protocol handler parses and strips header information immediately from the packet, requiring no intermediate memory. The resulting data are passed to the data handler which consists of data state machines that decode data formats such as email, graphics, Hypertext Transfer Protocol (HTTP), Java, and Hypertext Markup Language (HTML). Each data state machine reacts accordingly to the pertinent data, and any data that are required by more than one data state machine is provided to each state machine concurrently, and any data required more than once by a specific data state machine, are placed in a specific memory location with a pointer designating such data (thereby ensuring minimal memory usage). Resulting display data are immediately passed to a display controller. Any outgoing network packets are created by the data state machines and passed through the network protocol state machine which adds header information and forwards the resulting network packet via a transport level mechanism.

Description

BACKGROUND OF THE INVENTION

1. Technical Field

The invention relates to network protocols and data packets. More particularly, the invention relates to the decoding of network protocols and processing of packet data during packet reception without the time-consuming overhead of software or software/hardware implementations. In addition, the invention allows one pass parsing of the data, eliminating the buffering of data packets for different stacks, and thus minimizing the memory usage.

2. Description of the Prior Art

Computer networks necessitate the provision of various communication protocols to transmit and receive data. Typically, a computer network comprises a system of devices such as computers, printers and other computer peripherals, communicatively connected together. Data are transferred between each of these devices through data packets which are communicated through the network using a communication protocol standard. Many different protocol standards are in current use today. Examples of popular protocols are Internet Protocol (IP), Internetwork Packet Exchange (IPX), Sequenced Packet Exchange (SPX), Transmission Control Protocol (TCP), and Point to Point Protocol (PPP). Each network device contains a combination of hardware and software that translates protocols and process data.

An example is a computer attached to a Local Area Network (LAN) system, wherein a network device uses hardware to handle the Link Layer protocol, and software to handle the Network, Transport, and Communication Protocols and information data handling. The network device normally implements the one Link Layer protocol in hardware, limiting the attached computer to only that particular LAN protocol. The higher protocols, e.g. Network, Transport, and Communication protocols, along with the Data handlers, are implemented as software programs which process the data once they are passed through the network device hardware into system memory. The advantage to this implementation is that it allows a general purpose device such as the computer to be used in many different network setups and support any arbitrary network application that may be needed. The result of this implementation, however, is that the system requires a high processor overhead, a large amount of system memory, complicated configuration setup on the part of the computer user to coordinate the different software protocol and data handlers communicating to the computer's Operating System (O.S.) and computer and network hardware.

This high overhead required in processing time is demonstrated in U.S. Pat. No. 5,485,460 issued to Schrier et al on Jan. 16, 1996, which teaches a method of operating multiple software protocol stacks implementing the same protocol on a device. This type of implementation is used in Disk Operating System (DOS) based machines running Microsoft Windows. During normal operation, once the hardware verifies the transport or link layer protocol, the resulting data packet is sent to a software layer which determines the packets frame format and strips any specific frame headers. The packet is then sent to different protocol stacks where it is evaluated for the specific protocol. However, the packet may be sent to several protocols stacks before it is accepted or rejected. The time lag created by software protocol stacks prevent audio and video transmissions to be processed in real-time; the data must be buffered before playback. It is evident that the amount of processing overhead required to process a protocol is very high and extremely cumbersome and lends itself to applications with a powerful Central Processing Unit (CPU) and a large amount of memory.

Consumer products that do not fit in the traditional models of a network device are entering the market. A few examples of these products are pagers, cellular phones, game machines, smart telephones, and televisions. Most of these products have small footprints, 8-bit controllers, limited memory or require a very limited form factor. Consumer products such as these are simplistic and require low cost and low power consumption. The previously mentioned protocol implementations require too much hardware and processor power to meet these requirements. The complexity of such implementations are difficult to incorporate into consumer products in a cost effective way. If network access can be simplified such that it may be easily manufactured on a low-cost, low-power, and small form-factor device, these products can access network services, such as the Internet.

SUMMARY OF THE INVENTION

The invention provides a low-cost, low-power, easily manufacturable, small form-factor network access module which has a low memory demand and provides a highly efficient protocol decode. The invention comprises a hardware-integrated system that both decodes multiple network protocols in a byte-streaming manner concurrently and processes packet data in one pass, thereby reducing system memory and form factor requirements, while also eliminating software CPU overhead.

The preferred embodiment of the invention comprises a network protocol layer, data handler, O.S. State Machine, and memory manager state machines implemented at a hardware gate level. Network packets are received from a physical transport level mechanism by the network protocol layer state machine. The protocol state machine decodes network protocols such as TCP, IP, User Datagram Protocol (UDP), PPP, and Raw Socket concurrently as each byte is received. Each protocol handler parses, interprets, and strips header information immediately from the packet, requiring no intermediate memory. The resulting data are passed to the next protocol layer or data handler for which the latter case consists of data state machines that decode data formats such as email, graphics, Hypertext Transfer Protocol (HTTP), Java, and Hypertext Markup Language (HTML). Each data state machine reacts accordingly to the pertinent data, and any data that are required by more than one data state machine are provided to each state machine concurrently. Any data that are required more than once by a specific data state machine, are placed in a specific memory location with a pointer designating such data (thereby ensuring minimal memory usage). Resulting display data are immediately passed preformatted to a display controller. Any outgoing network packets are created by the data state machines and passed through the network protocol state machine which adds formats to the packet, and checksums the information header information, and forwards the resulting network packet via a physical transport level mechanism.

The preferred embodiment does not necessarily require a CPU and software to process the network packets, thereby greatly reducing system cost. The hardware gate level implementation provides a modular, embeddable design whereupon the designer may pick and choose the functionality that the particular application requires and still retain a low cost, low power, small form factor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a high-level data flow diagram of the core system according to the invention;

FIG. 2 is a high-level block diagram of a system according to the invention;

FIG. 3 is a functional block diagram of a complete system implementation according to the invention;

FIG. 3A is a functional block diagram of the UMA memory controller according to the invention;

FIG. 4 is a time comparison chart illustrating data task time requirements for a traditional architecture and the invention.

FIG. 5 illustrates the possible progression of applications according to the invention;

FIG. 6 illustrates the concept of an Internet Tuner according to the invention;

FIG. 7 illustrates two implementations according to the invention;

FIG. 8 illustrates Network PC implementations according to the invention;

FIG. 9 illustrates Handheld Devices implementations according to the invention;

FIG. 10 illustrates Smart Telephone implementations according to the invention;

FIG. 11 illustrates Smart Television, cable-box, Video Cassette Recorder (VCR), Digital Video Disc (DVD) and game machine implementations according to the invention; and

FIG. 12 is a timing diagram sharing a received packet according to the invention; and

FIG. 13 is a block schematic diagram showing signal flow for the packet of claim12 according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring toFIG. 1, the invention comprises aNetwork Protocol Layer101, aData Handler102, aMemory Control module103, and an Operating System (O.S.)State Machine module104, each implemented at the hardware gate level. TheNetwork Protocol Layer101 decodes incoming and encodes outgoing network packets. TheNetwork Protocol Layer101 comprises a plurality of state machines representing different network protocol stacks (i.e. PPP, TCP, IP, UDP, and Raw Socket) which simultaneously decode incoming network packets. The implementation of the protocol stacks in gate level logic allows the real time decoding of the network packet as the packet is received, thereby requiring no temporary memory storage. After all of the packet header information is stripped out and verified by the state machines, the resulting data is passed to theData Handler102. TheData Handler102 comprises a plurality of state machines, each of which process a specific data type (i.e. HTTP, email formats (Post Office Protocol (POP3), Internet Message Access Protocol (IMAP4), Simple Mail Transfer Protocol (SMTP)), graphics standards (Joint Photographic Experts Group (JPEG), Graphics Interchange Format (GIF)), Java, and HTML). The gate level implementation of the data handlers enable the invention to concurrently process received data in real time and is especially suitable for applications which handle streams of data as they are received, i.e. Java, HTML, POP3 email, and audio and video applications. Any data that are required by more than one data state machine are provided in a concurrent manner. Any data required more than once by a specific data state machine are placed in a specific memory location with a pointer designating them. All memory accesses are arbitrated through theMemory Control module103. Any resulting display data are also routed through theMemory Control module103. The O.S.State Machine104, acts as an arbitrator between all of the state machines for resource control, system, and user interface. Any user input is interpreted by the O.S. State Machine and routed to theData Handler102.

As an example, a data handler that interprets HTML format could decode the HTML tags using a Cyclic Redundancy Check (CRC) calculation. HTML format contains character strings known as tags, which control the formatting of a subsequent block of text when displayed on a video output device. These tags may be efficiently decoded by generating a CRC number for a given tag and using said number to enable a formatting instruction. Such a decoding algorithm is suited for gate level implementation and provides for an HTML encoded document to be displayed on a video output device much more quickly than is currently possible.

Although the invention is described as being at the hardware gate level, one skilled in the art can readily appreciate that these functions may be implemented in many other ways such as Programmable Array Logic (PALs), General Array Logic (GALs), Read Only Memory (ROMs), and software. Additionally, specific protocols and data types have been indicated and one skilled in the art can readily appreciate that the modularity of the invention does not limit it to those specific protocols or data types.

Turning toFIG. 2, the invention is represented in a high-level block diagram. This diagram describes the operational task of each module in a full implementation of the invention. The O.S.State Machine208, contains the system “glue” logic, and the device control interface, and acts as a “traffic cop” between the state machines of the other modules. TheNetwork Protocol Layer207, contains state machines for TCP/IP, UDP, Raw Socket, and PPP protocols. TheMemory Control module206 contains the logic for the Unified Memory Architecture (UMA) which allows the system and video display memory to reside in the same memory area. ADisplay Controller205 provides control of a VGA, television standard, or other type of display. Four data handlers are used in this implementation. An Email data handler201 interprets both POP3 and IMAP4 formats.Interpreters202 are implemented which decode JPEG and GIF formats (commerce and telephony standards may also be decoded). AJava Machine203 is also included which interprets the Java language byte codes. The World-Wide Web (WWW)Browser204, contains an HTML decoder/accelerator, HTTP Data handler and an integrated email state machine.

As an example, an incoming JPEG image packet is traced through the system, assuming a MODEM physical transport. The request starts with the user indicating a desire to download a given JPEG image by typing onkeyboard321. This input is interpreted by thekeyboard interface316 and passed to the O.S.State machine315. O.S.State machine315 processes the input and passes it as a command to theHTTP client311. The HTTP client creates a request packet and passes it via thePort Decoder309 to theTCP Layer308. The TCP Layer prepends the appropriate TCP header and passes it to theIP Layer307. The IP layer then prepends the appropriate IP header and passes the packet to thePPP layer306. The PPP Layer prepends the appropriate header, appends an FCS, and passes the data to thePhysical Transport Interface305. The Physical Transport Interface serializes the data into a bit stream and sends the packet to theMODEM unit304. When the request is accepted by the host server, it sends the requested JPEG image back to the client system. The data are first received by theMODEM304 which indicates to thePhysical Transport Interface305 that data are present. The Physical Transport interface then reads the bit serial data from the MODEM, converts it to a parallel byte data, and indicates to thePPP Layer306 that data are present. The PPP Layer reads in the received bytes. When it detects a valid start byte, it begins to parse the incoming bytes. When the byte stream reaches the PPP protocol field, the PPP Layer decodes it, and in this example decodes the embedded packet as being of type IP. In response to this protocol byte, the PPP Layer enables theIP Layer307 and indicates to it that IP data are being received. All further data bytes received are now passed directly to the IP Layer. The IP Layer then begins to parse the incoming data bytes. When it comes to the IP header protocol field, it determines which higher protocol to enable. In this example, the IP Layer decodes the protocol field as being of type TCP. At this point, the IP Layer enables theTCP Layer308 and indicates to it when TCP data are being received. When this indicator goes active, all further data bytes in the received packets are sent to both the IP and TCP Layers (IP Layer needs the data bytes to complete checksum calculations). The TCP Layer then begins to parse the incoming data bytes. When it comes to the TCP header destination port field, it determines which data handler to enable. In this example, the PORT field decodes to theHTTP client311. At this point, the PORT decoder enables the HTTP client and indicate to it that HTTP requested data are being received. The HTTP client then begins to parse received data bytes. When the HTTP client determines that the packet is of type JPEG image, the HTTP client enables theJPEG decoder313. At this point, all data bytes are now routed to the JPEG decoder. The JPEG decoder then receives all further incoming data bytes and processes them accordingly. The resulting decoded image is sent to the display memory via theMemory Controller312 to be processed by theDisplay Controller324 for output to displaydevice326.

As also noted inFIG. 3, various layers need access to a shared memory resource. All memory accesses are arbitrated by a single memory controller. This memory controller determines which layer or handler has access at any given cycle to the unified memory buffer. This memory controller is needed due to the fact that all system and display memory buffers are shared within a single memory buffer unit. Theunified memory controller312 takes read and write requests from the various layers, arbitrates the requests based on a dynamic rotating arbitration scheme with fixed priority weighting. This algorithm is depicted in FIG.3A. If, in the pictured configuration, device D2302A and device D3303A both request memory access at the same time, then the arbitor307A awards the cycle to the device that has not had the most recent memory access. The arbitor307A then passes its memory request to the A input arbitor309A. If the B input on arbitor309A is idle, then the request is passed up to the B input of arbitor310A. If the A input to the arbitor310A is idle, then the request is made to the memory unit. All arbitration determinations are performed using combinatorial logic, thereby eliminating any wait states to any device if no other memory requests are being made. Priority weighting is assigned by configuring the arbitration tree structure. InFIG. 3A, Device DO300A and Device D1301A each have 25% priority weighting meaning that if all devices requested constant memory usage, they would each win thearbitration 25% of the time. Devices D2302A, D3303A, D4304A, and D5305A each have 12.5% priority weighting. The memory controller design is simplified by having each of the individual arbitration units having the same logic structure. In this scheme, the number of requesting devices, and their priority weighting can easily be configured by adding and arranging arbitor units.

Turning toFIG. 4, the speed advantages that the invention offers are much higher than the traditional architecture currently in use. The figure represents the time needed to complete each task. For a series of packets that require anHTML download401, decode of theHTML402,JPEG download403, decode of theJPEG404,JAVA download405, decode of theJAVA bytes406, and streamingaudio407, the total time required for these tasks is shown for thetraditional architecture408 and the invention (iReady architecture)409. Theinvention409 is significantly faster for these tasks than thetraditional architecture408.

Turning toFIG. 5, the progression of applications for this type of network access is shown. Presently, the traditional model of the network client is being used, namely thecomputer501. The consumer appliance concepts of theNetwork PC502,handheld devices503,smart telephones504, set-top appliances505, andsmart televisions506 are now becoming a reality. The invention provides these products with a cost-effective, space, speed, and power conscious network access.

Referring toFIG. 6, the invention operates much like atelevision602 orradio tuner611—the signals (packets) are processed immediately without delay and sent to a display or audio output. Theterm Internet Tuner608 is used to describe the invention as an analogy to such signal processing devices. TheInternet Tuner608 acts as the interface between the Internet signals609 and application products such assmart televisions604, set-top appliances605,smart telephones606, andhandheld devices607. It processes Internet signals609 in real-time as dotelevision602 andradio tuners611.

FIG. 7 illustrates that a full implementation of the invention using the O.S.State Machine701,Network Protocol Layer702,Memory Control703,Display Controller704,email data handler708,Interpreters707,Java Machine706, andWWW Browser705 may be separated into two separate modules. The modularity of the invention allows functions such as the data handlers713 (email data handler717,Interpreters716,Java Machine715, and WWW Browser714) to be separated and placed into a high-level ROM code for certain applications.

The following application examples further illustrate the versatility of the modular design of the invention.

FIG. 8 demonstrates the possible configurations of the invention for a Network PC. One variation includes the O.S.State Machine801,Network Protocol Layer802,Memory Control803,Display Controller804,email data handler808,Interpreters807,Java Machine806, and theWWW Browser805. This can be varied by placing the data handlers foremail817.Interpreters816,Java Machine815, andWWW Browser814 code into high-level ROM running on amicroprocessor813. Themicroprocessor813 communicates through the O.S.State Machine809 for network and display functions. A third variation allows amicroprocessor822 running off of a3rd Party ROM823 to interpret the data coming from theNetwork Protocol Layer819 and O.S. State Machine818. Themicroprocessor822 displays data through theDisplay Controller821.

Turning toFIG. 9, a handheld device may use only theNetwork Protocol Layer901 and interface it to acustom Transport Mechanism902 and ExistingMicrocontroller904. Email functions may be added by including theemail data handler905 in the configuration. Further demonstrating the modularity of the invention, theNetwork Protocol Layer911 andJava Machine910 may be added to a handheld device, thereby allowing it to process Java applets.

Referring toFIG. 10, smart telephones may add email capabilities by implementing the O.S.State Machine1001,Network Protocol Layer1002,Memory Control1003, email data handler1006, andDisplay Controller1004. TheDisplay Controller1004 is capable of controlling Light Emitting Diode (LED), Liquid Crystal Display (LCD) displays, or big-mapped displays. APhysical Transport Control1005 may optionally be added, depending on the connectivity requirements of the smart telephone. The O.S.State Machine1007,Network Protocol Layer1008, andMemory Controller1009 may be added to smart telephones with an existingmicrocontroller1010. Themicrocontroller1010 performs email functions using a 3rd Partyemail client code1011.

Turning finally toFIG. 11, smart televisions, cable-boxes, Video Cassette Recorders (VCRs), Digital Video Disc (DVD) players, and game machines can take advantage of the network accessibility offereNety the invention. The O.S.State Machine1102,Network Protocol Layer1103,Memory Controller1104,WWW Browser1107,Java Machine1106, and (optionally) theDisplay Controller1105 are interfaced to an existingcontroller1101. If acontroller1101 is not present, theDisplay Controller1105 is used.Email1115 functions are easily added due to the modularity of the invention. As noted previously, the data handlers foremail1124,Interpreters1123,Java Machine1122, andWWW Browser1121 code are optionally placed into high level ROM running on amicroprocessor1120. Themicroprocessor1120 communicates through the O.S.State Machine1116 for network and display functions.

Example of Packet Reception

FIG. 12 depicts a received network packet. The packet contains the following items as shown from left to right:

PPP header

IP header

TCP header

JPEG Data

PPP FCS (Field Checksum)

The line labeled PPP LAYER ENABLE is activated when a valid start byte is detected, and is generated within the PPP block in FIG.13. Once this line goes high, the rest of the PPP block is activated. Within the PPP header is a field indicating the type of protocol that the PPP packet is encapsulating. In an uncompressed PPP header, these are bytes4 and5 (counting thestart byte 0×7e). InFIG. 12, these bytes are 0×00 and 0×21 indicating that the encapsulated data is an IP packet. After decoding this field, the PPP block activates the IP LAYER ENABLE and PPP DATA FIELD signals, which together enable the IP block in FIG.13. The IP LAYER ENABLE line is decoded from the PPP protocol field, and the PPP DATA FIELD line indicates that the incoming data byte stream is in the data field portion of the network packet. These two lines must be active for the IP block to be enabled. Once the IP block is enabled, it starts to parse the incoming data bytes. Referring back toFIG. 12, the data immediately following the PPP header is the IP header. Within the IP header is a field indicating the type of data that is encapsulated within the IP packet. InFIG. 12, this field is shown to be 0×06 indicating that the encapsulated data is a TCP packet. The TCP LAYER ENABLE line is activated in response to the IP block decoding this field. The IP DATA FIELD line goes active a couple of bytes later, because there are some bytes that come between the IP header protocol field and the start of the IP data field. The IP DATA FIELD signal indicates that the incoming data byte streams is in the data field portion of the network packet. Both the TCP LAYER ENABLE and IP DATA FIELD lines must be active in order for the TCP block inFIG. 13 to be enabled. Once the TCP block is enabled, it starts to parse incoming data bytes. Referring back toFIG. 12, the data immediately following the IP header is the TCP header. Within the TCP header is a 2 byte field for the destination port. This field indicates which application or data handler the encapsulated data is meant for. InFIG. 12, this field decodes to port 0×0003. InFIG. 13, port3 is designated as the HTTP port. After decoding the destination port field within the TCP header, the HTTP ENABLE line is activated. The TCP DATA FIELD line is activated a couple of bytes later because there are some intermediate bytes between the destination port field and the start of the TCP data field. Both the HTTP ENABLE and TCP DATA FIELD lines must be active for the HTTP/PORT3 block inFIG. 13 to be enabled. Once the HTTP block is enabled, it starts to parse incoming data bytes. When it decodes the JPEG header, it enables the JPEG decoder block in FIG.13. Once the JPEG decoder is enabled, it starts to process incoming bytes. The JPEG enable line is the only line needed to enable the JPEG block.

Although the invention is described herein with reference to the preferred embodiment, one skilled in the art will readily appreciate that other applications may be substituted for those set forth herein without departing from the spirit and scope of the present invention. Accordingly, the invention should only be limited by the Claims included below.

Claims (44)

1. An apparatus for decoding and encoding network protocols and data, comprising:

a network protocol layer module for receiving and transmitting network packets and for encoding and decoding network packets bytes which comprise packet data;

a data handler module for exchanging said packet data with said network protocol layer module and for processing a at least one specific data type or protocol;

a memory control module in communication with said data handler module for arbitrating memory accesses and for providing display data ; and

an operating system (o.s.)at least one state machine module that is optimized for a single selected network protocol, said o.s.at least one state machine module in communication with said data handler module and providing resource control and system and user interfaces ;

wherein said network protocol layer module, said data handler module, said memory control module, and said operating system (o.s.) at least one state machine module comprise corresponding dedicated hardware structures that are implemented in hardware gate level circuitry.

2. The apparatus ofclaim 1, wherein said network protocol layer module comprises a plurality of state machines representing different network protocols stacks.

3. The apparatus of claim21, wherein said network protocol layer module implements one or more of the following network protocols: Point to Point Protocol (PPP), Internetwork Packet (IP), Transmission Control Protocol (TCP), Raw Socket, and/or User Datagram Protocol (UDP).

4. The apparatus of claim21, wherein said network packets bytes are processed in real time.

5. The apparatus of claim21, wherein said network packets bytes are processed concurrently.

6. The apparatus of claim21, wherein said network packets bytes are processed byte- serially.

7. The apparatus ofclaim 1, wherein any data required more than once by a specific said state machine is placed in a specific memory location with a pointer designating said memory location.

8. The apparatus ofclaim 1, wherein said data handler module comprises at least one state machine which processes a specific data type.

9. The apparatus ofclaim 8, wherein said data handler module processes one or more of the following protocols: Hypertext Transfer Protocol (HTTP), Hypertext Markup Language (HTML), Post Office Protocol (POP3), Internet Message Access Protocol (IMAP4), Simple Mail Transfer Protocol (SMTP), Joint Photographic Experts Group (JPEG), Graphics Interchange Format (GIF), and/or Java language.

10. The apparatus ofclaim 8, wherein said data type is processed in real time.

11. The apparatus ofclaim 8, wherein said data type is processed concurrently.

12. The apparatus ofclaim 8, wherein said data type is processed byte serially.

13. The apparatus ofclaim 8, wherein any data shared by said at least one state machine or required more than once by a specific said state machine is placed in a specific memory location with a pointer designating said memory location.

14. The apparatus ofclaim 8, wherein any data shared by said at least one state machine is provided to said state machine(s) concurrently.

15. The apparatus ofclaim 1, wherein said memory control module arbitrates all memory accesses.

16. The apparatus ofclaim 1, wherein said memory control module contains a Unified Memory Architecture (UMA) which allows a system memory and a video memory to reside in a same memory area.

17. The apparatus ofclaim 1, wherein said memory control module is comprised of one or more arbiter logic blocks where an arbiter block arbitrates according to a dynamic rotating algorithm between two devices.

18. The apparatus ofclaim 1, wherein said memory control module is comprised of one or more arbiter logic blocks arranged in such a manner as to give a fixed weighted priority to each of a plurality of devices for memory access based on a given arbiter tree structure.

19. The apparatus ofclaim 1, wherein said o.s. further comprising an arbitrator state machine that acts as an arbitrator between said network protocol layer module, said data handler module, and said memory control module for resource control, system and user interface.

20. The apparatus ofclaim 1, further comprising:

a display controller.

21. The apparatus ofclaim 20, wherein said display controller controls one of the following types of displays: VGA, television, Liquid Crystal Display (LCD), or Light Emitting Diode (LED).

22. The apparatus ofclaim 1, wherein said apparatus acts as an interface between Internet signals and application products by processing Internet signals in real-time and sending said processed Internet signals to said application products.

23. A process for decoding and encoding network protocols and data, said process comprising the steps of:

providing a network protocol layer module for receiving and transmitting network packets and for encoding and decoding network packets bytes which comprise packet data;

providing a data handler module for exchanging said packet data with said network protocol layer module and for processing a at least one specific data type or protocol;

providing a memory control module in communication with said data handler module for arbitrating memory accesses and for providing display data ; and

providing an operating system (o.s.) at least one state machine module that is implemented in hardware and that is optimized for a single selected network protocol, said o.s. at least one state machine module in communication with said data handler module and providing resource control and system and user interfaces ;

wherein said network protocol layer module, said data handler module, said memory control module, and said operating system (o.s.) at least one state machine module comprise corresponding dedicated hardware structures that are implemented in hardware gate level circuitry.

24. The process ofclaim 23, wherein said step of encoding and decoding network packet bytes network protocol layer module further comprises the step of:

representing different network protocols stacks using a plurality of state machines.

25. The process ofclaim 24, wherein said step of encoding and decoding network packet bytes network protocol layer module further comprises the step of:

encoding and decoding one or more of the following network protocols: Point to Point Protocol (PPP), Internetwork Packet (IP), Transmission Control Protocol (TCP), Raw Socket, and/or User Datagram Protocol (UDP).

26. The process ofclaim 23, wherein said network protocol layer module step of encoding and decoding network packet bytes further comprises the step of:

processing network packets bytes in real time.

27. The process ofclaim 23, wherein said step of encoding and decoding network packet bytes network protocol layer module further comprises the step of:

processing network packets bytes concurrently.

28. The process ofclaim 23, wherein said step of encoding and decoding network packet bytes network protocol layer module further comprise the stepsof:

processing network packet bytes packets in a byte serial fashion.

29. The process ofclaim 23, wherein said step of processing packet data bytes data handler module further comprises the step of:

processing specific data type(s) using at least one state machine.

30. The process ofclaim 29, wherein said step of processing packet data bytes data handler module further comprises the step of:

use of a CRC algorithm to decode data fields.

31. The process ofclaim 29, wherein said step of processing packet data bytes data handler module further comprises the step of:

processing one or more of the following protocols: Hypertext Transfer Protocol (HTTP), Hypertext Markup Language (HTML), Post Office Protocol (POP3), Internet Message Access Protocol (IMAP4), Simple Mail Transfer Protocol (SMTP), Joint Photographic Experts Group (JPEG), Graphics Interchange Format (GIF), and/or Java language.

32. The process ofclaim 29, wherein said step of processing packet data bytes data handler module further comprises the step of:

processing packet data bytes in real time.

33. The process ofclaim 29, wherein said step of processing packet data bytes data handler module further comprises the step of:

processing packet data bytes concurrently.

34. The process ofclaim 29, wherein said step of processing packet data bytes data handler module further comprises the step of:

processing packet data bytes in a byte serial fashion.

35. The process ofclaim 29, wherein said step of processing packet data bytes data handler module further comprises the step of:

placing any data more than once by a specific one of said at least one state machine in a specific memory location with a pointer designating said memory location.

36. The process ofclaim 23, wherein said step of controlling memory accesses further comprises the step of: memory control module arbitrating es all memory accesses.

37. The process ofclaim 23, wherein said step of controlling memory accesses further comprises the step of: memory control module allowing s a system memory and a video memory to reside in a same memory area using a Unified Memory Architecture (UMA).

38. The process ofclaim 23, wherein said step of controlling state machine sequencing further comprises ing the step of:

arbitrating between said step of encoding and decoding network packet bytes network protocol layer module, said step of processing packet data bytes data handler module, and said step of controlling memory accesses memory control module for resource control, system and user interface.

39. The process ofclaim 23, wherein said step of controlling state machine sequencing further comprises ing the step of:

interpreting system and user input for the purpose of controlling data handler modules and network protocol layer modules.

40. The process ofclaim 23, further comprising the step of:

displaying output data.

41. The process ofclaim 40, wherein said step of displaying output data further comprises the step of:

controlling one of the following types of displays: VGA, television, Liquid Crystal Display (LCD), or Light Emitting Diode (LED).

42. The process ofclaim 23, wherein said process is used to implement an interface between Internet signals and application products by processing Internet signals in real-time and sending said processed Internet signals to said application products.

43. The apparatus ofclaim 1, wherein said memory control module provides display data.

44. The process ofclaim 23, wherein said memory control module provides display data.

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