USRE38482E1 - Delay stage circuitry for a ring oscillator - Google Patents

Abstract

A ring oscillator includes an even-numbered plurality of ring coupled delay stages. Each delay stage includes a differential amplifier, a voltage clamping circuit, and a current source. The differential amplifier receives first and second input signals from a preceding delay stage. The differential amplifier provides a first output signal and a complementary second output signal at first and second nodes, respectively. The voltage clamping circuit is coupled between the first and second nodes to limit a peak-to-peak voltage swing of each of the first and second output signals. The current source is coupled to the differential amplifier and varies a bias current in accordance with a delay bias voltage.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 08/347,844, filed Dec. 1, 1994 (now U.S. Pat. No. 5,596,610), which is a continuation of application Ser. No. 08/161,769, filed Dec. 2, 1993 (now abandoned), which is a divisional of application Ser. No. 07/890,034, filed May 28, 1992 (now abandoned).

FIELD OF INVENTION

The present invention relates to clock synchronization circuitry including a cascaded phase locked loop. In particular the present invention relates to a delay stage for a ring oscillator and a fine phase tuning circuitry, both used in the cascaded phase locked loop.

BACKGROUND OF THE INVENTION

Clock synchronization in integrated circuits is typically performed by a phase locked loop (PLL).

Some prior PLLs use a ring oscillator as a voltage controlled oscillator. A ring oscillator is a chain of inversion elements coupled together in a negative feedback fashion, with each element contributing a delay amount which adds up to half an oscillation period. Some prior phase locked loop implementations using ring oscillators suffer phase offset and deadband problems, which are difficult to minimize without compromising one or the other.

One disadvantage of prior ring oscillators is that the number of phase signals that can be generated are limited by the number of inversion elements contained in the ring oscillator. The number of inversion elements is, in turn, limited by the length of time delay contributed by each inversion element. The greater the time delay of the inversion element, the fewer the number of inversion elements that can be included in the ring oscillator.

Another disadvantage of some prior oscillators is that they must include an odd number of inversion elements to develop a phase shift of greater than 180°.

Other prior PLLs use voltage controlled delay line to generate the phase shift necessary for oscillation. Such prior PLLs have a limited delay range, typically a clock period or less. Hence, the frequency of operation of such prior PLLs is very limited. Prior PLLs including delay lines also tend to be susceptible to supply noise because of their use of CMOS inverters, which couple supply noise directly into output signals.

SUMMARY AND OBJECTS OF THE INVENTION

One object of the present invention is to provide a method and circuitry for synchronizing internal device functions to an external clock.

Another object of the present invention is to provide a method and circuitry for clock synchronization that allows phase deadband characteristics to be easily optimized.

Another object of the present invention is to provide a method and circuitry for clock synchronization that allows easy optimization of stability characteristics.

Another object of the present invention is to provide a method and circuitry for clock synchronization that minimizes the affect of the delay of clock buffers.

Another object of the present invention is to provide a method and circuitry for clock synchronization that minimizes the affect of a cock distribution network on loop stability.

A still further object of the present invention is to provide a method and circuitry for clock synchronization that allows easy optimization of loop bandwidth.

A further object of the present invention is to provide a method and circuitry for clock synchronization that provides high rejection of power supply noise.

Another object of the present invention is to provide a method and circuitry for fine phase adjustment with small static phase error and high loop stability.

Another object of the present invention is to provide a method and circuitry for phase adjustment in which there are no boundary conditions or start up conditions to be concerned with.

Another object of the present invention is to provide a method and circuitry for clock synchronization that provides smooth phase adjustment.

Another object of the present invention is to provide a method and circuitry for clock synchronization that is suitable for a wide range of frequencies.

Another object of the present invention is to provide a method and circuitry for clock synchronization that minimizes restart response time after power down.

Another object of the present invention is to provide a method and circuitry for clock synchronization that compensates for the delays associated with data input circuitry and data output circuitry.

A still further object of the present invention is to provide a method and circuitry for clock synchronization that generates an output signal with an controlled phase offset with respect to the input reference signal.

A method of performing phase adjustment in a phase locked loop is described. First, two phase signals are selected from a multiplicity of phase signals. The two selected phase signals are selected by a select signal. Next, an output signal is generated by interpolating between the two selected phase signals. The contribution of each of the two selected phase signals to the output signal is determined by a weighting signal.

Also described is phase tuning circuitry, which includes a phase selector and a phase interpolator. The phase selector selects two phase signals from a multiplicity of phase signals in response to a select signal. The two selected phase signals are coupled to the phase interpolator. The phase interpolator generates an output signal by interpolating between the two selected phase signals. The relative contribution of each of the two selected phase signals to the output signal is determined by a weighting signal.

Also described is a delay stage for a ring oscillator. The ring oscillator includes an even number of cascaded delay stages. Each delay stage includes a differential amplifier, which generates two complementary output signals. Coupled between the complementary output signals, two voltage clamping means limit the peak-to-peak voltage swing of the output signal. Limiting the peak-to-peak voltage swing of the output signal speeds-up the delay stage and allows the ring oscillator to includes a greater number of delay stages.

Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and the detailed description that follows.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements and in which:

FIG. 1 is a block diagram of a high speed computer bus.

FIG. 2 is a block diagram of a phase locked loop.

FIG. 3 is a block diagram of the VCO.

FIG. 4 is a diagram of the relationship between the external reference signal and the phase signals output by the VCO.

FIG. 5 is a schematic diagram of a delay stage of the VCO.

FIG. 6 is an illustration of the phase adjustment levels of the phase selection circuitry and the phase interpolator.

FIG. 7 is a detailed block diagram of the receive subloop within the phase locked loop.

FIG. 8 is a schematic diagram of the coarse select control circuit.

FIG. 9 is a block diagram of the even multiplexer and the odd multiplexer.

FIG. 10 is a schematic diagram of a multiplexer select stage.

FIG. 11 is a schematic diagram of the phase interpolator.

FIG. 12 is a timing diagram for a subloop of the phase locked loop.

FIG. 13 is a detailed block diagram of the transmit subloop within the phase locked loop.

FIG. 14 is a block diagram of the out-of-phase even multiplexer and the out-of-phase odd multiplexer.

DETAILED DESCRIPTION

FIG. 1 is a block diagram of a high speed digitalcomputer bus system20.Devices30 and32 useclock synchronization circuitry36 to synchronize the transfer of data betweendata bus38.Clock synchronization circuitry36 is a cascaded phase locked loop (PLL)36. The main loop ofPLL36 utilizes a ring voltage controlled oscillator (VCO), which includes an even number of cascaded delay stages of the present invention. Two subloops coupled to the main loop perform fine phase tuning according to the method and circuitry of the present invention to generate two internal clock signals.

As will be described in more detail below, each delay stage of the present invention generates two complementary output signals using a differential amplifier. Coupled between the two complementary output signals, two clamping devices limit the peak-to-peak voltage swing of the complementary output signals. When the delay stages are cascaded together, they provide twelve different phase signals that are used by the subloops.

The method and circuitry for fine phase adjustment used in the subloops also will be described in detail below. Briefly described, the phase tuning circuitry of the present invention includes a phase selector and a phase interpolator. The phase selector selects an even phase signal and an odd phase signal from the twelve phase signals output by the VCO of the main loop. The even and odd phase signals are selected by an even select signal and an odd select signal, respectively. The phase interpolator interpolates between the even phase signal and the odd phase signal to generate an output signal. The effect of the even phase signal and the odd phase signal on the output signal is determined by an even weighting signal and an odd weighting signal, respectively. The weighting signals allow even phase signals and odd phase signals to switch without introducing jitter onto the output signal.

The high speed digitalcomputer bus system20 of FIG. 1 includesmaster device30,slave devices32, only one of which is shown, anddata bus38.Data bus38 transfers data betweendevices30 and32 at data rates up to 500 MBytes per second, in the preferred embodiment.

Master device30 is an intelligent device, such as a microprocessor, an application specific integrated circuit (ASIC), a memory controller, or a graphics engine.Master30 differs fromslave device32 in thatmaster device30 initiates data requests, such as requests to read or writeslave devices32.

Slave devices32 do not include as much intelligence asmaster device30 and can only respond to data requests.Slave devices32 may be dynamic random access memories (DRAMs), static random access memories (SRAMs), read only memories (ROMs), electrically programmable read only memories (EPROMs), or flash memories.

Master device30 andslave devices32 transfer data synchronously. That is, data transfers are referenced to the clock edges of clock signalsCLOCKFROMMASTER42 andCLOCKTOMASTER44. Both clock signals42 and44 are generated byclock source46. Both clock signals42 and44 are carried by a single clockline, which turns around nearmaster device30. From there, the clockline extends back towardclock source46, where it is terminated. As a result, both CLOCKFROMMASTER42 andCLOCKTOMASTER44 run at the same frequency. The phase shift between clock signals42 and44 varies depending upon the location ofdevices30 and32 relative to the turnaround in the clockline. The phase difference between clock signals42 and44 is approximately 0° near the turnaround and increases as distance from the turnaround increases.

Slave devices32 transmit data with the edges of CLOCKTOMASTER44 and receive data withCLOCKFROMMASTER42. Analogously,master device30 transmits data with the edges of CLOCKFROMMASTER42 and receives data withCLOCKTOMASTER44. Clock and data signals remain synchronized as they propagate toward their destination because clock lines42 and44 anddata bus38 are matched for delay.

Devices30 and32 interface withdata bus38 and clock signals42 and44 usinginterface34.Interface34 performs a number of tasks. Among those tasks,interface34 converts the low voltage levels ofdata bus38 to ordinary CMOS levels.Interface34 also generates internal clocks for receiving and transmitting data.Interface34 usesclock synchronization circuitry36 to perform voltage level conversion and clock synchronization.

FIG. 2 illustrates in block diagram formclock synchronization circuitry36 that is the heart ofinterface34. Phase lockedloop36 synchronizes the reception of data to the device's external receive clock,CLOCKTOMASTER44 orCLOCKFROMMASTER42, as the case may be. Similarly, phase lockedloop36 synchronizes the transmission of data with the device's external transmit clock,CLOCKTOMASTER44 orCLOCKFROMMASTER42, as the case may be.

Phase lockedloop36 performs both synchronization tasks using a cascaded design, which includesmain loop52 and two subloops, a receivesubloop54 and a transmitsubloop56.Main loop52 acquires and tracks frequency, outputting12 phase signals, PH(11:0)58, all with the same frequency, to subloops54 and56. Subloops54 and56 perform fine phase tracking of clock signals42 and44 by selecting two phase signals from PH(11:0)58. The two selected phase signals are interpolated to generate internal receive and transmit clock signals,INTRCLK60,INTTCLK62, and LEADINGINTTCLK63.INTRCLK60 is in-phase with external receiveclock42.INTTCLK62 is also in phase with its external reference clock signal,TCLK_S44. In contrast, LEADINGINTTCLK63 leadsTCLK_S44 by 90° in a preferred embodiment.

Main loop52 uses a conventional second order architecture to track and acquire signal frequencies ranging from 50 MHz to 250 MHz.Main loop52 has a short pull in time of less than 10 usec. The amount of static phase error generated bymain loop52 has no affect upon the phase tracking accuracy ofPLL36 becausesubloops54 and56 perform phase acquisition. Thus, static phase error inmain loop52 may be, and is, traded for reduced deadband and improved stability characteristics. In contrast, the jitter of phase signals PH(11:0)58 is minimized because it directly affects the jitter withinsubloops54 and56.

Optimization of the stability of phase signals PH(11:0)58 is further aided by the cascaded design ofPLL36. Clock distribution and buffering is performed bysubloops54 and56, rather thanmain loop52. Thus, main loop stability is unaffected by buffer and clock distribution delay. Consequently, main loop bandwidth may be easily optimized and the size offilter8284reduced. This is particularly important in embodiments in which filter84 and all ofPLL36 is fabricated on a single die.

Main loop52 includesamplifiers74 and76, counters78, frequency-phase detector (FPD)80,charge pump82,filter84, and voltage controlled oscillator (VCO)86.

Amplifier74 amplifies RCLK_Sto a voltage swing of 0 volts to 5 volts, as required byFPD80.Amplifier76 similarly amplifiesPH090 to a voltage swing of 0 volts to 5 volts. The gain ofamplifiers74 and76 necessarily differ because the voltage swings of RCLK_SandPH090 differ. This difference in amplification prior to frequency and phase detection byFPD80 introduces static phase error intomain loop52. The static phase error so introduced is tolerable because it does not affect the phase tuning ofsubloops54 and56.

Prefered implementations of phase lockedloop36 includecounters78 to increase the frequency range ofPLL36.Counters78 divide the frequency of their inputs by two, prior to coupling their outputs toFPD80.Counters78 thus enhance the frequency response ofFPD80 by expanding the range of frequencies that FPD80 can accommodate.

FPD80 is a sequential frequency detector, selected for its large tracking range and short pull-in time.

Charge pump82 converts the output ofFPD80 into current pulses.Charge pump82 eliminates deadband with its high input sensitivity.Charge pump82 introduces static phase error because its mechanisms for switching from a high-to-low output and from a low-to-high output are not symmetrical. This static phase error is tolerable becausemain loop52 does not perform phase tuning. Thus,charge pump82 may, and does, differ from prior charge pumps because withinmain loop52 dead band characteristics may be reduced without concern for static phase error.

Filter84 converts the current pulses into theanalog control voltage85 coupled toVCO86 using a standard one-pole, one zero, passive filter.

VCO86 is a six delay stage ring oscillator. Each delay stage generates two of the twelve phase signals. PH(11:0)58. The differential design of the VCO stage provides high power-supply rejection (PSR), as well as complementary outputs.

FIG. 3 illustrates in block diagram form ring voltage controlledoscillator86.VCO86 varies from previous ring oscillators in two respects. First,VCO86 includes an even number of delay stages140.VCO86 is able to generate 180° phase shift with an even number of delay stages140 because eachdelay stage140 generates two complementary outputs that are appropriately coupled to the next delay stage. Second,VCO86 includes a greater number of delay stages than normal.VCO86 is able to include more delay stages because eachdelay stage140 contributes less delay then prior delay stages.

Eachdelay stage140a-140f ofVCO86 generates two pairs of complementary output signals, OUT and OUTB, and CK and CKB. CK and CKB are buffered, level shifted versions of OUT and OUTB. Thus, CK and CKB have the same voltage swings and frequencies as OUT and OUTB. The buffering of CK and CKB prevents their loading from affecting the stability ofVCO86.

Delaystages140a-140f are coupled together via OUT and OUTB so that the entire phase shift from the input ofdelay stage140a to the output ofdelay stage140f is greater than or equal to 180° at the oscillation frequency. Outputs OUT ofdelay stages140a-140e are coupled together to the INB inputs of thenext delay stage140b-140f. Outputs OUTB ofdelay stages140a-140e are coupled to inputs IN of delay stages140b-140f. Only the coupling between delay stages140f and140a varies from this pattern.

Outputs CK and CKB of eachstage stage140a-140f are coupled tosubloops54 and56 as two of the twelvephases58 output byVCO86.

Control voltage,V_c85, controls the frequency at which eachdelay stage140a-140f switches via bias voltage,V_BN160,V_c85 can vary between 3.5 volts to 0 volts, giving VCO86 a wide locking range,V_c85 also ensures that phase signals PH(11:0)58 have a symmetrical voltage swing via bias voltage,V_BP162.

FIG. 4 illustrates the relationship between the twelvephase signals58 generated byVCO86. WhenPLL36 is inlock PH090 should be in-phase with reference signal, RCLK_S, except for the static phase error contributed byamplifiers74 and76, andcharge pump82. The remaining phases, PH(11:1)58, are evenly spaced across the clock period of RCLK_S.

The first stage ofVCO86,delay stage140a,output PH090 andPH6102. These signals may be referred to as PH0 and its complement or PH6 and its complement.

Thesecond delay stage140b generatesPH192 andPH7104. These signals are also referred to as PH1 and it complement or PH7 and its complement.

PH294 andPH8106 are the outputs of thedelay stage140c. These signals are also referred to as PH2 and its complement or PH8 and its complement.

Complementary phase signalsPH396 andPH9108 are generated bydelay stage140d.

Thefifth delay stage140e generates the complementaryphase signals PH498 andPH10110.

Delay stage140f generatesPH5100 andPH11112. These signals are also referred to as PH5 and its complement or PH11 and its complement.

FIG. 5 is a schematic diagram of adelay stage140 withinVCO86.Delay stage140 includesdifferential amplifier164,current source166, andsource follower buffer168.

The delay time ofdelay stage140 is controlled by biascurrent I_B181. Varying I_B181 varies the delay time ofdelay stage140. Bias current I_B181 is, in turn, controlled by bias voltage,V_BN160. The delay time ofdelay stage140 is smallest when V_BNis at its maximum level of 3.5 volts.

Another factor contributes to the relatively small delay time ofdelay stage140. Unlike prior delay stages, the voltage swing of OUT and OUTB and CK and CKB is limited. This increases the frequency range ofdelay stage140, allowing it to operate at higher frequencies.

Limiting the voltage swing of OUT and OUTB and CK and CKB also increases power supply rejection (PSR) by preventingtransistors186,188 and167 from entering deeply into their linear region of operation and keeping their output resistance relatively high.

The biasing oftransistors186 and188 is controlled byV_BP162. The bias generator for V_BP162 (not shown) uses a simple current mirror design. More complex bias generators, which include common-mode feedback, could be used to setV_BP162 such that the desired voltage level is maintained at OUT and OUTB.

The voltage swing between OUT and OUTB is limited to approximately 1.5 volts peak-to-peak bytransistors190 and192.Transistors190 and192 are coupled in diode fashion between OUT and OUTB, thus clamping the peak-to-peak voltage swing.

The range of possible voltage levels for OUT and OUTB is 4.5 volts to 3.0 volts. This is illustrated by the two waveforms in the upper right corner of FIG.5. The range of voltage levels for CK and CKB is 3.3 volts to 1.8 volts. This is illustrated by the two waveforms in the lower right corner of FIG.5.

The symmetrical shape of CK, CKB, OUT and OUTB results because I_C180 is approximately equal to 2×I_B181. Setting the common mode voltage level of OUT and OUTB near 3.75 V preventsnode183 from going to ground. As a result, the output impedance ofcurrent source166 remains high, keeping the VCO common mode rejection of power supply noise high.

Referring once again to FIG. 2, consider now subloops54 and56.Subloop54 is a single first order loop.Subloop56, in contrast tosubloop54, includes two first order loops. One loop is closed and is used to generate the in phase internal transmit clock,INTTCLK62. This closed loop is essentially identical to subloop54, varying only in its input signal and output signal. The second loop withinsubloop56 operates open loop, generating the leading internal transmitclock LEADING INTTCLK63. The amount of phase by which LEADINGINTTCLK63 leadsINTTCLK62 is fixed, but selectable, as will be described in detail below.

For simplicity's sake,subloop54 will be described in detail first. Aided by that discussion, subloop56 will then be described.

Subloop54 performs phase tuning using the 12 phase signals generated byVCO86, PH(11:0)58. The heart ofsubloop54 is phaseselect circuitry120 andphase interpolator122a. Phaseselect circuitry120 performs coarse phase adjustment by selecting as outputs an even phase signal and an odd phase signal from PH(11:0)58. Even phase signals arePH090,PH294,PH498,PH6102,PH8106, andPH10110. Odd phase signals arePH192,PH396,PH5100,PH7104,PH9108, andPH11112. Normally, the selected odd phase signal and the selected even phase signal will be adjacent to each other. For example,PH396 is adjacent to even phasesPH294 andPH498.Phase interpolator122a generates a signal that lies between the selected odd phase signal and the selected even phase signal.Phase interpolator122a can generate 16 discrete values between the two selected phase signals using an even weighting signal and an odd weighting signal.

FIG. 6 illustrates the phase adjustment levels ofphase selection circuitry120 andphase interpolator122. The inputs to phaseselect circuitry120, PH(11:0)58, are represented by 12 horizontal lines, which are vertically evenly spaced apart. These lines represent twelve coarse adjustment levels across the period of the external reference clock; e.g., RCLK_S. These twelve levels are further subdivided byphase interpolator122, which generates 16 fine adjustment levels between each coarse adjustment level. Thus, the clock period is divided into 12×16, or 192, phase divisions.

Referring once again to FIG. 2,amplifier124a amplifies the output ofphase interpolator122a and passes it on toclock buffer126a.Clock buffer126a then distributes INTRCLK60 throughout the device,30 or32.

Phase detector128 compares the internal clock signal,INTTCLK60 to the external reference,RCLK_S42, and indicates the polarity of the phase error toaccumulator circuitry130.

In oneembodiment phase detector128 is a latch.Phase detector128 is preferably the same type of latch used by the data input circuitry ofinterface34, which allowssubloop54 to compensate for the delay caused by data input circuitry. Preferably, internal receive clock,INTRCLK60, is fedback to the latch's clock input and the reference signal,RCLK_S42, is coupled to the latch's data input. Thus,INTRCLK60 determines the time at whichRCLK_S42 is sampled. When subloop54 is in lock,phase detector128 outputs a stuttering string of logical 1s and 0s.Phase detector128 outputs alogic 1 when the low-to-high transition ofINTRCLK60 occurs before the low-to-high transition ofRCLK_S42. Conversely, phase detector125 outputs alogic 0 when the low-to-high transition ofINTRCLK60 occurs after the low-to-high transition ofRCLK_S42.

Accumulator circuitry130 uses the output ofphase detector128 to control both phaseselect circuitry120 andphase interpolator122. In other words,accumulator circuitry130 controls both coarse and fine phase adjustment.

The cooperation betweenaccumulator circuitry130, phaseselect circuitry120, andphase interpolator122 can be understood in greater detail with reference to FIG.7. FIG. 7 illustratesportion55 ofsubloop54.

Accumulator circuitry130 responds to two input signals,PHERR196 andLEADPHASE198.PHERR196 is the output ofphase detector128 and as such indicates the polarity of the phase error between the internal clock and the external clock.PHERR196 indicates that the internal clock lags the external clock with alogic 1. With alogic 0PHERR196 indicates the internal clock leads the external clock.LEADPHASE198 indicates whether the leading phase signal selected by phaseselect circuitry122 is even or odd.LEADPHASE198 is alogic 0 when the leading phase is even and alogic 1 when the leading phase is odd. For example, when phaseselect circuitry122 selects PH3 and PH4 as its outputs LEADPHASE is alogic 1.LEADPHASE198 is likewise alogic 1 when phaseselect circuitry122 selects PH11 and PH0. Conversely,LEADPHASE198 is alogic 0 when PH6 and PH7 are selected.

Counter control circuit200 exclusivelyNORes PHERR196 andLEADPHASE198 together to generate UP/DOWNB signal202. UP/DOWNB202 controls up/downcounter206. When UP/DOWNB202 is alogic 1 up/down counter206 counts up. Up/down counter206 counts down when UP/DOWNB202 is alogic 0.

Counter control circuit200 also generates aninternal clock signal204 to synchronize the operation ofsubloop54.Counter control circuit200 divides down the clock generated bysubloop54,INTRCLK60, to generateSLOWCLK204. In the preferred embodiment,counter control circuit200 dividesINTRCLK60 by 16.

Up/downcounter206 generates a number of signals,208,210,212, and214, in response to UP/DOWNB202. These signals,208,210,212, and214, control phaseselect circuitry120 andphase interpolator122. Up/downcounter206 represents the value of its count via COUNT(3:0)208. The sixteen levels of fine phase adjustment ofphase interpolator122 result from the resolution of COUNT(3:0)208 and its complement, COUNTB (3:0)210. Up/down counter206 outputs two other signals,OFLOW214 andUFLOW212. Overflow signal,OFLOW214, goes active high when up/downcounter206 is requested to increment COUNT (3:0)208 above it maximum value; i.e., 15. Analogously, underflow signal,UFLOW212, goes active high when up/downcounter206 is requested to decrement COUNT (3:0)208 below it minimum value; i.e., 0.UFLOW212 and OFLOW214 control phaseselect circuitry120.

Digital-to-analog converter (DAC)216 converts COUNT (3:0)208 into an analog signal to generateEVENWEIGHT218. Similarly, COUNTB(3:0)210 is converted into an analog signal to generateODDWEIGHT220.Phase interpolator122 determines the weighting of odd and phase select signals in response to EVENWEIGHT218 andODDWEIGHT220.

Phaseselect circuitry120 includes coarseselect control circuit230, which controls even phaseselect circuit240 and odd phaseselect circuit260. Coarseselect control circuit230 clocks even phaseselect circuit240 using even clock signal,ECLK232. The operation of even phaseselect circuit240 is controlled by shift right and shift left signals,SHR234 andSHL236,SHR234 andSHL236 also control odd phaseselect circuit260. Coarseselect control circuit230 generates a unique clock signal,OCLK238, to clock odd phaseselect circuit260.

While tuning up or down through phase PH(b11:0)58, coarseselect control circuit230 alternately bringsactive OCLK238 andECLK232. This alternating action derives from the alternating action ofUFLOW212 andOFLOW214.

The relationship betweenUFLOW212,OFLOW214,OCLK238, andECLK232 can be understood in greater detail with reference with FIG.8. FIG. 8 illustrates coarseselect control circuit230.

Shift clocksOCLK238 andECLK232 are generated using NORgate280, andNAND gates282 and284. RESET286 andSLOWCLK204 are NORed together bygate280. The output of NORgate280, signal281, is generally an inverted version ofSLOWCLK204, except whenRESET286 is active high.Signal281 is coupled togates282.NAND gate282 combines signal281 and UFLOW212 to generateECLK232. Similarly,NAND gate284 combines signal281 and OFLOW214 to generateOCLK238.

LEADPHASE198,SHR234, andSHL236 are generated usingNAND gate288 and toggle flip-flops290292and292294.NAND gate288 combines OCLK238 andECLK232 to generateTOGGLE290.TOGGLE290 is coupled to the T input of toggle flip-flop292, which outputsLEADPHASE198. Toggle flip-flop292 resetsLEADPHASE198 to a logic zero whenRESET286 is active high.

TOGGLE292290is inverted and then coupled to toggle flip-flop294. Toggle flip-flop294 couples itsoutput296 toEX-NOR gate298, which exclusivelyNORes output296 withOFLOW214.SHL236 is an inverted version of the output ofEX-NOR gate298 andSHR234.

Referring again to FIG. 7, consider the influence of coarseselect control circuit230 uponcircuits240 and260. Even phaseselect circuit240 includes abarrel shifter242 and an analog 6-to-1multiplexer246. Evenbarrel shifter242 generates six even select signals, ES(5:0)244, for evenmultiplexer246. Evenselect signals244 are digital signals.Barrel shifter242 brings only one of the six evenselect signals244 active high at a time. This is becausebarrel shifter242 is initially loaded with a value of 1. Which of the six even select signals is active depends upon the previous state ofbarrel shifter246 and the states ofSHR234 andSHL236.

From itsinputs58, even multiplexer246 selects one of the six even phase signals using even select signals, ES(5:0)244. Even multiplexer246 associates one even select signal with one even phase signal. As a result, even multiplexer246 selects as evenphase output signal248 the single even phase signal associated with an active even select signal.

Like even phaseselect circuit240, odd phaseselect circuit260 includes abarrel shifter262 and an analog 6:1multiplexer266. Oddselect circuit260 differs from even phaseselect circuit240 only in its input and output signals. In other words, odd phaseselect circuit260 functions like even phaseselect circuit240.

FIG. 9 is a block diagram of a preferred embodiment of even multiplexer246 andodd multiplexer266. For simplicity's sake, the pull-up circuitry associated withmultiplexer246 andodd multiplexer266 has been omitted. Eachmultiplexer246 and266 uses three identical multiplexerselect stages300.

Evenphase multiplexer246 includes threeselect stages300a,300c, and300e. Each evenselect stage300a,300c and300e receives two complementary even phase signals, and two even select signals. Using these input signals, each even selectstage300a,300c, and300e generate two complementary outputs,OUT302a,302c, and302e andOUTB304a,304c, and304e. All threeOUT signals302a,302c, and302e are tied together and coupled tophase interpolator122 as the even phase output signal. Similarly, all threeOUTB signals304a,304c, and304e are tied together and coupled tophase interpolator122 as the complement of the even phase output signal. To minimize propagation delay and maximize power supply rejection, the voltage swing of the even phase output signal and itscomplement248 are clamped bytransistors310 and312, which are coupled in diode fashion between the outputs ofdelay stages300a,300c, and300e.

Odd multiplexer266 mirrors the design of evenmultiplexer246. Odd multiplexer includes threeselect stages300b,300d, and300f. Each oddselect stage300b,300d, and300f receives two complementary odd phase signals, and two odd select signals. Using these input signals, each odd select stage generates two complementary outputs,OUT302b,302d, and302f andOUTB304b,304d, and304f. All threeOUT signals302b,302d, and302f are tied together and coupled tophase interpolator122 as the odd phase output signal. Similarly, all threeOUTB signals304b,304d, and304f are tied together and coupled tophase interpolator122 as the complement of the odd phase output signal. The peak-to-peak voltage swing of odd phase output signal and itscomplement268 is clamped bytransistors314 and316, which are coupled between the two signal lines in diode fashion.

The operation ofmultiplexers246 and266 can be understood in greater detail with reference to FIG.10. FIG. 10 illustrates schematically a single multiplexerselect stage300.

Multiplexerselect stage300 performs its function usingbuffering stage301 anddifferential amplifiers303 and305.Buffering stage301 buffers and shifts the voltage levels of input signals IN and INB. The outputs ofbuffering stage301, IN′ and INB′, are then coupled todifferential amplifiers303 and305. The selected differential amplifier,303 or305, then couples the appropriate input signals to OUT and OUTB.

The operation of multiplexerselect stage300 is controlled by the select signals coupled to SN and SN+6. The active signal of the pair of select signals, SN or SN+6, performs two functions. First, the active select signal enables bufferingstage301. Second, the active select signal turns on one of the twodifferential amplifiers303 and305.

The enabling ofbuffering stage301 is achieved via fourtransistors307,309,311, and313 near the top of bufferingstage301. Two transistors,307 and309, are coupled toamplifier315. Similarly,transistors311 and313 are coupled toamplifier317.Transistors307 and311 are turned on and off by an inverted version of SN, SN_B. An inverted version of SN+6, SN+6_B, turnstransistors309 and315 on and off.

Consider the operation ofbuffering stage301 when one of the select inputs, SN or SN+6, is active. For example assume SN is active high. SN_B places a low voltage on the gates oftransistors307 and311, causing them to conduct.Amplifiers315 and317 responds by coupling level shift versions of IN and IN_B, IN′ and IN_B′ to the inputs ofdifferential amplifiers303 and305.Buffering stage301 responds nearly identically to an active select signal onSN+6. In this case,transistors309 and313 conduct, rather thantransistors307 and311.

Eachdifferential amplifier303 and305 is controlled by a single select signal SN and SN+6. Thus, only one differential amplifier at a time drives OUT and OUT_B.

Both differential amplifiers are enabled via theircurrent sources319 and321. For example, when active high, SN turnscurrent source319 on.Differential amplifier303 responds by coupling IN′ and OUT and IN_B′ and OUTB. Similarly, active SN+6 turns oncurrent source321. In response,differential amplifier305 couples IN_B′ to OUT and IN′ to OUT_B.

Referring yet again to FIG. 7, consider now the influence ofphase selector120 uponphase interpolator122.Phase interpolator122 performs fine phase tuning by interpolating between its inputs, evenphase output signals248 and odd output signals268. The relative contribution of these input signals248 and268 to signalPIOUT123 is determined by weighting signals,EVENWEIGHT218 andODDWEIGHT220.

The manner in whichphase interpolator122 generatesPIOUT123 can be understood in greater detail with reference to the schematic diagram of FIG.11. Even phase output signal and itscomplement248 are weighted bydifferential amplifier320. Even phase output signal is coupled to one of theinputs322 ofdifferential amplifier320, while the complement of the even phase output signal is coupled to theother input324 ofdifferential amplifier320. The amplification ofsignals248 is determined by I_E326, the current generated bycurrent source328.EVENWEIGHT218 controls the magnitude of I_E326, thus controlling the contribution ofsignals248 toPIOUT123. AsEVENWEIGHT218 decreases in voltage level, the contribution of evenphase output signals248 toPIOUT123 also decreases, and vice-versa.

Similarly,differential amplifier330 weights odd phase output signals268. One signal is coupled to input332 and the other is coupled toinput334. The current generated bycurrent source338, I_O336, determines the amplification of odd phase output signals268.ODDWEIGHT220, the input tocurrent source338, controls the magnitude of I_O336 and thus the amplification of odd phase output signals268. The amplification of oddphase output signals268 decreases and increases directly with the voltage level ofODDWEIGHT220.

The outputs ofdifferential amplifiers320 and330 are summed together by coupling their outputs together. The peak-to-peak voltage swing of the outputs ofdifferential amplifiers320 and330 are clamped bytransistors350 and352 to minimize propagation delay and maximize power supply rejection. The voltage swings ofPIOUT123 and its complement could also be clamped by other means, such as diodes.

Armed with an understanding of the architecture ofsubloop54, consider its operation while locking onRCLK_S42. Assume that the phase ofRCLK_S42 is initially some value betweenPH294 andPH396. FIG. 12 illustrates the response ofsubloop54 under these circumstances.

Active RESET286 forces evenbarrel shifter242 to output a value of 000001 (binary) as even select signals, ES(5:0)244. Evenmultiplexer246 responds to ES(5:0)244 by couplingPH090 and its complement,PH6102, to phaseinterpolator122.Active RESET286 also forces odd select signals, OS(5:0)264, to 000001 (binary).Odd multiplexer266 responds by selectingPH192 and its complement,PH7104, as itsoutputs268.

Active RESET286 may also be used to force theoutputs208,210,212, and214 of up/down counter206 to known states, though this is not necessary. IfRESET286 does not control these signals they may begin in any state upon power up. In either case, for purposes of illustration, assume that COUNT(3:0)208 begins at 0000 (binary) and COUNTB (3:0)210 begins at 1111 (binary). Also assume that bothUFLOW212 andOFLOW214 start up their inactive state. Thus,EVENWEIGHT218 is at its minimum value andODDWEIGHT220 is at its maximum value.

Phase interpolator122 responds to its input signals218,220,248, and268 by bringingPIOUT123 in-phase withPH192. Thus, the output ofsubloop54,INTRCLK60, is also in-phase withPH192.

Phase detector128 responds to INTRCLK60 laggingRCLK_S42 by forcingPHERR196 to alogic 0.

Counter control circuit200 exclusivelyNORes PHERR96 withLEADPHASE198, which has had no opportunity to change from its reset value.Active RESET286 forces LEADPHASE198 to a logic low. Thus,counter control circuit200 forces UP/DOWNB202 to a logic low.

Up/downcounter206 responds to the command to count down from UP/DOWNB202 by underflowing; i.e., bringingunderflow signal UFLOW212 active high. The values of COUNT(3:0)208 and COUNTB(3:0)210 remain unchanged.

Coarseselect control circuit230 pulses active even shift clock,ECLK232. On the active edge ofECLK232,SHL236 goes active high. Evenbarrel shifter242 shifts left in response, forcing even select signals ES(5:0)244 to change to 000010 (binary). Evenmultiplexer246 is forced to switch its selection fromPH090 toPH294 by the new value of even select signals244.

Phase interpolator122 is not immediately affected by the switching of even phase output signals248.EVENWEIGHT218 remains at its minimum value after even multiplexer246 changes its selection, preventing evenphase output signals248 from contributing toPIOUT123. Thus,phase interpolator122 glitchlessly switches from an output generated by one pair of phase signals,PH090 andPH192, to an output generated by another pair of phase signals,PH192 andPH294.

It is not long the case that the evenphase output signals248 do not contribute toPIOUT123.LEADPHASE198 changes state withECLK232.LEADPHASE198 now indicates that odd phase output signal is the lower of the two selected phase signals coupled tophase interpolator122.Counter control circuit200 responds to this change inLEADPHASE198.PHERR196 remains high, thus counter controlcircuit200 forces UP/DOWNB202 high. Up/downcounter206 begins counting up, increasing the value of COUNT(3:0)208 and decreasing the value of COUNTB (3:0)210. As up/down counter206 counts up,phase interpolator122 graduallytunes PIOUT123 from phase alignment withPH192 to phase alignment withPH294. That occurs when COUNT(3:0)208 reaches its maximum value of COUNTB(3:0)210 reaches its minimum value.

INTRCLK60, in phase withPH294, continues to lagRCLK_S42, which has a phase somewhere betweenPH294 andPH396.Phase detector128 therefore maintainsPHERR196 at alogic 1. Consequently,counter control circuit202 continues to request that up/downcounter206 increase COUNT(3:0)208 until up/downcounter206 overflows, bringingOFLOW214 active high.

Active OFLOW214 pulses active odd shift clock,OCLK238. On the active edge ofOCLK238,SHL236 goes active high, forcingodd barrel shifter262 to shift left. Odd select signals, OS(5:0)264,select PH396 with a value of 000010 (binary).

The switching by oddphase output signal268 does not affectPIOUT123 because COUNTB(3:0) is 0000 (binary) during overflow conditions. Thus,ODDWEIGHT220 prevents oddphase output signal268 from contributing toPIOUT123. Once again,phase interpolator122 glitchlessly switches from an output generated from one pair of phase signals,PH192 andPH294, to an output generated by another pair of phase signals,PH294 andPH396.

Soon afterodd multiplexer268 changes its selection,ODDWEIGHT220 begins to increase in value and to affectPIOUT123. This gradual change begins whenLEADPHASE198 changes state withOCLK238. Afterward,LEADPHASE198 indicates that the low phase signal is evenphase output signal248.PHERR196 remains high, thus counter controlcircuit200 responds to LEADPHASE198 by forcing UP/DOWNB202 low. Up/downcounter206 begins counting down, decreasing the value of COUNT(3:0)208 and increasing the value of COUNTB(3:0)210. As up/down counter206 counts down,phase interpolator122 graduallytunes PIOUT123 into near phase alignment withRCLK_S42. When that occurs,PHERR96 stutters between alogic 1 and alogic 0. Up/downcounter206 responds by see-sawing COUNT(3:0)208 between two consecutive binary values, and may underflow or overflow, allowing evenselect signals248 and oddselect signals268 to change without causing glitches onPIOUT123.

Subloop54 is not only capable of turning up through PH(11:0)58 to lock on RCLK_S42.Subloop54 tunes down when necessary. For example, consider the situation whenRCLK_S42 changes phase after subloop54 has locked. Assume that the phase of RCLK_S42 changes from a value in betweenPH396 andPH294 to a value in betweenPH294 andPH192. FIG. 12 also illustrates the response ofsubloop54 to this situation.

PHERR198 initially indicates thatINTRCLK60 leadsRCLK_S42. In other words,PHERR198 becomes and remains alogic 0 for a relatively long period of time.Counter control logic200 responds by directing up/downcounter206 to count up. Up/downcounter206 does so until it overflows, bringingOFLOW214 active high while COUNT(3:0)208 remains at 1111 (binary) and COUNTB (3:0)210 remains at 0000 (binary).

Active OFLOW214 pulses odd shift clock,OCLK238, low.Active OFLOW214 also bringsSHR234 active high andforces SHL236 inactive low. Thus, on the active edge ofOCLK238odd barrel shifter262 shifts right. This changes OS(5:0)264 from 000010 (binary) to 000001 (binary).Odd multiplexer266 responds by deselectingPH396 and selectingPH192 as odd output signal. Again,phase interpolator122 prevents the switching of odd output signals268 from affectingPIOUT123 becauseODDWEIGHT220 is at it minimum value.Subloop54 tunes betweenPH294 andPH192 as necessary to lock on RCLK_S44.

Given this description ofsubloop54, consider now the operation ofsubloop56. Referring again to FIG. 2, the closed loop withinsubloop56 closely resemblessubloop54, includingphase detector128,accumulator circuitry130, phaseselect circuitry121, in-phase phase interpolator122c,amplifier124c,clock buffer126c, and output bufferdelay compensation circuit127. As its name implies, output bufferdelay compensation circuit127 allowssubloop56 to compensate for the delay contributed to INTTCLK62 by the output buffers ofinterface34. The open loop includes phaseselect circuitry121, out-of-phase interpolator122b,amplifier124b, andclock buffer126b.

The heart ofsubloop56 is phaseselect circuitry121, in-phase phase interpolator122c, and out-of-phase interpolator122b. Phaseselect circuitry121 performs coarse phase tuning for both the open loop and the closed loop withinsubloop56. Eachphase interpolator122b and122c generates a fine-tuned signal that lies between the two pairs of phase signals coupled to it byphase selector121. Likesubloop54, both loops withsubloop56 generate 16 fine levels of adjustment between each coarse adjustment level.

Phaseselect circuitry121 gives rise to a major difference betweensubloop54 andsubloop56. Unlike phaseselect circuitry120, phaseselect circuitry121 selects two pairs of even phase output signals and two pairs of odd phase output signals. One set of pairs of even and oddphase output signals248 and268 is in-phase withTCLK_S44 and are coupled to in-phase phase interpolator122c. The other set of pairs of even and oddphase output signals249 and269 are out-of-phase withTCLK_S44 and are coupled to out-of-phase phase interpolator122b.

The cooperation of phaseselect circuitry121 andphase interpolators122b and122c can be understood in greater detail with reference to FIG.13. As can be seen,portion57 closely resemblesportion55. For this reason, the following description ofportion57 focuses on its differences as compared toportion55. Unless otherwise stated,portion57 functions likeportion55, as described with reference to FIGS. 7-12.

The primary difference between phaseselect circuitry120 and phaseselect circuitry121 arises from evenselect circuit241 and oddselect circuit261. Where evenselect circuit240 included only one even multiplexer, evenselect circuit241 includes two, in-phase evenmultiplexer246 and out-of-phase evenmultiplexer247.Multiplexers246 and247 are identical and receive identical input signals, even selectsignals244 and phase signals58. Evenselect signals244 are coupled tomultiplexers246 and247 in different fashions, however. As a result, in-phase even multiplexer246 outputs signals248 that are substantially in-phase withTCLK_S44, while out-of-phase multiplexer247 outputs signals249 that are out-of-phase withTCLK_S44.

Similar to even selectcircuit241, oddselect circuit261 includes twoodd multiplexers266 and267. In-phaseodd multiplexer266 and out-of-phaseodd multiplexer267 are identical and receive identical input signals, oddselect signals264 and phase signals58. These input signals264 and58 are coupled tomultiplexers266 and267 in differing fashions such that in-phaseodd multiplexer266 outputs signals268 in substantially in-phase withTCLK_S44 and out-of-phaseodd multiplexer267 outputs signals out-of-phase withTCLK_S44.

In-phase evenmultiplexer246 and in-phaseodd multiplexer266 are coupled to even selectsignals244, oddselect signals264, and phase signals58 as shown in FIG.9. The coupling of evenselect signals244, oddselect signals266, and phase signals58 is shown in FIG.14. For simplicity's sake, the pull-up circuitry associated withmultiplexer247 andodd multiplexer267 has been omitted. In the embodiment shown, out-of-phase evenphase output signals249 and out-of-phase oddphase output signals269 lead their in-phase counterparts248 and268 by substantially 90°. This phase shift in the out-of-phase multiplexer is achieved by associating each select signal with aphase signal58 that leads by 90° the phase signal associated with that same select signal in the corresponding in-phase multiplexer. For example, in in-phase even multiplexer246 even select signal ES0 selectsphase signal PH090. In contrast, out-of-phase even multiplexer247 selectsPH9108 using ES0. Analogously, while OS3 is used to select PH7 in in-phaseodd multiplexer266, OS3 is used to selectPH498 in out-of-phaseodd multiplexer267.

The degree of phase shift betweensignals248 and249, and268 and269, may be arbitrarily selected in other embodiments simply by altering which select signal selects which phase signal in out-of-phase multiplexers247 and267.

Out-of-phase phase interpolator122b uses the output of out-of-phase multiplexers247 and267 to generate PIOUT- 90°123b. Out-of-phase interpolator122b also responds to EVENWEIGHT218 andODDWEIGHT220, as discussed with respect to FIGS. 7-12.

Thus, circuitry for performing fine phase adjustment within a phase locked loop has been described. The phase selector selects an even phase signal and an odd phase signal from the twelve phase signals output by the VCO. The even and odd phase signals are selected by an even select signal and an odd select signal, respectively. The phase interpolator interpolates between the even phase signal and the odd phase signal to generate an output signal. The affect of each phase input signal on the output signal is determined by an even weighting signal and an odd weighting signal, respectively. Together, the weighting signals and the switching mechanisms of the phase select circuitry prevent glitches from appearing on the output signal when either the even phase signal or the odd phase signal is switching.

A method of performing fine phase adjustment in a phase locked loop has also been described. First, two phase signals are selected from a multiplicity of phase signals. The two phase signals are selected by a select signal. Next, an output signal is generated by interpolating between the two phase signals. The contribution of each of the two phase signals to the output signal is determined by a weighting signal. The weighting signals prevent glitches from appearing on the output signal when either the even phase signal or the odd phase signal is switching.

Finally, a delay stage for a ring oscillator has also been described. Each delay stage includes a differential amplifier, which generates two complementary output signals. Coupled between the complementary output signals, two voltage clamping means limit the peak-to-peak voltage swing of the output signal. Limiting the peak-to-peak voltage swing of the output signal speeds-up the delay stage and allows the ring oscillator to include a greater number of delay stages, and increases the power supply rejection of the oscillator.

In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims (103)

What is claimed is:

1. A ring oscillator comprising:

a plurality of ring coupled delay stages, each delay stage comprising:

(A) a differential amplifier for generating a differential output signal comprising a first output signal at a first node and a second output signal at a second node, wherein the differential amplifier further comprises:

(i) a first transistor coupled to the first node;

(ii) a second transistor coupled to the second node and the first transistor, wherein the first and second transistors are biased by an output level biasing voltage;

(iii) a third transistor coupled to the first node, wherein the third transistor receives a first input signal from a preceding delay stage;

(iv) a fourth transistor coupled to the second node and the third transistor, wherein the fourth transistor receives a second input signal from the preceding delay stage;

(B) a self-biased voltage clamping circuit coupled to the first and second nodes to limit a peak-to-peak voltage swing of the differential output signal; and

(C) a current source coupled to the differential amplifier, the current source varying a bias current through the current source in accordance with a delay bias voltage.

2. The ring oscillator ofclaim 1, wherein the voltage clamping circuit further comprises:

(i) a first diode-coupled transistor; and

(ii) a second diode-coupled transistor, wherein the first and second diode-coupled transistors are cross-coupled between the first and second nodes.

3. The ring oscillator ofclaim 2, wherein the first and second diode-coupled transistor are metal-oxide semiconductor transistors.

4. The ring oscillator ofclaim 2, wherein the first and second diode-coupled transistors are N-type transistors.

5. The ring oscillator ofclaim 1, wherein the current source further comprises a fifth transistor.

6. The ring oscillator ofclaim 1 wherein the first and second transistors are of a first type, wherein the third and fourth transistors are of a second type.

7. The ring oscillator ofclaim 6 wherein the first and second transistors are P-type and the third and fourth transistors are N-type.

8. The ring oscillator ofclaim 6 wherein the first and second transistors are N-type and the third and fourth transistors are P-type.

9. The ring oscillator ofclaim 6 wherein the first and second types are complementary.

10. The ring oscillator ofclaim 1 wherein each delay stage further comprises a source follower buffer.

11. A ring oscillator comprising:

a plurality of ring coupled delay stages, each delay stage comprising:

(A) a differential amplifier for generating a first output signal at a first node and a second output signal at a second node, wherein the differential amplifier further comprises:

(i) a first transistor coupled between the first node and a first potential;

(ii) a second transistor coupled between the second node and the first potential, wherein the first and second transistors are biased by an output level biasing voltage;

(iii) a third transistor coupled between the first node and a third node, wherein the third transistor receives a first input signal from a preceding delay stage;

(iv) a fourth transistor coupled between the second node and the third node, wherein the fourth transistor receives a second input signal from the preceding delay stage;

(B) a current source coupled between the third node and a second potential, the current source varying a bias current through the current source in accordance with a delay bias voltage; and

(C) a voltage clamping circuit coupled to the first and second nodes to limit a relative peak-to-peak voltage swing of the first and second output signals without independently clamping each of the first and second nodes.

12. The ring oscillator ofclaim 11, wherein the voltage clamping circuit further comprises:

(i) a first diode-coupled transistor; and

(ii) a second diode-coupled transistor, wherein the first and second diode-coupled transistors are cross-coupled between the first and second nodes.

13. The ring oscillator ofclaim 12, wherein the first and second diode-coupled transistors are metal-oxide semiconductor transistors.

14. The ring oscillator ofclaim 12, wherein the first and second diode-coupled transistors are N-type transistors.

15. The ring oscillator ofclaim 11, wherein the current source further comprises a fifth transistor.

16. The ring oscillator ofclaim 11 wherein the first and second transistors are of a first type, wherein the third and fourth transistors are of a second type.

17. The ring oscillator ofclaim 16 wherein the first and second transistors are P-type and the third and fourth transistors are N-type.

18. The ring oscillator ofclaim 16 wherein the first and second transistors are N-type and the third and fourth transistors are P-type.

19. The ring oscillator ofclaim 16 wherein the first and second types are complementary.

20. The ring oscillator ofclaim 11 wherein each delay stage further comprises a source follower buffer.

21. A ring oscillator comprising:

a plurality of ring coupled delay stages, each delay stage comprising:

a differential amplifier providing a differential output signal;

a self-biased voltage clamping circuit coupled to limit a peak-to-peak voltage swing of the differential output signal; and

a current source coupled to the differential amplifier, the current source varying a bias current through the current source in accordance with a delay bias voltage.

22. The ring oscillator ofclaim 21, wherein the differential amplifier provides a first output signal at a first node and a second output signal at a second node, the first and second output signal forming the differential output signal, wherein the voltage clamping circuit further comprises:

(i) a first diode-coupled transistor; and

(ii) a second diode-coupled transistor, wherein the first and second diode-coupled transistors are cross-coupled between the first and second nodes.

23. A ring oscillator comprising:

a plurality of ring coupled delay stages, each delay stage comprising:

a differential amplifier providing a differential output signal comprising a first output signal at a first node and a second output signal at a second node;

a voltage clamping circuit coupled to the first and second nodes to limit a peak-to-peak voltage swing of the differential output signal without independently clamping each of the first and second nodes; and

a current source coupled to the differential amplifier, the current source varying a bias current through the current source in accordance with a delay bias voltage.

24. The ring oscillator ofclaim 23, wherein the voltage clamping circuit further comprises:

(i) a first diode-coupled transistor; and

(ii) a second diode-coupled transistor, wherein the first and second diode-coupled transistors are cross-coupled between the first and second nodes.

25. A synchronous memory device comprising:

an array of memory cells to store data;

a clock synchronization loop to generate a plurality of clock signals, each clock signal having a timing relationship with respect to a reference clock signal;

first interpolator circuitry to generate a first internal clock signal from a first and a second clock signal of the plurality of clock signals, wherein a phase of the first internal clock signal is interpolated from respective phases of the first and second clock signals according to phase information indicative of whether the first internal clock signal leads or lags a first external clock signal; and

interface circuitry to synchronize a transmission of data with the first internal clock signal.

26. The memory device ofclaim 25 wherein the clock synchronization loop is a phase locked loop circuit.

27. The memory device ofclaim 25 wherein the timing relationship of each one of the plurality of clock signals is a respective phase offset from a phase of the reference clock signal.

28. The memory device ofclaim 25 wherein the clock synchronization loop comprises a plurality of delay elements coupled in series, each delay element outputting at least one of the plurality of clock signals.

29. The memory device ofclaim 28 wherein the plurality of delay elements in an even number of delay elements.

30. The memory device ofclaim 25 further comprising selection circuitry, coupled to the clock synchronization loop, to select the first and second clock signals from the plurality of clock signals.

31. The memory device ofclaim 30 further comprising:

a detector circuit to detect a phase polarity between the first internal clock signal and the first external clock signal;

a shift register, coupled in parallel with the selection circuitry, to output selection signals that control selection of the first and second clock signals; and

a control circuit to provide shift information to the shift register based on the phase polarity such that the selection signals output by the shift register select clock signals of the plurality of clock signals that have phases neighboring, on respective either sides, the phase of the first external clock signal.

32. The memory device ofclaim 25, further comprising:

a detector circuit, coupled to the first interpolator circuitry, to detect the phase information; and

a control circuit to generate a control voltage that is responsive to the phase information, wherein the first interpolator circuitry steers the phase of the first internal clock signal between the phase of the first and second clock signals in response to the control voltage.

33. The memory device ofclaim 32 wherein after detection the phase information is represented by a binary value.

34. The memory device ofclaim 32 wherein the control circuit comprises:

a digital counter to generate a digital count value in response to the phase information; and

a digital to analog converter to generate the control voltage from the digital count value.

35. The memory device ofclaim 25 further comprising a buffer circuit to receive a second external clock signal and generate the reference clock signal using the second external clock signal.

36. The memory device ofclaim 35 wherein a reception of data is synchronized with the second external clock signal.

37. The memory device ofclaim 35 wherein the plurality of clock signals comprises a clock signal that is in phase with the second external clock signal.

38. The memory device ofclaim 25 further comprising second interpolator circuitry to generate a second internal clock signal from a pair of clock signals of the plurality of clock signals, wherein a phase of the second internal clock signal is interpolated from respective phases of the pair of clock signals according to phase information indicative of whether the second internal clock signal leads or lags a second external clock signal.

39. The memory device ofclaim 25 wherein the data is transmitted during a plurality of clock edge transitions of the first external clock signal.

40. An integrated circuit device comprising:

interface circuitry to receive first and second external clock signals; and

clock synchronization circuitry to synchronize a transmission of data with the first external clock signal and to synchronize a reception of data with the second external clock signal, the clock synchronization circuitry including:

a reference loop to receive a reference clock signal and generate a plurality of clock signals, each clock signal of the plurality of clock signals having a predetermined timing relationship with the reference clock signal;

a first subloop circuit, coupled to the reference loop, to synchronize the transmission of data with the first external clock signal using the plurality of clock signals; and

a second subloop circuit, coupled to the reference loop, to synchronize the reception of data with the second external clock signal using the plurality of clock signals.

41. The integrated circuit device ofclaim 40 wherein the first subloop circuit generates an internal transmit clock signal having a phase relationship with respect to the first external clock signal.

42. The integrated circuit device ofclaim 41 wherein the phase relationship is a quadrature relationship.

43. The integrated circuit device ofclaim 41 wherein the internal transmit clock is in phase with the first external clock signal.

44. The integrated circuit device ofclaim 40 wherein the first subloop circuit further comprises:

selection circuitry to select first and second clock signals of the plurality of clock signals;

interpolator circuitry to interpolate between the first and second clock signals, and to generate an internal transmit clock signal in response to a control signal, wherein the control signal steers the phase of the internal transmit clock signal between respective phases of the first and second clock signals; and

detector circuitry to detect phase information indicative of whether the internal transmit clock signal leads or lags the first external clock signal, and to generate the control signal using the phase information.

45. The integrated circuit device ofclaim 40 wherein the second subloop circuit generates an internal receive clock signal having a phase relationship with respect to the second external clock signal.

46. The integrated circuit device ofclaim 45 wherein the internal receive clock signal is in phase with the second external clock signal.

47. The integrated circuit device ofclaim 40 wherein the second subloop circuit further comprises:

selection circuitry to select first and second clock signals of the plurality of clock signals;

interpolator circuitry to interpolate between the first and second clock signals, and to generate an internal receive clock signal in response to a control signal, wherein the control signal steers the phase of the internal receive clock signal between respective phases of the first and second clock signals; and

detector circuitry to detect phase information indicative of whether the internal receive clock signal leads or lags the second external clock signal, and to generate the control signal using the phase information.

48. The integrated circuit device ofclaim 40 wherein a first clock signal of the plurality of clock signals is in phase with the second external clock signal, and the other clock signals of the plurality of clock signals have respective phases that are evenly spaced across a clock period of the second external clock signal.

49. The integrated circuit device ofclaim 40 wherein the reference loop is a phase locked loop circuit.

50. The integrated circuit device ofclaim 40 wherein the data is transmitted during a plurality of clock edge transitions of the first external clock signal.

51. The integrated circuit device ofclaim 40 further comprising a buffer circuit to receive the second external clock signal and to generate the reference clock signal from the second external clock signal.

52. A clock synchronization circuit comprising:

a plurality of delay stages coupled in series to output a plurality of clock signals, each delay stage having a delay time with respect to a reference clock signal;

interpolator circuitry to generate a first clock signal using a pair of clock signals of the plurality of clock signals, wherein a phase of the first clock signal is interpolated between respective phases of each clock signal of the pair of clock signals in accordance with information indicative of whether a phase of the first clock signal leads or lags a phase of an input clock signal; and

a detector circuit to compare the phase of the first clock signal with the phase of the input clock signal, to generate the information indicative of whether the phase of the first clock signal leads or lags the phase of the input clock signal.

53. The clock synchronization circuit ofclaim 52 wherein the plurality of delay stages is an even number of delay stages.

54. The clock synchronization circuit ofclaim 52 further comprising a buffer to output the reference clock signal, wherein the buffer receives the input clock signal.

55. The clock synchronization circuit ofclaim 52 wherein each delay stage of the plurality of delay stages comprises:

a first output terminal;

a second output terminal;

a first transistor having a source, a drain, and a gate, the source and gate being coupled to the first output terminal, and the drain being coupled to the second output terminal; and

a second transistor having a source, a drain, and a gate, the source and gate being coupled to the second output terminal, and the drain being coupled to the first output terminal.

56. The clock synchronization circuit ofclaim 52 wherein the plurality of delay stages is included in a phase locked loop circuit.

57. The clock synchronization circuit ofclaim 52 further comprising selection circuitry to select the pair of clock signals from the plurality of clock signals.

58. The clock synchronization circuit ofclaim 52 wherein the detector circuit comprises a phase detector to compare the phase of the first clock signal with the phase of the input clock signal, the phase detector to generate a binary signal that indicates whether the first clock signal leads or lags the input clock signal.

59. The clock synchronization circuit ofclaim 52 wherein the detector circuit comprises:

a counter circuit to change a count value in a first direction when the phase of the input clock signal lags the phase of the first clock signal, and change the count value in a second direction when the phase of the input clock signal leads the phase of the first clock signal; and

a digital to analog converter circuit to generate an analog control signal from the count value, wherein the analog control signal steers the phase of the first clock signal between the respective phases of each clock signal of the pair of clock signals.

60. A synchronous memory device comprising:

an array of memory cells to store data;

clock synchronization circuitry including:

a plurality of delay stages coupled in series;

a first multiplexer circuit, coupled to the plurality of delay stages, to perform selection of a delay time for a first internal clock signal, the selection being controlled by a first plurality of control signals;

a first shift register circuit to generate the first plurality of control signals in accordance with information indicative of whether a phase of an external clock signal leads or lags a phase of an internal transmit clock signal; and

a detector circuit to compare the phase of the external clock signal with the phase of the internal transmit clock signal and generate the information; and

interface circuitry to output data from the memory device, the data being output in synchronism with the internal transmit clock signal, the internal transmit clock signal being generated using the first internal clock signal.

61. The memory device ofclaim 60 further comprising:

a second multiplexer circuit, coupled to the plurality of delay stages, to perform selection of a delay time for a second internal clock signal, the selection being controlled by a second plurality of control signals; and

a second shift register circuit to generate the second plurality of control signals in accordance with the information indicative of whether the phase of the external clock signal leads or lags the phase of the internal transmit clock signal.

62. The memory device ofclaim 61 further comprising:

interpolator circuitry to generate the internal transmit clock signal by interpolating between phases of the first and a second internal clock signals in accordance with a control voltage; and

a control circuit to generate the control voltage according to the information indicative of whether the phase of the external clock signal leads or lags the phase of the internal transmit clock signal.

63. The memory device ofclaim 62 wherein the control circuit comprises:

a counter circuit to generate a digital count value based on the information; and

a digital to analog converter to generate the control voltage based on the digital count value.

64. The memory device ofclaim 60, wherein the first internal clock signal is generated by an output of a delay stage of the plurality of delay stages.

65. The memory device ofclaim 60 wherein the plurality of delay stages is included in a phase locked loop circuit.

66. A synchronous memory device comprising:

an array of memory cells to store data;

a plurality of delay elements coupled in series, each delay element generating a respective output signal having a different phase;

a detector circuit to compare a phase of an external clock signal with a phase of an internal transmit clock signal, the detector circuit to generate information indicative of whether the phase of the external clock signal leads or lags the phase of the internal transmit clock signal;

a multiplexer circuit, coupled to the plurality of delay elements, to select a first output signal generated by the plurality of delay elements in response to the information; and

an interface circuit to output data from the memory device, the data being output in synchronism with the internal transmit clock signal, the internal transmit clock signal being generated using at least the first output signal selected by the multiplexer circuit.

67. The memory device ofclaim 66 further comprising a shift register coupled to the multiplexer circuit to control selection of the first output signal.

68. The memory device ofclaim 66 further comprising:

a control circuit to generate a control voltage that is responsive to the information; and

interpolator circuitry to generate the internal transmit clock signal using the first output signal and a second output signal generated by the plurality of delay elements, the phase of the internal transmit clock signal being interpolated between the phases of the first and second output signals in response to the control voltage.

69. The memory device ofclaim 68 wherein the control circuit comprises:

a digital converter to generate a digital count value in response to the information; and

a digital to analog converter to generate the control voltage using the digital count value.

70. The memory device ofclaim 66 wherein the plurality of delay elements is included in a phase locked loop circuit.

71. A clock synchronization circuit comprising:

a plurality of delay stages coupled in series to output a plurality of clock signals, each delay stage having a respective delay time with respect to a reference clock signal; and

interpolator circuitry coupled to the plurality of delay stages, the interpolator circuitry to generate a first clock signal using a pair of clock signals of the plurality of clock signals, wherein a phase of the first clock signal is interpolated between respective phases of each clock signal of the pair of clock signals in accordance with information indicative of whether the phase of the first clock signal leads or lags a target phase, wherein the target phase is based on transitions in an input signal.

72. The clock synchronization circuit ofclaim 71 further comprising detector circuitry coupled to the interpolator circuitry, the detector circuitry to compare the phase of the first clock signal with the target phase, the detector circuitry to generate the information indicative of whether the phase of the first clock signal leads or lags the target phase.

73. The clock synchronization circuit ofclaim 72 wherein the detector circuitry comprises a counter circuit to change a count value in a first direction when the target phase lags the phase of the first clock signal, and change the count value in a second direction when the target phase leads the phase of the first clock signal, wherein the information indicative of whether the phase of the first clock signal leads or lags the target phase is based on the count value.

74. The clock synchronization circuit ofclaim 73 wherein the information indicative of whether the phase of the first clock signal leads or lags the target phase is provided as an analog control signal, and wherein the detector circuitry further comprises a digital to analog converter circuit coupled to the counter circuit, the digital to analog converter circuit to generate the analog control signal from the count value, wherein the analog control signal controls interpolation between the respective phases of the clock signals of the pair of clock signals to produce the phase of the first clock signal.

75. The clock synchronization circuit ofclaim 71 wherein the target phase is detected based on sampling of the input signal.

76. The clock synchronization circuit ofclaim 75 wherein the input signal is sampled using the first clock signal.

77. The clock synchronization circuit ofclaim 76 wherein the input signal is a clock signal.

78. The clock synchronization circuit ofclaim 71 wherein the input signal includes clock information.

79. The clock synchronization circuit ofclaim 78 wherein the input signal is a clock signal.

80. The clock synchronization circuit ofclaim 79 wherein the input signal and the reference clock signal are both derived from an external clock signal.

81. The clock synchronization circuit ofclaim 80 wherein the input signal is the reference clock signal.

82. The clock synchronization circuit ofclaim 71 wherein the plurality of delay stages is an even number of delay stages.

83. The clock synchronization circuit ofclaim 71 wherein the plurality of delay stages and the interpolator circuitry are formed on a single integrated circuit device.

84. The clock synchronization circuit ofclaim 83 further comprising a buffer coupled to the interpolator circuitry, the buffer to receive the input signal from external to the integrated circuit device.

85. The clock synchronization circuit ofclaim 83 further comprising a buffer coupled to the plurality of delay stages, the buffer to receive the reference clock signal from external to the integrated circuit device.

86. The clock synchronization circuit ofclaim 71 wherein each delay stage of the plurality of delay stages comprises:

a first output terminal;

a second output terminal;

a first transistor having a source, a drain, and a gate, the source and gate being coupled to the first output terminal, and the drain being coupled to the second output terminal; and

a second transistor having a source, a drain, and a gate, the source and gate being coupled to the second output terminal, and the drain being coupled to the first output terminal.

87. The clock synchronization circuit ofclaim 71 wherein the plurality of delay stages is included in a phase locked loop circuit.

88. The clock synchronization circuit ofclaim 71 further comprising selection circuitry coupled to the interpolator circuitry, the selection circuitry to select the pair of clock signals from the plurality of clock signals.

89. The clock synchronization circuit ofclaim 71 further comprising a phase detector to compare the phase of the first clock signal with the target phase, and to generate the information indicative of whether the phase of the first clock signal leads or lags the target phase, wherein the information is represented by a binary signal.

90. The clock synchronization circuit ofclaim 71 wherein each delay stage of the plurality of delay stages generates complementary outputs, wherein each output of the complementary outputs is one of the plurality of clock signals.

91. A method for clock synchronization, comprising:

generating a plurality of clock signals from a reference clock signal, wherein each clock signal of the plurality of clock signals is delayed from the reference clock signal by a corresponding delay time such that a plurality of different delays with respect to the reference clock signal are represented in the plurality of clock signals;

detecting phase of an input signal, wherein the phase of the input signal represents a target phase; and

generating a first clock signal based on a pair of clock signals of the plurality of clock signals, wherein generating the first clock signal includes interpolation between the pair of clock signals using information indicative of whether the phase of the first clock signal leads or lags the target phase.

92. The method ofclaim 91 wherein detecting phase of the input signal further comprises sampling the input signal.

93. The method ofclaim 92 wherein sampling the input signal further comprises sampling the input signal based on the first clock signal.

94. The method ofclaim 93 wherein the input signal is a clock signal.

95. The method ofclaim 94 wherein the input signal and the reference clock signal are generated from an external clock signal.

96. The method ofclaim 92 further comprises selecting the pair of clock signals from the plurality of clock signals based on the sampling of the input signal.

97. The method ofclaim 91 wherein generating the plurality of clock signals further comprises generating the plurality of clock signals using a plurality of delay stages coupled in series, wherein each delay stage of the plurality of delay stages generates complementary outputs, wherein each output of the complementary outputs is one of the plurality of clock signals.

98. The method ofclaim 91 wherein the input signal includes clock information.

99. The method ofclaim 98 wherein the input signal is a clock signal.

100. An integrated circuit comprising:

a plurality of delay stages coupled in series to output a plurality of clock signals, each delay stage of the plurality of delay stages having a delay time with respect to a reference clock signal;

a phase detector to determine the phase of an input signal by sampling the input signal, wherein the phase of the input signal is based on at least one transition in the input signal, the phase detector to generate information indicative of whether a phase of a first clock signal leads or lags the phase of the input signal; and

interpolator circuitry coupled to the plurality of delay stages and the phase detector, the interpolator circuitry to generate the first clock signal using a pair of clock signals of the plurality of clock signals, wherein the phase of the first clock signal is interpolated between respective phases of the pair of clock signals in accordance with the information indicative of whether the phase of the first clock signal leads or lags the phase of the input signal.

101. The integrated circuit ofclaim 100 wherein the phase detector samples the input signal using the first clock signal.

102. The integrated circuit ofclaim 100 wherein the input signal includes clock information.

103. The integrated circuit ofclaim 102 wherein the input signal is a clock signal.

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