USRE37982E1 - Method for preventing electrostatic discharge failure in an integrated circuit package - Google Patents
Method for preventing electrostatic discharge failure in an integrated circuit packageDownload PDFInfo
- Publication number
- USRE37982E1 USRE37982E1US09/498,126US49812600AUSRE37982EUS RE37982 E1USRE37982 E1US RE37982E1US 49812600 AUS49812600 AUS 49812600AUS RE37982 EUSRE37982 EUS RE37982E
- Authority
- US
- United States
- Prior art keywords
- power source
- bonding pads
- electrically
- protection device
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034methodMethods0.000titleclaimsdescription33
- 239000004065semiconductorSubstances0.000claimsabstractdescription28
- 239000002184metalSubstances0.000claimsabstractdescription11
- 239000003990capacitorSubstances0.000claimsdescription12
- 239000000758substrateSubstances0.000claimsdescription12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-NSiliconChemical compound[Si]XUIMIQQOPSSXEZ-UHFFFAOYSA-N0.000claimsdescription4
- 229910052710siliconInorganic materials0.000claimsdescription4
- 239000010703siliconSubstances0.000claimsdescription4
- 238000007599dischargingMethods0.000claimsdescription3
- 230000005669field effectEffects0.000claimsdescription3
- 230000008878couplingEffects0.000claims4
- 238000010168coupling processMethods0.000claims4
- 238000005859coupling reactionMethods0.000claims4
- 238000010586diagramMethods0.000description6
- 230000006378damageEffects0.000description3
- CFMYXEVWODSLAX-QOZOJKKESA-NtetrodotoxinChemical compoundO([C@@]([C@H]1O)(O)O[C@H]2[C@@]3(O)CO)[C@H]3[C@@H](O)[C@]11[C@H]2[C@@H](O)N=C(N)N1CFMYXEVWODSLAX-QOZOJKKESA-N0.000description3
- 238000005516engineering processMethods0.000description1
- 238000012986modificationMethods0.000description1
- 230000004048modificationEffects0.000description1
Images
Classifications
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
- H01L2924/13034—Silicon Controlled Rectifier [SCR]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Definitions
- This inventionrelates to an integrated circuit, more particularly to a method for preventing electrostatic discharge failure in an integrated circuit package.
- VLSI circuit packagesmake rapid progress to high pin counts and narrow pin pitch with increasing input/output signals by the trend of higher integrated function.
- ESDelectrostatic discharge
- the possibility of suffer from electrostatic discharge (ESD) failurewhich is due to electrostatic discharge stressing of the non-wired pin of the integrated circuit package, is increasing. Therefore, the ESD is considered a major reliability threat to integrated circuit technologies.
- little attentionhas been paid to the destruction mechanism of non-wired pin so far.
- the main objective of the present inventionis to provide a method of preventing electrostatic discharge failure in an integrated circuit package.
- a methodfor preventing electrostatic discharge failure in an integrated circuit package.
- the integrated circuit packageincludes a semiconductor chip, bonding pads on the semiconductor chip, a metal lead frame contacting electrically with the semiconductor chip, a plurality of wired pins wire-bonded respectively to the bonding pads, and at least one non-wired pin.
- the electrostatic discharge failureis due to electrostatic discharge stressing of the non-wired pin.
- the methodcomprises the step of wire-bonding the non-wired pin to the metal lead frame.
- FIG. 1is a schematic plan view illustrating the connection between a metal lead frame and a non-wired pin of an integrated circuit package in accordance with the present invention
- FIG. 2is a schematic circuit diagram illustrating one type of power-supply electrostatic discharge protected device connected to the non-wired pin of the integrated circuit package which has a semiconductor chip having an N-substrate;
- FIG. 3is a schematic circuit diagram illustrating another type of power-supply electrostatic discharge protection device connected to the non-wired pin of the integrated circuit package of FIG. 2;
- FIG. 4is a schematic circuit diagram illustrating another type of power-supply electrostatic discharge protection device connected to the non-wire pin of the integrated circuit package of FIG. 2;
- FIG. 5is a schematic circuit diagram illustrating another type of power-supply electrostatic discharge protection device connected to the non-wired pin of the integrated circuit package of FIG. 2;
- FIG. 6is a schematic circuit diagram illustrating another type of power-supply electrostatic discharge protection device connected to the non-wired pin of the integrated circuit package of FIG. 2;
- FIG. 7is a schematic circuit diagram similar to FIG. 2, the integrated circuit package having a semiconductor chip which has a P-substrate.
- FIG. 1shows an integrated circuit package 1 which includes a semiconductor chip 10 , bonding pads 11 on the semiconductor chip 10 , a metal lead frame 12 contacting electrically with the semiconductor chip 10 , a plurality of wired pins (WP) wire-bonded respectively to the bonding pads 11 , and at least one non-wired pin (NW).
- WPwired pins
- NWnon-wired pin
- the non-wired pinis wire-bonded to the metal lead frame 12 .
- the metal lead frame 12is connected electrically to one of the bonding pads 11 which is adapted to be connected electrically to a first power source via the semiconductor chip 10 .
- the semiconductor chip 10has an N-substrate with an inherent resistance of about 5 ⁇ , and the first power source is a positive power source.
- a power-supply electrostatic-discharge protection device 2is connected electrically to said one of the bonding pads 11 for discharging of current that results from electrostatic discharge stressing of the non-wired pin.
- the protection device 2includes a field effect transistor (T) which has a drain connected electrically to said one of the bonding pads 11 , a source adapted to be connected electrically to a second power source and a gate connected electrically to the source thereof.
- the second power sourceis grounded. Since the current that results from electrostatic discharge stressing of the non-wired pin (NW) is discharged through the protection device 2 , destruction of the adjacent wired pin (WP) that is adjacent to the non-wired pin (NW) and this caused by the ESD stressing to the non-wired pin (NW) is thus prevented.
- FIG. 3shows the relationship between another type of power-supply electrostatic discharge protection device ( 2 A) and the non-wired pin (NW′) of the integrated circuit package.
- the power-supply electrostatic discharge protection device ( 2 A) of FIG. 3include a capacitor (C) which may be a build-in capacitor or an externally-connected capacitor.
- the capacitor (C)has a first terminal connected electrically to one of the bonding pads ( 11 A) that is adapted to be connected electrically to a first power source, and a second terminal adapted to be connected electrically to a second power source.
- the first power sourceis a positive power source, while the second power source is grounded. It should be appreciated that the capacitance of the capacitor (C) should be relatively large.
- FIG. 4shows the relationship between another type of power-supply electrostatic discharge protection device ( 2 B) and the non-wired pin (NW′′) of the integrated circuit package.
- the power-supply electrostatic discharge protection device ( 2 B) of FIG. 4includes a diode (D) which has a cathode connected electrically to one of the bonding pads ( 11 B) that is adapted to be connected electrically to a first power source, and an anode adapted to be connected electrically to a second power source.
- the first power sourceis a positive power source, while the second power source is grounded.
- FIG. 5shows the relationship between another type of power-supply electrostatic discharge protection device ( 2 C) and the non-wired pin (NW′′′) of the integrated circuit package.
- the power-supply electrostatic discharge protection device ( 2 C) of FIG. 5includes a silicon-controlled-rectifier.
- the silicon-controlled-rectifierincludes a first transistor (BJT 1 ) having an emitter connected electrically to one of the bonding pads ( 11 C) that is adapted to be connected electrically to a first power source, a base adapted to be connected electrically to said one of the bonding pads ( 11 C) via a first resistor (R 1 ), and a collector adapted to be connected electrically to a second power source via a second resistor (R 2 ), and a second transistor (BJT 2 ) having a collector connected electrically to the base of the first transistor (BJT 1 ), a base connected electrically to the collector of the first transistor (BJT 1 ), and an emitter adapted to be connected electrically to the second power source.
- the first power sourceis a positive power source
- the second power sourceis granulated.
- FIG. 6shows the relationship between another type of power-supply electrostatic discharge protection device ( 2 D) and the non-wired pin (NW′′′′) of the integrated circuit package.
- the power-supply electrostatic discharge protection device ( 2 D) of FIG. 6includes a field device (FD) which has a drain connected electrically to one of the bonding pads ( 11 D) that is adapted to be connected electrically to a first power source, a source adapted to be connected electrically to a second power source, and a gate connected electrically to the drain thereof.
- the first power sourceis a positive power source
- the second power sourceis grounded.
- the metal lead frame ( 12 E)is connected electrically to one of the bonding pads ( 11 E) which is adapted to be connected electrically to a first power source via the semiconductor chip ( 10 E).
- the semiconductor chip ( 10 E)has a P-substrate with an inherent resistance of about 5 ⁇ , and the first power source is grounded.
- a power-supply electrostatic-discharge protection device ( 2 E)is connected electrically to said one of the bonding pads ( 11 E) for discharging of current that results from electrostatic discharge stressing of the non-wired pin.
- the protection device ( 2 E)includes a field effect transistor (TE) which has a drain connected electrically to said one of the bonding pads ( 11 E), a source adapted to be connected electrically to a second power source and a gate connected electrically to the drain thereof.
- the second power sourceis a positive power source. Since the current that results from electrostatic discharge stressing of the non-wired pin (NW′′′′′) is discharged through the protection device ( 2 E), destruction of the adjacent wired pin (not shown) that is adjacent to the non-wired pin (NW′′′′′) and that is caused by the ESD stressing to the non-wired pin (NW′′′′′) is thus prevented.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
U.S. Ser. No. 08/643,355, entitled “Method for Preventing Electrostatic Discharge Failure in an Integrated Circuit Package” filed May 6, 1996.
1. Field of the Invention
This invention relates to an integrated circuit, more particularly to a method for preventing electrostatic discharge failure in an integrated circuit package.
2. Description of the Related Art
The trend of very large-scale integrated (VLSI) circuit packages is toward smaller dimension and higher density. Also, VLSI circuit packages make rapid progress to high pin counts and narrow pin pitch with increasing input/output signals by the trend of higher integrated function. With the increasing of pin count, the possibility of suffer from electrostatic discharge (ESD) failure, which is due to electrostatic discharge stressing of the non-wired pin of the integrated circuit package, is increasing. Therefore, the ESD is considered a major reliability threat to integrated circuit technologies. However, little attention has been paid to the destruction mechanism of non-wired pin so far. Thus, there is a need to provide a method which can prevent electrostatic discharge failure in an integrated circuit package.
The main objective of the present invention is to provide a method of preventing electrostatic discharge failure in an integrated circuit package.
According to the present invention, a method is provided for preventing electrostatic discharge failure in an integrated circuit package. The integrated circuit package includes a semiconductor chip, bonding pads on the semiconductor chip, a metal lead frame contacting electrically with the semiconductor chip, a plurality of wired pins wire-bonded respectively to the bonding pads, and at least one non-wired pin. The electrostatic discharge failure is due to electrostatic discharge stressing of the non-wired pin. The method comprises the step of wire-bonding the non-wired pin to the metal lead frame.
Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiments, with reference to the accompanying drawings, of which:
FIG. 1 is a schematic plan view illustrating the connection between a metal lead frame and a non-wired pin of an integrated circuit package in accordance with the present invention;
FIG. 2 is a schematic circuit diagram illustrating one type of power-supply electrostatic discharge protected device connected to the non-wired pin of the integrated circuit package which has a semiconductor chip having an N-substrate;
FIG. 3 is a schematic circuit diagram illustrating another type of power-supply electrostatic discharge protection device connected to the non-wired pin of the integrated circuit package of FIG. 2;
FIG. 4 is a schematic circuit diagram illustrating another type of power-supply electrostatic discharge protection device connected to the non-wire pin of the integrated circuit package of FIG. 2;
FIG. 5 is a schematic circuit diagram illustrating another type of power-supply electrostatic discharge protection device connected to the non-wired pin of the integrated circuit package of FIG. 2;
FIG. 6 is a schematic circuit diagram illustrating another type of power-supply electrostatic discharge protection device connected to the non-wired pin of the integrated circuit package of FIG. 2; and
FIG. 7 is a schematic circuit diagram similar to FIG. 2, the integrated circuit package having a semiconductor chip which has a P-substrate.
FIG. 1 shows an integrated circuit package1 which includes asemiconductor chip 10,bonding pads 11 on thesemiconductor chip 10, ametal lead frame 12 contacting electrically with thesemiconductor chip 10, a plurality of wired pins (WP) wire-bonded respectively to thebonding pads 11, and at least one non-wired pin (NW).
In the method of the present invention, the non-wired pin (NW) is wire-bonded to themetal lead frame 12. As best shown in FIG. 2, themetal lead frame 12 is connected electrically to one of thebonding pads 11 which is adapted to be connected electrically to a first power source via thesemiconductor chip 10. It should be noted that, in the present embodiment, thesemiconductor chip 10 has an N-substrate with an inherent resistance of about 5Ω, and the first power source is a positive power source. A power-supply electrostatic-discharge protection device 2 is connected electrically to said one of thebonding pads 11 for discharging of current that results from electrostatic discharge stressing of the non-wired pin. Theprotection device 2 includes a field effect transistor (T) which has a drain connected electrically to said one of thebonding pads 11, a source adapted to be connected electrically to a second power source and a gate connected electrically to the source thereof. In the present embodiment, the second power source is grounded. Since the current that results from electrostatic discharge stressing of the non-wired pin (NW) is discharged through theprotection device 2, destruction of the adjacent wired pin (WP) that is adjacent to the non-wired pin (NW) and this caused by the ESD stressing to the non-wired pin (NW) is thus prevented.
FIG. 3 shows the relationship between another type of power-supply electrostatic discharge protection device (2A) and the non-wired pin (NW′) of the integrated circuit package. The power-supply electrostatic discharge protection device (2A) of FIG. 3 include a capacitor (C) which may be a build-in capacitor or an externally-connected capacitor. The capacitor (C) has a first terminal connected electrically to one of the bonding pads (11A) that is adapted to be connected electrically to a first power source, and a second terminal adapted to be connected electrically to a second power source. In the present embodiment, the first power source is a positive power source, while the second power source is grounded. It should be appreciated that the capacitance of the capacitor (C) should be relatively large.
FIG. 4 shows the relationship between another type of power-supply electrostatic discharge protection device (2B) and the non-wired pin (NW″) of the integrated circuit package. The power-supply electrostatic discharge protection device (2B) of FIG. 4 includes a diode (D) which has a cathode connected electrically to one of the bonding pads (11B) that is adapted to be connected electrically to a first power source, and an anode adapted to be connected electrically to a second power source. In the present embodiment, the first power source is a positive power source, while the second power source is grounded.
FIG. 5 shows the relationship between another type of power-supply electrostatic discharge protection device (2C) and the non-wired pin (NW′″) of the integrated circuit package. The power-supply electrostatic discharge protection device (2C) of FIG. 5 includes a silicon-controlled-rectifier. The silicon-controlled-rectifier includes a first transistor (BJT1) having an emitter connected electrically to one of the bonding pads (11C) that is adapted to be connected electrically to a first power source, a base adapted to be connected electrically to said one of the bonding pads (11C) via a first resistor (R1), and a collector adapted to be connected electrically to a second power source via a second resistor (R2), and a second transistor (BJT2) having a collector connected electrically to the base of the first transistor (BJT1), a base connected electrically to the collector of the first transistor (BJT1), and an emitter adapted to be connected electrically to the second power source. In the present embodiment, the first power source is a positive power source, while the second power source is granulated.
FIG. 6 shows the relationship between another type of power-supply electrostatic discharge protection device (2D) and the non-wired pin (NW″″) of the integrated circuit package. The power-supply electrostatic discharge protection device (2D) of FIG. 6 includes a field device (FD) which has a drain connected electrically to one of the bonding pads (11D) that is adapted to be connected electrically to a first power source, a source adapted to be connected electrically to a second power source, and a gate connected electrically to the drain thereof. In the present embodiment, the first power source is a positive power source, while the second power source is grounded.
Referring now to FIG. 7, the metal lead frame (12E) is connected electrically to one of the bonding pads (11E) which is adapted to be connected electrically to a first power source via the semiconductor chip (10E). It should be noted that, in the present embodiment, the semiconductor chip (10E) has a P-substrate with an inherent resistance of about 5Ω, and the first power source is grounded. A power-supply electrostatic-discharge protection device (2E) is connected electrically to said one of the bonding pads (11E) for discharging of current that results from electrostatic discharge stressing of the non-wired pin. The protection device (2E) includes a field effect transistor (TE) which has a drain connected electrically to said one of the bonding pads (11E), a source adapted to be connected electrically to a second power source and a gate connected electrically to the drain thereof. In the present embodiment, the second power source is a positive power source. Since the current that results from electrostatic discharge stressing of the non-wired pin (NW′″″) is discharged through the protection device (2E), destruction of the adjacent wired pin (not shown) that is adjacent to the non-wired pin (NW′″″) and that is caused by the ESD stressing to the non-wired pin (NW′″″) is thus prevented.
While the present invention has been described in connection with what is considered the most practical and preferred embodiments, it is understood that this invention is not limited to the disclosed embodiments, but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.
Claims (31)
1. A method for preventing electrostatic discharge failure in an integrated circuit package which includes a semiconductor chip, bonding pads on the semiconductor chip, a metal lead frame contacting electrically with the semiconductor chip, a plurality of wired pins wire-bonded respectively to the bonding pads, and at least one non-wired pin, the electrostatic discharge failure being due to electrostatic discharge stressing of the non-wired pin, said method comprising the step of:
wire-bonding the non-wired pin to the metal lead frame.
2. A method as claimed inclaim 1 , further comprising the step of connecting electrically a power-supply electrostatic-discharge protection device to the lead frame through the semiconductor chip for discharging of current that results from electrostatic discharge stressing of the non-wired pin.
3. A method as claimed inclaim 1 , further comprising the step of connecting electrically a power-supply electrostatic-discharge protection device to one of the bonding pads that is for connecting electrically to a first power source, said protection device including a field effect transistor which has a drain connected electrically to said one of the bonding pads, a source for connecting electrically to a second power source and a gate connected electrically to said source thereof.
4. A method as claimed inclaim 3 , wherein said first power source is a positive power source, while said second power source is grounded.
5. A method as claimed inclaim 1 , further comprising the step of connecting electrically a power-supply electrostatic-discharge protection device to one of the bonding pads that is for connecting electrically to a first power source, said protection device including a capacitor which has a first terminal connected electrically to said one of the bonding pads, and a second terminal for connecting electrically to a second power source.
6. A method as claimed inclaim 5 , wherein said first power source is a positive power source, while said second power source is grounded.
7. A method as claimed inclaim 1 , further comprising the step of connecting electrically a power-supply electrostatic-discharge protection device to one of the bonding pads that is for connecting electrically to a first power source, said protection device including a diode which has a cathode connected electrically to said one of the bonding pads, and anode for connecting electrically to a second power source.
8. A method as claimed inclaim 7 , wherein said first power source is a positive power source, while said second power source is grounded.
9. A method as claimed inclaim 1 , further comprising the step of connecting electrically a power-supply electrostatic-discharge protection device to one of the bonding pads that is for connecting electrically to a first power source, said protection device including a first transistor having an emitter connected electrically to said one of the bonding pads via a first resistor, and a collector for connecting electrically to a second power source via a second resistor, and a second transistor having a collector connected electrically to the base of the first transistor, a base connected electrically to the collector of the first transistor, and an emitter for connecting electrically to the second power source.
10. A method as claimed inclaim 9 , wherein said first power source is a positive power source, while said second power source is grounded.
11. A method as claimed inclaim 1 , further comprising the step of connecting electrically a power-supply electrostatic-discharge protection device to one of the bonding pads that is for connecting electrically to a first power source, said protection device including a field device which has a drain connected electrically to said one of the bonding pads, a source for connecting electrically to a second power source, and a gate connected electrically to the drain thereof.
12. A method as claimed inclaim 11 , wherein said first power source is a positive power source, while said second power source is grounded.
13. A method as claimed inclaim 11 , wherein said first power source is grounded, while said second power source is a positive power source.
14. A method for preventing electrostatic discharge failure in an integrated circuit package which includes a semiconductor chip with a substrate, a plurality of bonding pads on the semiconductor chip, a plurality of wired pins wire-bonded to the bonding pads, and at least one non-wired pin, the electrostatic discharge failure being due to electrostatic discharge stressing of the non-wired pin, said method comprising the step of:
providing an electrical coupling between the non-wired pin and the substrate of the semiconductor chip.
15. A method as claimed inclaim 14 , further comprising the steps of:
coupling electrically a first power source node to the substrate; and
coupling electrically an electrostatic-discharge protection device between the first power source node and a second power source node.
16. A method as claimed inclaim 15 , wherein the protection device includes a capacitor coupled between the first and second power source nodes.
17. A method as claimed inclaim 16 , wherein the capacitor is a built-in capacitor.
18. A method as claimed inclaim 15 , wherein one of the first and second power source nodes is a positive power source node, and the other one of the first and second power source nodes is a ground node.
19. A method as claimed inclaim 15 , wherein the protection device includes at least an element selected from the group of a diode, a transistor, a field device and a silicon-controlled-rectifier.
20. A method as claimed inclaim 15 , further comprising the step of coupling electrically the protection device to one of the bonding pads.
21. A method as claimed inclaim 14 , wherein the substrate is either one of an N-type substrate and a P-type substrate.
22. A method for preventing electrostatic discharge failure in an integrated circuit package which includes a semiconductor chip, bonding pads on the semiconductor chip, a lead frame for holding the semiconductor chip, a plurality of wired pins wire-bonded to the bonding pads, and at least one non-wired pin, said method comprising the step of:
wire-bonding the non-wired pin into the lead frame.
23. An integrated circuit package protected against electrostatic discharge failure, said integrated circuit package comprising a semiconductor chip, a plurality of bonding pads on said semiconductor chip, a plurality of wired pins wire-bonded to said bonding pads, and at least one non-wired pin coupled electrically to a first power-source node.
24. An integrated circuit package as claimed inclaim 23 , further comprising an electrostatic-discharge protection device coupled between said first power source node and a second power source node.
25. An integrated circuit package as claimed inclaim 23 , wherein said semiconductor chip has a substrate, and said first power source node is coupled electrically to said substrate.
26. An integrated circuit package as claimed inclaim 23 , wherein said first power source node is coupled electrically to one of said bonding pads.
27. An integrated circuit package as claimed inclaim 24 , wherein said protection device includes a capacitor.
28. An integrated circuit package as claimed inclaim 27 , wherein said capacitor is a built-in capacitor.
29. An integrated circuit package as claimed inclaim 24 , wherein said protection device includes at least an element selected from the group of a diode, a transistor, a field device and a silicon-controlled-rectifier.
30. An integrated circuit package as claimed inclaim 23 , wherein said first power source node is a positive power-source node.
31. An integrated circuit package as claimed inclaim 23 , wherein said first power source node is a ground node.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/498,126USRE37982E1 (en) | 1996-05-06 | 2000-02-02 | Method for preventing electrostatic discharge failure in an integrated circuit package |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/642,194US5715127A (en) | 1996-05-06 | 1996-05-06 | Method for preventing electrostatic discharge failure in an integrated circuit package |
| US09/498,126USRE37982E1 (en) | 1996-05-06 | 2000-02-02 | Method for preventing electrostatic discharge failure in an integrated circuit package |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US08/642,194ReissueUS5715127A (en) | 1996-05-06 | 1996-05-06 | Method for preventing electrostatic discharge failure in an integrated circuit package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| USRE37982E1true USRE37982E1 (en) | 2003-02-11 |
Family
ID=24575585
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US08/642,194CeasedUS5715127A (en) | 1996-05-06 | 1996-05-06 | Method for preventing electrostatic discharge failure in an integrated circuit package |
| US09/498,126Expired - Fee RelatedUSRE37982E1 (en) | 1996-05-06 | 2000-02-02 | Method for preventing electrostatic discharge failure in an integrated circuit package |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US08/642,194CeasedUS5715127A (en) | 1996-05-06 | 1996-05-06 | Method for preventing electrostatic discharge failure in an integrated circuit package |
Country Status (1)
| Country | Link |
|---|---|
| US (2) | US5715127A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050248028A1 (en)* | 2004-05-05 | 2005-11-10 | Cheng-Yen Huang | Chip-packaging with bonding options connected to a package substrate |
| US20050285280A1 (en)* | 2004-06-25 | 2005-12-29 | Sin-Him Yau | Electrostatic discharge (ESD) protection for integrated circuit packages |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6172590B1 (en) | 1996-01-22 | 2001-01-09 | Surgx Corporation | Over-voltage protection device and method for making same |
| TW359023B (en)* | 1996-04-20 | 1999-05-21 | Winbond Electronics Corp | Device for improvement of static discharge protection in ICs |
| US6246122B1 (en) | 1996-07-09 | 2001-06-12 | Winbond Electronics Corp. | Electrostatic discharge protective schemes for integrated circuit packages |
| US6043539A (en)* | 1997-11-26 | 2000-03-28 | Lsi Logic Corporation | Electro-static discharge protection of CMOS integrated circuits |
| US6130459A (en) | 1998-03-10 | 2000-10-10 | Oryx Technology Corporation | Over-voltage protection device for integrated circuits |
| US6064094A (en)* | 1998-03-10 | 2000-05-16 | Oryx Technology Corporation | Over-voltage protection system for integrated circuits using the bonding pads and passivation layer |
| US6236086B1 (en) | 1998-04-20 | 2001-05-22 | Macronix International Co., Ltd. | ESD protection with buried diffusion |
| US6211565B1 (en) | 1999-04-29 | 2001-04-03 | Winbond Electronics Corporation | Apparatus for preventing electrostatic discharge in an integrated circuit |
| US6597227B1 (en) | 2000-01-21 | 2003-07-22 | Atheros Communications, Inc. | System for providing electrostatic discharge protection for high-speed integrated circuits |
| US6476472B1 (en)* | 2000-08-18 | 2002-11-05 | Agere Systems Inc. | Integrated circuit package with improved ESD protection for no-connect pins |
| WO2002058155A1 (en)* | 2001-01-19 | 2002-07-25 | Koninklijke Philips Electronics N.V. | Semiconductor chip with internal esd matching |
| FR2974665A1 (en) | 2011-04-27 | 2012-11-02 | St Microelectronics Crolles 2 | MICROELECTRONIC CHIP, COMPONENT INCLUDING SUCH A CHIP AND METHOD OF MANUFACTURE |
| US12199088B2 (en)* | 2022-04-12 | 2025-01-14 | Ancora Semiconductors Inc. | Package structures |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4819047A (en)* | 1987-05-15 | 1989-04-04 | Advanced Micro Devices, Inc. | Protection system for CMOS integrated circuits |
| US4870530A (en)* | 1988-06-27 | 1989-09-26 | Advanced Micro Devices, Inc. | Electrostatic discharge protection circuitry for any two external pins of an I.C. package |
| US4878145A (en)* | 1988-11-21 | 1989-10-31 | Oneac Corporation | Surge/transient protector for a plurality of data lines |
| US5012317A (en)* | 1986-04-11 | 1991-04-30 | Texas Instruments Incorporated | Electrostatic discharge protection circuit |
| US5034845A (en)* | 1988-10-21 | 1991-07-23 | Sharp Kabushiki Kaisha | Integrated circuit apparatus including static electricity protection circuit |
| US5159518A (en)* | 1990-01-17 | 1992-10-27 | Vlsi Technology, Inc. | Input protection circuit for CMOS devices |
| US5515225A (en)* | 1993-08-06 | 1996-05-07 | Sgs-Thomson Microelectronics S.A. | Integrated circuit protected against electrostatic overvoltages |
| US5712753A (en)* | 1996-05-06 | 1998-01-27 | Winbond Electronics Corp. | Method for preventing electrostatic discharge failure in an integrated circuit package |
| US5818086A (en)* | 1996-06-11 | 1998-10-06 | Winbond Electronics Corporation | Reinforced ESD protection for NC-pin adjacent input pin |
| US5869870A (en)* | 1996-04-20 | 1999-02-09 | Winbond Electronics Corp. | Electrostatic discharge (ESD) protective device for integrated circuit packages with no-connect pins |
| US5978197A (en)* | 1997-11-18 | 1999-11-02 | Lsi Corporation | Testing ESD protection schemes in semiconductor integrated circuits |
| US6043539A (en)* | 1997-11-26 | 2000-03-28 | Lsi Logic Corporation | Electro-static discharge protection of CMOS integrated circuits |
| US6107681A (en)* | 1997-10-22 | 2000-08-22 | Winbond Electronics Corp. | Pin-assignment method for integrated circuit packages to increase the electro-static discharge protective capability thereof |
- 1996
- 1996-05-06USUS08/642,194patent/US5715127A/ennot_activeCeased
- 2000
- 2000-02-02USUS09/498,126patent/USRE37982E1/ennot_activeExpired - Fee Related
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5012317A (en)* | 1986-04-11 | 1991-04-30 | Texas Instruments Incorporated | Electrostatic discharge protection circuit |
| US4819047A (en)* | 1987-05-15 | 1989-04-04 | Advanced Micro Devices, Inc. | Protection system for CMOS integrated circuits |
| US4870530A (en)* | 1988-06-27 | 1989-09-26 | Advanced Micro Devices, Inc. | Electrostatic discharge protection circuitry for any two external pins of an I.C. package |
| US5034845A (en)* | 1988-10-21 | 1991-07-23 | Sharp Kabushiki Kaisha | Integrated circuit apparatus including static electricity protection circuit |
| US4878145A (en)* | 1988-11-21 | 1989-10-31 | Oneac Corporation | Surge/transient protector for a plurality of data lines |
| US5159518A (en)* | 1990-01-17 | 1992-10-27 | Vlsi Technology, Inc. | Input protection circuit for CMOS devices |
| US5515225A (en)* | 1993-08-06 | 1996-05-07 | Sgs-Thomson Microelectronics S.A. | Integrated circuit protected against electrostatic overvoltages |
| US5869870A (en)* | 1996-04-20 | 1999-02-09 | Winbond Electronics Corp. | Electrostatic discharge (ESD) protective device for integrated circuit packages with no-connect pins |
| US6025631A (en)* | 1996-04-20 | 2000-02-15 | Winbond Electronics Corp. | Electrostatic discharge (ESD) protective device for integrated circuit packages with no-connect pins |
| US5712753A (en)* | 1996-05-06 | 1998-01-27 | Winbond Electronics Corp. | Method for preventing electrostatic discharge failure in an integrated circuit package |
| US5818086A (en)* | 1996-06-11 | 1998-10-06 | Winbond Electronics Corporation | Reinforced ESD protection for NC-pin adjacent input pin |
| US6107681A (en)* | 1997-10-22 | 2000-08-22 | Winbond Electronics Corp. | Pin-assignment method for integrated circuit packages to increase the electro-static discharge protective capability thereof |
| US5978197A (en)* | 1997-11-18 | 1999-11-02 | Lsi Corporation | Testing ESD protection schemes in semiconductor integrated circuits |
| US6043539A (en)* | 1997-11-26 | 2000-03-28 | Lsi Logic Corporation | Electro-static discharge protection of CMOS integrated circuits |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050248028A1 (en)* | 2004-05-05 | 2005-11-10 | Cheng-Yen Huang | Chip-packaging with bonding options connected to a package substrate |
| US20080003714A1 (en)* | 2004-05-05 | 2008-01-03 | Cheng-Yen Huang | Chip-packaging with bonding options connected to a package substrate |
| US20050285280A1 (en)* | 2004-06-25 | 2005-12-29 | Sin-Him Yau | Electrostatic discharge (ESD) protection for integrated circuit packages |
| US7301229B2 (en) | 2004-06-25 | 2007-11-27 | Taiwan Semiconductor Manufacturing Company | Electrostatic discharge (ESD) protection for integrated circuit packages |
Also Published As
| Publication number | Publication date |
|---|---|
| US5715127A (en) | 1998-02-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| USRE37982E1 (en) | Method for preventing electrostatic discharge failure in an integrated circuit package | |
| US5955762A (en) | Microelectronic package with polymer ESD protection | |
| US5930098A (en) | Multichip semiconductor structures with interchip electrostatic discharge protection, and fabrication methods therefore | |
| JP3657246B2 (en) | Semiconductor device | |
| US5889308A (en) | Semiconductor device having an electrostatic discharging protection circuit using a non-ohmic material | |
| US7067914B2 (en) | Dual chip stack method for electro-static discharge protection of integrated circuits | |
| CN101009257A (en) | Semiconductor device | |
| CN212230426U (en) | integrated circuit device | |
| US7274048B2 (en) | Substrate based ESD network protection for a flip chip | |
| US20080230870A1 (en) | Input protection circuit preventing electrostatic discharge damage of semiconductor integrated circuit | |
| US6556409B1 (en) | Integrated circuit including ESD circuits for a multi-chip module and a method therefor | |
| US20040018662A1 (en) | Method of manufacturing a semiconductor device | |
| US5712753A (en) | Method for preventing electrostatic discharge failure in an integrated circuit package | |
| EP0188378B1 (en) | Semiconductor circuit device | |
| US6890794B2 (en) | Flip chip with novel power and ground arrangement | |
| US6426531B1 (en) | Semiconductor integrated circuit device and a method of assembly thereof | |
| JPH0362566A (en) | Integrated circuit package equipped with decoupling capacitor | |
| JP2002353396A (en) | Semiconductor integrated circuit device | |
| US6797993B2 (en) | Monolithic IC package | |
| US6404060B1 (en) | Semiconductor device having a chip-on-chip structure | |
| JP3692186B2 (en) | Semiconductor device | |
| JPS61180470A (en) | Semiconductor integrated circuit device | |
| CN113675173B (en) | Semiconductor package | |
| JP2993480B2 (en) | Semiconductor device | |
| JP2005057126A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Fee payment | Year of fee payment:8 | |
| REMI | Maintenance fee reminder mailed | ||
| LAPS | Lapse for failure to pay maintenance fees |