USRE37060E1

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Info

Publication number: USRE37060E1
Application number: US09/010,384
Authority: US
Inventors: Chiakang Sung; Wanli Chang; Joseph Huang
Original assignee: Altera Corp
Current assignee: Altera Corp
Priority date: 1995-11-08
Filing date: 1998-01-21
Publication date: 2001-02-20
Anticipated expiration: 2015-11-08
Also published as: US5555214A; GB9610014D0; GB2307074B; GB2307074A

Abstract

A method of serially reading and writing random access memory arrays is provided. Although the read/write inputs continually change as programming data are clocked into the input buffers, a read/write control circuit prevents the constantly changing read/write inputs from causing undesired reading and writing.

Description

BACKGROUND OF THE INVENTION

This invention relates to the serial programming of random access memory arrays, and particularly random access memory arrays contained within larger devices such that the number of input/output pins available for programming is limited.

Typically, in the programming of random access memory arrays, one provides the data to be stored and address information that indicates where in the array the data are to be stored. To read the array, the address of the locations desired would be provided. In addition, Output Enable and read/write control signals are typically provided. Typically, the programming data, address data, and control signals are fed in parallel to a buffer. Change of the read/write control signal to a write state then causes the programming data in the buffer to be written to the appropriate places in the array as determined by the address data.

A programming scheme such as that just described ordinarily is performed in parallel, requiring a large number of input/output (I/O) lines. For example, in the case of a 64×32-bit array, eleven (11) address lines are required—i.e., six lines for the 64-bit dimension (2⁶=64) and five lines for the 32-bit dimension (2⁵=32). In addition, the programming data are normally transferred in 8-bit bytes, necessitating another eight (8) lines, and the clock and control signals require at least two additional lines, for a total in that case of at least twenty-one (21) lines required for writing. The device is similarly read out into an output buffer, preferably under control of the same address lines as are used for input, when the read/write control signal changes to a read state. The output of the buffer is then read in parallel using, typically, eight lines. Thus, twenty-one lines are required for reading as well.

If the random access memory is a discrete memory device, the number of lines required for reading or writing is not of much concern, because the available I/O pins on the device are not required for other functions. However, random access memory arrays are frequently embedded in larger devices. For example, copending commonly-assigned U.S. patent application Ser. No. 08/442,795, filed May 17, 1995, which is hereby incorporated by reference in its entirety, describes a programmable logic device having a large number of interconnected programmable logic regions. In addition, there are a smaller number of random access memory regions embedded in the device (in that example, the random access memory is static random access memory). In that device, there is heavy competition for I/O pins, which must be shared by logic inputs and outputs, programming inputs, testing inputs and outputs, etc.

One way of reducing the number of pins required to access a large array device is to use serial techniques. For example, commonly-assigned U.S. Pat. No. 4,930,107 shows a method for serially programming an EPROM-type programmable logic device. However, where the array device is a random access memory, special considerations arise that may make serial programming more difficult.

Reading of the random access memory occurs in a similar way. Specifically, address data are written into the input buffers and the read/write control bit or bits are changed to a read state, causing the data in the array that is identified by the address in the buffer to be written to output buffers which can then be read either serially or in parallel (again, to optimize pin allocations, serial reading would be preferred). Here again, as the address data are clocked in, unintended reading or writing may occur as the read/write control bit changes state.

It would be desirable to be able to provide for serial reading and writing of random access memory while preventing unintended reading and writing of the memory as data are clocked into the input buffers.

SUMMARY OF THE INVENTION

It is an object of this invention to provide for serial reading and writing of random access memory while preventing unintended reading and writing of the memory as data are clocked into the input buffers.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:

FIG. 1 is a high-level diagram of a programmable logic device including embedded random access memory configured according to the present invention;

FIG. 2 is a block diagram of a plurality of random access memory arrays configured according to the present invention;

FIG. 3 is a block diagram of an example of a serial register configuration according to the present invention; and

FIG. 4 is a block diagram of a read/write control arrangement according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention allows for serial reading and writing of random access memory without unintended reading and writing as the state of the read/write control bit changes during the serial clocking of programming data. (As used herein, “programming data” means the data that are clocked into the random access memory input registers for reading or writing the random access memory, including address and control data which are used for either reading or writing, as well as data to be stored when in the write mode.) The invention accomplishes that result by interposing, between the read/write control register and the random access memory array, a read/write control circuit that allows the user to override the read/write control register during serial loading of the input registers.

The read/write control circuit preferably is a multiplexer having two data inputs and a control input. One data input is the output of the read/write control register. The other data input is a read/write mode selection signal which is applied to an I/O pin of the device by the user (or by some other device or circuit according to the design of the user) during the clocking of programming data into the random access memory input registers (and possibly at other times as discussed below). The control input is a read/write option signal applied to an I/O pin by the user (or by some other device or circuit according to the design of the user) during the clocking of programming data into the random access memory input registers (and possibly at other times as discussed below).

When data are to be clocked into the input registers to read or write the random access memory, the user would apply (or cause to be applied), to the read/write option input of the read/write control circuit, a signal that causes the read/write control circuit to select, as the read/write control input to the random access memory, the read/write mode selection signal rather than the contents of the read/write control register. The user would then apply (or cause to be applied) to the read/write mode selection input a signal that will keep the random access memory in read mode.

In a preferred embodiment of the invention, the read/write control input to the random access memory array is a Read/Not-Write input. That is, the array is in a read state when the Read/Not-Write input is high (a logic “1”), and in a write state when the Read/Not-Write input is low (a logic “)”). In that embodiment, the read state of the signal applied to the read/write mode selection input would be a logic “1.” It should be understood, however, that the read/write control input could be implemented in other ways, such as a Not-Read/Write input in which a logic “0” is the read state and a logic “1” is the write state. Other arrangements for read/write control might also be used.

There is normally no reason why the user would want the read/write mode selection signal to keep the random access memory in write mode. Therefore, the read/write mode selection input could be kept permanently in a read state—e.g., it could be tied high in a Read/Not-Write embodiment or tied low in a Not-Read/Write embodiment. The read/write option input alone would then determine whether the random access memory is in a read state, or in a state determined by the read/write control register. However, there may be applications where the user would want to force the random access memory into a write state, and such applications can be accomplished by applying the desired signal (in the Read/Not-Write example, a logic “0”) to the read/write mode selection input while selecting that input using the read/write option signal.

The invention thus provides a way to serially clock programming data into the input registers of a random access memory without the random access memory being rewritten every time a bit in the “write” state (a logic “0” in the example) is clocked through the read/write control register.

The invention can be further described with reference to FIGS. 1-4.

FIG. 1 shows, as an example of a device with which the present invention can be used, aprogrammable logic device10 having embedded random access memory. It should be recognized, however, that the present invention can be used with random access memory alone, or with random access memory that is part of some other kind of device.

As can be seen,device10 has a plurality of randomaccess memory arrays11, which are arranged in one column ondevice10. The remaining columns ofdevice10 are populated byprogrammable logic regions12. Each row has two groups ofhorizontal interconnection conductors13 that extend the entire length of the row, one group ofconductors13 being above the row and the other group being below the row.Conductors13 are sometimes referred to as full-horizontal conductors or as global horizontal conductors. Each row also has four groups of horizontal interconnection conductors14 that extend along half the length of the row. Two of these groups extend respectively along the top and bottom of the left half of the row. The other two groups of these conductors14 extend respectively along the top and bottom of the right half of the row. The conductors14 associated with each half of a row are preferably not directly connectable to the conductors14 associated with the other half of the row. Conductors14 are sometimes referred to as half-horizontal conductors. Each column ofregular logic regions12 has a group ofvertical interconnection conductors15 that extend continuously or substantially continuously along the entire length of the column.

In order to feed logic signals to eachregion12, each regular logic region has an associated plurality ofregion feeding conductors16 that can bring signals to the logic region from thehorizontal conductors13 and14 associated with that region. Eachregion12 also has eight associated local feedback conductors17. Each conductor17 makes the output signal of a respective one of thelogic modules18 in the associatedregion12 available as an input to any of the other logic modules in that region without having to use any interconnection resources that are not exclusively associated with the region.

Eachregion12 also hasoutput conductors19 for conveying the output logic signals of thelogic modules18 in that region to the associatedconductors13 and14. Programmable logic connectors (“PLCs”) (not shown) are associated with eachregular logic region12 for making connections from the vertical (15) to the horizontal (13 and14) conductors associated with the region. A plurality ofoutput networks100 connect the various conductors13-15) to input/output pins101.

As can be seen, many resources are competing for access to I/O pins101, hence the desire, as discussed above, to minimize the number of I/O pins101 required in order to carry out serial reading and writing of randomaccess memory arrays11. That minimization is achieved as discussed below.

In FIG. 2, N randomaccess memory arrays11 are depicted schematically as 64×32-bit arrays, arranged in N rows of a single column. Preferably,arrays11 are static random access memory arrays, but the invention applies equally to dynamic random access memory.Representative bits20 are shown schematically scattered throughout the uppermost one of arrays11 (in Row0). Associated with eacharray11 is aninput buffer21 made up of a plurality of registers. In the illustrative embodiment shown,input buffer21 includes twenty-one registers—eight data registers D0-D7, eleven address registers A0-A10, an Output Enable (OE) register and a read/write control register implemented as a Read/Not-Write (RNW) register.Buffer21 is connected toarray11 by eightdata inputs22, elevenaddress inputs23, and anOutput Enable input24.Buffer21 also has a read/write control output25 which is switched by read/write control circuit26. Read/write control circuit26 is also fed by read/writemode selection input27 and read/write option input28. The output of read/write control circuit26 feeds read/write control input25 ofarray11.

Eacharray11 preferably also has an associatedoutput buffer29 preferably made up of eight output registers Reg0-Reg7, each of which is preferably connected toarray11 by one of preferably eightoutputs200.

The registers ofbuffer21 and the registers ofbuffer29 preferably are positive edge trigger D-type flip-flops30 connected serially as shown in FIG.3.Buffers21 are preferably connected together serially as indicated by arrows A, with the last register in eachbuffer21 connected to the first register in thenext buffer21 in the same manner as the individual registers of eachbuffer21. Similarly, buffers29 are preferably connected together serially as indicated by arrows B, with the last register in eachbuffer29 connected to the first register in thenext buffer29 in the same manner as the individual registers of eachbuffer29.

FIG. 4 shows detail of read/write control circuit26. As can be seen, read/writecontrol circuit26 is preferably amultiplexer40, fed by read/write control output25 of the RNW register of buffer21( as a first data input), by read/write mode selection input27( as a second data input), and by read/write option input28( as a control input), the latter two preferably being fed by appropriate ones ofpins101.

In operation, the user, or a circuit or software under the direction or control of the user, would arrange a string of programming bits that are clocked intobuffers21 serially under the control of clock signal CLK1 from input DATA-SIN, both preferably fed fromappropriate pins101. The string of bits would be arranged so that after being clocked intobuffers21, the desired bit would be present in each of the registers ofbuffers21 to accomplish the desired read or write operation. For a read operation in the embodiment shown, in addition to arranging the data and address bits, the user would arrange that each bit in each RNW register is a logic “1,” while for a write operation in that embodiment, the user would arrange that each bit in each RNW register is a logic “0.” As the programming data are clocked intobuffers21, the user would activate read/write control circuit26 by applying a signal on read/write option input28 (e.g., from an appropriate pin101) to causemultiplexer40 to feed read/writemode selection signal27, rather than read/writecontrol output signal25, to read/write control input25′ ofarray11. The user would also apply a logic “1” to read/write mode selection input27 (e.g., from an appropriate pin101). As stated above, in the embodiment shown the user most likely will never wantinput27 to be anything other than a logic “1,” and so it could be permanently held high, with all control based oninput28. After the data have been clocked intobuffers21, the user will changeinput27 to a state that causesmultiplexer40 to selectoutput25. For a write operation in the embodiment shown the logic “0's” in registers RNW will then be applied toinputs25′, and the data in respective sets of registers D0-D7 will be written to the locations specified by the data in respective sets of registers A0-A11, which are decoded by anaddress decoder230 shown schematically as being part of randomaccess memory array11, although it could be a separate circuit between registers A0-A10 and randomaccess memory array11.

For a read operation, the logic “1's” in registers RNW would be applied bycircuit26 toinputs25′, and the data in array locations specified by the data in respective sets of registers A0-A11 will be written to respective sets of registers Reg0-Reg7 in output buffers29. The data can then be read by clocking them out on line RAMSOUT under control of clock signal CLK2.

In a programmable logic device, a write operation would most likely be used to load randomaccess memory arrays11 to function as look-up tables or other logic devices, which during normal operation would probably be accessed in a way that directs individual outputs to different parts of the device. Therefore, the serial output or read mode just described would probably be used only for testing (by the manufacturer or the user), although other uses would be possible. And if the random access memory were being used alone or in some other application, the serial read and write modes can be used as desired.

As described, the present invention allows serial reading and writing of relatively large random access memory arrays using preferably only six pins—CLK1, CLK2, DATASIN, RAMSOUT, read/writemode selection input27 and read/write option input28. Indeed, if read/writemode selection input27 is permanently held high (or low) as discussed, the number of pins needed can be reduced to five.

Thus it is seen that serial reading and writing of random access memory is provided, while preventing unintended reading and writing of the memory as data are clocked into the input buffers. One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.

Claims

What is claimed is:

1. Serially programmable random access memory comprising:

at least one random access memory array including:

a plurality of random access memory bits,

a plurality of data input lines for entering data to be stored in said random access memory array,

a plurality of address input lines and an address decoder for entering address information indicating in a write mode in which of said plurality of random access memory bits said data to be stored are to be stored, and for indicating in a read mode which of said plurality of random access memory bits are to be output from said random access memory array, and

a read/write control input, said random access memory array being in a read mode when a read/write control signal applied to said read/write control input is in a first logic state and being in a write mode when said read/write control signal applied to said read/write control input is in a second logic state;

for each said at least one random access memory array, a set of input/programming registers connected to said data input lines, said address input lines and said read/write control input for inputting programming data for said random access memory array, said programming data including said address information and a registered control signal to be applied to said read/write control input, and including said data to be written when said input/programming registers are used for writing, said input/programming registers being chained together such that said programming data can be entered serially into said registers; and

a read/write control circuit for selectively operating said at least one random access memory array in one of (a) a first mode in which said random access memory array is in one of (i) a read mode, and (ii) a write mode, regardless of said registered control signal, and (b) a second mode in which said random access memory array is in one of (i) a read mode, and (ii) a write mode, under control of said registered control signal.

2. The serially programmable random access memory of claim1, wherein:

said at least one random access memory array comprises a plurality of said random access memory arrays; said serially programmable random access memory further comprising:

a corresponding plurality of said at least one set of input registers.

3. The serially programmable random access memory of claim2 wherein said plurality of sets of input registers are chained together for serial input of said programming data for said plurality of said random access memory arrays.

4. The serially programmable random access memory of claim1 wherein said at least one random access memory array comprises static random access memory.

5. The serially programmable random access memory of claim1 wherein said read/write control circuit comprises a selector circuit having:

a first input connected to one of said input registers corresponding to said registered control signal;

a second input for a read/write mode selection signal; and

a third input for a read/write option signal; wherein:

when said read/write option signal is in a first logic state, said read/write control circuit selects said first input as said read/write control input; and

when said read/write option signal is in a second logic state, said read/write control circuit selects said second input as said read/write control input.

6. The serially programmable random access memory of claim5 wherein said selector circuit comprises a multiplexer.

7. The serially programmable random access memory of claim5 further comprising:

a first input pin for said programming data;

a second input pin for said read/write option signal; and

a third input pin for said read/write mode selection signal.

8. The serially programmable random access memory of claim1 wherein:

said at least one random access memory array further comprises a plurality of data output lines for outputting data stored in said random access memory array; said serially programmable random access memory further comprising:

for each said at least one random access memory array, a set of output registers connected to said data output lines for, when said at least one random access memory array is operated in a read mode, outputting from said random access memory array said data stored in said random access memory array, said output registers being chained together such that said data stored in said random access memory array can be output serially from said registers.

9. The serially programmable random access memory of claim8 wherein:

a corresponding plurality of said at least one set of output registers.

10. The serially programmable random access memory of claim9 wherein said plurality of sets of output registers are chained together for serial output of said data stored in said plurality of random access memory arrays.

11. A programmable logic device comprising a plurality of configurable logic circuits, serially programmable random access memory, and interconnect resource connecting said configurable logic circuits and said serially programmable random access memory, said serially programmable random access memory comprising:

at least one random access memory array including:

a plurality of random access memory bits,

a plurality of address input lines and an address decoder for entering address information indicating in a write mode in which of said plurality of random access memory bits said data to be stored are to be stored, and for indicating in a read mode which of said plurality of random access memory bits are to be output from said random access memory, and

12. The programmable logic device of claim11, wherein:

a corresponding plurality of said at least one set of input registers.

13. The programmable logic device of claim12 wherein said plurality of sets of input registers are chained together for serial input of said programming data for said plurality of said random access memory arrays.

14. The programmable logic device of claim11 wherein said at least one random access memory array comprises static random access memory.

15. The programmable logic device of claim11 wherein said read/write control circuit comprises a selector circuit having:

a second input for a read/write mode selection signal; and

a third input for a read/write option signal; wherein:

when said read/write selector signal is in a second logic state, said read/write control circuit selects said second input as said read/write control input.

16. The programmable logic device of claim15 wherein said selector circuit comprises a multiplexer.

17. The programmable logic device of claim15 further comprising:

a first input pin for said programming data;

a second input pin for said read/write option signal; and

a third input pin for said read/write mode selection signal.

18. The programmable logic device of claim11 wherein:

19. The programmable logic device of claim18 wherein:

a corresponding plurality of said at least one set of output registers.

20. The programmable logic device of claim19 wherein said plurality of sets of output registers are chained together for serial output of said data stored in said plurality of random access memory arrays.

21. An apparatus comprising:

a memory array including a plurality of storage locations; and

a serial register, coupled to said memory array, said serial register including:

a first field configured to store an address corresponding to one of said plurality of memory locations in said memory array;

a second field configured to store control information used to control access to said memory array, said control information indicating a write operation when said control information is in a first state and a read operation when said control information is in a second state; and

a third field configured to store data to be written into said one of said plurality of memory locations corresponding to said address stored in said first field when said control information is in said first state.

22. The apparatus of claim21 further comprising a clock circuit configured to generate a clock signal to clock said address, said control information, and said data into said first field, said second field and said third field, respectively, of said serial register.

23. The apparatus of claim22 further comprising a control circuit coupled between said serial register and said memory array, said control circuit configured to selectively provide to said memory array either said control information from said serial register during a registered access of said memory array or a second control signal during a non-registered access of said memory array.

24. The apparatus of claim23 wherein said second control signal originates from a source external to said apparatus.

25. An apparatus comprising:

a memory array including a plurality of memory locations; and

a serial register coupled to said memory array, said serial register including:

a first field configured to store an address corresponding to one of said plurality of memory locations in said memory array; and

a second field configured to store control information used to control access to said one of said plurality of memory locations in said memory array corresponding to said address in said first field of said serial register.

26. The apparatus of claim25 further including a clock circuit which generates a clock signal used to synchronize transfer of said address and said control information into said serial register.

27. The apparatus of claim25 further comprising a control circuit coupled between said serial register and said memory array, said control circuit configured to provide to said memory array either said control information in said second field of said serial register or a second control signal from a source external to said apparatus.

28. The apparatus of claim27 further including a clock circuit which generates a clock signal used to synchronize transfer of said address and said control information into said serial register.

29. The apparatus of claim27 wherein said control circuit is configured to provide said control information in said serial register to said memory array during a registered access of the memory array.

30. The apparatus of claim27 wherein said control circuit is configured to provide said second control signal to said memory array during a non-registered access of said memory array.

31. The apparatus of claim25 wherein said serial register further includes a data field which is configured to store data to be written into said memory array during a write operation.

32. The apparatus of claim25 wherein said control information includes information to control a write operation to said memory array.

33. The apparatus of claim25 wherein said control information includes information to control a read operation of said memory array.

34. The apparatus of claim25 wherein said control circuit is a multiplexer.

35. The apparatus of claim25 wherein said control information is used to control a write operation of said memory array when said control information is in a first state.

36. The apparatus of claim25 wherein said control information is used to control a read operation of said memory array when said control information is in a second state.

37. The apparatus of claim25 further comprising a parallel-to-serial register coupled to said memory array, said parallel-to-serial register configured to receive parallel data read from said memory array and to convert said parallel data into a serial data stream.

38. The apparatus of claim25 further comprising an address decoder coupled to said serial register, said address decoder configured to decode said address stored in said first field of said serial register.

39. The apparatus of claim25 wherein said memory array and serial register are provided on a programmable logic device.

40. The apparatus of claim39 wherein said programmable logic device is contained in a data processing system.