US9984960B2 - Integrated fan-out package and method of fabricating the same - Google Patents

Abstract

Provided is an integrated fan-out package including a die, a first redistribution circuit structure, a second redistribution circuit structure, a plurality of solder joints, a plurality of conductive posts, and an insulating encapsulation. The first redistribution circuit structure and the second redistribution circuit structure are formed respectively over a back surface and an active surface of the die to sandwich the die. The solder joints are formed aside the die and connected to the first redistribution circuit structure. The conductive posts are formed on the solder joints and connected to the second redistribution circuit structure, and connected to the first redistribution circuit structure through the solder joints. A plurality of sidewalls of the die, a plurality of sidewalls of the conductive posts, and a plurality of sidewalls of the solder joints are encapsulated by the insulating encapsulation. A fabricating process of the integrated fan-out package is also provided.

Description

BACKGROUND

The semiconductor industry has experienced rapid growth due to continuous improvement in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, the improvement in integration density has come from gradual reductions in minimum feature size, which allows more of the smaller components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than previous packages. Some smaller types of packages for semiconductor components include quad flat packages (QFPs), pin grid array (PGA) packages, ball grid array (BGA) packages, and so on.

Currently, integrated fan-out packages are becoming increasingly popular for their compactness. How to reduce fabrication costs of the integrated fan-out packages are important issues.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 toFIG. 15 are schematic cross sectional views of various stages in a fabricating process of an integrated fan-out package in accordance with some embodiments.

FIG. 16A toFIG. 16C are schematic perspective views of various stages in the fabricating process of the integrated fan-out package ofFIG. 8.

FIG. 17A toFIG. 17C are schematic cross sectional views of various stages in the fabricating process of the integrated fan-out package along cut line A-A′ ofFIG. 16C.

FIG. 18 is a schematic cross sectional view of a pallet in accordance with alternative embodiments.

FIG. 19 is an enlarged schematic partial cross sectional view of the conductive posts ofFIG. 8.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG. 1 toFIG. 15 are schematic cross sectional views of various stages in a fabricating process of an integrated fan-out package in accordance with some embodiments.

Referring toFIG. 1, a carrier C having a de-bonding layer DB and a firstdielectric layer102aformed thereon is provided, wherein the de-bonding layer DB is formed between the carrier C and the firstdielectric layer102a. In some embodiments, the carrier C is a glass substrate, the de-bonding layer DB is a light-to-heat conversion (LTHC) release layer formed on the glass substrate, and the firstdielectric layer102ais a photosensitive polybenzoxazole (PBO) layer formed on the de-bonding layer DB. In alternative embodiments, the de-bonding layer DB may be a photo-curable release film whose stickiness is decreased by a photo-curing process or a thermal curable release film whose stickiness is decreased by a thermal-curing process, and the firstdielectric layer102amay be made of other photosensitive or non-photosensitive dielectric materials. In some embodiments, the firstdielectric layer102amay be a polybenzoxazole (PBO) layer, a polyimide (PI) layer or other suitable dielectric layers.

Referring toFIG. 2, aseed layer104 is formed over the firstdielectric layer102a, for example, through physical vapor deposition (PVD). In some embodiments, physical vapor deposition includes sputtering deposition, vapor deposition, or any other suitable method. Theseed layer104 may be a metal seed layer including copper, aluminum, titanium, alloys thereof, or multi-layers thereof. In some embodiments, theseed layer104 includes a first metal layer such as a titanium layer (not shown) and a second metal layer such as a copper layer (not shown) over the first metal layer.

Referring toFIG. 3, after theseed layer104 is formed, a patternedphotoresist layer106 is formed on theseed layer104. The patternedphotoresist layer106 has a plurality of openings, such that portions of theseed layer104 are exposed by the openings of the patternedphotoresist layer106.

Referring toFIG. 4, first redistributionconductive layers102band102care formed on the portions of theseed layer104 through, for example, a plating process. Specifically, the first redistributionconductive layers102bare formed aside the first redistributionconductive layers102c. The first redistributionconductive layers102band102care plated on the portions of theseed layer104 exposed by the openings of the patternedphotoresist layer106. In some embodiments, the first redistributionconductive layers102band102cmay be metal layers including copper, aluminum, titanium, or alloys thereof.

Referring toFIG. 4 andFIG. 5, after the first redistributionconductive layers102band102care formed, the patternedphotoresist layer106 is stripped such that the portions of theseed layer104 that are not covered by the first redistributionconductive layers102band102care exposed.

As shown inFIG. 6, by using the first redistributionconductive layers102band102cas a mask, the portions of theseed layer104, which are not covered by the first redistributionconductive layers102band102c, are removed so as to formseed layers104aand expose surfaces of the firstdielectric layer102a. That is, the portions of theseed layer104 overlapped by the first redistributionconductive layers102band102care not etched and remain to form theseed layers104a. Therefore, a firstredistribution circuit structure102 is formed. The firstredistribution circuit structure102 includes the firstdielectric layer102aand the first redistributionconductive layers102band102cthereon. Throughout the description, the remaining portions of theseed layer104aare referred to as bottom portions of the first redistributionconductive layers102band102c. In subsequent drawings, the remaining portions of theseed layer104aare considered as portions of the first redistributionconductive layers102band102c, and are not shown separately.

On the other hand, as shown inFIG. 6, only one layer of the firstdielectric layer102a, one layer of the first redistributionconductive layers102b, and one layer of the first redistributionconductive layers102care shown inFIG. 6; however, the disclosure is not limited thereto. In alternative embodiments, the number of the layers and arrangement of the firstdielectric layer102aand the first redistributionconductive layers102band102cmay be adjusted based on the design and the requirements of the products. After the firstredistribution circuit structure102 is formed, the formation of another dielectric layer directly on the firstredistribution circuit structure102 and the firstdielectric layer102aand the process of patterning another dielectric layer are omitted.

Referring toFIG. 7 andFIG. 8, a plurality ofsolder pastes107 are formed on the first redistributionconductive layers102b. A plurality ofconductive posts110 are mounted on thesolder pastes107. Then, a reflowing process is performed, so that thesolder pastes107 are reflowed to formsolder joints108, and theconductive posts110 are bonded onto the first redistributionconductive layers102bthrough thesolder joints108. Referring toFIG. 7 andFIG. 8, the material of thesolder paste107 and the material of theconductive posts110 are different. In some embodiments, a melting point of thesolder pastes107 is lower than a melting point of theconductive posts110. In some embodiments, thesolder pastes107 may include metal layers including tin, silver, copper, or alloys thereof. Thesolder pastes107 may be formed by printing, jetting, or other suitable methods, for example. Theconductive posts110 include metal including copper or other suitable metals. In some embodiments, theconductive posts110 are pre-fabricated and available from material suppliers.

Referring toFIG. 8,conductive structures130 include first portions and second portions. The first portions are the solder joints108 and the second portions are theconductive posts110, for example. Sidewalls of the solder joints108 and sidewalls of theconductive posts110 have different profiles. In some embodiments, theconductive posts110 have straight sidewalls and the solder joints108 have tapered sidewalls (as shown inFIG. 8) or theconductive posts110chave stepped sidewalls and the solder joints108bhave arc-sidewalls (as shown inFIG. 19).

FIG. 16A toFIG. 16C are schematic perspective views of various stages in the fabricating process of the integrated fan-out package ofFIG. 8. Specifically, as shown inFIG. 16A andFIG. 16B, a plurality of the pre-fabricatedconductive posts110aare provided on apallet10 and placed inholes12aof thepallet10. In some embodiments, the pre-fabricatedconductive posts110ainclude copper posts or other suitable metal posts. Thepallet10 is, for example, vibrated by a vibration machine such that theconductive posts110aare partially inserted into theholes12aof thepallet10. Since theconductive posts110aare pre-fabricated, theconductive posts110awith a predetermined aspect ratio can be easily fabricated. Furthermore, the fabrication costs and the fabrication cycle time of theconductive posts110aare reduced because theconductive posts110aare not fabricated by sputtering, photolithography, plating, and photoresist stripping processes.

In some embodiments, theconductive posts110aare pre-fabricated. The characteristics (e.g. width, height, shape, electrical conductivity, and so on) of the pre-fabricatedconductive posts110amay be inspected in advance. Accordingly, the yield rate of production of theconductive posts110acan be increased.

Referring toFIG. 16B andFIG. 16C, the carrier C is flipped onto the pallet10 (i.e. the carrier C is turned upside down). The following process refers toFIG. 17A toFIG. 17C.

FIG. 17A toFIG. 17C are schematic cross sectional views of various stages in the fabricating process of the integrated fan-out package along cut line A-A′ ofFIG. 16C.FIG. 18 is a schematic cross sectional view of a pallet in accordance with alternative embodiments. As shown inFIG. 17A andFIG. 17B, the solder pastes107 on the flipped carrier C faces theconductive posts110ain theholes12aof thepallet10, such that the solder pastes107 are aligned with theconductive posts110ain theholes12aof thepallet10. In some embodiments, theconductive posts110ahave an I-shape and are disposed in theholes12aformed by blind holes inFIG. 17A. In alternative embodiments, as shown inFIG. 18, theconductive posts110bhave a T-shape or other suitable shapes that are easily fabricated and are disposed inholes12bformed by through holes.

Then, as shown inFIG. 17B andFIG. 17C, the solder pastes107 on the flipped carrier C contact withsurfaces111aof theconductive posts110a. Next, the reflowing process is performed so that the solder pastes107 are reflowed to form the solder joints108, and theconductive posts110aare fixed onto the first redistributionconductive layers102bby the solder joints108 (as shown inFIG. 17C). The melting point of the solder pastes107 is lower than the melting point of theconductive posts110a. Hence, when a reflow temperature reaches the melting point of the solder pastes107, the solder pastes107 are melted first, so as to achieve the bonding effects. At this time, theconductive posts110aremain in the shape without being melted.

In alternative embodiments, when the carrier C is flipped onto and bonded with thepallet10, the first redistributionconductive layers102care not in contact with the upper surface of thepallet10. After the first redistributionconductive layers102bare bonded to thesurfaces111aof theconductive posts110a, the carrier C is driven to move upwardly to pull out theconductive posts110afrom theholes12aof thepallet10. The solder joints108 provide sufficient adhesion to pull out theconductive posts110afrom theholes12aof thepallet10, such that theconductive posts110aare transfer-bonded to the first redistributionconductive layers102b. Afterwards, the carrier C is turned upside down again, as shown inFIG. 17C, so that thesurfaces111aof theconductive posts110afixed to the first redistributionconductive layers102bface downward (i.e. thesurfaces111aface toward the carrier C) whilesurfaces111bof theconductive posts110aface upward and become theupper surfaces111b.

As shown inFIG. 17B andFIG. 17C, since theholes12aof thepallet10 have flat lower surfaces and the pre-fabricatedconductive posts110ahave similar or the same height, coplanarity between theupper surfaces111bof theconductive posts110ainFIG. 17C is better than the conventional plated conductive posts. After theconductive posts110aare mounted, theupper surfaces111bof theconductive posts110aare substantially co-planar without performing the following grinding process on theconductive posts110a. As a result, the fabrication costs and the fabrication cycle time of the integrated fan-out package of the disclosure are further reduced.

On the other hand, even if the heights of the pre-fabricatedconductive posts110aare different, during the reflowing process, depths of theconductive posts110aembedded in the solder joints108 can be adjusted, such that theupper surfaces111bof theconductive posts110aare substantially co-planar or nearly the same. In other words, the solder joints108 between the first redistributionconductive layers102band theconductive posts110ahave an effect of enhancing the coplanarity between theupper surfaces111bof theconductive posts110a.

FIG. 19 is an enlarged schematic partial cross sectional view of the conductive posts ofFIG. 8. Referring toFIG. 19, after theconductive posts110care transfer-bonded to the first redistributionconductive layers102bfrom thepallet10, bottom portions of theconductive posts110cmay be disposed on the solder joints108aor embedded in the solder joints108b. A thickness t2 of the solder joints108 under theconductive posts110 is smaller than a height t3 of theconductive posts110. The height t3 of theconductive posts110 ranges from 100 μm to 500 μm, and the thickness t2 of the solder joints108 under theconductive posts110 ranges from 2 μm to 10 μm, and, for example. In some embodiments, t2/t3 ranges from 0.004 to 0.1. In some embodiments, the embedded depth t1 of the bottom portions of theconductive posts110cis less than ⅓ of the height t3 of theconductive posts110. That is, t1/t3 is less than ⅓. In some embodiments, the embedded depth t1 of the bottom portions of theconductive posts110cis less than 30 micrometers. In alternative embodiments, the embedded depth t1 of the bottom portions of theconductive posts110cis less than 10 micrometers. A level height difference ΔH between theupper surfaces111bof theconductive posts110cmay be less than 10 micrometers. The level height difference ΔH may be regarded as co-planar without affecting the following processes, and therefore, the grinding process to be performed on theconductive posts110cis omitted.

Specifically, as shown inFIG. 19, at least one of the solder joints108aand108bhas arc-sidewalls S108 concaved toward the center of therespective solder joints108aand108b. Take the solder joint108aas an example, the solder joint108ahas tapered sidewalls S108. A horizontal cross-sectional area of the solder joint108agradually decreases in a direction from the first redistributionconductive layers102btoward the correspondingconductive posts110c. In some embodiments, an upper width W2 of the solder joint108ais equal to a lower width W1 of theconductive post110con the solder joint108a, while a lower width W3 of the solder joint108ais larger than the lower width W1 of theconductive post110con the solder joint108a. In alternative embodiments, the solder joint108bcovers a portion of the sidewalls S110 of the correspondingconductive post110c, and an upper width W4 of the solder joint108bis larger than the lower width W1 of theconductive post110con the solder joint108b, wherein the upper width W4 is located at an interface between the solder joint108band the correspondingconductive post110c. In other words, after the reflowing process is performed, the solder joint108bis formed having a recess R on the top surface thereof. A depth t1 of the recess R is less than 10 micrometers, for example. A bottom portion of theconductive post110cis partially inserted into the recess R.

Referring back toFIG. 8 andFIG. 9, adie112 is mounted onto the first redistributionconductive layers102cby an adhesive AD. In some embodiments, thedie112 is directly bond onto the first redistributionconductive layers102cvia the adhesive AD. The adhesive AD is filled in the openings in the first redistributionconductive layers102cand covers the upper surfaces of the first redistributionconductive layers102c. Thedie112 is electrically insulated from the first redistributionconductive layers102cby the adhesive AD. In some embodiments, the adhesive AD serves as a die attach film (DAF) or film over wire (FoW). Thedie112 has anactive surface112aand aback surface112fopposite to theactive surface112a. In some embodiments, thedie112 includes a plurality ofpads112b, apassivation layer112c, and a plurality ofconductive pillars112d. Thepassivation layer112ccovers theactive surface112aand portions of thepads112b. Thepads112bare partially exposed by thepassivation layer112c. Theconductive pillars112dare formed on and electrically connected to thepads112b. Theback surface112fof thedie112 is in contact with the adhesive AD. Theconductive pillars112dare copper pillars or other suitable metal pillars, for example.

InFIG. 9, only onedie112 is mounted onto the first redistributionconductive layers102c. However, the number of the dies112 is merely for illustration, and the disclosure is not limited thereto. In alternative embodiments, a plurality of dies112 are mounted onto the first redistributionconductive layers102c, and the dies112 placed on the first redistributionconductive layers102cmay be arranged in an array. When the plurality of dies112 are mounted on the first redistributionconductive layers102c, a plurality of groups of theconductive posts110 may be mounted on the first redistributionconductive layers102band each of the dies112 is surrounded by one group of theconductive posts110.

Referring toFIG. 10, an insulating material (not shown) is formed on the carrier C to cover surfaces of the solder joints108, theconductive posts110 and thedie112. In some embodiments, the insulating material may be a molding compound formed by a molding process. In some embodiments, the insulating material may include epoxy or other suitable materials. Then, the insulating material and portions of thedie112 are ground until the upper surfaces of theconductive pillars112dare exposed. After the insulating material is ground, an insulatingencapsulation114 is formed over the firstredistribution circuit structure102 to encapsulate sidewalls of thedie112, the sidewalls of theconductive posts110, and the sidewalls of the solder joints108. In some embodiments, during the above-mentioned grinding process, portions of the insulating material, portions of theconductive pillars112dand portions of theconductive posts110 are removed until the upper surfaces of theconductive pillars112dand theupper surfaces111bof theconductive posts110 are exposed. In some embodiments, the insulatingencapsulation114 may be formed by mechanical grinding and/or chemical mechanical polishing (CMP).

The insulatingencapsulation114 encapsulates the sidewalls of thedie112 and the sidewalls of theconductive structures130. That is, theconductive structures130 and thedie112 are embedded in the insulatingencapsulation114. In other words, theconductive structures130, which include the solder joints108 and theconductive posts110, penetrate the insulatingencapsulation114, and theupper surfaces111bof theconductive posts110 are exposed. It is noted that theupper surfaces111bof theconductive posts110 and theupper surfaces113dof theconductive pillar112dare substantially coplanar with theupper surface114aof the insulatingencapsulation114 after the above-mentioned grinding process.

In alternative embodiments, the coplanarity between theupper surfaces111bof theconductive posts110 is good enough, and thus the grinding process is omitted. Specifically, after thedie112 is mounted on the first redistributionconductive layers102c, theupper surfaces111bof theconductive posts110 and theupper surfaces113dof theconductive pillar112dare substantially coplanar. A release film (not shown) is adhered to theupper surfaces111bof theconductive posts110 and theupper surfaces113dof theconductive pillar112d. Then, a mold (not shown) is applied to fix the carrier C having the release film, thedie112 and theconductive posts110 thereon. Next, the insulating material (not shown) is filled in gaps among the release film, thedie112, and theconductive structures130, and then a curing process is performed, so as to form the insulatingencapsulation114. Namely, the release film is able to prevent the insulatingencapsulation114 from adhering to theupper surfaces111bof theconductive posts110 and theupper surfaces113dof theconductive pillar112d. As a result, the grinding process may be omitted, such that the fabrication costs and the fabrication cycle time of the disclosure are reduced.

Referring toFIG. 11, after the insulatingencapsulation114 is formed, a secondredistribution circuit structure116 is formed on theupper surfaces111bof theconductive posts110, theupper surface114aof the insulatingencapsulation114, and theupper surfaces113dof theconductive pillars112d. As shown inFIG. 11, the secondredistribution circuit structure116 includes a plurality of seconddielectric layers116aand a plurality of second redistributionconductive layers116bstacked alternately. The second redistributionconductive layers116bare electrically connected to theconductive pillar112dof thedie112 and theconductive posts110. Namely, theconductive structures130, which include the solder joints108 and theconductive posts110, are electrically connected to the firstredistribution circuit structure102 and the secondredistribution circuit structure116. In some embodiments, theupper surfaces113dof theconductive pillars112dand theupper surfaces111bof theconductive posts110 are in contact with the bottommost second redistributionconductive layer116bof the secondredistribution circuit structure116. Theupper surfaces113dof theconductive pillars112dand theupper surfaces111bof theconductive posts110 are partially covered by the bottommost seconddielectric layer116a. Furthermore, the topmost second redistributionconductive layer116bincludes a plurality of pads. In some embodiments, the above-mentioned pads include a plurality of under-ball metallurgy (UBM)patterns116b1 for ball mount and/or at least oneconnection pad116b2 for mounting of passive components. The number of theUBM patterns116b1 and theconnection pads116b2 is not limited in this disclosure.

Referring toFIG. 12, after the secondredistribution circuit structure116 is formed, a plurality of firstconductive terminals118 are placed on theUBM patterns116b1, and a plurality ofpassive components120 are mounted on theconnection pads116b2. In some embodiments, the firstconductive terminals118 are placed on theUBM116b1 through a ball placement process, and thepassive components120 are mounted on theconnection pads116b2 through a soldering process or a reflowing process.

Referring toFIG. 12 andFIG. 13, after the firstconductive terminals118 and thepassive components120 are mounted on the secondredistribution circuit structure116, thefirst dielectric layer102ais de-bonded from the de-bonding layer DB, such that thefirst dielectric layer102ais separated or delaminated from the de-bonding layer DB and the carrier C. In some embodiments, the de-bonding layer DB (e.g., the LTHC release layer) may be irradiated by an UV laser such that thefirst dielectric layer102ais peeled from the carrier C.

As shown inFIG. 13, thefirst dielectric layer102ais then patterned such that a plurality ofcontact openings122 are formed to expose the lower surfaces of the first redistributionconductive layers102b. In some embodiments, the number of thecontact openings122 formed in thefirst dielectric layer102ais corresponding to the number of the first redistributionconductive layers102b.

Referring toFIG. 14, after thecontact openings122 are formed in thefirst dielectric layer102a, a plurality of second conductive terminals124 (e.g., conductive balls) are placed on the lower surfaces of the first redistributionconductive layers102bthat are exposed by thecontact openings122. In some embodiments, the second conductive terminals124 (e.g., conductive balls) are reflowed to be bonded to the exposed surfaces of the first redistributionconductive layers102b. In other words, the secondconductive terminals124 are electrically connected to the first redistributionconductive layers102b. As shown inFIG. 14, after the firstconductive terminals118 and the secondconductive terminals124 are formed, an integrated fan-outpackage100 having dual-side terminals is accomplished.

Referring toFIG. 15, anotherpackage200 is then provided. In some embodiments, thepackage200 is a memory device. Thepackage200 is stacked over and is electrically connected to the integrated fan-outpackage100 illustrated inFIG. 14 through the secondconductive terminals124, such that a package-on-package (POP) structure is fabricated.

According to some embodiments, a die is directly mounted onto the first redistribution conductive layers by an adhesive. In addition, the die is connected to a first redistribution circuit structure over a back surface of the die and a second redistribution circuit structure over an active surface of the die via a plurality of solder joints and a plurality of conductive posts. The conductive posts are mounted onto the first redistribution circuit structure through the solder joints. The solder joints are formed between the first redistribution circuit structure and the conductive posts to enhance the coplanarity between the upper surfaces of the conductive posts.

According to some embodiments, an integrated fan-out package includes a die, a first redistribution circuit structure, a second redistribution circuit structure, a plurality of solder joints, a plurality of conductive posts, and an insulating encapsulation. The first redistribution circuit structure and the second redistribution circuit structure are formed respectively over a back surface and an active surface of the die to sandwich the die. The solder joints are formed aside the die and connected to the first redistribution circuit structure. The conductive posts are formed on the solder joints and connected to the second redistribution circuit structure, and connected to the first redistribution circuit structure through the solder joints. A plurality of sidewalls of the die, a plurality of sidewalls of the conductive posts, and a plurality of sidewalls of the solder joints are encapsulated by the insulating encapsulation.

According to some embodiments, an integrated fan-out package includes a die, a first redistribution circuit structure, a second redistribution circuit structure, an insulating encapsulation, a plurality of conductive structures, a plurality of first conductive terminals, and a plurality of second conductive terminals. The first redistribution circuit structure is formed over a back surface of the die. The second redistribution circuit structure is formed on an active surface of the die. The insulating encapsulation is formed aside the die to encapsulate the die. The conductive structures penetrate the insulating encapsulation. At least one of the conductive structures includes a first portion and a second portion on the first portion. The first portion is electrically connected to the first redistribution circuit structure. The second portion is electrically connected to the second redistribution circuit structure, and electrically connected to the first redistribution circuit structure through the first portion. A material of the first portion and a material of the second portion are different. The first conductive terminals are electrically connected to the second redistribution circuit structure. The second conductive terminals are electrically connected to the first redistribution circuit structure.

According to some embodiments, a method of fabricating an integrated fan-out package includes the following steps. A first redistribution circuit structure is formed on a carrier. The first redistribution circuit structure includes a first dielectric layer and a plurality of first redistribution conductive layers on the first dielectric layer. A plurality of solder joints are formed on a portion of the first redistribution conductive layers. A plurality of conductive posts are mounted on the first redistribution conductive layers through the solder joints respectively. A die is mounted on another portion of the first redistribution conductive layers by an adhesive. An insulating encapsulation is formed to encapsulate a plurality of sidewalls of the die, a plurality of sidewalls of the conductive posts, and a plurality of sidewalls of the solder joints. A second redistribution circuit structure is formed on the insulating encapsulation, the die, and the conductive posts. The second redistribution circuit structure is electrically connected to the die and the conductive posts. The carrier is removed.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (20)

What is claimed is:

1. An integrated fan-out package, comprising:

a die;

a first redistribution circuit structure and a second redistribution circuit structure respectively over a back surface and an active surface of the die to sandwich the die;

a plurality of solder joints, aside the die and connected to the first redistribution circuit structure;

a plurality of conductive posts, on the solder joints and connected to the second redistribution circuit structure, and connected to the first redistribution circuit structure through the solder joints; and

an insulating encapsulation, encapsulating a plurality of sidewalls of the die, a plurality of sidewalls of the conductive posts, a plurality of sidewalls of first redistribution conductive layers of the first redistribution circuit structure, and a plurality of sidewalls of the solder joints,

wherein upper surfaces of the conductive posts are partially covered by a bottommost dielectric layer of the second redistribution circuit structure.

2. The integrated fan-out package ofclaim 1, wherein the die is bonded to the first redistribution circuit structure by an adhesive.

3. The integrated fan-out package ofclaim 1, wherein a material of the solder joints and a material of the conductive posts are different.

4. The integrated fan-out package ofclaim 1, wherein a thickness of the solder joints under the conductive posts is smaller than a height of the conductive posts.

5. The integrated fan-out package ofclaim 1, wherein at least one of the solder joints has a plurality of arc-sidewalls or a plurality of tapered sidewalls.

6. The integrated fan-out package ofclaim 1, wherein an upper width of each of the solder joints is larger than or equal to a lower width of each of the conductive posts, and a lower width of each of the solder joints is larger than the lower width of each of the conductive posts.

7. The integrated fan-out package ofclaim 1, wherein a horizontal cross-sectional area of at least one of the solder joints gradually decreases toward a corresponding conductive post.

8. The integrated fan-out package ofclaim 1, wherein the conductive posts comprise I-shaped conductive posts, T-shaped conductive posts, or a combination hereof.

9. The integrated fan-out package ofclaim 1, wherein at least one of the solder joints covers a portion of a plurality of sidewalls of a corresponding conductive post.

10. An integrated fan-out package, comprising:

a die;

a first redistribution circuit structure, over a back surface of the die;

a second redistribution circuit structure, over an active surface of the die;

an insulating encapsulation, aside the die to encapsulate the die and a plurality of sidewalls of first redistribution conductive layers of the first redistribution circuit structure;

a plurality of conductive structures, penetrating the insulating encapsulation, wherein at least one of the conductive structures comprises:

a first portion electrically connected to the first redistribution circuit structure; and

a second portion on the first portion and electrically connected to the second redistribution circuit structure, and electrically connected to the first redistribution circuit structure through the first portion, wherein a material of the first portion and a material of the second portion are different, and an upper surface of the second portion is partially covered by a bottommost dielectric layer of the second redistribution circuit structure;

a plurality of first conductive terminals electrically connected to the second redistribution circuit structure; and

a plurality of second conductive terminals electrically connected to the first redistribution circuit structure.

11. The integrated fan-out package ofclaim 10, wherein a melting point of the first portion is lower than a melting point of the second portion.

12. The integrated fan-out package ofclaim 10, wherein the first portion has a plurality of arc-sidewalls or a plurality of tapered sidewalls.

13. The integrated fan-out package ofclaim 10, wherein the die is bonded to the first redistribution circuit structure by an adhesive.

14. The integrated fan-out package ofclaim 10, wherein the first portion further covers a portion of a plurality of sidewalls of the second portion.

15. A fabricating method of an integrated fan-out package, the fabricating method comprising:

forming a first redistribution circuit structure on a carrier, wherein the first redistribution circuit structure comprises a first dielectric layer and a plurality of first redistribution conductive layers on the first dielectric layer;

forming a plurality of solder joints on a portion of the first redistribution conductive layers;

mounting a plurality of conductive posts on the first redistribution conductive layers through the solder joints respectively;

mounting a die on another portion of the first redistribution conductive layers by an adhesive;

forming an insulating encapsulation to encapsulate a plurality of sidewalls of the die, a plurality of sidewalls of the conductive posts, the plurality of sidewalls of the first redistribution conductive layers, and a plurality of sidewalls of the solder joints;

forming a second redistribution circuit structure on the insulating encapsulation, the die, and the conductive posts, wherein the second redistribution circuit structure is electrically connected to the die and the conductive posts, and upper surfaces of the conductive posts are partially covered by a bottommost dielectric layer of the second redistribution circuit structure; and

removing the carrier.

16. The fabricating method ofclaim 15, wherein a method of mounting the conductive posts on the solder joints comprises:

placing the conductive posts in a plurality of holes of a pallet respectively;

forming a plurality of solder pastes on the portion of the first redistribution conductive layers of the carrier;

flipping the carrier having the solder pastes onto the pallet, to align the solder pastes of the carrier with the conductive posts in the holes of the pallet; and

performing a reflowing process on the solder pastes to form the solder joints and fix the conductive posts on the solder joints.

17. The fabricating method ofclaim 16, wherein the holes of the pallet comprise a plurality of blind holes or through holes.

18. The fabricating method ofclaim 16, wherein a plurality of upper surfaces of the conductive posts are substantially co-planar after performing the reflowing process.

19. The fabricating method ofclaim 16, wherein a level height different between the upper surfaces of the conductive posts is less than 10 micrometers after performing the reflowing process.

20. The fabricating method ofclaim 15, further comprising:

before removing the carrier, forming a plurality of first conductive terminals on the second redistribution circuit structure respectively; and

after removing the carrier, patterning the first dielectric layer to expose a plurality of surfaces of the first redistribution conductive layers, and forming a plurality of conductive terminals on the exposed surfaces of the first redistribution conductive layers respectively.

Images