US9893163B2 - 3D capacitor and method of manufacturing same - Google Patents

Abstract

A 3D capacitor and method for fabricating a 3D capacitor is disclosed. An exemplary 3D capacitor includes a substrate including a fin structure, the fin structure including a plurality of fins. The 3D capacitor further includes an insulation material disposed on the substrate and between each of the plurality of fins. The 3D capacitor further includes a dielectric layer disposed on each of the plurality of fins. The 3D capacitor further includes a first electrode disposed on a first portion of the fin structure. The first electrode being in direct contact with a surface of the fin structure. The 3D capacitor further includes a second electrode disposed on a second portion of the fin structure. The second electrode being disposed directly on the dielectric layer and the first and second portions of the fin structure being different.

Description

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of the IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.

For example, as the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design have resulted in the development of three-dimensional (3D) devices. Along with the development of 3D devices, there is a need for capacitors for the 3D devices. Accordingly, although existing capacitors and methods of fabricating capacitors have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a flowchart illustrating a method of fabricating a semiconductor device according to various aspects of the present disclosure.

FIGS. 2A-10A illustrate perspective views of one embodiment of a semiconductor device at various stages of fabrication, according to the method ofFIG. 1.

FIGS. 2B-10B illustrate diagrammatic cross-sectional side views of the semiconductor device, in portion or entirety, illustrated inFIGS. 2A-10A, respectively.

FIG. 11 is a flowchart illustrating a method of fabricating a semiconductor device according to various aspects of the present disclosure.

FIGS. 12A-18A illustrate perspective views of one embodiment of a semiconductor device at various stages of fabrication, according to the method ofFIG. 11.

FIGS. 12B-18B illustrate diagrammatic cross-sectional side views of the semiconductor device, in portion or entirety, illustrated inFIGS. 12A-18A, respectively.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Also, the components disclosed herein may be arranged, combined, or configured in ways different from the exemplary embodiments shown herein without departing from the scope of the present disclosure. It is understood that those skilled in the art will be able to devise various equivalents that, although not explicitly described herein, embody the principles of the present invention.

Examples of devices that can benefit from one or more embodiments of the present invention are semiconductor devices. Such a device, for example, is a capacitor for a three-dimensional (3D) device. The capacitor may be a 3D capacitor such as a metal insulator metal (MIM) or a metal insulator semiconductor (MIS) capacitor. The 3D capacitor, for example, may be used in conjunction with a 3D device such as a fin-like field effect transistor (FinFET) device. The FinFET device, for example, may be a P-type metal-oxide-semiconductor (PMOS) FinFET device or a N-type metal-oxide-semiconductor (NMOS) FinFET device. The following disclosure will continue with a MIM capacitor example for a FinFET device to illustrate various embodiments of the present disclosure. It is understood, however, that the disclosure should not be limited to a particular type of device, except as specifically claimed.

With reference toFIGS. 1 and 2A,B-10A,B, amethod100 and asemiconductor device200 are collectively described below.FIG. 1 is a flow chart of amethod100 for fabricating an integrated circuit device according to various aspects of the present disclosure. In the present embodiment, themethod100 is for fabricating an integrated circuit device that includes a 3D capacitor. Themethod100 begins atblock102 where a substrate is provided. Atblock104, a fin structure is formed over the substrate. The formation of the fin structure may include patterning a mask layer and etching the semiconductor substrate using the mask layer. Atblock106, the fin structure is implanted to form a low-resistance surface on the fin structure. The method continues withblock108 where an insulation material is deposited on the fin structure. The insulation material may be deposited such that it covers the fin structure and substantially fills regions between each fin of the fin structure. A planarizing process may be subsequently performed such that the top surface of the dielectric layer is planarized, exposing a top portion of the fin structure. The method continues withblock110 where an etching process is performed on the insulation material such that a portion of the fin structure is exposed. At block112, a dielectric layer is formed over the low-resistance surface of the fin structure. Themethod100 continues withblock114 where a first electrode is formed on a first portion of the fin structure and a second electrode is formed on a second portion of the fin structure. The first and second portions are different. Themethod100 continues with block116 where fabrication of the integrated circuit device is completed. Additional steps can be provided before, during, and after themethod100, and some of the steps described can be replaced or eliminated for other embodiments of the method. The discussion that follows illustrates various embodiments of an integrated circuit device that can be fabricated according to themethod100 ofFIG. 1.

FIGS. 2A-10A illustrate perspective views of one embodiment of a semiconductor device at various stages of fabrication, according to the method ofFIG. 1.FIGS. 2B-10B illustrate diagrammatic cross-sectional side views of the semiconductor device, in portion or entirety, illustrated inFIGS. 2A-10A, respectively, taken along line a-a. In the present disclosure, the semiconductor device is a 3D capacitor. The3D capacitor200 may be included in a microprocessor, memory cell, and/or other integrated circuit device.FIGS. 2A,B-10A,B have been simplified for the sake of clarity to better understand the concepts of the present disclosure. Additional features can be added in the3D capacitor200, and some of the features described below can be replaced or eliminated in other embodiments of thesemiconductor device200.

Referring toFIGS. 2A and 2B, the3D capacitor200 includes a substrate (e.g., wafer)210. Thesubstrate210 is a bulk silicon substrate. Alternatively, thesubstrate210 comprises an elementary semiconductor, such as silicon or germanium in a crystalline structure; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; or combinations thereof. Alternatively, thesubstrate210 includes a silicon-on-insulator (SOI) substrate. The SOI substrate can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods.

With further reference toFIGS. 2A and 2B, formed over thesubstrate210 is adielectric layer212. Thedielectric layer212 is formed by any suitable process to any suitable thickness. In the present embodiment, thedielectric layer212 includes silicon oxide and is formed by a CVD or a thermal oxidation process. The thermal oxidation process may be a dry or a wet process. In various examples, the silicon oxide can be formed by physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), other suitable methods, and/or combinations thereof. The CVD process, for example, may use chemicals including Hexachlorodisilane (HCD or Si2Cl6), Dichlorosilane (DCS or SiH2Cl2), Bis(TertiaryButylAmino) Silane (BTBAS or C8H22N2Si) and Disilane (DS or Si2H6).

Formed over thedielectric layer212 is amask layer214. In the present embodiment, themask layer214 includes silicon nitride and is formed by a CVD process. Themask layer214 may be a stop/hard mask layer. Themask layer214 is formed by any suitable process to any suitable thickness. Themask layer214 may include a material such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, other suitable material, or combinations thereof. In the present embodiment, themask layer214 includes silicon nitride and is formed by a chemical vapor deposition (CVD) process. In various examples, the silicon nitride can be formed by physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), other suitable methods, and/or combinations thereof. The CVD process, for example, may use chemicals including Hexachlorodisilane (HCD or Si2Cl6), Dichlorosilane (DCS or SiH2Cl2), Bis(TertiaryButylAmino) Silane (BTBAS or C8H22N2Si) and Disilane (DS or Si2H6).

Formed over themask layer214 is aphotoresist layer216. Thephotoresist layer216 is formed by any suitable process to any suitable thickness.

Referring toFIGS. 3A and 3B, fin structure218 (including a plurality offins218a,218b, and218c) is formed by any suitable process, such as a photolithography and etching process. For example, in the present embodiment, thefin structure218 is formed by exposing thephotoresist layer216 to a pattern, performing a post-exposure bake process, and developing thephotoresist layer216 to form a masking element including thephotoresist layer216 and themask layer214. Thephotoresist layer216 patterning may include processing steps of photoresist coating, soft baking, mask aligning, exposing pattern, post-exposure baking, developing photoresist, and hard baking. The patterning may also be implemented or replaced by other proper methods, such as maskless photolithography, electron-beam writing, ion-beam writing, and molecular imprint. The masking element (including thephotoresist layer216 and the mask layer214) may then be used in an etching process to etch thefin structure218 into thesubstrate210. The etching process uses the patternedmask layer214 to define the area to be etched and to protect other regions of the3D capacitor200. The etching process may include a wet etching process, a dry etching process, or a combination thereof. Thefin structure218 may be formed by an etching process using a reactive ion etch (RIE) and/or other suitable process. In one example, a hydrofluoric acid (HF) or buffered HF may be used to etch thedielectric layer212 to expose thesubstrate210 according to the pattern defined by themask layer214. In one example, a dry etching process used to etch thesubstrate210 includes a chemistry including fluorine-containing gas. In furtherance of the example, the chemistry of the dry etch includes CF4, SF6, or NF3. Alternatively, thefin structure218 is formed by a double-patterning lithography (DPL) process. DPL is a method of constructing a pattern on a substrate by dividing the pattern into two interleaved patterns. DPL allows enhanced feature (e.g., fin) density. Various DPL methodologies may be used including double exposure (e.g., using two mask sets).

Referring toFIGS. 4A and 4B, thedielectric layer212 and themask layer214 are removed to expose top portions of eachfin218a,b,c, of thefin structure218. Thedielectric layer212 and themask layer214 may be removed by any suitable process. For example, removing thedielectric layer212 and themask layer214 may include a wet etching process, a dry etching process, or a combination thereof.

Referring toFIGS. 5A and 5B, animplantation process220 is performed on the3D capacitor200 to dope/implant thefin structure218 and thereby form a low-resistance surface221 on thefin structure218. Theimplantation process220 may include using dopants, such as boron, BF2, phosphorus, arsenic, or any other suitable implantation species to provide for a low-resistance surface221. In some embodiments, this is accomplished via ion implantation of boron or phosphorous, at an energy between about 5 to 150 KeV, at a dose between about 1E15 to 1E 16 atoms/cm2.

Referring toFIGS. 6A and 6B, deposited over the substrate210 (and over the low-resistance surface221 of the fin structure218) is aninsulation material222. Theinsulation material222 is deposited such that theinsulation material222 surrounds and isolates eachfin218a,b,cof thefin structure218 from other fins. Theinsulation material222 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, low k materials, air gap, other suitable material, or combinations thereof. In the present embodiment, theinsulation material222 includes silicon oxide. The silicon oxide can be deposited by a CVD process. In various examples, the silicon oxide can be formed by physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), other suitable methods, and/or combinations thereof. The silicon oxide may be alternatively formed by a high aspect ratio process (HARP). In various embodiments, an optional thermal oxide trench liner may be grown to improve the trench interface. The CVD process, for example, may use chemicals including Hexachlorodisilane (HCD or Si2Cl6), Dichlorosilane (DCS or SiH2Cl2), Bis(TertiaryButylAmino) Silane (BTBAS or C8H22N2Si) and Disilane (DS or Si2H6). Theinsulation material222 may have a multi-layer structure, for example, a thermal oxide liner layer with silicon nitride formed over the liner.

Referring toFIGS. 7A and 7B, a planarizing process is performed on the3D capacitor200. In one embodiment, the planarizing process includes a chemical mechanical polishing (CMP) process applied to the3D capacitor200 to remove excessive portions of theinsulation material222. The planarizing process may be performed such that theinsulation material222 is removed, thus exposing a top portion of eachfin218a,b,c, of thefin structure218.

Referring toFIGS. 8A and 8B, an etching process is used to etch-backexcessive insulation material222 between eachfin218a,b,cof thefin structure218, thereby exposing first and second sidewalls of each fin of thefin structure218. The etching process may include a wet etching, a dry etching process, or a combination thereof. In one example, the dry etching process used to etch theinsulation material222 may include a chemistry including fluorine-containing gas. In furtherance of the example, the chemistry of the dry etch includes CF4, SF6, or NF3.

Referring toFIGS. 9A and 9B, the3D capacitor200 includes adielectric layer224. Thedielectric layer224 traverses thefin structure218. In some embodiments, thedielectric layer224 may comprise silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectric. High-k dielectrics comprise certain metal oxides. Examples of metal oxides used for high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and mixtures thereof. In the present embodiment, thedielectric layer224 is a high-k dielectric layer comprising HfO_x. Thedielectric layer224 may be formed using a suitable process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, UV-ozone oxidation, or combinations thereof. Thedielectric layer224 may further comprise an interfacial layer (not shown) to reduce damage between thedielectric layer224 and thesubstrate210 and/orfin structure218. The interfacial layer may comprise silicon oxide.

Referring toFIGS. 10A and 10B, the3D capacitor200 includes afirst electrode226 formed on a first portion of thefin structure218 and asecond electrode228 formed on a second portion of thefin structure218. The first and second portion offin structure218 are different. In the illustrated embodiment, the first portion includes a portion offin218aand the second portion includes a portion offins218b,c. Thefirst electrode226 and thesecond electrode228 include any suitable conductive material. For example, the first andsecond electrodes226,228, include Al, Cu, and W, other conductive materials, or combinations thereof.

The first andsecond electrodes226,228, may be formed by any suitable process, including deposition, lithography patterning, and etching processes. The deposition processes include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plating, other suitable methods, or combinations thereof. The lithography patterning processes include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof. Alternatively, the lithography exposing process is implemented or replaced by other methods, such as maskless photolithography, electron-beam writing, and ion-beam writing. In yet another alternative, the lithography patterning process could implement nanoimprint technology. The etching processes include dry etching, wet etching, and/or other etching methods.

As illustrated inFIGS. 10A and 10B, the3D capacitor200 comprises asubstrate210 including afin structure218 including a plurality offins218a,b,c. Although the current embodiment illustrates three fins (218a,b,c) more/less fins are contemplated. Thesubstrate210 and thefin structure218 includes a low-resistance surface221. The low-resistance surface221 is formed on the top portion/layer of thesubstrate210 and thefin structure218. Further, the low-resistance surface221 is formed on the sidewalls of eachfin218a,b,c, of thefin structure218. The3D capacitor200 further includes an insulatingmaterial222 disposed in a region between eachfin218a,b,cof thefin structure218 and on the low-resistance surface221. Formed over thefin structure218 and the low-resistance surface221 is adielectric layer224. Thedielectric layer224 traverses eachfin218a,b,cof thefin structure218. Formed over thedielectric layer224 is afirst electrode226. Thefirst electrode226 is formed in a central region of at least one fin (e.g.,218a) of thefin structure218. In the illustrated embodiment, thefirst electrode226 is in direct contact with the low-resistance surface221 of the first fin (e.g.,218a) which underlies thefirst electrode226 such that a current can pass between thefirst electrode226 and thefin structure218 through the low-resistance surface221. Formed on a second portion of thefin structure218 is asecond electrode228. Thesecond electrode228 is formed on thedielectric layer224 thereby being isolated from thefin structure218. Thesecond electrode228 is formed along the length offins218b,c, on a second portion of thefin structure218 and traverses thefin structure218. In the illustrated embodiment, thesecond electrode228 is also formed on thedielectric layer224 in the region between thefins218a,b,c, of thefin structure218. In the illustrated embodiment, the first andsecond electrodes226,228 are formed such that they do not have one fin of thefin structure218 in common. The first andsecond electrodes226,228 are isolated one from the other.

The embodiment ofFIGS. 10A and 10B provides for a metal insulator semiconductor (MIS) capacitor. As illustrated, thefirst electrode226 provides connectivity to thesubstrate210 including thefin structure218 through the low-resistance surface221. Thesubstrate210 including the fin structure218 (having the low-resistance surface221) being separated by thedielectric layer224 from thesecond electrode228 provides for a MIS capacitor. It is understood that although the3D capacitor200 is illustrated in the present embodiment ofFIGS. 10A and 10B includes only three fins, the3D capacitor200 may include any number of one or more fins, depending upon design requirements. Further, it is understood that although in the illustrated embodiment the first electrode is formed on only one fin, the first electrode may be formed on more than one fin, depending on design requirements.

Referring toFIG. 11, amethod300 for fabricating a semiconductor device is described according to various aspects of the present disclosure. The embodiment ofmethod300 may include similar process steps as an embodiment of themethod100 which is disclosed above. In disclosing the embodiment ofmethod300, some details regarding processing and/or structure may be skipped for simplicity if they are similar to those described in the embodiment ofmethod100.

In the present embodiment, themethod300 is for fabricating an integrated circuit device that includes a 3D capacitor. Themethod300 begins at block302 where a substrate is provided. Atblock304, a fin structure is formed over the substrate. The formation of the fin structure may include patterning a mask layer and etching the semiconductor substrate using the mask layer. At block306, an insulation material is deposited on the fin structure. The insulation material may be deposited such that it covers the fin structure and substantially fills regions between each fin of the fin structure. A planarizing process may be subsequently performed such that the top surface of the dielectric layer is planarized, exposing a top portion of the fin structure. The method continues with block308 where an etching process is performed on the insulation material such that a portion of the fin structure is exposed. Atblock310, the fin structure is implanted to form a low-resistance surface on the fin structure. Atblock312, a dielectric layer is formed over the low-resistance surface of the fin structure. Themethod300 continues withblock314 where a first electrode is formed on a first portion of the fin structure and a second electrode is formed on a second portion of the fin structure. The first and second portions are different. Themethod300 continues with block316 where fabrication of the integrated circuit device is completed. Additional steps can be provided before, during, and after themethod300, and some of the steps described can be replaced or eliminated for other embodiments of the method. The discussion that follows illustrates various embodiments of an integrated circuit device that can be fabricated according to themethod300 ofFIG. 11.

FIGS. 12A,B-18A,B illustrate diagrammatic cross-sectional side views of one embodiment of asemiconductor device400 at various stages of fabrication according to themethod300 ofFIG. 11. Thesemiconductor device400 ofFIGS. 12A,B-18A,B is similar in certain respects to thesemiconductor device200 ofFIGS. 2A,B-10A,B. Accordingly, similar features inFIGS. 2A,B-10A,B andFIGS. 12A,B-18A,B are identified by the same reference numerals for clarity and simplicity.

Referring toFIGS. 12A and 12B, the3D capacitor400 includes asubstrate210. In the present embodiment, thesubstrate210 defined in the3D capacitor400 is substantially similar to thesubstrate210 of the3D capacitor200 in terms of composition, formation and configuration. In an alternative embodiment, they are different. With further reference toFIGS. 12A and 12B, the3D capacitor400 also includes adielectric layer212, amask layer214, and aphotoresist layer216. In the present embodiment, thedielectric layer212, themask layer214, and thephotoresist layer216 defined in the3D capacitor400 are substantially similar to thedielectric layer212, themask layer214, and thephotoresist layer216 of the3D capacitor200 in terms of composition, formation and configuration. In an alternative embodiment, they are different.

Referring toFIGS. 13A and 13B, fin structure218 (including a plurality offins218a,218b, and218c) is formed by any suitable process, such as a photolithography and etching process. In the present embodiment, the process that formsfin structure218 of3D capacitor400 is substantially similar to the process that forms thefin structure218 of3D capacitor200. In an alternative embodiment, they are different.

Referring toFIGS. 14A and 14B, deposited over thesubstrate210 is aninsulation material222. In the present embodiment, theinsulation material222 defined in the3D capacitor400 is substantially similar to theinsulation material222 of the3D capacitor200 in terms of composition, formation and configuration. In an alternative embodiment, they are different.

Referring toFIGS. 15A and 15B, a planarizing process is performed on the3D capacitor200. In one embodiment, the planarizing process includes a chemical mechanical polishing (CMP) process applied to the3D capacitor200 to remove excessive portions of theinsulation material222. The planarizing process may be performed such that theinsulation material222, thedielectric layer212, and thehard mask214 are removed, thus exposing a top surface of eachfin218a,b,c, of thefin structure218.

Referring toFIGS. 16A and 16B, an etching process is used to etch-backexcessive insulation material222 between eachfin218a,b,cof thefin structure218, thereby exposing first and second sidewalls of each fin of thefin structure218. In the present embodiment, the etching process that is used to etch-backexcessive insulation material222 of3D capacitor400 is substantially similar to the etching process that is used to etch-backexcessive insulation material222 of3D capacitor200. In an alternative embodiment, they are different.

Referring toFIGS. 16A and 16B, animplantation process220 is performed on the3D capacitor400 to implant thefin structure218 and thereby form a low-resistance surface221 on thefin structure218. In the present embodiment, theimplantation process220 that is used to implant thefin structure218 of3D capacitor400 is substantially similar to theimplantation process220 that is used to implant thefin structure218 of3D capacitor200. In an alternative embodiment, they are different.

Referring toFIGS. 17A and 17B, the3D capacitor400 includes adielectric layer410. Thedielectric layer410 traverses thefin structure218. In some embodiments, thedielectric layer410 may comprise silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectric. High-k dielectrics comprise certain metal oxides. Examples of metal oxides used for high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and mixtures thereof. In the present embodiment, thedielectric layer410 is a high-k dielectric layer comprising HfO_x. Thedielectric layer410 may be formed using a suitable process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, UV-ozone oxidation, or combinations thereof. Thedielectric layer410 may further comprise an interfacial layer (not shown) to reduce damage between thedielectric layer410 and thesubstrate210 and/orfin structure218. The interfacial layer may comprise silicon oxide.

Still referring toFIGS. 17A and 17B, the3D capacitor400 further includes afirst electrode412 formed on a first portion of thefin structure218. In the illustrated embodiment, the first portion includes a portion offins218a,b,c. Thefirst electrode412 includes, for example, a conductive material such as Al, Cu, and W, other suitable conductive materials, or combinations thereof. Thefirst electrode412 may be formed by any suitable process, including deposition, lithography patterning, and etching processes. The deposition processes include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plating, other suitable methods, or combinations thereof. The lithography patterning processes include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof. Alternatively, the lithography exposing process is implemented or replaced by other methods, such as maskless photolithography, electron-beam writing, and ion-beam writing. In yet another alternative, the lithography patterning process could implement nanoimprint technology. The etching processes include dry etching, wet etching, and/or other etching methods.

With further reference toFIGS. 17A and 17B, the3D capacitor400 also includesspacers414 formed on two sidewalls of thefirst electrode412. Thespacers414 traverse eachfin218a,b,cof thefin structure218. Thespacers414 are formed by a suitable process to a suitable thickness. For example, a dielectric layer, such as a silicon oxide layer, is blanket deposited over the3D capacitor400; and then, the silicon oxide layer is etched to remove the silicon oxide layer to formspacers414 as illustrated inFIGS. 17A and 17B. Alternatively, thespacers414 include another dielectric material, such as silicon nitride, silicon oxynitride, or combinations thereof.

Referring toFIGS. 18A and 18B, the3D capacitor400 includes asecond electrode416 formed on a second portion of thefin structure218. As illustrated, The first portion (that includes the first electrode412) and second portion (that includes the second electrode416) offin structure218 are different. In the illustrated embodiment, the second portion includes a portion offins218a,b,c. Thesecond electrode416 includes, for example, a conductive material such as Al, Cu, and W, other suitable conductive materials, or combinations thereof. Thesecond electrode416 may be formed by any suitable process, including deposition, lithography patterning, and etching processes. The deposition processes include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plating, other suitable methods, or combinations thereof. The lithography patterning processes include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof. Alternatively, the lithography exposing process is implemented or replaced by other methods, such as maskless photolithography, electron-beam writing, and ion-beam writing. In yet another alternative, the lithography patterning process could implement nanoimprint technology. The etching processes include dry etching, wet etching, and/or other etching methods.

As illustrated inFIGS. 18A and B, the3D capacitor400 comprises asubstrate210 including afin structure218 including a plurality offins218a,b,c. Although the current embodiment illustrates three fins (218a,b,c) more/less fins are contemplated. Thefin structure218 includes a low-resistance surface221 on a portion of the sidewalls of eachfin218a,b,c, of the fin structure. The low-resistance surface221 is formed on the top portion/layer of thefin structure218. The3D capacitor400 further includes an insulatingmaterial222 disposed in a region between eachfin218a,b,cof thefin structure218 on thesubstrate210. Formed over a first portion of thefin structure218 including the low-resistance surface221 is adielectric layer410. Thedielectric layer410 traverses eachfin218a,b,cof thefin structure218. Formed over thedielectric layer410 is afirst electrode412. Thefirst electrode412 traverses eachfin218a,b,cof thefin structure218 and is isolated from thefin structure218 by thedielectric layer410. Formed on the sidewalls of thefirst electrode412 and on a portion of eachfin218a,b,cof thefin structure218 arespacers414 which serve to isolate thefirst electrode412 from thesecond electrode416, which is formed on the opposing side of one of thespacers414. Thesecond electrode416 is formed on a portion of thefin structure218 and traverses a plurality offins218a,b,c. In the illustrated embodiment, thesecond electrode416 is formed directly on the low-resistance surface221 of the plurality offins218a,b,cof thefin structure218, such that a current can pass between thesecond electrode416 and thefin structure218 through the low-resistance surface221. Further the second electrode is formed on the insulatingmaterial222 in the region between eachfin218a,b,c, of thefin structure218. Thesecond electrode416 includes a surface that is in direct contact with a surface of thespacers414. The first andsecond electrodes412,416 are formed such that they are parallel one to the other and on at least one common fin (e.g.,fins218a,b,c) of thefin structure218. The first andsecond electrodes412,416 are isolated one from the other.

The embodiment ofFIGS. 18A and 18B provides for a metal insulator metal (MIM) capacitor and a metal insulator semiconductor (MIS) capacitor. As illustrated, thefirst electrode412 and thesecond electrode416 being separated byspacer414 provide for a MIM capacitor. Further, thefirst electrode412 and thesubstrate210 including thefin structure218 being separated by thedielectric layer410 provide for a MIS capacitor. It is understood that although the3D capacitor400 is illustrated inFIGS. 18A and 18B with only three fins, the3D capacitor400 may include one or more fins, depending upon design requirements. Further, it is understood that although in the illustrated embodiment, the first and second electrodes have all fins in common (i.e., they are depicted as sharing each and every fin of the fin structure) in certain embodiments, the first and second electrodes may have no fins in common or only some fins in common, depending on design requirements.

The3D capacitor200,400 may include additional features, which may be formed by subsequent processing. For example, various contacts/vias/lines and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) may be formed over thesubstrate210, configured to connect the various features or structures of the3D capacitor200,400. The additional features may provide electrical interconnection to the3D capacitor200,400. For example, a multilayer interconnection includes vertical interconnects, such as conventional vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may implement various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure.

The3D capacitors200,400 can be used for various functions such as for decoupling capacitance and high-frequency noise filters in mixed-signal applications, for decoupling capacitance in microprocessor applications, for storage retention in memory applications, and for oscillators, phase-shift networks, bypass filters, and coupling capacitance in radio frequency (RF) applications. It is understood that the3D capacitors200,400 are included in a semiconductor device/integrated circuit that includes other features and structures such as transistors, inductors, passivation layers, bonding pads, and packaging, but the illustrated embodiments are simplified for the sake of simplicity and clarity.

Thus, provided is a 3D capacitor. An exemplary 3D capacitor includes a substrate including a fin structure, the fin structure including a plurality of fins. The 3D capacitor further includes an insulation material disposed on the substrate and between each of the plurality of fins. The 3D capacitor further includes a dielectric layer disposed on each of the plurality of fins. The 3D capacitor further includes a first electrode disposed on a first portion of the fin structure. The first electrode being in direct contact with a surface of the fin structure. The 3D capacitor further includes a second electrode disposed on a second portion of the fin structure. The second electrode being disposed directly on the dielectric layer and the first and second portions of the fin structure being different.

In some embodiments, the dielectric layer is disposed on the insulation material and between each of the plurality of fins of the fin structure. In certain embodiments, the first portion includes a first fin of the plurality of fins of the fin structure, the second portion includes second and third fins of the plurality of fins of the fin structure, and the first, second, and third fins are each different fins. In various embodiments, the first electrode is disposed in a central region of the first fin, and the second electrode is disposed along the length of the second and third fins. In further embodiments, the first electrode is on a different fin than the second electrode. In some embodiments, the first portion includes only one fin of the plurality of fins, the second portion includes more than one fin of the plurality of fins, and the first and second portions do not have any fins in common. In various embodiments, the first and second electrodes include a material selected from the group consisting of Al, Cu, and W

Also provided is a alternative embodiment of a 3D capacitor. The exemplary 3D capacitor includes a semiconductor substrate and a fin structure including one or more fins formed on the semiconductor substrate. The 3D capacitor further includes an insulator material formed between each of the one or more fins. The 3D capacitor further includes a dielectric layer formed on a first portion of the fin structure and a first electrode formed on the dielectric layer. The 3D capacitor further includes spacers formed on sidewalls of the first electrode. The first and second portions are different. The second electrode includes a surface that is in direct contact with a surface of the spacers.

In some embodiments, the semiconductor substrate is a bulk silicon substrate. In certain embodiments, the second electrode is formed directly on the fin structure and directly on the insulating material. In various embodiments, the first electrode traverses each of the one or more fins, and the second electrode traverses each of the one or more fins. In some embodiments, the semiconductor substrate and the fin structure include silicon.

Also provided is a method of forming a 3D capacitor. The method includes providing a substrate and forming a fin structure including one or more fins on the substrate. The method further includes depositing an insulation material on the substrate and on the fin structure. The insulation material substantially filling a region between each of the one or more fins. The method further includes removing a portion of the insulation material from the region between each of the one or more fins such that a portion of each of the one or more fins is exposed. The method further includes forming a dielectric layer over each of the one or more fins. The method further includes forming a first electrode on a first portion of the fin structure and forming a second electrode on a second portion of the fin structure. The first and second portions are different and the first and second electrodes are isolated one from the other.

In some embodiments, the method further includes after forming the fin structure and before depositing the insulation material, implanting the fin structure such that the fin structure has a low-resistance surface, wherein forming the first electrode includes forming the first electrode such that the first electrode has direct contact with the low-resistance surface of the fin structure, wherein forming the second electrode includes forming the second electrode on the dielectric layer such that the second electrode does not have direct contact with the low-resistance surface of the fin structure, and wherein the first and second electrodes do not share a common fin. In various embodiments, the method further includes after forming the fin structure and before depositing the insulation material, implanting the fin structure such that the fin structure has a low-resistance surface, wherein the first portion includes a first fin of the one or more fins of the fin structure, wherein the second portion includes second and third fins of the one or more fins of the fin structure, and wherein the first, second, and third fins are each different fins. The method further includes after removing a portion of the insulation material from the region between each of the one or more fins, implanting the fin structure such that the fin structure has a low-resistance surface, wherein forming the first electrode includes forming the first electrode such that the first electrode has direct contact with the low-resistance surface of the fin structure, wherein forming the second electrode includes forming the second electrode on the dielectric layer such that the second electrode does not have direct contact with the low-resistance surface of the fin structure, and wherein the first and second electrodes do not share a common fin. In certain embodiments, the method further includes after removing a portion of the insulation material from the region between each of the one or more fins, implanting the fin structure such that the fin structure has a low-resistance surface, and forming spacers on sidewalls of the first electrode, wherein the second electrode includes a surface that is in direct contact with a surface of the spacers.

In some embodiments, forming the first electrode includes forming the first electrode such that each of the one or more fins are traversed, and forming the second electrode includes forming the second electrode such that each of the one or more fins are traversed. In various embodiments, forming the first electrode includes forming the first electrode directly on the dielectric layer and in the region between each of the one or more fins, and forming the second electrode includes forming the second electrode directly on the low-resistance surface of the fin structure and in the region between each of the one or more fins. In certain embodiments, forming the second electrode includes forming the second electrode directly on the insulation material in the region between each of the one or more fins.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (18)

What is claimed is:

1. A device comprising:

a three-dimensional (3D) capacitor comprising:

a substrate including a top surface and a fin structure, the fin structure including first and second portions, the first portion of the fin structure including a first fin and the second portion of the fin structure including a second fin, each of the first and second fins including a fin-top surfaces and a sidewall surface;

a low-resistance layer on the top surface of the substrate, the fin-top surfaces of the first and second fins, and sidewall surfaces of the first and second fins;

an insulation material disposed over a first portion of the low-resistance layer over the top surface of the substrate between the first fin and the second fin;

a dielectric layer disposed over a second portion of the low-resistance layer, and over the insulation material;

a first electrode disposed over the first fin, the first electrode being in direct contact with the low-resistance layer on the fin-top surface of the first fin; and

a second electrode disposed over the dielectric layer that is disposed over the second fin,

wherein the first and second portions of the fin structure are different.

2. The device ofclaim 1 wherein the insulation material is disposed on opposing sides of the second fin.

3. The device ofclaim 1 wherein the first electrode is disposed in a central region of the first fin, and wherein the second electrode is disposed along the length of the second fin.

4. The device ofclaim 1, wherein the low-resistance layer comprises boron, phosphorous, or arsenic.

5. A device comprising:

a three-dimensional (3D) capacitor comprising:

a substrate including a plurality of fins, the substrate including a top surface, the plurality of fins including fin-top surfaces and sidewall surfaces, wherein the top surface, the fin-top surfaces and sidewall surfaces comprises a low-resistance surface;

an insulation material disposed on the low-resistance surface over the top surface of the substrate between each of the plurality of fins;

a dielectric layer disposed on the low-resistance surface on each of the plurality of fins;

a first electrode disposed on a first portion of the plurality of fins, the first electrode being in direct contact with the low-resistance surface on only one fin, the one fin being of the first portion; and

a second electrode disposed on a second portion of the plurality of fins, the second electrode terminating in a central area between the first portion and the second portion and without contacting the dielectric layer disposed on sidewalls of the one fin,

wherein the first and second portions do not have any fins of the plurality of fins in common.

6. The device ofclaim 5 wherein the first and second electrodes include a material selected from the group consisting of Al, Cu, and W.

7. The device ofclaim 5 wherein the low resistance surface of the one fin of the first portion includes an implanted dopant selected from the group consisting of boron, phosphorus, and arsenic.

8. The device ofclaim 5 wherein the first electrode is in direct contact with the low resistance surface of the one fin of the first portion.

9. The device ofclaim 5 wherein the insulation material and the dielectric layer include different dielectric materials.

10. The device ofclaim 5 wherein the plurality of fins and the substrate include same materials.

11. The device ofclaim 5 the second portion includes a low resistance surface.

12. The device ofclaim 5, wherein the low-resistance surface comprises boron, phosphorous, or arsenic.

13. A device comprising:

a three-dimensional (3D) capacitor comprising:

a substrate including a plurality of fins, the plurality of fins including a first portion including one or more fins and a second portion including two or more fins directly adjacent to each other;

an insulation material disposed over the substrate and between each fin of the plurality of fins;

a dielectric layer traversing each fin of the plurality of fins and the insulation material between each fin of the plurality of fins;

a first electrode extending through the dielectric layer traversing the one or more fins of the first portion of the plurality of fins, the first electrode being in physical contact with a conductive surface of only one fin, the one fin being of the one or more fins of the first portion of the plurality of fins; and

a second electrode traversing the dielectric layer disposed over the two or more fins of the second portion of the plurality of fins without contacting a portion of the dielectric layer traversing sidewalls of the one or more fins of the first portion of the plurality of fins, the second electrode traversing the dielectric layer and the insulation material disposed between the two or more fins of the second portion of the plurality of fins,

wherein a continuous low resistance surface traverses the one or more fins of the first portion of the plurality of fins and extends to and traverses the two or more fins of the second portion of the plurality of fins.

14. The device ofclaim 13 wherein the first electrode is disposed in a central region of the first portion.

15. The device ofclaim 13 wherein the first and the second electrodes include a material selected from the group consisting of Al, Cu, and W.

16. The device ofclaim 13 wherein each of the two or more fins of the second portion of the plurality of fins includes a low resistance surface.

17. The device ofclaim 13 wherein the substrate is a silicon-on-insulator (SOI) substrate.

18. The device ofclaim 13, wherein the continuous low resistance surface comprises boron, phosphorous, or arsenic.

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