US9841843B2 - Semiconductor device and driving method thereof - Google Patents

Abstract

A semiconductor device with high definition, which includes a plurality of sets each including a photosensor and a display element including a light-emitting element arranged in a matrix is provided, wherein a power supply line electrically connected to the display element also serves as a power supply line electrically connected to the photosensor. Thus, the semiconductor device with high definition can be provided without decreasing the width of each power supply line. Thus, the definition of the semiconductor device can be improved while securing the stability of the potential of the power supply line. The stability of the potential of the power supply line leads to the stability of the driving voltage of the display element and the stability of the driving voltage of the photosensor. Accordingly, the semiconductor device with high definition, high display quality, and high accuracy of imaging or detection of an object can be provided.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

One embodiment of the present invention relates to a semiconductor device including a photosensor. One embodiment of the present invention also relates to a semiconductor device including a photosensor and a display element. In particular, one embodiment of the present invention relates to a semiconductor device including a light-emitting element as a display element. Further, one embodiment of the present invention relates to a driving method of a semiconductor device. Still further, one embodiment of the present invention relates to an electronic device equipped with a semiconductor device.

2. Description of the Related Art

An example of a semiconductor device including a plurality of sensors that detect light (each also referred to as a “photosensor”) arranged in a matrix is a solid-state imaging device (also referred to as an image sensor) used in electronic devices such as digital still cameras or mobile phones.

In particular, a semiconductor device including a plurality of sets each including a photosensor and a display element arranged in a matrix, which has an image displaying function in addition to the imaging function, is also referred to as a touch panel, a touch screen, or the like (hereinafter simply referred to as a “touch panel”). In the touch panel, a region where the sets each including a photosensor and a display element are arranged in a matrix is an image display, data input region.

A touch panel having an image display, data input region where sets each including a photosensor and a display element including an organic light-emitting element are arranged in a matrix has been proposed (see FIGS. 8 and 9 in Patent Document 1).

In the touch panel using such a display element including a light-emitting element, first, the light-emitting elements arranged in a matrix are made to emit light. When an object to be detected exists, the light is blocked by the object and partly reflected. The photosensors arranged in a matrix detect light reflected by the object. In this manner, the touch panel captures an image of the object and detects the position of the object.

REFERENCE

• [Patent Document 1] Japanese Published Patent Application No. 2010-153834

SUMMARY OF THE INVENTION

According to the structure described inPatent Document 1, at least a wiring to which a signal for controlling the display element including an organic light-emitting element is input and a power supply line thereof, and a wiring to which a signal for controlling the photosensor is input and a power supply line thereof are provided. Thus, the number of wirings provided in the image display, data input region is increased, leading to a drawback in the improvement of the definition of a semiconductor device.

It is an object of one embodiment of the present invention to provide a semiconductor device with high definition, which includes a plurality of sets each including a photosensor and a display element including a light-emitting element arranged in a matrix.

One embodiment of the present invention is a semiconductor device in which a photosensor and a display element including a light-emitting element are provided, and a power supply line which is electrically connected to the display element including the light-emitting element also serves as a power supply line which is electrically connected to the photosensor.

One embodiment of the present invention is a semiconductor device in which a plurality of sets each including a photosensor and a display element including a light-emitting element are arranged in a matrix, and a power supply line which is electrically connected to the display element including the light-emitting element also serves as a power supply line which is electrically connected to the photosensor per set.

One embodiment of the present invention is a semiconductor device in which a plurality of sets each including a photosensor and a display element including a light-emitting element are arranged in a matrix of m (m is a natural number greater than or equal to 2) rows by n (n is a natural number greater than or equal to 2) columns. The photosensor includes a photoelectric converter and an amplifier which is electrically connected to the photoelectric converter. The display element including the light-emitting element includes a controller which is electrically connected to the light-emitting element. The amplifier and the controller are electrically connected to the same power supply line per set.

One embodiment of the present invention is a semiconductor device in which a plurality of sets each including a photosensor and a display element including a light-emitting element are arranged in a matrix of m (m is a natural number greater than or equal to 2) rows by n (n is a natural number greater than or equal to 2) columns, and a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, a sixth wiring, a seventh wiring, and a eighth wiring are provided. The photosensor includes a photoelectric converter and an amplifier which is electrically connected to the photoelectric converter. The display element including the light-emitting element includes a controller which is electrically connected to the light-emitting element. The amplifier includes a first transistor, a second transistor, and a third transistor. The second transistor and the third transistor are electrically connected in series between the first wiring and the second wiring. A gate of the second transistor is electrically connected to one of a source and a drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to one of a pair of electrodes of the photoelectric converter. The other electrode of the pair of electrodes of the photoelectric converter is electrically connected to the fourth wiring. A gate of the first transistor is electrically connected to the third wiring, and a gate of the third transistor is electrically connected to the fifth wiring. The controller includes a fourth transistor and a fifth transistor. A gate of the fourth transistor is electrically connected to the sixth wiring, one of a source and a drain of the fourth transistor is electrically connected to the eighth wiring, and the other of the source and the drain of the fourth transistor is electrically connected to a gate of the fifth transistor. One of a source and a drain of the fifth transistor is electrically connected to the first wiring, and the other of the source and the drain of the fifth transistor is electrically connected to one of a pair of electrodes of the light-emitting element. The other of the pair of electrodes of the light-emitting element is electrically connected to the seventh wiring. The first wiring is a power supply line.

In the above structure, the controller may further include a sixth transistor, one of a source and a drain of the sixth transistor may be electrically connected to one of the pair of electrodes of the light-emitting element, and the other of the source and the drain of the sixth transistor may be electrically connected to the first wiring. A gate of the sixth transistor may be electrically connected to a ninth wiring.

In the above structure, the controller may further include a capacitor, one of a pair of electrodes of the capacitor may be electrically connected to the gate of the fifth transistor, and the other of the pair of electrodes of the capacitor may be electrically connected to one of the source and the drain of the fifth transistor. The other of the pair of electrodes of the capacitor may be electrically connected to the first wiring. The other of the pair of electrodes of the capacitor may be electrically connected not to one of the source and the drain of the fifth transistor but to a tenth wiring.

In any of the first to sixth transistors, a channel can be formed in an oxide semiconductor layer. A channel can be formed in an oxide semiconductor layer in one or more of the first to sixth transistors, and a channel can be formed in a silicon layer in the other transistor(s).

Each set may include one display element and one photosensor; two or more display elements and one photosensor; two or more photosensors and one display element; or two or more display elements and two or more photosensors. That is, the numbers of display elements and photosensors included in one set are not limited.

The light-emitting element is an element whose luminance is controlled by current or voltage; a light-emitting diode, an organic light-emitting diode (OLED), or the like can be used.

A photodiode or a phototransistor can be used as the photoelectric converter.

One embodiment of the present invention is the followingdriving method 1 ordriving method 2 of a semiconductor device in which a plurality of sets each including a photosensor and a display element including a light-emitting element are arranged in a matrix of m (m is a natural number greater than or equal to 2) rows by n (n is a natural number greater than or equal to 2) columns, the photosensor includes a photoelectric converter and an amplifier which is electrically connected to the photoelectric converter, the display element including the light-emitting element includes a controller which is electrically connected to the light-emitting element, and the amplifier and the controller are electrically connected to the same power supply line per set.

(Driving Method 1)

The amplifier performs a reset operation of discharging electric charge stored in the amplifier, a storage operation of storing electric charge corresponding to the amount of photocurrent flowing through the photoelectric converter, and a selection operation of reading an output signal including the amount of the electric charge as data. All the light-emitting elements are made to emit light to irradiate an object with light, and then, the photosensors in the p-th (p is a natural number less than or equal to m) row detect the amount of light reflected by the object. During the period in which the light-emitting elements emit light, the reset operation and the storage operation are performed in the photosensors in the p-th row, and then, all the light-emitting elements are made not to emit light, and during the period in which the light-emitting elements do not emit light, the reset operation and the storage operation are performed in the photosensors in the (p+1)-th row. The selection operation described above is performed sequentially by the photosensors in all the rows, then, a difference between output signals obtained from the photosensors in adjacent rows is obtained. With the difference, a captured image of the object is generated and a position of the object is detected.

According to the above-describeddriving method 1, all the light-emitting elements are made to emit light to irradiate an object with light, and during the period in which the light-emitting elements emit light, the reset operation and the storage operation are performed in the photosensors in the p-th row in order to detect the amount of light reflected by the object. And then, all the light-emitting elements are made not to emit light, and during the period in which the light-emitting elements do not emit light, the reset operation and the storage operation are performed in the photosensors in the (p+1)-th row. Alternatively, the followingdriving method 2 may be employed: all the light-emitting elements are made to emit light to irradiate an object to be detected, and during the period in which the light-emitting elements emit light, the reset operation and the storage operation are performed in the photosensors in the q-th column (q is a natural number less than or equal to n), and then, all the light-emitting elements are made not to emit light, and during the period in, which the light-emitting elements do not emit light, the reset operation and the storage operation are performed in the photosensors in the (q+1)-th column.

(Driving Method 2)

The amplifier performs a reset operation of discharging electric charge stored in the amplifier, a storage operation of storing electric charge corresponding to the amount of photocurrent flowing through the photoelectric converter, and a selection operation of reading an output signal including the amount of the electric charge as data. All the light-emitting elements are made to emit light to irradiate an object with light, and then, the photosensors in the q-th (q is a natural number less than or equal to n) column detect the amount of light reflected by the object. During the period in which the light-emitting elements emit light, the reset operation and the storage operation are performed in the photosensors in the q-th column, and then, all the light-emitting elements are made not to emit light, and during the period in which the light-emitting elements do not emit light, the reset operation and the storage operation are performed in the photosensors in the (q+1)-th column. The selection operation described above is performed sequentially by the photosensors in all the rows, then, a difference between output signals obtained from the photosensors in adjacent columns is obtained. With the difference, a captured image of the object is generated and a position of the object is detected.

(Variations on Light-Emission Timing of Light-Emitting Element)

In thedriving method 1, in order to perform the reset operation and the storage operation with the photosensors in the p-th row, the light-emitting elements may emit light simultaneously or sequentially row-by-row.

Similarly, in thedriving method 2, in order to perform the reset operation and the storage operation with the photosensors in the q-th column, the light-emitting elements may emit light simultaneously or sequentially row-by-row.

Alternatively, for the reset operation and the storage operation with the photosensors in the p-th row in thedriving method 1, only the light-emitting elements in the p-th row and the light-emitting elements in the row(s) near the p-th row among all of the light-emitting elements may emit light. Similarly, for the reset operation and the storage operation with the photosensors in the (p+1)-th row in thedriving method 1, only the light-emitting elements in the (p+1)-th row and the light-emitting elements in the row(s) near the (p+1)-th row among all of the light-emitting elements may emit no light.

(Variations on Timing of Reset Operation and Storage Operation of Photosensor)

The drivingmethods 1 and 2 employ a driving method in which the timing of the reset operation and the storage operation differs in adjacent rows or columns, which is a rolling shutter system. On the other hand, a driving method in which the timing of the reset operation and the storage operation is the same in all the rows or columns is a global shutter system.

In thedriving method 1, the reset operation and the storage operation may be performed either sequentially row-by-row or at the same time in plural rows. For example, with light emission of the light-emitting elements, the reset operation and the storage operation can be performed sequentially on the photosensors in the odd-numbered rows row-by-row, and with no light emission of the light-emitting elements, the reset operation and the storage operation can be performed sequentially on the photosensors in the even-numbered rows row-by-row. In that case, the photosensors either only in the odd-numbered rows or only in the even-numbered rows are driven by a rolling shutter system. Alternatively, with light emission of the light-emitting elements, the reset operation and the storage operation can be performed at the same time on the photosensors in the odd-numbered rows, and with no light emission of the light-emitting elements, the reset operation and the storage operation can be performed at the same time on the photosensors in the even-numbered rows. In that case, the photosensors in the odd-numbered rows or the photosensors in the even-numbered rows are driven by a global shutter system.

In thedriving method 2, the reset operation and the storage operation may be performed either sequentially column-by-column or at the same time in plural columns. For example, with light emission of the light-emitting elements, the reset operation and the storage operation can be performed sequentially on the photosensors in the odd-numbered columns column-by-column, and with no light emission of the light-emitting elements, the reset operation and the storage operation can be performed sequentially on the photosensors in the even-numbered columns column-by-column. In that case, the photosensors either only in the odd-numbered columns or only in the even-numbered columns are driven by a rolling shutter system. Alternatively, with light emission of the light-emitting elements, the reset operation and the storage operation can be performed at the same time on the photosensors in the odd-numbered columns, and with no light emission of the light-emitting elements, the reset operation and the storage operation can be performed at the same time on the photosensors in the even-numbered columns. In that case, the photosensors in the odd-numbered columns or the photosensors in the even-numbered columns are driven by a global shutter system.

In each of the drivingmethods 1 and 2, the order of the timing of making the light-emitting elements to emit light and the timing of making the light-emitting elements not to emit light may be reversed.

The power supply line which is electrically connected to the photosensor also serves as the power supply line which is electrically connected to the display element including the light-emitting element, whereby the number of power supply lines included in a semiconductor device can be reduced. In this manner, the width of each power supply line can be increased and a semiconductor device with high definition can be provided. Thus, the definition of the semiconductor device can be improved while securing the stability of the potential of the power supply line. The stability of the potential of the power supply line leads to the stability of the driving voltage of the display element including the light-emitting element and the stability of the driving voltage of the photosensor. That is, even in a high-definition semiconductor device, the driving voltage of the display element including the light-emitting element and the driving voltage of the photosensor can be stabilized. Accordingly, a semiconductor device with high definition, high display quality, and high accuracy of imaging or detection of an object can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A and 1B are circuit diagrams illustrating structures of a set including a photosensor and a display element including a light-emitting element, andFIGS. 1C and 1D are circuit diagrams illustrating structures of a plurality of sets arranged in a matrix;

FIGS. 2A and 2B are circuit diagrams illustrating configurations of a set including a photosensor and a display element including a light-emitting element;

FIG. 3 is a circuit diagram illustrating a configuration of adjacent two sets among a plurality of sets arranged in a matrix;

FIGS. 4A to 4D are circuit diagrams illustrating configurations of a display element including a light-emitting element;

FIGS. 5A to 5C are circuit diagrams illustrating configurations of a photosensor;

FIG. 6 is a top view illustrating a structure of a set including a photosensor and a display element including a light-emitting element;

FIG. 7 is a top view illustrating a structure of adjacent two sets among a plurality of sets arranged in a matrix;

FIGS. 8A to 8C are cross-sectional views illustrating structures of a photosensor and a display element including a light-emitting element;

FIGS. 9A and 9B are timing charts each for describing an operation of a photosensor;

FIGS. 10A and 10B are timing charts each for describing an operation of a set including a photosensor and a display element including a light-emitting element;

FIGS. 11A and 11B are timing charts each for describing an operation of a set including a photosensor and a display element including a light-emitting element;

FIGS. 12A and 12B are timing charts each for describing an operation of a set including a photosensor and a display element including a light-emitting element;

FIGS. 13A and 13B are timing charts each for describing an operation of a set including a photosensor and a display element including a light-emitting element;

FIGS. 14A and 14B are timing charts each for describing an operation of a display element including a light-emitting element;

FIGS. 15A and 15B are timing charts each for describing an operation of a display element including a light-emitting element;

FIGS. 16A to 16E are views each illustrating a crystal structure of an oxide material;

FIGS. 17A to 17C are diagrams illustrating a crystal structure of an oxide material;

FIGS. 18A to 18C are diagrams illustrating a crystal structure of an oxide material;

FIG. 19 is a graph showing the gate voltage dependency of mobility according to calculation results;

FIGS. 20A to 20C are graphs each showing the gate voltage dependency of drain current and mobility according to calculation results;

FIGS. 21A to 21C are graphs each showing the gate voltage dependency of drain current and mobility according to calculation results;

FIGS. 22A to 22C are graphs each showing the gate voltage dependency of drain current and mobility according to calculation results;

FIGS. 23A and 23B are diagrams each illustrating a cross-sectional structure of a transistor which was used in calculation;

FIGS. 24A to 24C are graphs each showing characteristics of a transistor including an oxide semiconductor film;

FIGS. 25A and 25B are graphs each showing V_g−I_dcharacteristics of a transistor ofSample 1 before and after being subjected to a BT test;

FIGS. 26A and 26B are graphs each showing V_g−I_dcharacteristics of a transistor ofSample 2 before and after being subjected to a BT test;

FIG. 27 is a graph showing the V_gdependency of I_dand field-effect mobility;

FIGS. 28A and 28B are a threshold voltage vs. substrate temperature graph and a field-effect mobility vs. substrate temperature graph, respectively;

FIG. 29 is a graph showing XRD spectra of Sample A and Sample B;

FIG. 30 is a graph of transistor off-state current vs. substrate temperature in measurement;

FIGS. 31A and 31B are diagrams illustrating a structure of a transistor;

FIGS. 32A and 32B are diagrams illustrating, a structure of a transistor.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments of the present invention are described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description and it is easily understood by those skilled in the art that the mode and details can be variously changed without departing from the scope and spirit of the present invention. Accordingly, the present invention should not be construed as being limited to the description of the embodiments below.

The terms of a “source electrode” and a “drain electrode” of the transistor interchange with each other depending on the polarity of the transistor and the levels of potentials applied to the electrodes. In general, in an n-channel transistor, an electrode to which a lower potential is applied is called a source electrode, whereas an electrode to which a higher potential is applied is called a drain electrode. Further, in a p-channel transistor, an electrode to which a lower potential is applied is called a drain electrode, whereas an electrode to which a higher potential is applied is called a source electrode. In the description below, one of a source electrode and a drain electrode is referred to as a first terminal and the other thereof is referred to as a second terminal.

Further, being “electrically connected” in this specification refers to the state where a current, a voltage, or a potential can be supplied or transmitted. Therefore, the state of being “electrically connected” means not only a state of direct connection but also a state of indirect connection through a circuit element such as a wiring, a resistor, a diode, or a transistor, where a current, a voltage, or a potential can be supplied or transmitted.

Further, independent components, which are connected to each other in a circuit diagram, may include a shared conductive film with each other, having functions of a plurality of components; for example, part of a wiring may function as an electrode.

In this specification, a state in which transistors are electrically connected in series with each other means, for example, a state in which only one of a first terminal and a second terminal of one transistor is electrically connected to only one of a first terminal and a second terminal of the other transistor. Further, a state in which transistors are electrically connected in parallel with each other means a state in which a first terminal of one transistor is electrically connected to a first terminal of the other transistor and a second terminal of the one transistor is electrically connected to a second terminal of the other transistor.

In this specification, unless otherwise specified, an off-state current of an n-channel transistor is a current which flows between a source electrode and a drain electrode of the transistor where the potential of the drain electrode is higher than those of the source electrode and a gate electrode of the transistor at a potential of the gate electrode of less than or equal to 0 V relative to the potential of the source electrode. In addition, an off-state current of a p-channel transistor is a current which flows between a source electrode and a drain electrode of the transistor where the potential of the drain electrode is lower than those of the source electrode and a gate electrode of the transistor at a potential of the gate electrode of greater than or equal to 0 V relative to the potential of the source electrode

Embodiment 1

In this embodiment, a structure of a semiconductor device according to one embodiment of the present invention is described.

(One Embodiment of Structure of Semiconductor Device)

FIG. 1A is a circuit diagram showing a structure of aset110 of aphotosensor301 and adisplay element101 including a light-emittingelement102 of a semiconductor device. Thephotosensor301 includes aphotoelectric converter302 and anamplifier303 electrically connected to thephotoelectric converter302. Thedisplay element101 including the light-emittingelement102 includes acontroller103 electrically connected to the light-emittingelement102. Theamplifier303 and thecontroller103 are electrically connected to the same power supply line VR. The power supply line VR is shared between the photosensor301 and thedisplay element101, whereby the definition of the semiconductor device can be improved.

Further, as shown inFIG. 1B, the same power supply line VR can also be shared between two adjacent sets (aset110aand aset110b). By sharing the power supply line VR between a plurality ofsets110, the definition of the semiconductor device can be further improved. The structures of thesets110aand110beach are the same as the structure of theset110, and each of thesets110aand110bis also called theset110.

FIG. 1C is a circuit diagram showing a structure of a semiconductor device in which the plurality ofsets110 whose structure is shown inFIG. 1A are arranged in a matrix of m (m is a natural number greater than or equal to 2) rows by n (n is a natural number greater than or equal to 2) columns. InFIG. 1C, m is 4 and n is 4 as an example. The power supply line VR is shared between sets per column in the longitudinal direction in the drawing.

FIG. 1D is a circuit diagram showing a structure of a semiconductor device in which the plurality ofsets110 whose structure is shown inFIG. 1B are arranged in a matrix of m (m is a natural number greater than or equal to 2) rows by n (n is a natural number greater than or equal to 2) columns. InFIG. 1D, m is 4 and n is 4 as an example. In the drawing, the power supply line VR is shared between sets per column in the longitudinal direction and is shared between adjacent columns.

Although the plurality ofsets110 each include onedisplay element101 and onephotosensor301 inFIGS. 1A to 1D, one embodiment of the present invention is not limited thereto. Theset110 may include two ormore display elements101 and onephotosensor301; two ormore photosensors301 and onedisplay element101; or two ormore display elements101 and two ormore photosensors301. That is, the numbers ofdisplay elements101 andphotosensors301 included in oneset110 are not limited.

The light-emittingelement102 is an element whose luminance is controlled by current or voltage; a light-emitting diode, an organic light-emitting diode (OLED), or the like can be used.

A photodiode or a phototransistor can be used as thephotoelectric converter302.

(One Embodiment of Specific Configurations of Amplifier and Controller)

FIG. 2A is a diagram showing an example of specific configurations of theamplifier303 and thecontroller103 in the structure shown inFIG. 1A.

Theamplifier303 includes atransistor304, atransistor305, and atransistor306. Thetransistor305 and thetransistor306 are electrically connected in series between a wiring OUT and the wiring VR. A gate of thetransistor305 is electrically connected to one of a source and a drain of thetransistor304. The other of the source and the drain of thetransistor304 is electrically connected to one of a pair of electrodes of thephotoelectric converter302. The other electrode of the pair of electrodes of thephotoelectric converter302 is electrically connected to a wiring PR. A gate of thetransistor304 is electrically connected to a wiring TX. A gate of thetransistor306 is electrically connected to a wiring SE. The node where one of the source and the drain of thetransistor304 is electrically connected to the gate of thetransistor305 is denoted by a node FD. The potential of an output signal of the amplifier303 (a signal output from the wiring OUT) is decided by the amount of electric charge stored in the node FD. In order to retain electric charge in the node FD more surely, a capacitor may be electrically connected to the node FD.

Thecontroller103 includes atransistor201 and atransistor202. A gate of thetransistor201 is electrically connected to a wiring GL. One of a source and a drain of thetransistor201 is electrically connected to a wiring SL. The other of the source and the drain of thetransistor201 is electrically connected to a gate of thetransistor202. One of a source and a drain of thetransistor202 is electrically connected to the wiring VR. The other of the source and the drain of thetransistor202 is electrically connected to one of a pair of electrodes of the light-emittingelement102. The other of the pair of electrodes of the light-emittingelement102 is electrically connected to a wiring VB. The wiring VR is a power supply line.

Further, acapacitor203 is included in thecontroller103, one of a pair of electrodes of thecapacitor203 is electrically connected to the gate of thetransistor202 and the other of the source and the drain of thetransistor201, and the other of the pair of electrodes of thecapacitor203 is electrically connected to a wiring CS inFIG. 2A; however, one embodiment of the present invention is not limited thereto. For example, the wiring CS is not necessarily provided and the other of the pair of electrodes of thecapacitor203 may be electrically connected to one of the source and the drain of the transistor202 (or the wiring VR) as shown inFIG. 4A. Configurations of only thedisplay element101 are illustrated inFIGS. 4A to 4D; in practice, likeFIG. 2A, thephotosensor301 and thedisplay element101 are electrically connected to the same wiring VR.

Further, as shown inFIG. 4B, thecapacitor203 can be omitted. For example, a transistor whose off-state current is extremely small may be used as thetransistor201, by which the potential of the gate of thetransistor202 can be retained for a long period of time, whereby thecapacitor203 functioning as a retention capacitor can be omitted. A transistor in which a channel is formed in an oxide semiconductor layer can be used as the transistor whose off-state current is extremely small. Further, instead of provision of thecapacitor203, parasitic capacitance of thetransistor202 and the like can be effectively used.

Further, the configuration of thecontroller103 is not limited to the configurations shown inFIGS. 2A, 4A, and 4B. For example, a configuration shown inFIG. 4C can be employed. The configuration of thecontroller103 shown inFIG. 4C includes atransistor204 in addition to the configuration shown inFIG. 2A. One of a source and a drain of thetransistor204 is electrically connected to one of the pair of electrodes of the light-emittingelement102, and the other of the source and the drain of thetransistor204 is electrically connected to the wiring VR. A gate of thetransistor204 is electrically connected to a wiring SA. It can be said that thetransistor204 is provided in parallel with thetransistor202.

Further alternatively, a configuration shown inFIG. 4D can be employed as the configuration of thecontroller103. The configuration of thecontroller103 shown inFIG. 4D includes a transistor205 in-addition to the configuration shown inFIG. 2A. One of a source and a drain of the transistor205 is electrically connected to the wiring VR, and the other of the source and the drain of the transistor205 is electrically connected to one of the source and the drain of thetransistor202. A gate of the transistor205 is electrically connected to a wiring ER. It can be said that the transistor205 is provided in series with thetransistor202.

In each of the configurations shown inFIGS. 4C and 4D, thecapacitor203 can be either provided as shown inFIG. 4A or omitted as shown inFIG. 4B.

Further, the configuration of theamplifier303 is not limited to the configuration shown inFIG. 2A. For example, a configuration shown inFIG. 5A can be employed. Thetransistors306 and305 are electrically connected in series in this order between the wiring OUT and the wiring VR inFIG. 2A; thetransistors305 and306 are electrically connected in series in this order between the wiring OUT and the wiring VR inFIG. 5A.

Further alternatively, any of configurations shown inFIGS. 5B and 5C can be employed as the configuration of theamplifier303. The configurations of theamplifier303 shown inFIGS. 5B and 5C include atransistor307 in addition to the configuration shown in any ofFIG. 2A andFIG. 5A.FIG. 5B is an example in which thetransistor307 is added to the configuration shown inFIG. 2A, whereasFIG. 5C is an example in which thetransistor307 is added to the configuration shown inFIG. 5A. In each of theFIGS. 5B and 5C, one of a source and a drain of thetransistor307 is electrically connected to the wiring VR, and the other of the source and the drain of thetransistor307 is electrically connected to the gate of thetransistor305. A gate of thetransistor307 is electrically connected to a wiring RE.

In any of thetransistors201,202,204,205,304,305,306, and307, a channel can be formed in an oxide semiconductor layer. A channel can be formed in an oxide semiconductor layer in one or more of thetransistors201,202,204,205,304,305,306, and307, and a channel can be formed in a silicon layer in the other transistor(s).

(Variations on Wiring Arrangement)

FIG. 2B is a diagram of the configuration shown inFIG. 2A, where the wirings VR, SE, OUT, TX, PR, SL, GL, VB, and CS are extended. InFIG. 2B, the wirings PR, TX, SE, GL, CS, and VB are arranged in parallel with each other, and the wirings SL, OUT, and VR are arranged in parallel with each other so as to intersect with the wirings PR, TX, SE, GL, CS, and VB.

An example in which the configuration shown inFIG. 2B is applied to the configuration shown inFIG. 1B where the power supply line VR is shared between two adjacent sets is shown inFIG. 3. The arrangement of the wirings is the same asFIG. 2B.

There are variations on the direction in which the wiring extends and on the arrangement of the wirings (e.g., parallel arrangement or arrangement where the wirings intersect with each other); any configuration other than the configuration shown inFIG. 2B orFIG. 3 may alternatively be employed.

Further, also in the case where any configuration shown inFIGS. 4A to 4D and/or any configuration shown inFIGS. 5A to 5C described above is/are employed instead of thecontroller103 and/or theamplifier303 inFIG. 2A, each wiring can be extended in an appropriate direction likeFIGS. 2B and 3.

As shown inFIGS. 1C and 1D, in the case where the plurality of sets each including thedisplay element101 and thephotosensor301 are arranged in a matrix, a wiring can be shared between thesets110 per row or column in the direction in which the wiring extends.

Further, wirings in which the same potential or the same signal is input can be used in common in plural sets. For example, the wiring VB can be shared between all the sets. In that case, the wiring VB can be referred to as an “electrode” instead of the “wiring”. Further, for example, the wiring PR can be shared in plural sets. As one example thereof, the wiring PR can be shared between plural sets in which the reset operation and the storage operation in thephotosensor301 are performed simultaneously.

The power supply line which is electrically connected to the photosensor also serves as the power supply line which is electrically connected to the display element including the light-emitting element as described above, whereby the number of power supply lines included in a semiconductor device can be reduced. In this manner, the width of each power supply line can be increased and a semiconductor device with high definition can be provided. Thus, the definition of the semiconductor device can be improved while securing the stability of the potential of the power supply line. The stability of the potential of the power supply line leads to the stability of the driving voltage of the display element including the light-emitting element and the stability of the driving voltage of the photosensor. That is, even in a high-definition semiconductor device, the driving voltage of the display element including the light-emitting element and the driving voltage of the photosensor can be stabilized. Accordingly, a semiconductor device with high definition, high display quality, and high accuracy of imaging or detection of an object can be provided.

This embodiment can be combined as appropriate with any other embodiment.

Embodiment 2

In this embodiment, a more specific structure of the semiconductor device according to one embodiment of the present invention is described using top views and cross-sectional views.

FIG. 6 is an example of a top view of a semiconductor device with the configuration shown inFIG. 2B. InFIG. 6, the same portions as those inFIG. 2B are denoted by the same reference symbols as those inFIG. 2B, and description thereof is omitted.FIG. 7 is an example of a top view of a semiconductor device with the configuration shown inFIG. 3. InFIG. 7, the same portions as those inFIG. 3 are denoted by the same reference symbols as those inFIG. 3, and description thereof is omitted. Further, cross-sectional views along line A1-A2, along line B1-B2, and line C1-C2 inFIGS. 6 and 7 areFIGS. 8A, 8B, and 8C, respectively. InFIG. 6,FIG. 7, andFIGS. 8A to 8C, there is a component illustrated with a size different from the actual size. InFIGS. 6 and 7, the light-emittingelement102, a substrate, an insulating layer functioning as an interlayer film, and the like are not illustrated for easy understanding of the views.

A more specific structure of the semiconductor device is described usingFIG. 6,FIG. 7, andFIGS. 8A to 8C.

An insulatinglayer501 is provided over asubstrate500, and over the insulatinglayer501, semiconductor layers511ato511dare provided.

Thesemiconductor layer511aincludes an impurity region containing an impurity element imparting a p-type conductivity or an n-type conductivity. Thesemiconductor layer511afunctions as a layer in which a channel is formed (a channel formation layer) in thetransistor201 in thecontroller103 and one of a pair of electrodes of thecapacitor203.

Thesemiconductor layer511bincludes an impurity region containing an impurity element imparting a p-type conductivity or an n-type conductivity. Thesemiconductor layer511bfunctions as a channel formation layer in thetransistor202 in thecontroller103.

Thesemiconductor layer511cincludes animpurity region503acontaining an impurity element imparting one of a p-type conductivity and an n-type conductivity, animpurity region503bcontaining an impurity element imparting the other of the p-type conductivity and the n-type conductivity, animpurity region503ccontaining an impurity element imparting the other of the p-type conductivity and the n-type conductivity, a first semiconductor region provided between theimpurity regions503aand503b, and a second semiconductor region provided between theimpurity regions503band503c. In thesemiconductor layer511c, the first semiconductor region may contain an impurity element imparting a p-type conductivity or an n-type conductivity at a concentration lower than that of the impurity element in theimpurity region503aor theimpurity region503b. Thephotoelectric converter302 is formed using theimpurity regions503aand503band the first semiconductor region provided therebetween. That is, thesemiconductor layer511cfunctions as thephotoelectric converter302. A direction in which light enters thephotoelectric converter302 is indicated by a hollowed arrow inFIG. 8A. Thesemiconductor layer511calso functions as a channel formation layer in thetransistor304 in theamplifier303. Thephotoelectric converter302 can be formed not only by using such a semiconductor layer including the p-type impurity region and the n-type impurity region, but also by using a stacked layer including a p-type semiconductor layer and an n-type semiconductor layer.

Thesemiconductor layer511dincludes an impurity region containing an impurity element imparting a p-type conductivity or an n-type conductivity. Thesemiconductor layer511dfunctions as channel formation layers in thetransistors305 and306 in theamplifier303.

One embodiment of the present invention is not limited to the above-described example in which the plurality of semiconductor layers is formed over thesubstrate500. A plurality of semiconductor regions which are electrically isolated from each other may be formed in a semiconductor substrate, so that the plurality of semiconductor regions can be provided as an alternative to the semiconductor layers511ato511d. In that case, for example, a single crystal semiconductor substrate can be used as the semiconductor substrate; a single crystal silicon substrate can be used, for example.

An insulatinglayer512 is provided over the semiconductor layers511ato511d. The insulatinglayer512 functions as gate insulating layers of thetransistors201,202,304,305, and306 and a dielectric layer of thecapacitor203.

Aconductive layer513aoverlaps with part of thesemiconductor layer511awith the insulatinglayer512 provided therebetween. The part in thesemiconductor layer511awhich overlaps with theconductive layer513ais the channel formation region of thetransistor201. Theconductive layer513afunctions as the gate of thetransistor201. Theconductive layer513aalso functions as the wiring GL. Although theconductive layer513aoverlaps with a plurality of parts of thesemiconductor layer511ainFIGS. 8A to 8C, theconductive layer513adoes not necessarily overlap with a plurality of parts of thesemiconductor layer511a. However, the switching characteristics of thetransistor201 can be improved by overlapping theconductive layer513awith a plurality of parts of thesemiconductor layer511a. The part of thesemiconductor layer511awhich overlaps with theconductive layer513amay contain an impurity element imparting a p-type conductivity or an n-type conductivity at a concentration lower than that of the impurity element in the impurity region (region which overlaps with none of theconductive layer513aandconductive layers513band513c) of thesemiconductor layer511a.

Theconductive layer513boverlaps with part of thesemiconductor layer511awith the insulatinglayer512 provided therebetween. Theconductive layer513bfunctions as the other of the pair of electrodes of thecapacitor203. The part of thesemiconductor layer511awhich overlaps with theconductive layer513bmay contain an impurity element imparting a p-type conductivity or an n-type conductivity at a concentration lower than that of the impurity element in the impurity region (region which overlaps with none of theconductive layers513a,513b, and513c) of thesemiconductor layer511a. Theconductive layer513balso functions as the wiring CS.

Theconductive layer513coverlaps with part of thesemiconductor layer511aand part of thesemiconductor layer511bwith the insulatinglayer512 provided therebetween. The part in thesemiconductor layer511bwhich overlaps with theconductive layer513cis the channel formation region of thetransistor202. Theconductive layer513cfunctions as the gate of thetransistor202. The part of thesemiconductor layer511aand/or the part of thesemiconductor layer511bwhich overlaps with theconductive layer513cmay contain an impurity element imparting a p-type conductivity or an n-type conductivity at a concentration lower than that/those of the impurity element(s) in the impurity region(s) (region(s) which overlap(s) with none of theconductive layers513a,513b, and513c) of thesemiconductor layer511aand/or thesemiconductor layer511b.

Aconductive layer513doverlaps with part of thesemiconductor layer511cwith the insulatinglayer512 provided therebetween. Theconductive layer513dfunctions as the wiring PR. The part of thesemiconductor layer511cwhich overlaps with theconductive layer513dmay contain an impurity element imparting a p-type conductivity or an n-type conductivity at a concentration lower than that of the impurity element in the impurity region (theimpurity region503a,503b,503c) of thesemiconductor layer511c.

Aconductive layer513eoverlaps with part of thesemiconductor layer511cwith the insulatinglayer512 provided therebetween. The part in thesemiconductor layer511cwhich overlaps with theconductive layer513eis the channel formation region of thetransistor304. Theconductive layer513efunctions as the gate of thetransistor304. Theconductive layer513ealso functions as the wiring TX. The part of thesemiconductor layer511cwhich overlaps with theconductive layer513emay contain an impurity element imparting a p-type conductivity or an n-type conductivity at a concentration lower than that of the impurity element in the impurity region (theimpurity region503a,503b,503c) of thesemiconductor layer511c.

Aconductive layer513foverlaps with part of thesemiconductor layer511dwith the insulatinglayer512 provided therebetween. The part in thesemiconductor layer511dwhich overlaps with theconductive layer513fis the channel formation region of thetransistor305. Theconductive layer513ffunctions as the gate of thetransistor305. The part of thesemiconductor layer511dwhich overlaps with theconductive layer513fmay contain an impurity element imparting a p-type conductivity or an n-type conductivity at a concentration lower than that of the impurity element in the impurity region (region which overlaps with none of theconductive layer513fand aconductive layer513g) of thesemiconductor layer511d.

Theconductive layer513goverlaps with part of thesemiconductor layer511dwith the insulatinglayer512 provided therebetween. The part in thesemiconductor layer511dwhich overlaps with theconductive layer513gis the channel formation region of thetransistor306. Theconductive layer513gfunctions as the gate of thetransistor306. Theconductive layer513galso functions as the wiring SE. The part of thesemiconductor layer511dwhich overlaps with theconductive layer513gmay contain an impurity element imparting a p-type conductivity or an n-type conductivity at a concentration lower than that of the impurity element in the impurity region (region which overlaps with none of theconductive layers513fand513g) of thesemiconductor layer511d.

An insulatinglayer514 is provided over the insulatinglayer512 with theconductive layers513ato513gprovided therebetween.

Aconductive layer515ais electrically connected to one of the plurality of impurity regions in thesemiconductor layer511athrough an opening passing through the insulatinglayers512 and514. Theconductive layer515afunctions as the wiring SL.

Aconductive layer515bis electrically connected to one of the plurality of impurity regions in thesemiconductor layer511dthrough an opening passing through the insulatinglayers512 and514. Theconductive layer515bfunctions as the wiring OUT.

Aconductive layer515cis electrically connected to theconductive layer513cthrough an opening passing through the insulatinglayer514, and is electrically connected to one of the plurality of impurity regions in thesemiconductor layer511athrough an opening passing through the insulatinglayers512 and514.

Aconductive layer515dis electrically connected to one of the plurality of impurity regions in thesemiconductor layer511bthrough an opening passing through the insulatinglayers512 and514, and is electrically connected to one of the plurality of impurity regions in thesemiconductor layer511dthrough an opening passing through the insulatinglayers512 and514. Theconductive layer515dfunctions as the wiring VR.

Aconductive layer515eis electrically connected to theimpurity region503ain thesemiconductor layer511cthrough an opening passing through the insulatinglayers512 and514, and is electrically connected to theconductive layer513dwhich functions as the wiring PR through an opening passing through the insulatinglayer514.

Aconductive layer515fis electrically connected to theimpurity region503cin thesemiconductor layer511cthrough an opening passing through the insulatinglayers512 and514, and is electrically connected to theconductive layer513fthrough an opening passing through the insulatinglayer514.

Aconductive layer515gis electrically connected to one of the plurality of impurity regions in thesemiconductor layer511bthrough an opening passing through the insulatinglayers512 and514.

An insulatinglayer516 is provided over the insulatinglayer514 with theconductive layers515ato515gprovided therebetween.

Aconductive layer517 is provided over the insulatinglayer516, and is electrically connected to theconductive layer515gthrough an opening passing through the insulatinglayer516. Theconductive layer517 functions as one of a pair of electrodes of the light-emittingelement102.

An insulatinglayer518 is provided over theconductive layer517.

Anelectroluminescent layer519 is provided over the insulatinglayer518. Theelectroluminescent layer519 is electrically connected to theconductive layer517 in a region where theconductive layer517 is provided and the insulatinglayer518 is not provided. Theelectroluminescent layer519 functions as an electroluminescent layer of the light-emittingelement102.

Aconductive layer520 is provided over theelectroluminescent layer519 and is electrically connected to theelectroluminescent layer519. Theconductive layer520 functions as the other electrode of the pair of electrodes of the light-emittingelement102. Theconductive layer520 also functions as the wiring VB. The wiring VB may be processed into a shape over thesubstrate500 or may be formed entirely over thesubstrate500 without being processed into a shape.

The light-emittingelement102 is formed using theconductive layer517, theelectroluminescent layer519, and theconductive layer520. The light-emittingelements102 in twoadjacent sets110 are separated from each other by the insulatinglayer518. In this embodiment, the light-emittingelement102 has a top-emission structure; the light emission direction is indicated by a hollowed arrow inFIG. 8B.

Although the light-emittingelement102 has the structure in which light is emitted upwardly (in the direction opposite to the direction toward the substrate500) in this embodiment, one embodiment of the present invention is not limited thereto; for example, a structure in which light is emitted upwardly and downwardly (in the direction toward the substrate500) can be employed.

Acoloring layer522 is provided for one plane of asubstrate521 so as to transmit light from theelectroluminescent layer519. Thecoloring layer522 is provided in order to transmit only a certain wavelength of light emitted from theelectroluminescent layer519 to provide a certain color. Thecoloring layer522 functions as a color filter. Thecoloring layer522 is not necessarily provided in the case where a material or the like of theelectroluminescent layer519 is selected as appropriate such that the light-emittingelement102 emits light of an appropriate color. No provision of thecoloring layer522 leads to a reduction in loss of light and a reduction of power consumption of a semiconductor device.

An insulatinglayer523 is provided for the plane of thesubstrate521 with thecoloring layer522 provided therebetween. The insulatinglayer523 functions as a passivation film for preventing an impurity in thecoloring layer522 or the like from entering the light-emittingelement102 or the like. The insulatinglayer523 also functions as a planarization film for relaxing a step between a region where thecoloring layer522 is provided and a region where thecoloring layer522 is not provided for thesubstrate521.

An insulatinglayer524 is provided between the insulatinglayer523 and theconductive layer520. The insulatinglayer524 functions as a seal member of the light-emittingelement102, and also functions as a sealant between thesubstrates500 and521. The space between the insulatinglayer523 and theconductive layer520 may be filled with a gas, instead of provision of the insulatinglayer524.

As each of thesubstrates500 and521, a glass substrate or a plastic substrate can be used, for example. Further, both thesubstrates500 and521 are not necessarily provided.

A gallium oxide layer, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer can be used as the insulatinglayer501, for example. For example, a silicon oxide layer, a silicon oxynitride layer, or the like can be used as the insulatinglayer501. In addition, halogen may be included in the insulatinglayer501. Further, a stack of layers of materials applicable to the insulatinglayer501 can be used as the insulatinglayer501. The insulatinglayer501 is not necessarily provided.

As the semiconductor layers511ato511d, a layer containing an amorphous semiconductor, a microcrystalline semiconductor, a polycrystalline semiconductor, or a single crystal semiconductor can be used, for example. Further, a semiconductor layer including a semiconductor belonging to Group 14 of the periodic table (e.g., silicon) can be used as the semiconductor layers511ato511d.

An oxide semiconductor layer can be used as the semiconductor layers511ato511d.

In the case of using an oxide semiconductor layer, an oxide semiconductor containing at least indium (In) or zinc (Zn) is preferably used. In particular, In and Zn are preferably contained. In addition, gallium (Ga) is preferably contained as a stabilizer for reducing variation in electric characteristics of a transistor using the oxide semiconductor. Tin (Sn) is preferably contained as the stabilizer. Hafnium (Hf) is preferably contained as the stabilizer. Aluminum (Al) is preferably contained as the stabilizer.

As the stabilizer, one or plural kinds of lanthanoid such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu) may be contained.

As the oxide semiconductor, for example, an indium oxide, a tin oxide, a zinc oxide, a two-component metal oxide such as an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, or an In—Ga-based oxide, a three-component metal oxide such as an In—Ga—Zn-based oxide (also referred to as IGZO), an In—Al—Zn-based oxide, an In—Sn—Zn-based oxide, a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, an In—Hf—Zn-based oxide, an In—La—Zn-based oxide, an In—Ce—Zn-based oxide, an In—Pr—Zn-based oxide, an In—Nd—Zn-based oxide, an In—Sm—Zn-based oxide, an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide, an In—Tb—Zn-based oxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-based oxide, an In—Er—Zn-based oxide, an In—Tm—Zn-based oxide, an In—Yb—Zn-based oxide, or an In—Lu—Zn-based oxide, a four-component metal oxide such as an In—Sn—Ga—Zn-based oxide, an In—Hf—Ga—Zn-based oxide, an In—Al—Ga—Zn-based oxide, an In—Sn—Al—Zn-based oxide, an In—Sn—Hf—Zn-based oxide, or an In—Hf—Al—Zn-based oxide can be used.

In this specification, for example, the “In—Ga—Zn-based oxide” refers to an oxide containing In, Ga, and Zn as its main components and there is no particular limitation on the ratio of In:Ga:Zn. The In—Ga—Zn-based oxide may contain a metal element other than In, Ga, and Zn.

Further, a material represented by InMO₃(ZnO)_m(m>0 and m is not an integer) may be used as the oxide semiconductor, where M represents one or more metal elements selected from Ga, Fe, Mn, and Co. Further, as the oxide semiconductor, a material represented by In₃SnO₅(ZnO)_n(n>0, n is an integer) may be used.

For example, an In—Ga—Zn-based oxide with an atomic ratio of In:Ga:Zn=1:1:1 (=1/3:1/3:1/3) or In:Ga:Zn=2:2:1 (=2/5:2/5:1/5), or any of oxides whose composition is close to any of the above compositions can be used. Alternatively, an In—Sn—Zn-based oxide with an atomic ratio of In:Sn:Zn=1:1:1 (=1/3:1/3:1/3), In:Sn:Zn=2:1:3 (=1/3:1/6:1/2), or In:Sn:Zn=2:1:5 (=1/4:1/8:5/8), or any of oxides whose composition is close to any of the above compositions may be used.

However, without limitation to the materials given above, a material with an appropriate composition may be used considering semiconductor characteristics (e.g., mobility, threshold voltage, and variation). Further, considering semiconductor characteristics, it is preferable that the carrier density, the impurity concentration, the defect density, the atomic ratio between a metal element and oxygen, the interatomic distance, the density, and the like be adjusted as appropriate.

For example, a high mobility can be exhibited relatively easily with an In—Sn—Zn-based oxide. However, even with an In—Ga—Zn-based oxide, the mobility can be increased by reducing the defect density in the bulk of the In—Ga—Zn-based oxide.

Note that for example, the expression the “composition of an oxide with an atomic ratio of In:Ga:Zn=a:b:c (a+b+c=1) is close to the composition of an oxide with an atomic ratio of In:Ga:Zn=A:B:C (A+B+C=1)” means that a, b, and c satisfy the following relation: (a−A)²+(b−B)²+(c−C)²≦r²where r is, for example, 0.05. The same applies to other oxides.

The oxide semiconductor may be either a single crystal or a non-single-crystal. In the latter case, the oxide semiconductor may be either amorphous or polycrystal. Further, the oxide semiconductor may either have a structure including a crystal portion in an amorphous state or may be non-amorphous.

An amorphous oxide semiconductor can be provided with a flat surface with relative ease, which enables interface scattering in a transistor to be reduced, so that a relatively high mobility can be exhibited with relative ease.

In an oxide semiconductor having crystallinity, defects in the bulk can be further reduced, and a mobility higher than that of an amorphous oxide semiconductor layer can be exhibited by improving the flatness of its surface. In order to improve its surface flatness, the oxide semiconductor is preferably formed on a flat surface; specifically, the oxide semiconductor is preferably formed on a surface with an average surface roughness (Ra) of less than or equal to 1 nm, further preferably less than or equal to 0.3 nm, still further preferably less than or equal to 0.1 nm.

The average surface roughness (Ra) is a three-dimensional expanded version of center line average roughness that is defined by JIS B 0601 so as to be applied to a plane, and can be expressed as an “average value of the absolute values of deviations from a reference surface to a specific surface” and is defined by the following formula.

$\begin{array}{cc}\mathrm{Ra}=\frac{1}{{\mathrm{<figure-callout\; label="S"\; filenames="US09841843-20171212-D00016.png,US09841843-20171212-D00017.png"\; state="\{\{state\}\}">S</figure-callout>}}_0}{\int }_{y_1}^{{\mathrm{<figure-callout\; label="y"\; filenames="US09841843-20171212-D00009.png,US09841843-20171212-D00010.png"\; state="\{\{state\}\}">y</figure-callout>}}_2}{\int }_{x_1}^{x_2}f\left(x,y\right)-{\mathrm{<figure-callout\; label="Z"\; filenames="US09841843-20171212-D00016.png,US09841843-20171212-D00017.png"\; state="\{\{state\}\}">Z</figure-callout>}}_0dxdy& \left[\mathrm{Formula}1\right]\end{array}$

In the above formula, S₀denotes an area of a plane to be measured (a rectangular region which is defined by four points at coordinates (x₁, y₁), (x₁, y₂), (x₂, y₁), (x₂, y₂)), and Z₀denotes an average height of the plane. The average surface roughness Ra can be measured with an atomic force microscope (AFM).

The oxide semiconductor layer is preferably fainted by a sputtering method. For example, with the use of a target of any of the above oxides, the oxide semiconductor layer can be formed by a sputtering method.

A high purity of the target which is 99.99% or higher leads to suppression of entrance of alkali metal, hydrogen atoms, hydrogen molecules, water, a hydroxyl group, hydride, or the like into the oxide semiconductor layer. In addition, the use of the target leads to a reduction in the concentration of alkali metal such as lithium, sodium, or potassium in the oxide semiconductor layer.

An In—Sn—Zn-based oxide can be referred to as ITZO. In the case where ITZO is used as the oxide semiconductor layer, an oxide target whose composition has an atomic ratio of In:Sn:Zn of 1:2:2, 2:1:3, 1:1:1, or 20:45:35 can be used, for example.

In addition, by setting the pressure of a treatment chamber in a sputtering apparatus to 0.4 Pa or less in forming the oxide semiconductor layer, mixing of an impurity such as alkali metal or hydrogen to an object to be formed or a surface of the object can be suppressed. Hydrogen may be contained in the object not only in the form of a hydrogen atom but also in the form of a hydrogen molecule, water, a hydroxyl group, or hydride in some cases.

Further, with the use of an entrapment vacuum pump (e.g., a cryopump) as an evacuation system of the chamber of the sputtering apparatus, counter flow of impurities such as alkali metal, a hydrogen atom, a hydrogen molecule, water, a hydroxyl group, or hydride from the evacuation system can be suppressed. The evacuation unit may be a turbo pump provided with a cold trap.

After the oxide semiconductor layer is formed, if necessary, heat treatment may be performed in an atmosphere which contains hydrogen and moisture as less as possible (a nitrogen atmosphere, an oxygen atmosphere, a dry-air atmosphere (for example, as for moisture, the dew point is −40° C. or less, preferably −60° C. or less), or the like) at a temperature higher than or equal to 200° C. and lower than or equal to 450° C. This heat treatment can be called dehydration or dehydrogenation for detaching H, OH, or the like from the oxide semiconductor layer; in the case where the temperature is raised in an inert atmosphere and is switched to an atmosphere containing oxygen during the heat treatment, or in the case where an oxygen atmosphere is employed in the heat treatment, such heat treatment can also be called treatment for supplying oxygen.

As the oxide semiconductor layer, an oxide semiconductor layer that is purified by reduction of impurities such as moisture, hydrogen, and alkali metal elements (e.g., sodium or lithium), which serve as electron donors (donors), is used. The concentration of hydrogen in the oxide semiconductor layer according to secondary ion mass spectrometry (SIMS) is less than or equal to 5×10¹⁹/cm³, preferably less than or equal to 5×10¹⁸/cm³, further preferably less than or equal to 5×10¹⁷/cm³, still further preferably less than or equal to 1×10¹⁶/cm³. In addition, the carrier density of the oxide semiconductor layer according to Hall effect measurement is less than 1×10¹⁴/cm³, preferably less than 1×10¹²/cm³, further preferably less than 1×10¹¹/cm³. Furthermore, the band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, further preferably 3 eV or more.

It has been pointed out that an oxide semiconductor is insensitive to impurities, there is no problem even when a considerable amount of metal impurities is contained in the film, and therefore, soda-lime glass which contains a large amount of alkali metal such as sodium and is inexpensive can also be used (Kamiya, Nomura, and Hosono, “Engineering application of solid state physics: Carrier transport properties and electronic structures of amorphous oxide semiconductors: the present status”,KOTAI BUTSURI(SOLID STATE PHYSICS), 2009, Vol. 44, pp. 621-633). But such consideration is not appropriate. Alkali metal is not a component of an oxide semiconductor, and thus is an impurity. Also, alkaline earth metal is an impurity in the case where the alkaline earth metal is not a component of the oxide semiconductor. Among alkali metals, in particular, sodium (Na) is diffused into an insulating film which is in contact with the oxide semiconductor layer when the insulating film is an oxide. Further, in the oxide semiconductor layer, Na cuts or enters a bond between metal and oxygen which are components of the oxide semiconductor. As a result, for example, deterioration of characteristics of the transistor, such as a normally-on state of the transistor due to shift of a threshold voltage in the negative direction, or reduction in mobility, occurs; in addition, variation in characteristics also occurs. Such deterioration of characteristics of the transistor and variation in characteristics due to the impurity remarkably appear when the hydrogen concentration in the oxide semiconductor layer is very low. Therefore, when the hydrogen concentration in the oxide semiconductor layer is less than or equal to 1×10¹⁸/cm³, preferably less than or equal to 1×10¹⁷/cm³, the concentration of the above impurity is preferably reduced as much as possible. Specifically, the Na concentration according to secondary ion mass spectrometry is reduced to preferably less than or equal to 5×10¹⁶/cm³, further preferably less than or equal to 1×10¹⁶/cm³, still further preferably less than or equal to 1×10¹⁵/cm³. In addition, the lithium (Li) concentration according to secondary ion mass spectrometry is reduce to preferably less than or equal to 5×10¹⁵/cm³, further preferably less than or equal to 1×10¹⁵/cm³. In addition, the potassium (K) concentration according to secondary ion mass spectrometry is reduced to preferably less than or equal to 5×10¹⁵/cm³, further preferably less than or equal to 1×10¹⁵/cm³.

It is known that with SIMS, it is difficult to accurately obtain data in the proximity of a surface of a sample or in the proximity of an interface between stacked layers formed using different materials in principle when the concentration of alkali metal elements or hydrogen in the layer is measured. Thus, in the case where distribution of the concentration of alkali metal elements or hydrogen in the layer in the thickness direction is analyzed by SIMS, an average value in a region of the layer where there is no great variation in the value and the value is almost constant is adopted as the concentration of alkali metal elements or hydrogen. Further, in the case where the thickness of the layer is small, such a region where the value is almost constant cannot be found in some cases because of the influence of the concentration of alkali metal elements or hydrogen of another layer adjacent to the layer. In that case, the maximum value or the minimum value of the concentration of alkali metal elements or hydrogen of a region where the layer exists is adopted as the concentration of alkali metal elements or hydrogen of the layer. Furthermore, in the case where a mountain-shaped peak having the maximum value or a valley-shaped peak having the minimum value does not exist in the region where the layer exists, the value at an inflection point is adopted as the concentration of alkali metal elements or hydrogen.

The off-state current density of a transistor whose channel is formed in an oxide semiconductor layer can be suppressed to less than or equal to 100 yA/μm, preferably less than or equal to 10 yA/μm, further preferably less than or equal to 1 yA/μm.

Further, the oxide semiconductor layer may be doped with an impurity which imparts p-type conductivity, such as Sn, so as to make the oxide semiconductor layer to have weak p-type conductivity, whereby the off-state current of the transistor whose channel is formed in the oxide semiconductor layer can be reduced.

As the oxide semiconductor, an oxide including a crystal with c-axis alignment (also referred to as C-Axis Aligned Crystal (CAAC)), which has a triangular or hexagonal atomic arrangement when seen from the direction of the a-b plane, a top surface, or an interface may be used. In the crystal, metal atoms are arranged in a layered manner along the c-axis, or metal atoms and oxygen atoms are arranged in a layered manner along the c-axis, and the direction of the a-axis or the b-axis is varied in the a-b plane (the crystal twists around the c-axis).

In a broad sense, an oxide including CAAC means a non-single-crystal oxide including a phase which has a triangular, hexagonal, regular triangular, or regular hexagonal atomic arrangement when seen from the direction perpendicular to the a-b plane and in which metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis direction.

The CAAC is not a single crystal, but does not consist of only an amorphous state. Further, although the CAAC includes a crystallized portion (crystalline portion), a boundary between one crystalline portion and another crystalline portion is not clear in some cases.

In the case where oxygen is included in the CAAC, nitrogen may be substituted for part of oxygen included in the CAAC. The c-axes of individual crystalline portions included in the CAAC may be aligned in one direction (e.g., a direction perpendicular to a surface of a substrate provided with the CAAC or a top surface of the CAAC). Alternatively, the normals to the a-b planes of the individual crystalline portions included in the CAAC may be aligned in one direction (e.g., a direction perpendicular to a surface of a substrate provided with the CAAC or a top surface of the CAAC).

The CAAC is a conductor, a semiconductor, or an insulator depending on its composition or the like. The CAAC transmits or does not transmit visible light depending on its composition or the like.

As an example of such a CAAC, there is a crystal which is formed into a film shape and has a triangular or hexagonal atomic arrangement when observed from the direction perpendicular to a top surface of the film or a surface of a substrate provided with the CAAC, and in which metal atoms are arranged in a layered manner or metal atoms and oxygen atoms (or nitrogen atoms) are arranged in a layered manner when a cross section of the film is observed.

Examples of a crystal structure of the CAAC are described in detail usingFIGS. 16A to 16E,FIGS. 17A to 17C, andFIGS. 18A to 18C. InFIGS. 16A to 16E,FIGS. 17A to 17C, andFIGS. 18A to 18C, the vertical direction corresponds to the c-axis direction and a plane perpendicular to the c-axis direction corresponds to the a-b plane, unless otherwise specified. A simply “upper half” and a simply “lower half” refer to an upper half above the a-b plane and a lower half below the a-b plane (an upper half and a lower half with respect to the a-b plane). Furthermore, inFIGS. 16A to 16E, O surrounded by a circle represents tetracoordinate O and O surrounded by a double circle represents tricoordinate O.

FIG. 16A illustrates a structure including one hexacoordinate In atom and six tetracoordinate oxygen (hereinafter referred to as tetracoordinate O) atoms proximate to the In atom. In this specification, a structure showing only oxygen atoms proximate to one metal atom is referred to as a small group. The structure inFIG. 16A is actually an octahedral structure, but is illustrated as a planar structure for simplicity. Three tetracoordinate O atoms exist in each of the upper half and the lower half inFIG. 16A. The electric charge of the small group illustrated inFIG. 16A is 0.

FIG. 16B illustrates a structure including one pentacoordinate Ga atom, three tricoordinate oxygen (hereinafter referred to as tricoordinate O) atoms proximate to the Ga atom, and two tetracoordinate O atoms proximate to the Ga atom. All the three tricoordinate O atoms exist on the a-b plane. One tetracoordinate O atom exists in each of the upper half and the lower half inFIG. 16B. An In atom can also have the structure illustrated inFIG. 16B because the In atom can have five ligands. The electric charge of the small group illustrated inFIG. 16B is 0.

FIG. 16C illustrates a structure including one tetracoordinate Zn atom and four tetracoordinate O atoms proximate to the Zn atom. InFIG. 16C, one tetracoordinate O atom exists in the upper half and three tetracoordinate O atoms exist in the lower half. Alternatively, three tetracoordinate O atoms may exist in the upper half and one tetracoordinate O atom may exist in the lower half inFIG. 16C. The electric charge of the small group illustrated inFIG. 16C is 0.

FIG. 16D illustrates a structure including one hexacoordinate Sn atom and six tetracoordinate O atoms proximate to the Sn atom. InFIG. 16D, three tetracoordinate O atoms exist in each of the upper half and the lower half. The electric charge of the small group illustrated inFIG. 16D is +1.

FIG. 16E illustrates a small group including two Zn atoms. InFIG. 16E, one tetracoordinate O atom exists in each of the upper half and the lower half. The electric charge of the small group illustrated inFIG. 16E is −1.

In this specification, a group of a plurality of small groups is referred to as a medium group, and a group of a plurality of medium groups is referred to as a large group (also referred to as a unit cell).

Now, a rule of bonding the small groups to each other is described. The three O atoms in the upper half with respect to the hexacoordinate In atom inFIG. 16A has three proximate In atoms in the downward direction, and the three O atoms in the lower half has three proximate In atoms in the upward direction. The one O atom in the upper half with respect to the pentacoordinate Ga atom inFIG. 16B has one proximate Ga atom in the downward direction, and the one O atom in the lower half has one proximate Ga atom in the upward direction. The one O atom in the upper half with respect to the one tetracoordinate Zn atom inFIG. 16C has one proximate Zn atom in the downward direction, and the three O atoms in the lower half has three proximate Zn atoms in the upward direction. In this manner, the number of tetracoordinate O atoms above a metal atom is equal to the number of metal atoms proximate to and below the tetracoordinate O atoms; similarly, the number of tetracoordinate O atoms below a metal atom is equal to the number of metal atoms proximate to and above the tetracoordinate O atoms. Since the coordination number of the tetracoordinate O atom is 4, the sum of the number of metal atoms proximate to and below the O atom and the number of metal atoms proximate to and above the O atom is 4. Accordingly, when the sum of the number of tetracoordinate O atoms above a metal atom and the number of tetracoordinate O atoms below another metal atom is 4, the two kinds of small groups including the metal atoms can be bonded to each other. For example, in the case where the hexacoordinate metal (In or Sn) atom is bonded through three tetracoordinate O atoms in the lower half, it is bonded to a pentacoordinate metal (Ga or In) atom or a tetracoordinate metal (Zn) atom.

A metal atom whose coordination number is 4, 5, or 6 is bonded to another metal atom through a tetracoordinate O atom in the c-axis direction. In addition, a medium group can also be formed in a different manner by combining a plurality of small groups so that the total electric charge of the layered structure is 0.

FIG. 17A illustrates a model of a medium group included in a layered structure of an In—Sn—Zn—O-based material.FIG. 17B illustrates a large group including three medium groups.FIG. 17C illustrates an atomic arrangement where the layered structure shown inFIG. 17B is observed from the c-axis direction.

InFIG. 17A, a tricoordinate O atom is omitted for simplicity, and a tetracoordinate O atom is illustrated by a circle; the number in the circle shows the number of tetracoordinate O atoms. For example, three tetracoordinate O atoms existing in each of the upper half and the lower half with respect to a Sn atom are denoted by circled3. Similarly, inFIG. 17A, one tetracoordinate O atom existing in each of the upper half and the lower half with respect to an In atom is denoted by circled1.FIG. 17A also illustrates a Zn atom proximate to one tetracoordinate O atom in the lower half and three tetracoordinate O atoms in the upper half, and a Zn atom proximate to one tetracoordinate O atom in the upper half and three tetracoordinate O atoms in the lower half.

In the medium group included in the layered structure of the In—Sn—Zn—O-based material inFIG. 17A, in the order starting from the top, a Sn atom proximate to three tetracoordinate O atoms in each of the upper half and the lower half is bonded to an In atom proximate to one tetracoordinate O atom in each of the upper half and the lower half, the In atom is bonded to a Zn atom proximate to three tetracoordinate O atoms in the upper half, the Zn atom is bonded to an In atom proximate to three tetracoordinate O atoms in each of the upper half and the lower half through one tetracoordinate O atom in the lower half with respect to the Zn atom, the In atom is bonded to a small group that includes two Zn atoms and is proximate to one tetracoordinate O atom in the upper half, and the small group is bonded to a Sn atom proximate to three tetracoordinate O atoms in each of the upper half and the lower half through one tetracoordinate O atom in the lower half with respect to the small group. A plurality of such medium groups is bonded to form a large group.

Here, electric charge for one bond of a tricoordinate O atom and electric charge for one bond of a tetracoordinate O atom can be assumed to be −0.667 and −0.5, respectively. For example, electric charge of a (hexacoordinate or pentacoordinate) In atom, electric charge of a (tetracoordinate) Zn atom, and electric charge of a (pentacoordinate or hexacoordinate) Sn atom are +3, +2, and +4, respectively. Accordingly, electric charge in a small group including a Sn atom is +1. Therefore, electric charge of −1, by which the electric charge of +1 is canceled, is needed to form a layered structure including a Sn atom. As a structure having electric charge of −1, the small group including two Zn atoms as illustrated inFIG. 16E can be given. For example, with one small group including two Zn atoms, electric charge of one small group including a Sn atom can be cancelled, so that the total electric charge of the layered structure can result in 0.

Specifically, by repeating the large group illustrated inFIG. 17B, an In—Sn—Zn—O-based crystal (In₂SnZn₃O₈) can be formed. The layered structure of the In—Sn—Zn—O-based crystal can be expressed by a composition formula, In₂SnZn₂O₇(ZnO)_m(m is 0 or a natural number).

The above-described rule is also applied to the following oxides: a four-component metal oxide such as an In—Sn—Ga—Zn-based oxide; a three-component metal oxide such as an In—Ga—Zn-based oxide (also referred to as IGZO), an In—Al—Zn-based oxide, a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, an In—Hf—Zn-based oxide, an In—La—Zn-based oxide, an In—Ce—Zn-based oxide, an In—Pr—Zn-based oxide, an In—Nd—Zn-based oxide, an In—Sm—Zn-based oxide, an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide, an In—Tb—Zn-based oxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-based oxide, an In—Er—Zn-based oxide, an In—Tm—Zn-based oxide, an In—Yb—Zn-based oxide, or an In—Lu—Zn-based oxide; a two-component metal oxide such as an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, or an In—Ga-based oxide; and the like.

For example,FIG. 18A illustrates a model of a medium group included in a layered structure of an In—Ga—Zn—O-based material.

In the medium group included in the layered structure of the In—Ga—Zn—O-based material inFIG. 18A, in the order starting from the top, an In atom proximate to three tetracoordinate O atoms in each of the upper half and the lower half is bonded to a Zn atom proximate to one tetracoordinate O atom in the upper half, the Zn atom is bonded to a Ga atom proximate to one tetracoordinate O atom in each of the upper half and the lower half through three tetracoordinate O atoms in the lower half with respect to the Zn atom, and the Ga atom is bonded to an In atom proximate to three tetracoordinate O atoms in each of the upper half and the lower half through one tetracoordinate O atom in the lower half with respect to the Ga atom. A plurality of such medium groups are bonded to form a large group.

FIG. 18B illustrates a large group including three medium groups.FIG. 18C illustrates an atomic arrangement where the layered structure shown inFIG. 18B is observed from the c-axis direction.

Here, since electric charge of a (hexacoordinate or pentacoordinate) In atom, electric charge of a (tetracoordinate) Zn atom, and electric charge of a (pentacoordinate) Ga atom are +3, +2, +3, respectively, electric charge of a small group including any of the In atom, the Zn atom, and the Ga atom is 0. As a result, the total electric charge of a medium group having a combination of these small groups always results in 0.

In order to form the layered structure of the In—Ga—Zn—O-based material, a large group can be formed using not only the medium group illustrated inFIG. 18A but also a medium group in which the arrangement of the In atom, the Ga atom, and the Zn atom is different from that inFIG. 18A.

As the insulatinglayer512, for example, a layer of a material applicable to the insulatinglayer501 can be used. A stack of layers of materials applicable to the insulatinglayer512 can be used as the insulatinglayer512.

A layer formed using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium can be used as any of theconductive layers513ato513g. For example, a Cu—Mg—Al alloy can be used. Further, a layer containing a conductive metal oxide can be used as any of theconductive layers513ato513gas well. As the conductive metal oxide, a metal oxide such as indium oxide (In₂O₃), tin oxide (SnO₂), zinc oxide (ZnO), an alloy of indium oxide and tin oxide (In₂O₃—SnO₂, which is abbreviated to ITO in some cases), or an alloy of indium oxide and zinc oxide (In₂O₃—ZnO); or the metal oxide containing silicon, silicon oxide, or nitrogen can be used, for example. A stack of layers of materials applicable to each of theconductive layers513ato513gcan be used as any of theconductive layers513ato513g. For example, a stacked-layer structure of a layer including a Cu—Mg—Al alloy and a layer including Cu can be employed. For example, a stack of a tantalum nitride layer and a tungsten layer can be used as each of theconductive layers513ato513g. The side surface of any of theconductive layers513ato513gmay be tapered.

As the insulatinglayer514, a layer of a material applicable to the insulatinglayer501 can be used, for example. A stack of layers of materials applicable to the insulatinglayer501 can be used as the insulatinglayer514. For example, the insulatinglayer514 can be formed using a stack of a silicon oxynitride layer and a silicon nitride oxide layer.

As any of theconductive layers515ato515g, a layer of a material applicable to each of theconductive layers513ato513gcan be used. A stack of layers of materials applicable to each of theconductive layers515ato515gcan be used as any of theconductive layers515ato515g. For example, a stack of a titanium layer, an aluminum layer, and a titanium layer can be used as each of theconductive layers515ato515g. The side surface of any of theconductive layers515ato515gmay be tapered.

As the insulatinglayer516, a layer of a material applicable to the insulatinglayer512 can be used, for example. A stack of layers of materials applicable to the insulatinglayer516 can be used as the insulatinglayer516.

As theconductive layer517, a layer of a material which reflects light and is applicable to each of theconductive layers513ato513gcan be used. A stack of layers of materials applicable to theconductive layer517 can be used as theconductive layer517. One embodiment of the present invention is not thereto; in the case of a dual-emission structure, a layer of a material through which light passes and which is applicable to each of theconductive layers513ato513gcan be used as theconductive layer517. The side surface of theconductive layer517 may be tapered.

As the insulatinglayer518, for example, either an organic insulating layer or an inorganic insulating layer can be used.

Theelectroluminescent layer519 is a layer which emits light of single color exhibiting one color. As theelectroluminescent layer519, for example, a light-emitting layer using a light-emitting material which emits light of one color can be used. Theelectroluminescent layer519 can also be formed using a stack of light-emitting layers which emit light of different colors. As the light-emitting material, an electroluminescent material such as a fluorescent material or a phosphorescent material can be used. A material including a plurality of electroluminescent materials may be used as the light-emitting material. For example, a light-emitting layer which emits white light may be formed using a stack of a layer of a fluorescent material which emits blue light, a layer of a first phosphorescent material which emits orange light, and a layer of a second phosphorescent material which emits orange light. Further, as the electroluminescent material, either an organic electroluminescent material or an inorganic electroluminescent material can be used. Further, in addition to the light-emitting layer, the electroluminescent layer may include one or more of a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer.

A layer of a material through which light passes and which is applicable to each of theconductive layers513ato513gcan be used as theconductive layer520. A stack of layers of materials applicable to theconductive layer520 can be used as theconductive layer520. The side surface of theconductive layer520 may be tapered.

As thecoloring layer522, for example, a layer including a dye or a pigment, through which red light, green light, or blue light passes can be used. Further or alternatively, a layer including a dye or a pigment, through which cyan light, magenta light, or yellow light passes may be used as thecoloring layer522.

As the insulatinglayer523, a layer of a material applicable to the insulatinglayer501 can be used, for example. A stack of layers of materials applicable to the insulatinglayer523 can be used as the insulatinglayer523. The insulatinglayer523 is not necessarily provided.

As the insulatinglayer524, for example, a layer applicable to the insulatinglayer501 or a layer of a resin material can be used. A stack of layers of materials applicable to the insulatinglayer524 can be used as the insulatinglayer524.

Further, a light-blocking layer may be provided for part of thesubstrate500 and/or part of thesubstrate521. Unnecessary light incidence into the transistor or the like can be suppressed with the light-blocking layer.

The gate is provided only over the semiconductor layer of the transistor (transistor201,transistor202,transistor304,transistor305, transistor306) inFIGS. 8A to 8C. However, one embodiment of the present invention is not limited thereto. A gate may be provided only under the semiconductor layer of the transistor (transistor201,transistor202,transistor304,transistor305, transistor306). Alternatively, two gates may be provided with the semiconductor layer provided therebetween in the transistor (transistor201,transistor202,transistor304,transistor305, transistor306). In that case where the transistor includes the two gates with the semiconductor layer provided therebetween, one of the gates can be supplied with a signal for controlling switching of the transistor, and the other of the gates can be supplied with a potential. In that case, potentials with the same level may be supplied to the two gates, or a fixed potential such as a ground potential may be supplied only to the other of the gates. By controlling the level of the potential supplied to the other of the gates, the threshold voltage of the transistor can be controlled. The other of the gates may be in a floating state, which is an electrically insulated state, as long as the threshold voltage of the transistor is not adversely affected.

The above-described structure of any of thetransistor201, thetransistor202, thetransistor304, thetransistor305, and thetransistor306 can be applied to any of thetransistors204 and205 inFIGS. 4A to 4D and thetransistor307 inFIGS. 5A to 5C.

The power supply line (corresponding to theconductive layer515d) which is electrically connected to the photosensor also serves as the power supply line (corresponding to theconductive layer515d) which is electrically connected to the display element including the light-emitting element, whereby the number of power supply lines included in a semiconductor device can be reduced. In this manner, the width of each power supply line can be increased and a semiconductor device with high definition can be provided. Thus, the definition of the semiconductor device can be improved while securing the stability of the potential of the power supply line. The stability of the potential of the power supply line leads to the stability of the driving voltage of the display element including the light-emitting element and the stability of the driving voltage of the photosensor. That is, even in a high-definition semiconductor device, the driving voltage of the display element including the light-emitting element and the driving voltage of the photosensor can be stabilized. Accordingly, a semiconductor device with high definition, high display quality, and high accuracy of imaging or detection of an object can be provided.

This embodiment can be combined as appropriate with any other embodiment.

Embodiment 3

In this embodiment, an example of a driving method of a semiconductor device is described.

(Driving Method of Photosensor)

Examples of a driving method of a photosensor is described.

(Driving Method 1 of Photosensor)

A driving method of the photosensor301 having the configuration shown inFIGS. 2A and 2B,FIG. 3, andFIG. 5A is described.FIG. 9A is an example of a timing chart illustrating changes in potentials of each wiring (the wiring TX, the wiring PR, the wiring SE, the wiring OUT) and the node FD illustrated inFIGS. 2A and 2B,FIG. 3, andFIG. 5A. A photodiode is used as thephotoelectric converter302, as an example, in this embodiment.

In the timing chart ofFIG. 9A, for easy understanding of the operation of thephotosensor301, it is assumed that either a high-level potential or a low-level potential is supplied to the wiring TX, the wiring SE, and the wiring PR. Specifically, it is assumed that the wiring TX is supplied with a high-level potential HTX and a low-level potential LTX; the wiring SE is supplied with a high-level potential HSE and a low-level potential LSE; and the wiring PR is supplied with a high-level potential HPR and a low-level potential LPR. The wiring VR is supplied with a predetermined potential, for example, a high-level power supply potential VDD.

Although description is made assuming that thetransistors304,305, and306 are n-channel transistors, one embodiment of the present invention is not limited thereto; one or more of thetransistors304,305, and306 may be a p-channel transistor. Also in that case where one or more or each of thetransistors304,305, and306 is/are a p-channel transistor/p-channel transistors, the potential of each wiring is set so that ON/OFF of the transistors are the same as in the following description.

First, at time T1, the potential of the wiring TX is changed from the potential LTX to the potential HTX. Consequently, thetransistor304 is turned on. At the time T1, the wiring SE is supplied with the potential LSE, and the wiring PR is supplied with the potential LPR.

At time T2, the potential of the wiring PR is changed from the potential LPR to the potential HPR. At the time T2, the potential of the wiring TX is kept at the potential HTX, and the potential of the wiring SE is kept at the potential LSE. Consequently, a forward bias voltage is applied to thephotoelectric converter302. Accordingly, the potential HPR of the wiring PR is supplied to the node FD; thus, electric charge retained at the node FD is discharged.

Then, at time T3, the potential of the wiring PR is changed from the potential HPR to the potential LPR. Until just before the time T3, the potential of the node FD is kept at the potential HPR. Thus, when the potential of the wiring PR is changed to the potential LPR, a reverse bias voltage is applied to thephotoelectric converter302. Then, light (e.g., light reflected on an object to be detected) enters thephotoelectric converter302 being applied with the reverse bias voltage, whereby current (photocurrent) flows from the cathode to the anode of thephotoelectric converter302. The amount of photocurrent varies in accordance with the intensity of incident light. That is, as the intensity of light entering thephotoelectric converter302 gets higher, the amount of photocurrent increases and the greater electric charge is transferred between the node FD and thephotoelectric converter302; as the intensity of light entering thephotoelectric converter302 gets lower, the amount of photocurrent decreases and the less electric charge is transferred between the node FD and thephotoelectric converter302. Thus, the higher the intensity of light is, the greater the potential of the node FD changes; the lower the intensity of light is, the less the potential of the node FD changes.

At time T4, the potential of the wiring TX is changed from the potential HTX to the potential LTX, so that thetransistor304 is turned off. Consequently, electric charge is stopped transferring between the node FD and thephotoelectric converter302, so that the potential of the node FD is fixed.

At time T5, the potential of the wiring SE is changed from the potential LSE to the potential HSE, so that thetransistor306 is turned on. Consequently, electric charge is transferred between the wiring VR and the wiring OUT in accordance with the potential of the node FD.

An operation of setting the potential of the wiring OUT to a predetermined potential (precharge operation) is completed before the time T5.FIG. 9A illustrates the case where the potential of the wiring OUT is precharged to a low-level potential before the time T5 and increases from the time T5 to time T6 in accordance with the light intensity; however, one embodiment of the present invention is not limited to this case. The potential of the wiring OUT may be precharged to a high-level potential before the time T5 and decrease from the time T5 to the time T6 in accordance with the light intensity.

The precharge operation can be conducted in the following manner, for example: the wiring OUT and a wiring supplied with a predetermined potential are electrically connected to each other through a switching element such as a transistor and the transistor is turned on. After the precharge operation is completed, the transistor is turned off.

Then, at the time T6, the potential of the wiring SE is changed from the potential HSE to the potential LSE, so that electric charge is stopped transferring from the wiring VR to the wiring OUT, whereby the potential of the wiring OUT is fixed. This potential of the wiring OUT corresponds to the potential of the output signal of thephotosensor301. The potential of the output signal includes data on the object to be detected.

In this method, when the potential of the wiring TX is changed at the time T1 and the time T4, the potential of the node FD is changed by parasitic capacitance between the wiring TX and the node FD. If such a change of the potential is large, the output signal cannot be correctly output. In order to suppress the change of the potential of the node FD at the time of changing the potential of the wiring TX, it is effective to reduce the capacitance between the gate and source or between the gate and drain of thetransistor304. Further, it is effective to increase the gate capacitance of thetransistor305. Still further, it is effective to electrically connect a capacitor to the node FD. Such a change in the potential of the node FD at the time of changing the potential of the wiring TX is considered negligible inFIG. 9A, for example, by taking appropriate measures.

Described above is the driving method of the photosensor301 having the configuration shown inFIGS. 2A and 2B,FIG. 3, andFIG. 5A.

(Driving Method 2 of Photosensor)

Next, a driving method of the photosensor301 having any of the configurations shown inFIGS. 5B and 5C is described.FIG. 9B is an example of a timing chart illustrating changes in potentials of each wiring (the wiring TX, the wiring RE, the wiring SE, the wiring OUT) and the node FD illustrated inFIGS. 5B and 5C. A photodiode is used as thephotoelectric converter302, as an example, in this embodiment.

In the timing chart ofFIG. 9B, for easy understanding of the operation of thephotosensor301, it is assumed that either a high-level potential or a low-level potential is supplied to the wiring TX, the wiring RE, and the wiring SE. Specifically, it is assumed that the wiring TX is supplied with a high-level potential HTX and a low-level potential LTX; the wiring SE is supplied with a high-level potential HSE and a low-level potential LSE; and the wiring RE is supplied with a high-level potential HRE and a low-level potential LRE. The wiring PR is supplied with a predetermined potential, for example, a low-level power supply potential VSS.

Although description is made assuming that thetransistors304,305,306, and307 are n-channel transistors, one embodiment of the present invention is not limited thereto; one or more of thetransistors304,305,306, and307 may be a p-channel transistor. Also in that case where one or more or each of thetransistors304,305,306, and307 is/are a p-channel transistor/p-channel transistors, the potential of each wiring is set so that ON/OFF of the transistors are the same as in the following description.

First, at time T1, the potential of the wiring TX is changed from the potential LTX to the potential HTX. Consequently, thetransistor304 is turned on. At the time T1, the wiring SE is supplied with the potential LSE, and the wiring RE is supplied with the potential LRE.

Next, at time T2, the potential of the wiring RE is changed from the potential LRE to the potential HRE. Consequently, thetransistor307 is turned on. At the time T2, the potential of the wiring TX is kept at the potential HTX, and the potential of the wiring SE is kept at the potential LSE. Consequently, the power supply potential VDD is supplied to the node FD, whereby electric charge retained at the node FD is reset. In addition, a reverse bias voltage is applied to thephotoelectric converter302.

Then, at time T3, the potential of the wiring RE is changed from the potential HRE to the potential LRE. Until just before the time T3, the potential of the node FD is kept at the power supply potential VDD. Thus, even after the potential of the wiring RE is changed to the potential LRE, the reverse bias voltage is kept to be applied to thephotoelectric converter302. Then, light enters thephotoelectric converter302 being applied with the reverse bias voltage, whereby photocurrent flows from the cathode to the anode of thephotoelectric converter302. The amount of photocurrent varies in accordance with the intensity of incident light. That is, as the intensity of light entering thephotoelectric converter302 gets higher, the amount of photocurrent increases and the greater electric charge is transferred between the node FD and thephotoelectric converter302; as the intensity of light entering thephotoelectric converter302 gets lower, the amount of photocurrent decreases and the less electric charge is transferred between the node FD and thephotoelectric converter302. Thus, the higher the intensity of light is, the greater the potential of the node FD changes; the lower the intensity of light is, the less the potential of the node FD changes.

Next, at time T4, the potential of the wiring TX is changed from the potential HTX to the potential LTX, so that thetransistor304 is turned off. Consequently, electric charge is stopped transferring between the node FD and thephotoelectric converter302, so that the potential of the node FD is fixed.

Then, at time T5, the potential of the wiring SE is changed from the potential LSE to the potential HSE, so that thetransistor306 is turned on. Consequently, electric charge is transferred between the wiring VR and the wiring OUT in accordance with the potential of the node FD.

An operation of setting the potential of the wiring OUT to a predetermined potential (precharge operation) is completed before the time T5.FIG. 9B illustrates the case where the potential of the wiring OUT is precharged to a low-level potential before the time T5 and increases from the time T5 to time T6 in accordance with the light intensity; however, one embodiment of the present invention is not limited to this case. The potential of the wiring OUT may be precharged to a high-level potential before the time T5 and decrease from the time T5 to the time T6 in accordance with the light intensity.

The precharge operation can be conducted in the following manner, for example: the wiring OUT and a wiring supplied with a predetermined potential are electrically connected to each other through a switching element such as a transistor and the transistor is turned on. After the precharge operation is completed, the transistor is turned off.

Then, at the time T6, the potential of the wiring SE is changed from the potential HSE to the potential LSE, so that electric charge is stopped transferring from the wiring VR to the wiring OUT, whereby the potential of the wiring OUT is fixed. This potential of the wiring OUT corresponds to the potential of the output signal of thephotosensor301. The potential of the output signal includes data on an object to be detected.

In this method, when the potential of the wiring TX is changed at the time T1 and the time T4, the potential of the node FD is changed by parasitic capacitance between the wiring TX and the node FD. If such a change of the potential is large, the output signal cannot be correctly output. In order to suppress the change of the potential of the node FD at the time of changing the potential of the wiring TX, it is effective to reduce the capacitance between the gate and source or between the gate and drain of thetransistor304. Further, it is effective to increase the gate capacitance of thetransistor305. Still further, it is effective to electrically connect a capacitor to the node FD. Such a change in the potential of the node FD at the time of changing the potential of the wiring TX is considered negligible inFIG. 9B, for example, by taking appropriate measures.

Described above is the driving method of the photosensor301 having any of the configurations shown inFIGS. 5B and 5C.

The series of operations of the photosensor301 illustrated in any of the timing charts ofFIGS. 9A and 9B is roughly classified into a reset operation, a storage operation, and a selection operation. In other words, the operation from the time T2 to the time T3 corresponds to the reset operation; the operation from the time T3 to the time T4 corresponds to the storage operation; and the operation from the time T5 to the time T6 corresponds to the selection operation. Further, a period after the storage operation before the selection operation, that is, a period from the time T4 to the time T5 corresponds to a charge retention period in which electric charge is retained at the node FD. In this specification, a period during which the reset operation is performed is denoted by TR, a period during which the storage operation is performed is denoted by TI, and a period during which the selection operation is performed is denoted by TS.

The above is the description of the driving method of thephotosensor301.

(Driving Method of Display Element Including Light-Emitting Element)

Examples of a driving method of a display element including a light-emitting element are described.

(Driving Method 1 of Display Element Including Light-Emitting Element)

A driving method of thedisplay element101 of any of the configurations shown inFIGS. 2A and 2B,FIG. 3, andFIGS. 4A and 4B is described.FIG. 14A is an example of a timing chart of changing of the potential of each wiring (the wiring GL, the wiring SL) and the voltage (EL) applied between the pair of electrodes of the light-emittingelement102 shown inFIGS. 2A and 2B,FIG. 3, andFIGS. 4A and 4B.

In the timing chart ofFIG. 14A, for easy understanding of the operation of thedisplay element101, it is assumed that either a high-level potential or a low-level potential is supplied to the wiring GL and the wiring SL. Respective predetermined potentials are supplied to the wiring VR and the wiring VB. The potential difference between the potential supplied to the wiring VR and the potential supplied to the wiring VB is set as large as the light-emittingelement102 emits light at a voltage of the potential difference applied between the electrodes of the light-emittingelement102. For example, a high-level power supply potential VDD and a low-level power supply potential VSS may be supplied to the wiring VR and, the wiring VB, respectively.

Although description is made assuming that thetransistors201 and202 both are n-channel transistors, one embodiment of the present invention is not limited thereto; one or both of thetransistors201 and202 may be a p-channel transistor. Also in that case where one or each of thetransistors201 and202 is a p-channel transistor, the potential of each wiring is set so that ON/OFF of the transistors are the same as in the following description.

At time T1, the potential of the wiring GL is set to high, so that thetransistor201 is turned on. At that time, with the potential of the wiring SL set to high, thetransistor202 is also turned on. Consequently, the potential of the wiring VR is input to one of the electrodes of the light-emittingelement102 through thetransistor202. In this manner, a predetermined voltage is applied between the electrodes of the light-emittingelement102, so that the light-emittingelement102 emits light. Even after the time T1, the potential of the gate of thetransistor202 is kept by thecapacitor203, the parasitic capacitance, or the like, whereby the light-emittingelement102 keeps emitting light even after the potential of the wiring GL is set to low to turn off thetransistor201.

Then, at time T2, the potential of the wiring GL is set to high again, so that thetransistor201 is turned on. At that time, with the potential of the wiring SL set to low, thetransistor202 is turned off. Thus, the light-emittingelement102 can be made not to emit light.

The period during which the light-emittingelement102 emits light is denoted by TL.

(Driving Method 2 of Display Element Including Light-Emitting Element)

Next, another example of the driving method of thedisplay element101 of any of the configurations shown inFIGS. 2A and 2B,FIG. 3, andFIGS. 4A and 4B, which is different from the above-described driving method is described.FIG. 14B is an example of a timing chart of changing of the potential of each wiring (the wiring GL, the wiring SL, the wiring VB) and the voltage (EL) applied between the pair of electrodes of the light-emittingelement102 shown inFIGS. 2A and 2B,FIG. 3, andFIGS. 4A and 4B.

In the timing chart ofFIG. 14B, for easy understanding of the operation of thedisplay element101, it is assumed that either a high-level potential or a low-level potential is supplied to the wiring GL, the wiring SL, and the wiring VB. A predetermined potential is supplied to the wiring VR. For example, a high-level power supply potential VDD may be supplied to the wiring VR.

Although description is made assuming that thetransistors201 and202 both are n-channel transistors, one embodiment of the present invention is not limited thereto; one or both of thetransistors201 and202 may be a p-channel transistor. Also in that case where one or each of thetransistors201 and202 is a p-channel transistor, the potential of each wiring is set so that ON/OFF of the transistors are the same as in the following description.

At time T0, the potential of the wiring GL is set to high, so that thetransistor201 is turned on. At that time, with the potential of the wiring SL set to high, thetransistor202 is also turned on. Consequently, the potential of the wiring VR is input to one of the electrodes of the light-emittingelement102 through thetransistor202. However, since the potential of the wiring VB is substantially equal to the potential of the wiring VR, the light-emittingelement102 does not emit light.

At time T1, the potential of the wiring VB is changed (from a high-level to a low-level in the timing chart shown inFIG. 14B), so that a voltage as high as the light-emittingelement102 is made to emit light is applied between the electrodes of the light-emittingelement102. In this manner, the light-emittingelement102 emits light.

At time T2, the potential of the wiring VB is changed (from the low-level to the high-level in the timing chart shown inFIG. 14B), so that the potential of the wiring VB is substantially equal to the potential of the wiring VR. In this manner, the light-emittingelement102 can be made not to emit light.

The period during which the light-emittingelement102 emits light is denoted by TL.

(Driving Method 3 of Display Element Including Light-Emitting Element)

Next, an example of a driving method of thedisplay element101 of the configuration shown inFIG. 4D is described.FIG. 15A is an example of a timing chart of changing of the potential of each wiring (the wiring GL, the wiring SL, the wiring ER) and the voltage (EL) applied between the pair of electrodes of the light-emittingelement102 shown inFIG. 4D.

In the timing chart ofFIG. 15A, for easy understanding of the operation of thedisplay element101, it is assumed that either a high-level potential or a low-level potential is supplied to the wiring GL, the wiring SL, and the wiring ER. Respective predetermined potentials are supplied to the wiring VR and the wiring VB. The potential difference between the potential supplied to the wiring VR and the potential supplied to the wiring VB is set as large as the light-emittingelement102 emits light at a voltage of the potential difference applied between the electrodes of the light-emittingelement102. For example, a high-level power supply potential VDD and a low-level power supply potential VSS may be supplied to the wiring VR and the wiring VB, respectively.

Although description is made assuming that thetransistors201,202, and205 are n-channel transistors, one embodiment of the present invention is not limited thereto; one or more of thetransistors201,202, and205 may be a p-channel transistor. Also in that case where one or more or each of thetransistors201,202, and205 is/are a p-channel transistor/p-channel transistors, the potential of each wiring is set so that ON/OFF of the transistors are the same as in the following description.

At time T1, the potential of the wiring GL is set to high, so that thetransistor201 is turned on. At that time, with the potential of the wiring SL set to high, thetransistor202 is also turned on. Further at that time, the potential of the wiring ER is set to high to turn on the transistor205. Consequently, the potential of the wiring VR is input to one of the electrodes of the light-emittingelement102 through thetransistors202 and205. In this manner, a predetermined voltage is applied between the electrodes of the light-emittingelement102, so that the light-emittingelement102 emits light. Even after the time T1, the potential of the gate of thetransistor202 is kept by thecapacitor203, the parasitic capacitance, or the like, whereby the light-emittingelement102 keeps emitting light even after the potential of the wiring GL is set to low to turn off thetransistor201.

Then, at time T2, the potential of the wiring ER is set to low, so that the transistor205 is turned off. Thus, the light-emittingelement102 can be made not to emit light.

The period during which the light-emittingelement102 emits light is denoted by TL.

(Driving Method 4 of Display Element Including Light-Emitting Element)

Next, an example of a driving method of thedisplay element101 of the configuration shown inFIG. 4C is described.FIG. 15B is an example of a timing chart of changing of the potential of the wiring (the wiring SA) and the voltage (EL) applied between the pair of electrodes of the light-emittingelement102 shown inFIG. 4C.

In the timing chart ofFIG. 15B, for easy understanding of the operation of thedisplay element101, it is assumed that either a high-level potential or a low-level potential is supplied to the wiring SA. Respective predetermined potentials are supplied to the wiring VR and the wiring VB. The potential difference between the potential supplied to the wiring VR and the potential supplied to the wiring VB is set as large as the light-emittingelement102 emits light at a voltage of the potential difference applied between the electrodes of the light-emittingelement102. For example, a high-level power supply potential VDD and a low-level power supply potential VSS may be supplied to the wiring VR and the wiring VB, respectively.

Although description is made assuming that thetransistors201,202, and204 are n-channel transistors, one embodiment of the present invention is not limited thereto; one or more of thetransistors201,202, and204 may be a p-channel transistor. Also in that case where one or more or each of thetransistors201,202, and204 is/are a p-channel transistor/p-channel transistors, the potential of each wiring is set so that ON/OFF of the transistors are the same as in the following description.

Thedisplay element101 of the configuration shown inFIG. 4C can be driven byDriving Method 1 of Display Element including Light-Emitting Element orDriving Method 2 of Display Element including Light-Emitting Element described above when thetransistor204 is OFF. In addition, the light-emittingelement102 can be made to emit light regardless of the states (ON/OFF) of thetransistors201 and202 by setting the potential of the wiring SA to be high to turn on thetransistor204. The light-emittingelement102 keeps emitting light during which thetransistor204 is ON.

The period during which the light-emittingelement102 emits light is denoted by TL.

Described above is the driving method of the display element including the light-emitting element. Next, a driving method of the set including the photosensor and the display element including the light-emitting element is described.

(Driving Method of Sets Including Photosensors and Display Elements Including Light-Emitting Elements)

A reset operation and a storage operation are performed in thephotosensor301 during a period in which the light-emittingelement102 emits light with a predetermined luminance. That is, the period TR and the period TI are provided in the above-described period TL. In this manner, an object to be detected is irradiated with light emitted from the light-emittingelement102, and then light is reflected by the object and detected by thephotosensor301. During the period of the reset operation, the light-emittingelement102 may emit light with any luminance or does not necessarily emit light.

(Driving Method of Semiconductor Device Including Matrix of Sets Including Photosensors and Display Elements including Light-Emitting Elements)

The plurality of light-emittingelements102 arranged in a matrix is made to emit light simultaneously or sequentially with the same luminance to irradiate an object to be detected. Further, the reset operation and the storage operation are performed simultaneously or sequentially in the plurality ofphotosensors301 arranged in a matrix. In this driving method, the reset operation and the storage operation are performed in the photosensor during a period in which at least the light-emittingelement102 next to that photosensor emits light. For example, in one set including the light-emittingelement102 and thephotosensor301, the reset operation and the storage operation are performed in thephotosensor301 during a period in which the light-emittingelement102 in that set emits light. In this manner, a captured image of the object is generated and a position of the object is detected. The period of the storage operation can be made to equal to each other in the plurality ofphotosensors301.

The following driving method can be applied thereto, according to which noise of external light is reduced.

The light-emittingelements102 in one or more of the rows are made to emit light to irradiate an object to be detected with light, during which the reset operation and the storage operation are performed in thephotosensors301 in one row (or one column), and then, the light-emittingelements102 are made not to emit light, during which the reset operation and the storage operation are performed in thephotosensors301 in another row (or another column). It is preferable that the distance between the two rows (or two columns) be as close as possible. For example, one row and another row may be adjacent to each other; or one column and another column may be adjacent to each other. According to this method, fast change between light emission and non light emission of the light-emitting elements means that the object less moves between the time of light emission and the time of non light emission. After that, the selection operation is sequentially performed in thephotosensors301 in all the rows. Thus, a difference of an output signal obtained by thephotosensor301 between one row (or column) and another row (or column) is obtained. This difference is a signal component whose S/N ratio is improved with noise of external light cancelled. A captured image of the object is generated with the difference. In this manner, a captured image can be generated with higher accuracy.

Hereinafter, specific examples of the driving method of a semiconductor device such that noise of external light is reduced are described. In the semiconductor device, the plurality ofsets110 each of thephotosensor301 and thedisplay element101 including the light-emittingelement102 are arranged in a matrix of m (m is a natural number greater than or equal to 2) rows by n (n is a natural number greater than or equal to 2) columns. Thephotosensor301 includes thephotoelectric converter302 and theamplifier303 which is electrically connected to thephotoelectric converter302. Thedisplay element101 including the light-emittingelement102 includes thecontroller103 which is electrically connected to the light-emittingelement102. The amplifier and the controller are electrically connected to the same power supply line per set. Timing charts ofFIGS. 10A and 10B, 11A and 11B, 12A and 12B, and 13A and 13B are used for the description.

InFIGS. 10A and 10B, 11A and 11B, 12A and 12B, and 13A and 13B, (p, q) denotes theset110 in the p-th (p is a natural number less than or equal to m) row in the q-th (q is a natural number less than or equal to n) column in the plurality ofsets110 arranged in the matrix of m rows by n columns. InFIGS. 10A and 10B, 11A and 11B, 12A and 12B, and 13A and 13B, seven adjacent sets ((p, q), (p+1, q), (p+2, q), (p+3, q), (p, q+1), (p, q+2), (p, q+3)) are shown as a representative. In addition, the horizontal axis indicates time. As described above usingFIGS. 9A and 9B, 14A and 14B, and 15A and 15B, the period TL is a period during which the light-emittingelement102 emits light, the period TR is a period during which thephotosensor301 performs the reset operation, the period TI is a period during which thephotosensor301 performs the storage operation, and the period TS is a period during which thephotosensor301 performs the selection operation.

When a captured image of an object to be detected is generated or a position of the object is detected, the luminance of the light-emittingelements102 is uniform. On the other hand, when an image is displayed in the semiconductor device, the luminance of the light-emittingelement102 is adjusted in accordance with an image signal. A known driving method can be employed as a driving method for displaying an image in thedisplay device101, and thus description thereof is omitted.

(Driving Method 1)

A driving method illustrated in the timing chart ofFIG. 10A is used. In that case, any of the driving method illustrated inFIGS. 14A, 14B, 15A, and 15B can be used as the driving method of the light-emittingelement102, and any of the driving method illustrated inFIGS. 9A and 9B can be used as the driving method of thephotosensor301.

The light-emittingelements102 are made to emit light sequentially row-by-row. During the period in which the light-emittingelements102 emit light, the reset operation and the storage operation are performed simultaneously in the photosensors in the p-th row and (p+2)-th row. After that, with the light-emittingelements102 made not to emit light, the reset operation and the storage operation are performed simultaneously in the photosensors in the (p+1)-th row and (p+3)-th row. Then, the selection operation is performed by thephotosensors301 in all the rows sequentially row-by-row. Then, a difference between output signals obtained by the photosensors in adjacent rows is obtained. Using this difference, a captured image of an object to be detected is generated and a position of the object is detected.

The light-emittingelements102 in the (p+1)-th row and (p+3)-th row are not necessarily made to emit light in the period during which the reset operation and the storage operation are performed simultaneously in the photosensors in the p-th row and (p+2)-th row in the driving method illustrated inFIG. 10A.

Although the light-emittingelements102 are made to emit light sequentially row-by-row in the driving method illustrated in the timing chart ofFIG. 10A, the light-emittingelements102 in all the rows may be simultaneously made to emit light. For example, a driving method illustrated in the timing chart ofFIG. 10B can be used. In that case, any of the driving method illustrated inFIGS. 14B and 15B can be used as the driving method of the light-emittingelement102, and any of the driving method illustrated inFIGS. 9A and 9B can be used as the driving method of thephotosensor301.

The light-emittingelements102 in all the rows are made to emit light all at once. During the period in which the light-emittingelements102 emit light, the reset operation and the storage operation are performed simultaneously in the photosensors in the p-th row and (p+2)-th row. After that, with the light-emittingelements102 made not to emit light, the reset operation and the storage operation are performed simultaneously in the photosensors in the (p+1)-th row and (p+3)-th row. Then, the selection operation is performed by thephotosensors301 in all the rows sequentially row-by-row. Thus, a difference between output signals obtained by the photosensors in adjacent rows is obtained. Using this difference, a captured image of an object to be detected is generated and a position of the object is detected.

The light-emittingelements102 in the (p+1)-th row and (p+3)-th row are not necessarily made to emit light in the period during which the reset operation and the storage operation are performed simultaneously in the photosensors in the p-th row and (p+2)-th row in the driving method illustrated inFIG. 10B.

Although the reset operation and the storage operation are performed simultaneously in the photosensors in the p-th row and (p+2)-th row and the reset operation and the storage operation are performed simultaneously in the photosensors in the (p+1)-th row and (p+3)-th row in each of the driving methods illustrated in the timing charts ofFIGS. 10A and 10B, one embodiment of the present invention is not limited thereto. The reset operation and the storage operation may be performed sequentially in order of row in the photosensors in the p-th row and (p+2)-th row, and the reset operation and the storage operation may be performed sequentially in order of row in the photosensors in the (p+1)-th row and (p+3)-th row. For example, a driving method illustrated in the timing chart ofFIG. 11A can be used. In that case, any of the driving method illustrated inFIGS. 14A and 14B, and 15A and 15B can be used as the driving method of the light-emittingelement102, and any of the driving method illustrated inFIGS. 9A and 9B can be used as the driving method of thephotosensor301.

The light-emittingelements102 are made to emit light sequentially row-by-row. During the period in which the light-emittingelements102 emit light, the reset operation and the storage operation are performed sequentially in order of row in the photosensors in the p-th row and (p+2)-th row. After that, with the light-emittingelements102 made not to emit light, the reset operation and the storage operation are performed sequentially in order of row in the photosensors in the (p+1)-th row and (p+3)-th row. Then, the selection operation is performed by thephotosensors301 in all the rows sequentially row-by-row. Thus, a difference between output signals obtained by the photosensors in adjacent rows is obtained. Using this difference, a captured image of an object to be detected is generated and a position of the object is detected.

The light-emittingelements102 in the (p+1)-th row and (p+3)-th row are not necessarily made to emit light in the period during which the reset operation and the storage operation are performed sequentially in order of row in the photosensors in the p-th row and (p+2)-th row in the driving method illustrated inFIG. 11A.

In the driving method illustrated inFIG. 11A, the light-emittingelements102 in all the rows may be simultaneously made to emit light as is in the driving method illustrated inFIG. 10B. A timing chart of such a driving method isFIG. 11B. In that case, any of the driving method illustrated inFIGS. 14B and 15B can be used as the driving method of the light-emittingelement102, and any of the driving method illustrated inFIGS. 9A and 9B can be used as the driving method of thephotosensor301.

The light-emittingelements102 in all the rows are made to emit light all at once. During the period in which the light-emittingelements102 emit light, the reset operation and the storage operation are performed sequentially in order of row in the photosensors in the p-th row and (p+2)-th row. After that, with the light-emittingelements102 made not to emit light, the reset operation and the storage operation are performed sequentially in order of row in the photosensors in the (p+1)-throw and (p+3)-th row. Then, the selection operation is performed by thephotosensors301 in all the rows sequentially row-by-row. Thus, a difference between output signals obtained by the photosensors in adjacent rows is obtained. Using this difference, a captured image of an object to be detected is generated and a position of the object is detected.

The light-emittingelements102 in the (p+1)-th row and (p+3)-th row are not necessarily made to emit light in the period during which the reset operation and the storage operation are performed sequentially in order of row in the photosensors in the p-th row and (p+2)-th row in the driving method illustrated inFIG. 11B.

In the driving methods illustrated inFIGS. 10A and 10B and 11A and 11B, the order of the timing of making the light-emitting elements to emit light and the timing of making the light-emitting elements not to emit light may be reversed.

(Driving Method 2)

According toDriving Method 1 described above, the light-emitting elements are made to emit light to irradiate an object, during which the reset operation and the storage operation are performed in the photosensors in the p-th row, and then, the light-emitting elements are made not to emit light, during which the reset operation and the storage operation are performed in the photosensors in the (p+1)-th row. Alternatively,Driving Method 2 described below may be employed: an object is irradiated with light while the light-emitting elements are made to emit light, during which the reset operation and the storage operation are performed in the photosensors in the q-th column (q is a natural number less than or equal to n), and then, the light-emitting elements are made not to emit light, during which the reset operation and the storage operation are performed in the photosensors in the (q+1)-th column.

A driving method illustrated in the timing chart ofFIG. 12A is used. In that case, any of the driving method illustrated inFIGS. 14A and 14B and 15A and 15B can be used as the driving method of the light-emittingelement102, and any of the driving method illustrated inFIGS. 9A and 9B can be used as the driving method of thephotosensor301.

The light-emittingelements102 are made to emit light sequentially row-by-row. During the period in which the light-emittingelements102 emit light, the reset operation and the storage operation are performed simultaneously in the photosensors in the q-th column and (q+2)-th column. After that, with the light-emittingelements102 made not to emit light, the reset operation and the storage operation are performed simultaneously in the photosensors in the (q+1)-th column and (q+3)-th column. Then, the selection operation is performed by thephotosensors301 in all the rows sequentially row-by-row. Thus, a difference between output signals obtained by the photosensors in adjacent columns is obtained. Using this difference, a captured image of an object to be detected is generated and a position of the object is detected.

Although the light-emittingelements102 are made to emit light sequentially row-by-row in the driving method illustrated in the timing chart ofFIG. 12A, the light-emittingelements102 in all the rows may be simultaneously made to emit light. For example, a driving method illustrated in the timing chart ofFIG. 12B can be used. In that case, any of the driving method illustrated inFIGS. 14B and 15B can be used as the driving method of the light-emittingelement102, and any of the driving method illustrated inFIGS. 9A and 9B can be used as the driving method of thephotosensor301.

The light-emittingelements102 in all the rows are made to emit light all at once. During the period in which the light-emittingelements102 emit light, the reset operation and the storage operation are performed simultaneously in the photosensors in the q-th column and (q+2)-th column. After that, with the light-emittingelements102 made not to emit light, the reset operation and the storage operation are performed simultaneously in the photosensors in the (q+1)-th column and (q+3)-th column. Then, the selection operation is performed by thephotosensors301 in all the rows sequentially row-by-row. Thus, a difference between output signals obtained by the photosensors in adjacent columns is obtained. Using this difference, a captured image of an object to be detected is generated and a position of the object is detected.

Although the reset operation and the storage operation are performed simultaneously in the photosensors in the q-th column and (q+2)-th column and the reset operation and the storage operation are performed simultaneously in the photosensors in the (q+1)-th column and (q+3)-th column in each of the driving methods illustrated in the timing charts ofFIGS. 12A and 12B, one embodiment of the present invention is not limited thereto. The reset operation and the storage operation may be performed sequentially in order of column in the photosensors in the q-th column and (q+2)-th column, and the reset operation and the storage operation may be performed sequentially in order of column in the photosensors in the (q+1)-th column and (q+3)-th column. For example, a driving method illustrated in the timing chart ofFIG. 13A can be used. In that case, any of the driving method illustrated inFIGS. 14A and 14B and 15A and 15B can be used as the driving method of the light-emittingelement102, and any of the driving method illustrated inFIGS. 9A and 9B can be used as the driving method of thephotosensor301.

The light-emittingelements102 are made to emit light sequentially row-by-row. During the period in which the light-emittingelements102 emit light, the reset operation and the storage operation are performed sequentially in order of column in the photosensors in the q-th column and (q+2)-th column. After that, with the light-emittingelements102 made not to emit light, the reset operation and the storage operation are performed sequentially in order of column in the photosensors in the (q+1)-th column and (q+3)-th column. Then, the selection operation is performed by thephotosensors301 in all the rows sequentially row-by-row. Thus, a difference between output signals obtained by the photosensors in adjacent columns is obtained. Using this difference, a captured image of an object to be detected is generated and a position of the object is detected.

In the driving method illustrated inFIG. 13A, the light-emittingelements102 in all the rows may be simultaneously made to emit light as is in the driving method illustrated inFIG. 12B. A timing chart of such a driving method isFIG. 13B. In that case, any of the driving method illustrated inFIGS. 14B and 15B can be used as the driving method of the light-emittingelement102, and any of the driving method illustrated inFIGS. 9A and 9B can be used as the driving method of thephotosensor301.

The light-emittingelements102 in all the rows are made to emit light all at once. During the period in which the light-emittingelements102 emit light, the reset operation and the storage operation are performed sequentially in order of column in the photosensors in the q-th column and (q+2)-th column. After that, with the light-emittingelements102 made not to emit light, the reset operation and the storage operation are performed sequentially in order of column in the photosensors in the (q+1)-th column and (q+3)-th column. Then, the selection operation is performed by thephotosensors301 in all the rows sequentially row-by-row. Thus, a difference between output signals obtained by the photosensors in adjacent columns is obtained. Using this difference, a captured image of an object to be detected is generated and a position of the object is detected.

In the driving methods illustrated inFIGS. 12A and 12B and 13A and 13B, the order of the timing of making the light-emitting elements to emit light and the timing of making the light-emitting elements not to emit light may be reversed.

According toDriving Method 1 andDriving Method 2, the length of the interval from the reset and storage operations to the selection operation of thephotosensor301 differs depending on the row and/or column. However, a transistor in which a channel is formed in an oxide semiconductor layer can be used as a transistor included in theamplifier303, whereby noise caused by leakage due to off-state current of a transistor can be reduced. In this manner, a signal component whose S/N ratio is improved with noise cancelled can be obtained with accuracy.

This embodiment can be combined as appropriate with any other embodiment.

Example 1

In this example, the field-effect mobility of a transistor applicable to the semiconductor device described in the above-described embodiment is described.

The actually measured field-effect mobility of an insulated gate transistor is lower than its inherent mobility because of a variety of reasons, which occurs not only in the case of using an oxide semiconductor. One of causes for reduction in the mobility is a defect inside a semiconductor or a defect at an interface between the semiconductor and an insulating film. With a Levinson model, the field-effect mobility on the assumption that no defect exists inside the semiconductor can be calculated theoretically. In this example, the field-effect mobility of an ideal oxide semiconductor without a defect inside the semiconductor was calculated theoretically, and calculation results of characteristics of minute transistors that were manufactured using such an oxide semiconductor are shown.

Assuming a potential barrier (such as a grain boundary) exists in a semiconductor, the measured field-effect mobility of the semiconductor, denoted by μ can be expressed by the following formula where the inherent mobility of the semiconductor is μ₀.

$\begin{array}{cc}\mu ={\mathrm{<figure-callout\; label="\mu "\; filenames="US09841843-20171212-D00016.png,US09841843-20171212-D00017.png"\; state="\{\{state\}\}">\mu </figure-callout>}}_0\exp \left(-\frac{E}{\mathrm{kT}}\right)& \left[\mathrm{Formula}2\right]\end{array}$

In the formula, E denotes the height of the potential barrier, k denotes the Boltzmann constant, and T denotes the absolute temperature. Further, on the assumption that the potential barrier is attributed to a defect, the height of the potential barrier can be expressed by the following formula according to the Levinson model.

$\begin{array}{cc}E=\frac{e^2{\mathrm{<figure-callout\; label="N"\; filenames="US09841843-20171212-D00009.png,US09841843-20171212-D00010.png"\; state="\{\{state\}\}">N</figure-callout>}}^2}{8\varepsilon n}=\frac{e^3{\mathrm{<figure-callout\; label="N"\; filenames="US09841843-20171212-D00009.png,US09841843-20171212-D00010.png"\; state="\{\{state\}\}">N</figure-callout>}}^2\mathrm{<figure-callout\; label="t"\; filenames="US09841843-20171212-D00024.png"\; state="\{\{state\}\}">t</figure-callout>}}{8\varepsilon }{C}_{\mathrm{ox}}{V}_g& \left[\mathrm{Formula}3\right]\end{array}$

In the formula, e denotes the elementary charge, N denotes the average defect density per unit area in a channel, ε denotes the permittivity of the semiconductor, n denotes the number of carriers per unit area in the channel, C_oxdenotes the capacitance per unit area, V_gdenotes the gate voltage, and t denotes the thickness of the channel. In the case where the thickness of the semiconductor layer is less than or equal to 30 nm, the thickness of the channel can be regarded as being the same as the thickness of the semiconductor layer. The drain current I_din a linear region of the semiconductor layer can be expressed by the following formula.

$\begin{array}{cc}{I}_d=\frac{W_{\mu }{V}_g{V}_d{C}_{\mathrm{ox}}}{L}\exp \left(-\frac{E}{\mathrm{kT}}\right)& \left[\mathrm{Formula}4\right]\end{array}$

In the formula, L denotes the channel length and W denotes the channel width, and L and W are each 10 μm in this example. In addition, V_ddenotes the drain voltage. Both sides of the above formula is divided by V_gand then logarithms of both the sides are taken, resulting in the following formula.

$\begin{array}{cc}\ln \left(\frac{I_d}{V_g}\right)=\ln \left(\frac{W_{\mu }{V}_d\mathrm{Cox}}{L}\right)-\frac{E}{\mathrm{kT}}=\ln \left(\frac{W_{\mu }{V}_d{C}_{\mathrm{ox}}}{L}\right)-\frac{{\mathrm{<figure-callout\; label="e"\; filenames="US09841843-20171212-D00010.png,US09841843-20171212-D00011.png"\; state="\{\{state\}\}">e</figure-callout>}}^3{\mathrm{<figure-callout\; label="N"\; filenames="US09841843-20171212-D00009.png,US09841843-20171212-D00010.png"\; state="\{\{state\}\}">N</figure-callout>}}^2\mathrm{<figure-callout\; label="t"\; filenames="US09841843-20171212-D00024.png"\; state="\{\{state\}\}">t</figure-callout>}}{8\mathrm{kT}\varepsilon C_{\mathrm{ox}}{V}_g}& \left[\mathrm{Formula}5\right]\end{array}$

InFormula 5, a logarithm of V_gis expressed in the right side. From the formula, it is found that the defect density N can be obtained from the slope of a line in a graph which is obtained by plotting actual measured values with ln(I_d/V_g) as the ordinate and 1/V_gas the abscissa. That is, the defect density can be evaluated from the I_d−V_gcharacteristics of the transistor. The defect density N of an oxide semiconductor in which the ratio of indium (In), tin (Sn), and zinc (Zn) is 1:1:1 is about 1×10¹²/cm².

On the basis of the defect density obtained in this manner, or the like, μ₀results in 120 cm²/Vs fromFormula 2 andFormula 3. The measured mobility of an In—Sn—Zn oxide including a defect is about 40 cm²/Vs. However, assuming that no defect exists inside an oxide semiconductor and at the interface between the oxide semiconductor and an insulating layer, the mobility μ₀of the oxide semiconductor is estimated to be 120 cm²/Vs.

However, even when no defect exists inside the semiconductor, scattering at an interface between a channel and a gate insulating layer affects the transport property of the transistor. In other words, the mobility μ₁at a position that is a distance x away from the interface between the channel and the gate insulating layer is expressed by the following formula.

$\begin{array}{cc}\frac{1}{{\mathrm{<figure-callout\; label="\mu "\; filenames="US09841843-20171212-D00004.png,US09841843-20171212-D00009.png"\; state="\{\{state\}\}">\mu </figure-callout>}}_1}=\frac{1}{{\mathrm{<figure-callout\; label="\mu "\; filenames="US09841843-20171212-D00016.png,US09841843-20171212-D00017.png"\; state="\{\{state\}\}">\mu </figure-callout>}}_0}+\frac{D}{B}\exp \left(-\frac{x}{G}\right)& \left[\mathrm{Formula}6\right]\end{array}$

In the formula, D denotes the electric field in the gate direction, and B and G are constants. The values of B and G can be obtained from actual measurement results; according to the above measurement results, B is 4.75×10⁷cm/s and G is 10 nm (the depth to which the influence of interface scattering reaches). As D increases (i.e., when the gate voltage is increased), the second term ofFormula 6 is increased and accordingly the mobility μ₁is decreased.

Calculation results of the mobility μ₂of a transistor whose channel is formed in an ideal oxide semiconductor without a defect inside the semiconductor are shown inFIG. 19. For the calculation, device simulation software Sentaurus Device manufactured by Synopsys, Inc. was used, and the bandgap, the electron affinity, the relative permittivity, and the thickness of the oxide semiconductor were set to 2.8 eV, 4.7 eV, 15, and 15 nm, respectively according to measurement of a thin film of an oxide semiconductor that was formed by a sputtering method.

Further, the work functions of a gate, a source, and a drain of the transistor were set to 5.5 eV, 4.6 eV, and 4.6 eV, respectively. The thickness of a gate insulating layer of the transistor was set to 100 nm, and the relative permittivity thereof was set to 4.1. The channel length and the channel width were each 10 μm, and the drain voltage V_dwas set to 0.1 V.

As shown inFIG. 19, the mobility has a peak of more than 100 cm²/Vs at a gate voltage that is a little over 1 V, and decreases as the gate voltage becomes higher because the influence of interface scattering is increased. In order to reduce interface scattering, it is desirable that a top surface of the semiconductor layer be flat at the atomic level (atomic layer flatness).

Calculation results of characteristics of minute transistors which were manufactured using an oxide semiconductor having such a mobility are shown inFIGS. 22A to 22C,FIGS. 21A to 21C, andFIGS. 22A to 22C.FIGS. 23A and 23B illustrate cross-sectional structures of the transistors used for the calculation. The transistors illustrated inFIGS. 23A and 23B each include asemiconductor region1103aand asemiconductor region1103cwhich have n⁺-type conductivity in an oxide semiconductor layer. The resistivities of thesemiconductor region1103aand thesemiconductor region1103care 2×10⁻³Ωcm.

The transistor illustrated inFIG. 23A is formed over abase insulating film1101 and an embeddedinsulator1102 which is embedded in thebase insulating film1101 and formed of aluminum oxide. The transistor includes thesemiconductor region1103a, thesemiconductor region1103c, anintrinsic semiconductor region1103bserving as a channel formation region therebetween, and agate1105. The width of thegate1105 is 33 nm.

Agate insulating layer1104 is provided between thegate1105 and thesemiconductor region1103b. In addition, asidewall insulator1106aand asidewall insulator1106bare provided on both sides of thegate1105, and aninsulator1107 is provided over thegate1105 so as to prevent a short circuit between thegate1105 and another wiring. The sidewall insulator has a width of 5 nm. Further, asource1108aand adrain1108bare provided in contact with thesemiconductor region1103aand thesemiconductor region1103c, respectively. The channel width of the transistor is 40 nm.

The transistor illustrated inFIG. 23B is the same as the transistor inFIG. 23A in that it is formed over thebase insulating film1101 and the embeddedinsulator1102 formed of aluminum oxide and that it includes thesemiconductor region1103a, thesemiconductor region1103c, theintrinsic semiconductor region1103bprovided therebetween, thegate1105 having a width of 33 nm, thegate insulating layer1104, thesidewall insulator1106a, thesidewall insulator1106b, theinsulator1107, thesource1108a, and thedrain1108b.

The transistor illustrated inFIG. 23A is different from the transistor illustrated inFIG. 23B in the conductivity type of semiconductor regions under thesidewall insulator1106aand thesidewall insulator1106b. In the transistor illustrated inFIG. 23A, the semiconductor regions under thesidewall insulator1106aand thesidewall insulator1106bare part of thesemiconductor region1103ahaving n⁺-type conductivity and part of thesemiconductor region1103chaving n⁺-type conductivity, whereas in the transistor illustrated inFIG. 23B, the semiconductor regions under thesidewall insulator1106aand thesidewall insulator1106bare part of theintrinsic semiconductor region1103b. In other words, in the semiconductor layer ofFIG. 23B, a region having a width of L_offwhere thesemiconductor region1103a(thesemiconductor region1103c) does not overlap with thegate1105 is provided. This region is called an offset region, and the width L_offis called an offset length. As is clear from the drawing, the offset length is equal to the width of thesidewall insulator1106a(thesidewall insulator1106b).

The other parameters used in calculation are as described above. For the calculation, device simulation software Sentaurus Device manufactured by Synopsys, Inc. was used.FIGS. 20A to 20C show the gate voltage (V_g: a potential difference between the gate and the source) dependence of the drain current (I_d, indicated by a solid line) and the mobility (μ, indicted by a dotted line) of the transistor having the structure illustrated inFIG. 23A. The drain current I_dwas calculated where the drain voltage (a potential difference between the drain and the source) was +1 V and the mobility μ was calculated where the drain voltage was +0.1 V.

The thickness of the gate insulating layer was 15 nm, 10 nm, and 5 nm inFIG. 20A,FIG. 20B, andFIG. 20C, respectively. As the gate insulating layer gets thinner, the drain current I_d(off-state current) particularly in an off state is significantly decreased. In contrast, there is no noticeable change in the peak value of the mobility μ and the drain current I_d(on-state current) in an on state. The graphs show that the drain current exceeds 10 μA at a gate voltage of around 1 V.

FIGS. 21A to 21C show the gate voltage V_gdependence of the drain current I_d(indicated by a solid line) and the mobility μ (indicated by a dotted line) of the transistor having the structure illustrated inFIG. 23B where the offset length L_offwas 5 nm. The drain current I_dwas calculated where the drain voltage was +1 V and the mobility μ was calculated where the drain voltage was +0.1 V. The thickness of the gate insulating layer was 15 nm, 10 nm, and 5 nm inFIG. 21A,FIG. 21B, andFIG. 21C, respectively.

FIGS. 22A to 22C show the gate voltage V_gdependence of the drain current I_d(indicated by a solid line) and the mobility μ (indicated by a dotted line) of the transistor having the structure illustrated inFIG. 23B where the offset length L_offwas 15 nm. The drain current I_dwas calculated where the drain voltage was +1 V and the mobility μ was calculated where the drain voltage was +0.1 V. The thickness of the gate insulating layer was 15 nm, 10 nm, and 5 nm inFIG. 22A,FIG. 22B, andFIG. 22C, respectively.

In either of the structures, as the gate insulating layer gets thinner, the off-state current is significantly decreased, whereas no noticeable change occurs in the peak value of the mobility μ and the on-state current.

The peak of the mobility μ is about 80 cm²/Vs inFIGS. 20A to 20C, about 60 cm²/Vs inFIGS. 21A to 21C, and about 40 cm²/Vs inFIGS. 22A to 22C; thus, the peak of the mobility μ decreases as the offset length L_offis increased. The same applies to the off-state current. The on-state current also decreases as the offset length L_offis increased; however, the decrease in the on-state current is much more gradual than the decrease in the off-state current. Further, either graph shows that the drain current exceeds 10 μA at a gate voltage of around 1 V.

A transistor in which an oxide semiconductor including In, Sn, and Zn as main components is used as a channel formation region can be provided with favorable characteristics by depositing the oxide semiconductor while heating a substrate or by performing heat treatment after an oxide semiconductor film is formed. The main component refers to an element included in composition at 5 atomic % or more.

By heating the substrate after formation of the oxide semiconductor film including In, Sn, and Zn as main components, the field-effect mobility of the transistor can be improved. Further, the threshold voltage of the transistor can be shifted in the positive direction to make the transistor a normally-off transistor.

As an example,FIGS. 24A to 24C each show characteristics of a transistor that includes an oxide semiconductor film including In, Sn, and Zn as main components with a channel length L of 3 μm and a channel width W of 10 μm, and a gate insulating layer with a thickness of 100 nm. The drain voltage V_dwas set to 10 V.

FIG. 24A shows characteristics of a transistor whose oxide semiconductor film including In, Sn, and Zn as main components was formed by a sputtering method without heating a substrate. The field-effect mobility of the transistor was up to 18.8 cm²/Vsec. On the other hand, when the oxide semiconductor film including In, Sn, and Zn as main components is formed while heating the substrate, the field-effect mobility can be improved.FIG. 24B shows characteristics of a transistor whose oxide semiconductor film including In, Sn, and Zn as main components was formed while heating a substrate at 200° C.; the field-effect mobility of the transistor was up to 32.2 cm²/Vsec.

The field-effect mobility can be further improved by performing heat treatment after formation of the oxide semiconductor film including In, Sn, and Zn as main components.FIG. 24C shows characteristics of a transistor whose oxide semiconductor film including In, Sn, and Zn as main components was formed by sputtering at 200° C. and then subjected to heat treatment at 650° C. The field-effect mobility of the transistor was up to 34.5 cm²/Vsec.

The heating of the substrate can be expected to have an effect of reducing entrance of moisture into the oxide semiconductor film during the formation by sputtering. Further, the heat treatment after film formation enables hydrogen, a hydroxyl group, or moisture to be removed from the oxide semiconductor film, so that the field-effect mobility can be improved as described above. Such an improvement in the field-effect mobility is considered to be achieved not only by removal of impurities by dehydration or dehydrogenation but also by a reduction in the interatomic distance due to an increase in density. In addition, by removal of impurities from the oxide semiconductor, the oxide semiconductor can be crystallized with high purification. With such a highly purified non-single-crystal oxide semiconductor, ideally, a field-effect mobility over 100 cm²/Vsec can be expected to be realized.

The oxide semiconductor including In, Sn, and Zn as main components may be crystallized in the following manner: oxygen ions are implanted into the oxide semiconductor, hydrogen, a hydroxyl group, or moisture included in the oxide semiconductor is released by heat treatment, and the oxide semiconductor is crystallized through the heat treatment or by another heat treatment performed later. By such crystallization treatment or recrystallization treatment, a non-single-crystal oxide semiconductor having favorable crystallinity can be provided.

The heating of the substrate during film formation and/or the heat treatment after the film formation contribute(s) not only to improvement of the field-effect mobility but also to make the transistor a normally-off transistor. In a transistor in which an oxide semiconductor film including In, Sn, and Zn as main components and is formed without heating a substrate is used as a channel formation region, the threshold voltage tends to be shifted in the negative direction. However, when the oxide semiconductor film formed while heating the substrate is used, such a negative shift of the threshold voltage can be prevented. That is, the threshold voltage is shifted so that the transistor becomes a normally-off transistor; this tendency can be confirmed by comparison betweenFIGS. 24A and 24B.

The threshold voltage can also be controlled by changing the ratio of In, Sn, and Zn; a normally-off transistor is expected to be formed with a composition ratio of In:Sn:Zn of 2:1:3. In addition, the composition ratio of In:Sn:Zn=2:1:3 enables an oxide semiconductor film having high crystallinity to be formed.

The temperature of the heating of the substrate or the temperature of the heat treatment is higher than or equal to 150° C., preferably higher than or equal to 200° C., further preferably higher than or equal to 400° C. With film formation or heat treatment at a higher temperature, the transistor can be made to a normally-off transistor.

Further, by heating of the substrate during film formation and/or by heat treatment after the film formation, the stability against a gate-bias stress can be increased. For example, when a gate bias is applied with an intensity of 2 MV/cm at 150° C. for one hour, a drift of the threshold voltage can be suppressed to less than ±1.5 V, preferably less than ±1.0 V.

A BT test was performed on the following two transistors:Sample 1 on which heat treatment was not performed after formation of an oxide semiconductor film, andSample 2 on which heat treatment at 650° C. was performed after formation of an oxide semiconductor film.

First, V_g−I_dcharacteristics of the transistors were measured at a substrate temperature of 25° C. at V_dsof 10 V where V_dsis the drain voltage (the potential difference between the drain and the source) of each transistor. Next, the substrate temperature was changed to 150° C. and V_dswas changed to 0.1 V. Then, V_gof 20 V was applied so that the intensity of the electric field applied to each gate insulating layer was 2 MV/cm, and the condition was kept for one hour. Next, V_gwas changed to 0 V. Then, V_g−I_dcharacteristics of the transistors were measured at a substrate temperature of 25° C. at V_dsof 10 V. This process is called a positive BT test.

In a similar manner, first, V_g−I_dcharacteristics of the transistors were measured at a substrate temperature of 25° C. at V_dsof 10 V. Next, the substrate temperature was changed to 150° C. and V_dswas changed to 0.1 V. Then, V_gof −20 V was applied so that the intensity of the electric field applied to each gate insulating film was −2 MV/cm, and the condition was kept for one hour. Next, V_gwas changed to 0 V. Then, V_g−I_dcharacteristics of the transistors were measured at a substrate temperature of 25° C. at V_dsof 10 V. This process is called a negative BT test.

FIGS. 25A and 25B show a result of the positive BT test ofSample 1 and a result of the negative BT test ofSample 1, respectively.FIGS. 26A and 26B show a result of the positive BT test ofSample 2 and a result of the negative BT test ofSample 2, respectively.

The amount of shift in the threshold voltage ofSample 1 due to the positive BT test and that amount due to the negative BT test were 1.80 V and −0.42 V, respectively. The amount of shift in the threshold voltage ofSample 2 due to the positive BT test and that amount due to the negative BT test were 0.79 V and 0.76 V, respectively. It is found that, in each ofSample 1 andSample 2, the amount of shift in the threshold voltage by the BT test is small and the reliability of each transistor is high.

The heat treatment can be performed in an oxygen atmosphere; the heat treatment may be performed first in an atmosphere of nitrogen or an inert gas or under reduced pressure, and then in an atmosphere including oxygen. Oxygen can be supplied to the oxide semiconductor after dehydration or dehydrogenation, whereby an effect of the heat treatment can be further increased. As a method for supplying oxygen after dehydration or dehydrogenation, a method in which oxygen ions are accelerated by an electric field and implanted into the oxide semiconductor film may be employed.

A defect due to oxygen deficiency is likely to be caused in the oxide semiconductor or at an interface between the oxide semiconductor and a film in contact with the oxide semiconductor; however, by supplying excess oxygen into the oxide semiconductor through the heat treatment, oxygen deficiency caused later can be compensated with excess oxygen. The excess oxygen is oxygen existing mainly between lattices, which can be included in the oxide semiconductor without causing crystal distortion or the like as long as the concentration of excess oxygen is greater than or equal to 1×10¹⁶/cm³and less than or equal to 2×10²⁰/cm³.

Further, a more stable oxide semiconductor film can be obtained by performing heat treatment to form a crystal in at least part of the oxide semiconductor. For example, when an oxide semiconductor film which is formed by sputtering using a target having a composition ratio of In:Sn:Zn=1:1:1 without heating a substrate is analyzed by X-ray diffraction (XRD), a halo pattern is observed. That oxide semiconductor film can be crystallized by heat treatment. When heat treatment at 650° C. is performed thereon, for example, a clear diffraction peak can be observed by X-ray diffraction, though the temperature of the heat treatment can be set as appropriate.

An XRD analysis of an In—Sn—Zn—O film was conducted. The XRD analysis was conducted using an X-ray diffractometer D8 ADVANCE manufactured by Bruker AXS, in the out-of-plane direction.

Sample A and Sample B were prepared, on which the XRD analysis were performed. Methods for manufacturing Sample A and Sample B are described below.

An In—Sn—Zn—O film with a thickness of 100 nm was formed over a quartz substrate that had been subjected to dehydrogenation treatment.

The In—Sn—Zn—O film was formed with a sputtering apparatus with a power of 100 W (DC) in an oxygen atmosphere. An In—Sn—Zn—O target having an atomic ratio of In:Sn:Zn=1:1:1 was used as a target. The substrate heating temperature in film formation was set at 200° C. A sample manufactured in this manner was used as Sample A.

Next, a sample manufactured by a method similar to that of Sample A was subjected to heat treatment at 650° C. As the heat treatment, heat treatment in a nitrogen atmosphere was first performed thereon for one hour and heat treatment in an oxygen atmosphere was further performed thereon for one hour without lowering the temperature. A sample manufactured in this manner was used as Sample B.

FIG. 29 shows XRD spectra of Sample A and Sample B. No peak derived from a crystal was observed in Sample A, whereas peaks derived from a crystal were observed at 2θ of around 35 deg and 2θ in the range of from 37 deg to 38 deg in Sample B.

These substrate heating and heat treatment have an effect of preventing hydrogen and a hydroxyl group, which are adverse impurities for an oxide semiconductor, from being included in the film or an effect of removing them from the film. That is, an oxide semiconductor can be highly purified by removing hydrogen serving as a donor impurity from the oxide semiconductor, whereby a normally-off transistor can be obtained. The high purification of an oxide semiconductor enables the off-state current of the transistor to be reduced to 1 aA/μm or less, where the unit of the off-state current means the amount per micrometer of a channel width.

FIG. 30 shows a relation between the off-state current of a transistor and the inverse of substrate temperature (absolute temperature) T at measurement, where for simplicity, the horizontal axis indicates a value (1000/T) obtained by multiplying an inverse of the substrate temperature at measurement by 1000.

Specifically, as shown inFIG. 30, the off-state current can be reduced to 1 aA/μm (1×10⁻¹⁸A/μm) or less, 100 zA/μm (1×10⁻¹⁹A/μm) or less, and 1 zA/μm (1×10⁻²¹A/μm) or less at substrate temperatures of 125° C., 85° C., and room temperature (27° C.), respectively. Preferably, the off-state current can be reduced to 0.1 aA/μm (1×10⁻¹⁹A/μm) or less, 10 zA/μm (1×10⁻²⁰A/μm) or less, and 0.1 zA/μm (1×10⁻²²A/μm) or less at 125° C., 85° C., and room temperature, respectively.

Needless to say, in order to prevent hydrogen and moisture from entering the oxide semiconductor film during formation thereof, it is preferable to increase the purity of a sputtering gas by sufficiently suppressing leakage from the outside of a deposition chamber and degasification through an inner wall of the deposition chamber. For example, a gas with a dew point of −70° C. or lower is preferably used as the sputtering gas in order to prevent moisture from entering the film. In addition, it is preferable to use a target which is highly purified so as not to include impurities such as hydrogen and moisture. Although it is possible to remove moisture from a film of an oxide semiconductor including In, Sn, and Zn as main components by heat treatment, the temperature at which moisture is released from the oxide semiconductor including In, Sn, and Zn as main components is higher than the temperature at which moisture is released from an oxide semiconductor including In, Ga, and Zn as main components; therefore, a moisture-free film is preferably formed in an as-depo state.

In addition, the relation between the substrate temperature and electric characteristics of a transistor using Sample B which has been subjected to the heat treatment at 650° C. after formation of the oxide semiconductor film was evaluated.

The transistor used for the measurement has a channel length L of 3 μm, a channel width W of 10 μm, Lov of 0 μm, and dW of 0 μm. In addition, V_dswas set to 10 V. The substrate temperature was set to −40° C., −25° C., 25° C., 75° C., 125° C., and 150° C. In the transistor, the width of a portion where a gate electrode overlaps with one of a pair of electrodes is denoted by Lov, and the width of a portion of the pair of electrodes, which does not overlap with the oxide semiconductor film, is denoted by dW.

FIG. 27 shows the V_gdependence of I_d(indicated by a solid line) and of the field-effect mobility (indicated by a dotted line). Further,FIG. 28A shows a relation between the substrate temperature and the threshold voltage, andFIG. 28B shows a relation between the substrate temperature and the field-effect mobility.

It is seen fromFIG. 28A that the threshold voltage gets lower as the substrate temperature increases. The threshold voltage is decreased from 1.09 V to −0.23 V in the range from −40° C. to 150° C.

Further, it is seen fromFIG. 28B that the field-effect mobility gets lower as the substrate temperature increases. The field-effect mobility is decreased from 36 cm²/Vs to 32 cm²/Vs in the range from −40° C. to 150° C. Thus, it is found that variation in electric characteristics is small in the above temperature range.

In a transistor in which such an oxide semiconductor including In, Sn, and Zn as main components is used as a channel formation region, a field-effect mobility of 30 cm²/Vsec or higher, preferably 40 cm²/Vsec or higher, further preferably 60 cm²/Vsec or higher can be exhibited with the off-state current suppressed to 1 aA/μm or less, which can provide an on-state current as high as is needed for an LSI. For example, in an FET where L/W is 33 nm/40 nm, an on-state current of 12 μA or more can flow at a gate voltage of 2.7 V at a drain voltage of 1.0 V. In addition, sufficient electric characteristics can be ensured in a temperature range needed for operation of the transistor. With such characteristics, an integrated circuit can be equipped with a novel function without decreasing the operation speed by providing a transistor including an oxide semiconductor in the integrated circuit formed using a Si semiconductor.

As described above, heating of a substrate during deposition of an oxide semiconductor including In, Sn, and Zn as main components and/or heat treatment after deposition of the oxide semiconductor leads to an improvement in characteristics of a transistor.

This example can be implemented in combination with any of the embodiments and the other examples as appropriate.

Example 2

In this example, examples of a transistor in which an In—Sn—Zn—O film is used as an oxide semiconductor film are described usingFIGS. 31A and 31B andFIGS. 32A and 32B.

FIGS. 31A and 31B are a top view and a cross-sectional view of a coplanar transistor having a top-gate top-contact structure.FIG. 31A is the top view of the transistor.FIG. 31B shows the cross section A-B along dashed-dotted line A-B inFIG. 31A.

The transistor illustrated inFIG. 31B includes asubstrate2100; abase insulating film2102 provided over thesubstrate2100; a protectiveinsulating film2104 provided in the periphery of thebase insulating film2102; anoxide semiconductor film2106 which is provided over thebase insulating film2102 and the protectiveinsulating film2104 and includes a high-resistance region2106aand a low-resistance region2106b; agate insulating layer2108 provided over theoxide semiconductor film2106; agate electrode2110 provided to overlap with theoxide semiconductor film2106 with thegate insulating layer2108 provided therebetween; asidewall insulating film2112 provided in contact with a side surface of thegate electrode2110; a pair ofelectrodes2114 provided in contact with at least the low-resistance region2106b; aninterlayer insulating film2116 provided to cover at least theoxide semiconductor film2106, thegate electrode2110, and the pair ofelectrodes2114; and awiring2118 provided to be connected to at least one of the pair ofelectrodes2114 through an opening formed in theinterlayer insulating film2116.

Further, a protective film may be provided to cover theinterlayer insulating film2116 and thewiring2118, though not shown. With the protective film, a minute amount of leakage current generated by surface conduction of theinterlayer insulating film2116 can be reduced and thus the off-state current of the transistor can be reduced.

Another example of the transistor in which an In—Sn—Zn—O film is used as an oxide semiconductor film is described below.

FIGS. 32A and 32B are a top view and a cross-sectional view which illustrate a structure of a transistor which was manufactured in this example.FIG. 32A is the top view of the transistor.FIG. 32B is a cross-sectional view along dashed-dotted line A-B inFIG. 32A.

The transistor illustrated inFIG. 32B includes asubstrate3600; abase insulating film3602 provided over thesubstrate3600; anoxide semiconductor film3606 provided over thebase insulating film3602; a pair ofelectrodes3614 in contact with theoxide semiconductor film3606; agate insulating layer3608 provided over theoxide semiconductor film3606 and the pair ofelectrodes3614; agate electrode3610 provided to overlap with theoxide semiconductor film3606 with thegate insulating layer3608 provided therebetween; aninterlayer insulating film3616 provided to cover thegate insulating layer3608 and thegate electrode3610;wirings3618 connected to the pair ofelectrodes3614 through openings formed in thegate insulating layer3608 and theinterlayer insulating film3616; and aprotective film3620 provided to cover theinterlayer insulating film3616 and thewirings3618.

A glass substrate was used as thesubstrate3600. A silicon oxide film was used as thebase insulating film3602. An In—Sn—Zn—O film was used as theoxide semiconductor film3606. A tungsten film was used as the pair ofelectrodes3614. A silicon oxide film was used as thegate insulating layer3608. A stacked-layer structure of a tantalum nitride film and a tungsten film was used as thegate electrode3610. A stacked-layer structure of a silicon oxynitride film and a polyimide film was used as theinterlayer insulating film3616. A stacked-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order was used as thewirings3618. A polyimide film was used as theprotective film3620.

Note that in the transistor having the structure illustrated inFIG. 32A, the width of a portion where thegate electrode3610 overlaps with the pair ofelectrodes3614 is denoted by Lov. In addition, the width of a portion of the pair ofelectrodes3614, which does not overlap with theoxide semiconductor film3606, is denoted by dW.

This example can be implemented in combination with any of the embodiments and the other examples as appropriate.

Example 3

One feature of a semiconductor device of one embodiment of the present invention is high definition.

Such a semiconductor device of one embodiment of the present invention can be used for display devices, laptop computers, or image reproducing devices provided with recording media (typically, devices which reproduce the content of recording media such as digital versatile discs (DVDs) and have displays for displaying the reproduced images). Other than the above, as electronic devices which can be equipped with the semiconductor device according to one embodiment of the present invention, mobile phones, portable game machines, portable information terminals, e-book readers, video cameras such as digital still cameras, goggle-type displays (head mounted displays), navigation systems, audio reproducing devices (e.g., car audio systems and digital audio players), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATM), vending machines, and the like can be given.

This example can be implemented in combination with any of the embodiments and the other examples as appropriate.

This application is based on Japanese Patent Application serial no. 2010278905 and 2011108276 filed with Japan Patent Office on Dec. 15, 2010 and May 13, 2011, the entire contents of which are hereby incorporated by reference.

Claims (17)

What is claimed is:

1. A semiconductor device comprising:

a plurality of sets, each of the plurality of sets including:

a first photosensor including a first photoelectric converter, a first transistor, a second transistor and a third transistor;

a display element including a light-emitting element, a fourth transistor and a fifth transistor; and

a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, a sixth wiring, a seventh wiring and an eighth wiring,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,

wherein the other of the source and the drain of the third transistor is electrically connected to the first wiring,

wherein a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to one of a pair of electrodes of the first photoelectric converter,

wherein the other of the pair of electrodes of the first photoelectric converter is electrically connected to the fourth wiring,

wherein a gate of the first transistor is electrically connected to the third wiring,

wherein a gate of the third transistor is electrically connected to the fifth wiring,

wherein a gate of the fourth transistor is electrically connected to the sixth wiring,

wherein one of a source and a drain of the fourth transistor is electrically connected to the eighth wiring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to a gate of the fifth transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to one of a pair of electrodes of the light-emitting element,

wherein the other of the pair of electrodes of the light-emitting element is electrically connected to the seventh wiring,

wherein the second wiring which is electrically connected to the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fifth transistor in one of the plurality of sets,

wherein a channel is formed in an oxide semiconductor layer comprising In, Ga, and Zn in each of the first to third transistors,

wherein an off-state current density of the each of the first to third transistors is less than or equal to 100 yA/μm,

wherein the first photosensor is configured to perform a reset operation and a storage operation in a p-th row during all the light-emitting elements emit light,

wherein the first photosensor is configured to perform the reset operation and the storage operation in a (p+1)-th row during all the light-emitting elements does not emit light,

wherein p is a natural number, and

wherein the semiconductor device is configured to obtain a difference between output signals in the p-th row and the (p+1)-th row.

2. The semiconductor device according toclaim 1, wherein the plurality of sets are arranged in a matrix of m (m is a natural number greater than or equal to 2) rows by n (n is a natural number greater than or equal to 2) columns.

3. The semiconductor device according toclaim 1,

wherein the first photosensor is configured to perform a selection operation during all the light-emitting elements do not emit light.

4. A semiconductor device comprising:

a plurality of sets, each of the plurality of sets including:

a first photosensor including a first photoelectric converter and a first transistor, a second transistor and a third transistor;

a display element including a light-emitting element, a fourth transistor and a fifth transistor;

a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, a sixth wiring and a seventh wiring; and

a power supply line,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the second wiring,

wherein a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to one of a pair of electrodes of the first photoelectric converter,

wherein the other of the pair of electrodes of the first photoelectric converter is electrically connected to the fourth wiring,

wherein a gate of the first transistor is electrically connected to the third wiring,

wherein a gate of the third transistor is electrically connected to the fifth wiring,

wherein a gate of the fourth transistor is electrically connected to the sixth wiring,

wherein one of a source and a drain of the fourth transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to a gate of the fifth transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to one of a pair of electrodes of the light-emitting element,

wherein the other of the pair of electrodes of the light-emitting element is electrically connected to the seventh wiring,

wherein the other of the source and the drain of the fifth transistor and the other of the source and the drain of the second transistor are electrically connected to the power supply line in one of the plurality of sets,

wherein a channel is formed in an oxide semiconductor layer comprising In, Ga, and Zn in each of the first to third transistors,

wherein an off-state current density of the each of the first to third transistors is less than or equal to 100 yA/μm,

wherein the first photosensor is configured to perform a reset operation and a storage operation in a q-th column during all the light-emitting elements emit light,

wherein the first photosensor is configured to perform the reset operation and the storage operation in a (q+1)-th column during all the light-emitting elements does not emit light,

wherein q is a natural number, and

wherein the semiconductor device is configured to obtain a difference between output signals in the q-th column and the (q+1)-th column.

5. The semiconductor device according toclaim 4, wherein the plurality of pixels are arranged in a matrix of m (m is a natural number greater than or equal to 2) rows by n (n is a natural number greater than or equal to 2) columns.

6. A semiconductor device comprising:

a plurality of sets, each of the plurality of sets including:

a first photosensor and a display element including a light-emitting element, a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, a sixth wiring, a seventh wiring, and an eighth wiring,

wherein the first photosensor includes a first photoelectric converter which is electrically connected to an amplifier,

wherein the display element includes a controller which is electrically connected to the light-emitting element,

wherein the amplifier includes a first transistor, a second transistor and a third transistor,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the third transistor is electrically connected to the second wiring,

wherein a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to one of a pair of electrodes of the first photoelectric converter,

wherein the other of the pair of electrodes of the first photoelectric converter is electrically connected to the fourth wiring,

wherein a gate of the first transistor is electrically connected to the third wiring,

wherein a gate of the third transistor is electrically connected to the fifth wiring,

wherein the controller includes a fourth transistor and a fifth transistor,

wherein a gate of the fourth transistor is electrically connected to the sixth wiring,

wherein one of a source and a drain of the fourth transistor is electrically connected to the eighth wiring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to a gate of the fifth transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a pair of electrodes of the light-emitting element,

wherein the other of the pair of electrodes of the light-emitting element is electrically connected to the seventh wiring,

wherein a channel is formed in an oxide semiconductor layer comprising In, Ga, and Zn in each of the first to third transistors,

wherein an off-state current density of the each of the first to third transistors is less than or equal to 100 yA/μm,

wherein the first photosensor is configured to perform a reset operation and a storage operation in a p-th row during all the light-emitting elements emit light,

wherein the first photosensor is configured to perform the reset operation and the storage operation in a (p+1)-th row during all the light-emitting elements does not emit light,

wherein p is a natural number, and

wherein the semiconductor device is configured to obtain a difference between output signals in the p-th row and the (p+1)-th row.

7. The semiconductor device according toclaim 6, wherein the plurality of sets are arranged in a matrix of m (m is a natural number greater than or equal to 2) rows by n (n is a natural number greater than or equal to 2) columns.

8. The semiconductor device according toclaim 6, wherein the first photoelectric converter is a photodiode or a phototransistor.

9. The semiconductor device according toclaim 6, wherein the light-emitting element is a light-emitting diode or an organic light-emitting element.

10. The semiconductor device according toclaim 6, wherein a channel is found in an oxide semiconductor layer in at least one of the fourth to sixth transistors.

11. The semiconductor device according toclaim 6,

wherein the controller includes a capacitor,

wherein one of a pair of electrodes of the capacitor is electrically connected to the gate of the fifth transistor, and

wherein the other of the pair of electrodes of the capacitor is electrically connected to one of the source and the drain of the fifth transistor.

12. The semiconductor device according toclaim 6,

wherein the controller includes a capacitor,

wherein one of a pair of electrodes of the capacitor is electrically connected to the gate of the fifth transistor and the other of the source and the drain of the fourth transistor, and

wherein the other of the pair of electrodes of the capacitor is electrically connected to the first wiring.

13. The semiconductor device according toclaim 6, further comprising a tenth wiring,

wherein the controller includes a capacitor,

wherein one of a pair of electrodes of the capacitor is electrically connected to the gate of the fifth transistor and the other of the source and the drain of the fourth transistor, and

wherein the other of the pair of electrodes of the capacitor is electrically connected to the tenth wiring.

14. The semiconductor device according toclaim 6, further comprising a ninth wiring,

wherein the controller includes a seventh transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to one of the pair of electrodes of the light-emitting element,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the one of the source and the drain of the fifth transistor, and

wherein a gate of the seventh transistor is electrically connected to the ninth wiring.

15. The semiconductor device according toclaim 14, wherein a channel is formed in an oxide semiconductor layer in at least one of the fourth to seventh transistors.

16. The semiconductor device according toclaim 6, further comprising a tenth wiring,

wherein the controller includes a seventh transistor,

wherein the seventh transistor is electrically connected between the first wiring and the one of the source and the drain of the fifth transistor, and

wherein a gate of the seventh transistor is electrically connected to the tenth wiring.

17. The semiconductor device according toclaim 16, wherein a channel is formed in an oxide semiconductor layer in at least one of the fourth to seventh transistors.

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