US9768345B2 - LED with current injection confinement trench - Google Patents

Abstract

A method and structure for forming an array of LED devices is disclosed. The LED devices in accordance with embodiments of the invention may include a confined current injection area, embedded mirror, or sidewall passivation layer, and any combination thereof.

Description

BACKGROUND

Field

The present invention relates to light emitting diode (LED) devices.

Background Information

Light emitting diodes (LEDs) are increasingly being considered as a replacement technology for existing light sources. For example, LEDs are found in signage, traffic signals, automotive tail lights, mobile electronics displays, and televisions. Various benefits of LEDs compared to traditional lighting sources may include increased efficiency, longer lifespan, variable emission spectra, and the ability to be integrated with various form factors.

One type of LED is an organic light emitting diode (OLED) in which the emissive layer of the diode is formed of an organic compound. One advantage of OLEDs is the ability to print the organic emissive layer on flexible substrates. OLEDs have been integrated into thin, flexible displays and are often used to make the displays for portable electronic devices such as cell phones and digital cameras.

Another type of LED is a semiconductor-based LED in which the emissive layer of the diode includes one or more semiconductor-based quantum well layers sandwiched between thicker semiconductor-based cladding layers. Some advantages of semiconductor-based LEDs compared to OLEDs can include increased efficiency and longer lifespan. High luminous efficacy, expressed in lumens per watt (lm/W), is one of the main advantages of semiconductor-based LED lighting, allowing lower energy or power usage compared to other light sources. Luminance (brightness) is the amount of light emitted per unit area of the light source in a given direction and is measured in candela per square meter (cd/m²) and is also commonly referred to as a Nit (nt). Luminance increases with increasing operating current, yet the luminous efficacy is dependent on the current density (A/cm²), increasing initially as current density increases, reaching a maximum and then decreasing due to a phenomenon known as “efficiency droop.” Many factors contribute to the luminous efficacy of an LED device, including the ability to internally generate photons, known as internal quantum efficiency (IQE). Internal quantum efficiency is a function of the quality and structure of the LED device. External quantum efficiency (EQE) is defined as light output divided by the electrical input power. EQE is a function of IQE and the light extraction efficiency of the LED device. At low operating current density (also called injection current density, or forward current density) the IQE and EQE of an LED device initially increases as operating current density is increased, then begins to tail off as the operating current density is increased in the phenomenon known as the efficiency droop. At low current density the efficiency is low due to the strong effect of defects or other processes by which electrons and holes recombine without the generation of light, called non-radiative recombination. As those defects become saturated radiative recombination dominates and efficiency increases. An “efficiency droop” or gradual decrease in efficiency begins as the injection-current density surpasses a low value, typically between 1.0 and 10 A/cm².

Semiconductor-based LEDs are commonly found in a variety of applications, including low-power LEDs used as indicators and signage, medium-power LEDs such as for light panels and automotive tail lights, and high-power LEDs such as for solid-state lighting and liquid crystal display (LCD) backlighting. In one application, high-powered semiconductor-based LED lighting devices may commonly operate at 400-1,500 mA, and may exhibit a luminance of greater than 1,000,000 cd/m². High-powered semiconductor-based LED lighting devices typically operate at current densities well to the right of peak efficiency on the efficiency curve characteristic of the LED device. Low-powered semiconductor-based LED indicator and signage applications often exhibit a luminance of approximately 100 cd/m²at operating currents of approximately 20-100 mA. Low-powered semiconductor-based LED lighting devices typically operate at current densities at or to the right of the peak efficiency on the efficiency curve characteristic of the LED device. To provide increased light emission, LED die sizes have been increased, with a 1 mm²die becoming a fairly common size. Larger LED die sizes can result in reduced current density, which in turn may allow for use of higher currents from hundreds of mA to more than an ampere, thereby lessening the effect of the efficiency droop associated with the LED die at these higher currents.

Thus, the trend in current state-of-the art semiconductor-based LEDs is to increase both the operating current as well as LED size in order to increase efficiency of LEDs since increasing the LED size results in decreased current density and less efficiency droop. At the moment, commercial semiconductor-based LEDs do not get much smaller than 1 mm².

SUMMARY

LED devices and manners of forming LED devices with a confined current injection area, embedded mirror, and/or passivation layer are disclosed. In an embodiment, an LED device includes a p-n diode layer including a top surface and a bottom surface that includes an interior bottom surface and a surrounding bottom surface. External sidewalls extend between the top surface and the surrounding bottom surface. A quantum well layer is located between an n-doped layer and a p-doped layer of the p-n diode layer. A confinement trench extends from the bottom surface of the p-n diode layer through the quantum well layer and physically isolates an interior portion of the quantum well layer from a surrounding portion of the quantum well layer adjacent the external sidewalls. The confinement trench also physically isolates the interior bottom surface of the p-n diode layer from the surrounding bottom surface of the p-n diode layer adjacent the external sidewalls. A bottom electrically conductive contact is on and in electrical contact with the interior bottom surface of the p-n diode layer, and is not in electrical contact with the surrounding bottom surface of the p-n diode layer. In this manner, the current injection area of the LED device is confined to the interior portion of the p-n diode layer.

A mirror layer may be formed on the LED device spanning along the interior bottom surface and along confinement trench sidewalls within the confinement trench. In an embodiment, the mirror layer does not span along the external sidewalls of the p-n diode layer. A passivation layer may be formed between the mirror layer and the confinement trench sidewalls. In an embodiment, the passivation layer also spans along the external sidewalls of the p-n diode layer. An opening may be formed in the passivation on the interior bottom surface of the p-n diode layer. In an embodiment, the mirror layer is formed within the opening of the passivation layer on the interior bottom surface of the p-n diode layer.

A top surface area of the top surface of the p-n diode layer may be larger than a surface area of the interior bottom surface of the p-n diode layer surrounded by the confinement trench. In an embodiment, the LED device is supported by a post, and a surface area of a top surface of the post is less than a surface area of the interior bottom surface of the p-n diode layer surrounded by the confinement trench. LED devices in accordance with embodiments of the invention may be incorporated into a variety of lighting or display applications, such as a display area of a portable electronic device.

In an embodiment, a method of forming an LED device array includes patterning a p-n diode layer to form an array of mesa structures separated by an array of mesa trenches, and a corresponding array of confinement trenches within the array of mesa structures. The confinement trenches extend through a quantum well layer in each of the mesa structures and physically isolate an interior bottom surface of the p-n diode layer from a surrounding bottom surface of the p-n diode layer in each mesa structure. An array of bottom electrically conductive contact is formed on an in electrical contact with the array of interior bottom surfaces without being in electrical contact with the corresponding surrounding bottom surface of the p-n diode layer for each respective mesa structure. The patterned p-n diode layer is then bonded to a carrier substrate, and a handle substrate is removed from the patterned p-n diode layer. In an embodiment, a conductive contact layer may be deposited on the p-n diode layer prior to patterning the p-n diode layer to form the array of mesa structures and prior to forming an array of bottom electrically conductive contacts.

A patterned mirror layer may be formed on the array of mesa structures and within the array of confinement trenches. For example, a photoresists lift-off technique may be used in an embodiment. A sacrificial release layer may be deposited over the array of mesa structure, and patterned to form an array of openings in the sacrificial release layer over an array of the interior bottom surfaces of the p-n diode layer. After patterning the sacrificial release layer, the handle substrate including the sacrificial release layer is bonded to a carrier substrate with a bonding material such that the bonding material is located within the array of openings in the sacrificial release layer.

In an embodiment, a passivation layer is deposited on the array of bottom electrically conductive contacts and within the array of mesa trenches and within the array of confinement trenches. In an embodiment, the passivation layer is deposited using atomic layer deposition. In an embodiment, annealing may is performed to form ohmic contacts between the array of bottom electrically conductive contacts and the array of mesa structures after patterning the p-n diode layer to form the array of mesa trenches and the corresponding array of confinement trenches. In an embodiment an array of openings are formed in the passivation layer, and a patterned mirror layer is formed on the array of mesa structures, within the array of openings in the passivation layer, and within the array of confinement trenches.

In an embodiment, a method of operating a display, such as a portable electronic device, includes sending a control signal to a driving transistor and driving a current through an LED device including a confined current injection area in response to the control signal. The LED device comprises a confinement trench that extends through a quantum well layer and physically isolates an interior portion of the quantum well layer from a surrounding portion of the quantum well layer adjacent external sidewalls of the LED device. In an embodiment, the current is from 1 nA-400 nA. The current flowing through the device may depend upon resolution of the display and brightness. In an embodiment the current is from 1 nA-30 nA. For example, a corresponding current density may be from 0.001 A/cm²to 3 A/cm². In an embodiment the current is from 200 nA-400 nA. For example, a corresponding current density may be from 0.2 A/cm²to 4 A/cm². In an embodiment the current is from 100 nA-300 nA. For example, a corresponding current density may be from 0.01 A/cm²-30 A/cm².

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional side view illustration of a bulk LED substrate in accordance with an embodiment of the invention.

FIG. 2A is a cross-sectional side view illustration of a conductive contact layer on a bulk LED substrate in accordance with an embodiment of the invention.

FIG. 2B is a cross-sectional side view illustration of a patterned conductive contact layer on a bulk LED substrate in accordance with an embodiment of the invention.

FIG. 3A-3B are cross-sectional side view illustrations of an array of mesa trenches and confinement trenches formed in a p-n diode layer in accordance with embodiments of the invention.

FIGS. 4A-4B are cross-sectional side view illustrations of a passivation layer formed over a an array of mesa structures in accordance with embodiments of the invention.

FIGS. 5A-5B is a cross-sectional side view illustrations of contact openings formed in a passivation layer over an array of mesa structures in accordance with an embodiment of the invention.

FIG. 6 is a cross-sectional side view illustration of a patterned mirror layer formed over an array of mesa structures in accordance with an embodiment of the invention.

FIG. 7 is a cross-sectional side view illustration of a sacrificial release layer formed over an array of mesa structures in accordance with an embodiment of the invention.

FIG. 8 is a cross-sectional side view illustration an array of openings formed in a sacrificial release layer over an array of mesa structures in accordance with an embodiment of the invention.

FIG. 9A-9B are cross-sectional side view illustrations of a patterned bulk LED substrate bonded to a carrier substrate with a stabilization layer in accordance with embodiments of the invention.

FIG. 10 is a cross-sectional side view illustration of an array of mesa structures on a carrier substrate after removal of a handle substrate in accordance with an embodiment of the invention.

FIG. 11 is a cross-sectional side view illustration of a top conductive contact layer formed over an array of mesa structures on a carrier substrate in accordance with an embodiment of the invention.

FIG. 12 is a cross-sectional side view illustration of a patterning layer formed over a top conductive contact layer formed over an array of mesa structures on a carrier substrate in accordance with an embodiment of the invention.

FIG. 13 is a cross-sectional side view illustration of a partially removed conductive contact layer and passivation layer at filled mesa trench locations in accordance with an embodiment of the invention.

FIG. 14 is a cross-sectional side view illustration of an array of LED devices embedded in a sacrificial release layer after removal of a patterning layer in accordance with an embodiment of the invention.

FIGS. 15A-15B are cross-sectional side view illustrations of an array of LED devices supported by an array of stabilization posts after the removal of a sacrificial release layer in accordance with embodiments of the invention.

FIG. 16A is a cross-sectional side view illustrations of an LED device in accordance with an embodiment of then invention.

FIGS. 16B-16E are top-bottom combination schematic view illustrations LED devices in accordance with embodiments of the invention.

FIG. 17A-17E are cross-sectional side view illustrations of an array of electrostatic transfer heads transferring LED devices from carrier substrate to a receiving substrate in accordance with an embodiment of the invention.

FIG. 18A is a top view illustration of a display panel in accordance with an embodiment of the invention.

FIG. 18B is a side-view illustration of the display panel ofFIG. 18A taken along lines X-X and Y-Y in accordance with an embodiment of the invention.

FIG. 19 is a schematic illustration of a display system in accordance with an embodiment of the invention.

FIG. 20 is a schematic illustration of a lighting system in accordance with an embodiment of the invention.

FIG. 21 is a graphical illustration of the relationship of internal quantum efficiency to current density for an LED device in accordance with embodiments of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention describe LED devices and manners of forming LED devices with a confined current injection area, embedded mirror, and/or passivation layer. In particular, some embodiments of the present invention may relate to micro LED devices and manners of forming micro LED devices with a confined current injection area, embedded mirror, and/or passivation layer.

In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions and processes, etc., in order to provide a thorough understanding of the present invention. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the present invention. Reference throughout this specification to “one embodiment” means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase “in one embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.

The terms “spanning”, “over”, “to”, “between” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “spanning,” “over” or “on” another layer or bonded “to” or in “contact” with another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.

In one aspect, embodiments of the invention describe an LED device integration design in which an LED device is transferred from a carrier substrate and bonded to a receiving substrate using an electrostatic transfer head assembly. In accordance with embodiments of the present invention, a pull-in voltage is applied to an electrostatic transfer head in order to generate a grip pressure on an LED device. It has been observed that it can be difficult to impossible to generate sufficient grip pressure to pick up micro devices with vacuum chucking equipment when micro device sizes are reduced below a specific critical dimension of the vacuum chucking equipment, such as approximately 300 μm or less, or more specifically approximately 100 μm or less. Furthermore, electrostatic transfer heads in accordance with embodiments of the invention can be used to create grip pressures much larger than the 1 atm of pressure associated with vacuum chucking equipment. For example, grip pressures of 2 atm or greater, or even 20 atm or greater may be used in accordance with embodiments of the invention. Accordingly, in one aspect, embodiments of the invention provide the ability to transfer and integrate micro LED devices into applications in which integration is not possible with current vacuum chucking equipment. In some embodiments, the term “micro” LED device or structure as used herein may refer to the descriptive size, e.g. length or width, of certain devices or structures. In some embodiments, “micro” LED devices or structures may be on the scale of 1 μm to approximately 300 μm, or 100 μm or less in many applications. However, it is to be appreciated that embodiments of the present invention are not necessarily so limited, and that certain aspects of the embodiments may be applicable to larger micro LED devices or structures, and possibly smaller size scales.

In one aspect, embodiments of the invention describe LED devices that are poised for pick up and supported by one or more stabilization posts. In accordance with embodiments of the present invention, a pull-in voltage is applied to a transfer head in order to generate a grip pressure on an LED an LED device and pick up the LED device. In accordance with embodiments of the invention, the minimum amount pick up pressure required to pick up an LED device from a stabilization post can be determined by the adhesion strength between the adhesive bonding material from which the stabilization posts are formed and the LED device (or any intermediate layer), as well as the contact area between the top surface of the stabilization post and the LED device. For example, adhesion strength which must be overcome to pick up an LED device is related to the minimum pick up pressure generated by a transfer head as provided in equation (1):
P₁A₁=P₂A₂  (1)
where P₁is the minimum grip pressure required to be generated by a transfer head, A₁is the contact area between a transfer head contact surface and LED device contact surface, A₂is the contact area on a top surface of a stabilization post, and P₂is the adhesion strength on the top surface of a stabilization post. In an embodiment, a grip pressure of greater than 1 atmosphere is generated by a transfer head. For example, each transfer head may generate a grip pressure of 2 atmospheres or greater, or even 20 atmospheres or greater without shorting due to dielectric breakdown of the transfer heads. Due to the smaller area, a higher pressure is realized at the top surface of the corresponding stabilization post than the grip pressure generate by a transfer head.

In another aspect, embodiments of the invention describe LED devices, which may be micro LED devices, including a confined current injection area. In an embodiment, an LED device includes a p-n diode layer including a top surface and a bottom surface including an interior bottom surface and a surrounding bottom surface. External sidewalls extend between the top surface and the surrounding bottom surface, and a quantum well layer is between an n-doped layer and a p-doped layer of the p-n diode layer. A confinement trench extends from the bottom surface of the p-n diode layer through the quantum well layer and physically isolates an interior portion of the quantum well layer from a surrounding portion of the quantum well layer adjacent the external sidewalls of the p-n diode layer, as well as physically isolates the interior bottom surface of the p-n diode layer from the surrounding bottom surface of the p-n diode layer adjacent the external sidewalls. A bottom electrically conductive contact located on the interior bottom surface is in electrical contact with the interior bottom surface and is not in electrical contact with the surrounding bottom surface of the p-n diode layer so as to confine the current injection area to the interior portion of the LED device. In this manner, it is possible to design an LED device in which a top surface area of the top surface of the p-n diode layer is larger than a surface area of the interior bottom surface of the p-n diode layer that is surrounded by the confinement trench. This enables larger LED devices to be fabricated, which may be beneficial for transferring the LED devices using an electrostatic transfer head assembly, while also providing a structure in which the confined current injection area results in an increased current density and increased efficiency of the LED device, particularly when operating at injection currents and injection current densities below or near the pre-droop region of the LED device internal quantum efficiency curve, since the current injection area is confined to the interior portion of the quantum well layer defined by the confinement trench location.

The LED devices in accordance with embodiments of the invention are highly efficient at light emission and may consume very little power compared to LCD or OLED display technologies. For example, a conventional display panel may achieve a full white screen luminance of 100-750 cd/m². It is understood that a luminance of greater than 686 cd/m²may be required for sunlight readable screens. In accordance with some embodiments of the invention, an LED device may be transferred and bonded to a display backplane such as a thin film substrate backplane used for OLED display panels, where the semiconductor-based LED device replaces the organic LED film of the OLED display. In this manner, a highly efficient semiconductor-based LED device replaces a less efficient organic LED film. Furthermore, the width/length of the semiconductor-based LED device may be much less than the allocated subpixel area of the display panel, which is typically filled with the organic LED film.

For illustrative purposes, in accordance with embodiments of the invention it is contemplated that the LED devices may be driven using a similar driving circuitry as a conventional OLED display panel, for example a thin film transistor (TFT) backplane. However, embodiments are not so limited. For example, in another embodiment the LED devices are driven by micro controller chips that are also electrostatically transferred to a receiving substrate. Assuming subpixel operating characteristics of 25 nA injection current, an exemplary LED device having a 1 μm²confined current injection area roughly corresponds to a current density of 2.5 A/cm², an exemplary LED device having a 25 μm²confined current injection area roughly corresponds to a current density of 0.1 A/cm², and an exemplary LED device having a 100 μm²confined current injection area roughly corresponds to a current density of 0.025 A/cm². Referring toFIG. 21, in accordance with embodiments of the invention these low injection currents and current densities may correspond to a pre-droop region of a characteristic efficiency curve or a region of the efficiency curve at or just past the maximum IQE for the LED devices. This is well below the normal or designed operating conditions for standard LEDs. Furthermore, in some embodiments, the low injection currents and current densities may correspond to a portion on the pre-droop region of the characteristic efficiency curve for the LED device in which the slope of the curve is greater than 1:1 such that a small increase in current density results in a greater increase in IQE, and hence EQE, of the LED device. Accordingly, in accordance with embodiments of the invention, significant efficiency increases may be obtained by confining the current injection area of the LED device, resulting in increased luminous efficacy and luminance of the LED device. In some embodiments, LED devices with confined current injection areas are implemented into display panel applications designed for target luminance values of approximately 300 Nit for indoor display applications and greater than 686 cd/m²for outdoor display applications. In some embodiments, the embedded mirrors may additionally change the emission profile of the LED devices, further increasing the luminance of an LED device. It is to be appreciated that the above examples, including injection currents and display applications are exemplary in nature in order to provide a context for implementing embodiments of the invention, and that embodiments are not so limited and may be used with other operating conditions, and that embodiments are not limited to display applications or TFT backplanes.

In another aspect, embodiments of the invention describe LED devices including an embedded mirror. In an embodiment, an LED device, which may be a micro LED device, includes a mirror layer spanning along an interior bottom surface of the p-n diode layer surrounded by the confinement trench and along sidewalls within the confinement trench. A passivation layer may be formed between the mirror layer and the confinement trench sidewalls to prevent shorting between the p-doped layer and the n-doped layer of the p-n diode layer. Embedding the mirror layer within the p-n diode layer of the LED device may increase light extraction from the LED device since the mirror layer is directly adjacent the quantum well layer. By moving the mirror closer to the quantum well layer, where a majority of the light emission may occur, this reduces light absorbance from intermediate materials used for passivation or packaging around the LED device, for example when an external mirror is used outside of an LED device. In an embodiment, the embedded mirror is directly adjacent an interior portion of the quantum well layer corresponding to a confined current injection area. In this manner the mirror layer is able to reflect light emitted from the interior portion of the LED device so that it is not required for the light to pass through the surrounding portion of the LED device which may be absorbing. The embedded mirror may also improve contrast of the lighting or display application since the embedded mirror may reflect less ambient light than a configuration including an external mirror.

In one aspect, embodiments of the invention describe an LED device integration scheme in which LED devices including an embedded mirror are integrated into a display panel in which external mirror layers not provided on the display substrate to reflect light from the LED devices. It has been observed that display substrate mirrors used for reflecting light from LED devices may also reflect ambient light. For example, circular polarizers may be used in emissive displays to enhance readability and suppress ambient light reflection. It has been observed that while circular polarizers may suppress ambient light reflection, they may also absorb light emitted from an emissive display. In accordance with some embodiments of the invention, a circular polarizer may not be required to suppress ambient light reflection. As a result, display panels in accordance with embodiments of the invention may be packaged without a circular polarizer, resulting in increased luminance of the display panel.

In yet another aspect, embodiments of the invention describe LED devices, which may be micro LED devices, including a sidewall passivation layer. The sidewall passivation layer may span sidewalls of the p-n diode layer, including the confinement trench sidewalls and external sidewalls of the p-n diode layer. The sidewall passivation layer may protect the quantum well from other materials that could degrade or short the LED device as well as terminate dangling bonds on the exposed surface. In an embodiment, the sidewall passivation layer may also be used to passivate surface states on the sidewalls of the LED device (e.g. along confinement trench sidewalls) to improve the IQE of the LED device, and reduce non-radiative recombination along those sidewalls. In an embodiment, the sidewall passivation layer may protect the LED device from a conductive material used as an electrical contact (e.g. anode or cathode) to the top surface of the p-n diode layer. The sidewall passivation layer can also provide passivation between the LED devices while retained on the carrier substrate and protect against potential arcing between LED devices during electrostatic transfer. In some embodiments the sidewall passivation layer is formed within the confinement trench to electrically insulate the p-n diode layer from the mirror layer within the confinement trench. In this manner, the sidewall passivation layer can be patterned to assist with confining the current injection area through the interior portion of the quantum well layer.

In the following description exemplary processing sequences are described for forming an array of LED devices, which may be micro LED devices. Specifically, exemplary primary processing sequences are described for forming an array of red emitting LED devices, while supplementary descriptions and figures are provided for blue or green emitting LED devices. It is to be appreciated that the exemplary processing sequences for red, blue, and green emitting LED device may share similar features and methods. Where possible, similar features are illustrated with similar annotations in the figures and following description. While the primary processing sequences are described for red emitting LED devices, it is to be understood that the exemplary processing sequences can be used for LED devices with different emission spectra, and that certain modifications are contemplated, particularly when processing different materials. Accordingly, it is to be understood that embodiments of the invention describing the formation and transfer of LED devices including a confined current injection area, an embedded mirror layer, and/or a sidewall passivation layer are not limited to red, blue, or green emitting LED devices.

Referring now toFIG. 1, a cross-sectional side view illustration is provided of abulk LED substrate100 in accordance with an embodiment of the invention. For example, the bulk LED substrate illustrated inFIG. 1 may be designed for emission of red light (e.g. 620-750 nm wavelength), green light (e.g. 495-570 nm wavelength), or blue light (e.g. 450-495 nm wavelength), though embodiments of the invention are not limited to these exemplary emission spectra.

In an embodiment, abulk LED substrate100 includes ap-n diode layer105 formed on agrowth substrate102. An optionaletch stop layer104 orbuffer layer107 may be formed between thep-n diode layer105 depending upon the materials selection and color emission spectra of thep-n diode layer105. Thep-n diode layer105 may include a doped semiconductor layer106 (e.g. n-doped), one or more quantum well layers108, and a doped semiconductor layer110 (e.g. p-doped). Thep-n diode layer105 may optionally include an ohmic layer between thedoped semiconductor layer106 and thegrowth substrate102 to aid in the subsequent formation of an ohmic contact with the p-n diode layer. Theetch stop layer104 orbuffer layer107 andp-n diode layer105 may be formed on thegrowth substrate102 by a variety of techniques. In an embodiment, theetch stop layer104 orbuffer layer107 andp-n diode layer105 are formed by one or more heterogeneous epitaxial growth techniques.

Thep-n diode layer105 may be formed of a variety of compound semiconductors having a bandgap corresponding to a specific region in the spectrum. For example, thep-n diode layer105 can include one or more layers based on II-VI materials (e.g. ZnSe) or III-V materials including III-V nitride materials (e.g. GaN, AlN, InN, InGaN, and their alloys) and III-V phosphide materials (e.g. GaP, AlGaInP, and their alloys). Thegrowth substrate102 may include any suitable substrate such as, but not limited to, silicon, SiC, GaAs, GaN, and sapphire.

Referring toFIG. 1, in one embodiment, thebulk LED substrate100 is designed for emission of red light. In such an embodiment thehandle substrate102 is a growth substrate formed of GaAs, and may be approximately 500 μm thick. Theetch stop layer104 may be formed of InGaP and approximately 2,000 angstroms thick. The ohmic layer may be formed of GaAs and approximately 500 angstroms thick. In an embodiment, n-dopedlayer106 is formed of AlGaInP, and is approximately 1 μm to 3 μm thick. The one or more quantum well layers108 may have a thickness of approximately 0.5 μm. In an embodiment, p-dopedlayer110 is formed of GaP, and is approximately 1 μm to 2 μm thick.

The following embodiments are not limited to the formation of red emitting LED devices and may also be applicable to the formation of other LED devices such as green emitting LED devices formed of materials such as indium gallium nitride (InGaN), gallium nitride (GaN), gallium phosphide (GaP), aluminum gallium indium phosphide (AlGaInP), and aluminum gallium phosphide (AlGaP), or blue emitting LED devices formed of materials such as gallium nitride (GaN), indium gallium nitride (InGaN), and zinc selenide (ZnSe).

Still referring toFIG. 1, in an embodiment, thebulk LED substrate100 is designed for emission of blue or green light, thehandle substrate102 is a growth substrate formed of sapphire, and may be approximately 200 μm thick. Thebuffer layer107 is formed of GaN and has a thickness of approximately 0.5 μm to 5 μm. In an embodiment, n-dopedlayer106 is formed of GaN, and is approximately 0.1 μm to 3 μm thick. The one or more quantum well layers108 may have a thickness of approximately 0.3 μm. In an embodiment, p-dopedlayer110 is formed of GaN, and is approximately 0.1 μm to 1 μm thick.

Referring now toFIG. 2A, aconductive contact layer111 may then be formed over thep-n diode layer105 of thebulk LED substrate100. In an embodiment, thebulk LED substrate100 illustrated inFIG. 2A is an aluminum gallium indium phosphide (AlGaInP) system on gallium arsenide (GaAs) substrate designed for red, yellow, orange or infra-red emission.Conductive contact layer111 may be formed of a variety of conductive materials including metals, conductive oxides, and conductive polymers. In an embodiment,conductive contact layer111 is formed using a suitable technique such as evaporation or sputtering. In an embodiment,conductive contact layer111 is formed of a transparent electrode material.Conductive contact layer111 may include BeAu metal alloy, or a metal stack of Au/GeAu/Ni/Au layers.Conductive contact layer111 may also be a transparent conductive oxide (TCO) such as indium-tin-oxide (ITO). Conductive contact layer can also be a combination of one or more metal layers and a conductive oxide. In an embodiment,conductive contact layer111 is approximately 600 angstroms thick ITO.

FIG. 2B is a cross-sectional side view illustration of a conductive contact layer that has been patterned to form an array of electricallyconductive contacts112 on a bulk LED substrate in accordance with an embodiment of the invention. In an embodiment, thebulk LED substrate100 illustrated inFIG. 2B is designed for blue or green emission. The electrically conductive contacts ofFIG. 2B may be formed of the same materials as theconductive contact layer112 ofFIG. 2A. In an embodiment, the electricallyconductive contacts112 ofFIG. 2B include a BeAu metal alloy, or a metal stack of Au/GeAu/Ni/Au layers.

Referring now toFIGS. 3A-3B, thep-n diode layer105 is patterned to form an array ofLED mesa structures120 separated by an array ofmesa trenches116 over thehandle substrate102. Thep-n diode layer105 is also patterned to include a corresponding array ofconfinement trenches118 within the array ofLED mesa structures120. As illustrated, theconfinement trenches118 extend through the quantum well layer(s)108 in each of theLED mesa structures120. In an embodiment,confinement trenches118 extend partially into dopedlayer106, but not completely through the p-n diode layer105 (e.g. not completely through dopedlayer106 or an ohmic contact layer, if present). In an embodiment,mesa trenches116 extend completely through the dopedlayer106. In an embodiment illustrated inFIG. 3A,mesa trenches116 extend throughetch stop layer104. In such an embodiment,mesa trenches116 may stop on thehandle substrate102 or extend partially intohandle substrate102. In an embodiment illustrated inFIG. 3B,mesa trenches116 do not extend completely through dopedlayer106. In another embodiment,mesa trenches116 extend partially or completely throughbuffer layer107.

As illustrated, eachmesa structure120 includes aninterior bottom surface166 defined by theconfinement trench118, and a surroundingbottom surface164 between theconfinement trench118 andmesa trench116. Themesa trenches116 andconfinement trenches118 illustrated inFIGS. 3A-3B may be formed sequentially, in either order, or simultaneously. In an embodiment,trenches116,118 are simultaneously etched with relative depths being controlled by opening size in a mask layer used for etching. Etching may be wet or dry depending upon the desired angles for sidewalls oftrenches116,118.Conductive contact layer112 ofFIG. 3A may be patterned to form an array of electricallyconductive contacts112 over the array interior bottom surfaces166 of the p-n diode layer, and an array of electricallyconductive traces113 over the surroundingbottom surfaces164 of the p-n diode layer. As illustrated the array of electricallyconductive contacts112 are physically and electrically separated from the electrically conductive traces113.Conductive contact layer112 ofFIG. 3A may be etched with the same or different etching chemistry used to etch thep-n diode layer105 andetch stop layer104. In an embodiment, dry etching techniques such as reactive ion etching (RIE), electro-cyclotron resonance (ECR), inductively coupled plasma reactive ion etching (ICP-RIE), and chemically assisted ion-beam etching (CAIBE) may be used. The etching chemistries forFIGS. 3A-3B may be halogen based, containing species such as Cl₂, BCl₃, or SiCl₄. The etching chemistries forFIG. 3A may also be wet chemistries containing species such as Br₂or HIO₄. In such an embodiment, a separate wet etching chemistry can be used for etching theconductive contact layer112. In an embodiment illustrated inFIG. 3Aconductive contact layer112 is dry etched with themesa structures120 using a suitable dry etching chemistry such as Cl₂, BCl₃, or SiCl₄.

Referring toFIG. 3A, in an embodiment whereetch stop layer104 is formed of InGaP, theetch stop layer104 may be removed by wet etching in a solution of HCl+H₃PO₄. As illustrated inFIG. 3A, etching ofmesa trenches116 may be continued into thegrowth substrate102. For example, aGaAs growth substrate102 can be etched with a H₂SO₄+H₂O₂solution, NH₄OH+H₂O₂solution, or CH₃OH+Br₂chemistry.

Referring toFIG. 3B, in an embodiment, etching ofmesa trenches116 stops inside the dopedlayer106. In an embodiment, where dopedlayer106 andbuffer layer107 are formed of the same material, such as GaN, the only difference between the layers may be doping profile. In such an instance, a physical layer boundary is not present.

Following the formation ofmesa trenches116 and confinement trenches118 apassivation layer122 may be formed over the topography of the resulting structure as illustrated inFIGS. 4A-4B. In the particular embodiments illustrated thepassivation layer122 is conformal to and forms an outline of the topography of the underlying structure.Passivation layer122 may be formed of any suitable electrical insulator material such an oxide or nitride. In an embodiment, passivation layer is approximately 50 angstroms to 3,000 angstroms thick Al₂O₃. In an embodiment,passivation layer122 is formed using a high quality thin film deposition procedure, such as atomic layer deposition (ALD). As will become more apparent in the following description, a high quality thin film deposition procedure may protect the integrity of thepassivation layer122 during the sacrificial release layer etch operation. Following deposition of thepassivation layer122, in an embodiment, the substrate assembly is annealed in order to make ohmic contact with the array of electricallyconductive contacts112 and the array ofmesa structures120. In an embodiment, annealing after formation of thetrenches116,118 aids in healing damage on thesidewalls168,119 of thep-n diode layer105 that resulted from the formation oftrenches116,118. It is anticipated that performing the anneal operation after formation oftrenches116,118 may increase efficiency of the resultant LED device.

Still referring toFIGS. 4A-4B, the electricallyconductive contacts112 on the interior bottom surfaces166 of the p-n diode layer are in electrical contact with the interior bottom surfaces166 and are not in electrical contact with the surroundingbottom surfaces164 of the p-n diode layer.

Referring now toFIGS. 5A-5B,contact openings124 may be formed in thepassivation layer122 over the interior bottom surfaces166 of themesa structures120 defined by theconfinement trenches118. In an embodiment, an area ofcontact openings124 is less than an area of the electricallyconductive contact112 on the interior bottom surfaces166 of themesa structures120 defined by theconfinement trenches118. In this manner, thepassivation layer122 andcontact openings124 can be used to at least partly define the current injection area within the LED device. In an embodiment,openings124 are formed using photolithography and a buffered oxide etch (BOE) chemistry such as a dilute hydrofluoric acid (HF).

In interests of clarity and conciseness, the following description with regard toFIGS. 6-14 is made with regard to the structure ofFIG. 5A. Separate description and illustration is not provided with regard to the structure ofFIG. 5B, though it is to be appreciated that similar processing sequences are contemplated.

Referring now toFIG. 6, in an embodiment a patternedmirror layer126 is then formed on the array ofmesa structures120. In the particular embodiment illustrated, a patternedmirror layer126 spans along the bottom surface of the p-n diode layer and along the confinement trench sidewalls119 within theconfinement trench118. For example, the patternedmirror layer126 may be formed within thecontact openings124 in thepassivation layer122 in order to make electrical contact with the electricallyconductive contacts112 on the interior bottom surfaces166 of themesa structures120 defined by theconfinement trenches118. Thepassivation layer122 may prevent the patternedmirror layer126 from making electrical contact with the surroundingbottom surfaces164 of themesa structures120. In the particular embodiment illustrated, the patternedmirror layer126 does not span along theexternal sidewalls168 of the p-n diode layer defined by themesa trenches116. This may aid in forming laterally separate LED devices in the following processing sequence. This may also be beneficial for an electrostatic transfer operation, where a conductor located along external sidewalls of the LED devices could potentially short an electrostatic transfer head, resulting in the LED device not being picked up.

The patternedmirror layer126 may be formed from a variety of different materials based upon the emission spectra characteristics of thep-n diode layer105, and formed using different methods. For example, the patternedmirror layer126 may be formed by blanket deposition followed by lithography and etching, or the patternedmirror layer126 may be formed using a photoresist lift-off technique. In an embodiment, where thep-n diode layer105 is designed for red color emission, the patternedmirror layer126 may be formed of gold, for example with a thickness of 500 angstroms to 0.5 μm. Gold may reflect greater than 90% of the red wavelength spectrum. Furthermore, gold may be a suitable bonding material for thestabilization layer132 that is yet to be formed. In applications where thep-n diode layer105 is designed for green or blue emission, then the patternedmirror layer126 may include one or more layers. In an embodiment, aluminum or silver is used to reflect the green or blue emission spectra. In an embodiment, the patternedmirror layer126 additionally includes a bonding layer such as gold to control the bonding strength with thestabilization layer132 that is yet to be formed. For example, a patternedmirror layer126 may include a first reflective layer such as aluminum or silver for blue or green wavelength reflection, for example with a thickness of 500 angstroms to 0.5 μm, followed by a barrier layer such as Ti, Pt, TiW with a thickness of 50 angstroms to 200 angstroms, and a 500 angstroms to 0.5 μm thick bonding layer such as gold deposited on the barrier layer to control adhesion strength with thestabilization layer132.

Asacrificial release layer128 may then be formed over the array ofmesa structures120 as illustrated inFIG. 7. In the particular embodiment illustrated, thesacrificial release layer128 is formed within both themesa trenches116 andconfinement trenches118. As will become more apparent in the following description, the thickness of thepassivation layer122,mirror layer126, andsacrificial release layer128 may all contribute to the dimensions of theopenings129, which will become thestaging cavity sidewalls136 following the formation of the stabilization layer. In an embodiment, thesacrificial release layer128 is not used to make electrical contact with the array of LED devices and is formed of an electrically insulating material. In an embodiment, thesacrificial release layer128 is formed of a material which can be readily and selectively removed with vapor (e.g. vapor HF) or plasma etching. In an embodiment, the sacrificial release layer is formed of an oxide (e.g. SiO₂) or nitride (e.g. SiN_x), with a thickness of 0.2 μm to 2 μm. In an embodiment, the sacrificial release layer is formed using a comparatively low quality film formation technique compared to thepassivation layer122. In an embodiment, thesacrificial release layer128 formed by sputtering, low temperature plasma enhanced chemical deposition (PECVD), or electron beam evaporation.

Referring now toFIG. 8, thesacrificial release layer128 is patterned to from an array ofopenings130 over the array ofmesa structures120. In the particular embodiment illustrated, the array ofopenings130 are formed over the interior bottom surfaces166 of themesa structures120 defined by theconfinement trenches118. In an embodiment, eachopening130 exposes anunderlying mirror layer126. As will become more apparent in the following description, the dimensions of theopenings130 in thesacrificial release layer128 correspond to the dimensions and contact area of the stabilization posts to be formed, and resultantly to the adhesion strength that must be overcome to pick up the array of LED devices that is supported by and poised for pick from the array of stabilization posts. In an embodiment,openings130 are formed using lithographic techniques and have a length and width of approximately 1 μm by 1 μm, though the openings may be larger or smaller. In an embodiment,openings130 have a width (or area) that is less than the width (or area) of the interior bottom surfaces166 of themesa structures120 defined by theconfinement trenches118. In an embodiment, one ormore openings130 are formed within theconfinement trenches118. In this manner, the stabilization posts to be formed will be embedded within the LED devices, further stabilizing the LED devices on the carrier substrate.

Referring now toFIGS. 9A-9B, in an embodiment astabilization layer132 is formed over the patternedsacrificial release layer128 and bonded to acarrier substrate140. In accordance with embodiments of the invention,stabilization layer132 may be formed of an adhesive bonding material. In an embodiment the adhesive bonding material is a thermosetting material such as benzocyclobutene (BCB) or epoxy. For example, the thermosetting material may be associated with 10% or less volume shrinkage during curing, or more particularly about 6% or less volume shrinkage during curing so as to not delaminate from themirror layer126 on the LED devices to be formed. In order to increase adhesion the underlying structure can be treated with an adhesion promoter such as AP3000, available from The Dow Chemical Company, in the case of a BCB stabilization layer in order to condition the underlying structure. AP3000, for example, can be spin coated onto the underlying structure, and soft-baked (e.g. 100° C.) or spun dry to remove the solvents prior to applying thestabilization layer132 over the patternedsacrificial release layer128.

In an embodiment,stabilization layer132 is spin coated or spray coated over the patternedsacrificial release layer128, though other application techniques may be used. Following application of thestabilization layer132, the stabilization layer may be pre-baked to remove the solvents. After pre-baking thestabilization layer132 the patternedbulk substrate100 is bonded to thecarrier substrate140 with thestabilization layer132. In an embodiment, bonding includes curing thestabilization layer132. Where thestabilization layer132 is formed of BCB, curing temperatures should not exceed approximately 350° C., which represents the temperature at which BCB begins to degrade. Achieving a 100% full cure of the stabilization layer may not be required in accordance with embodiments of the invention. In an embodiment,stabilization layer132 is cured to a sufficient curing percentage (e.g. 70% or greater for BCB) at which point thestabilization layer132 will no longer reflow. Moreover, it has been observed that partially cured BCB may possess sufficient adhesion strengths withcarrier substrate140 and the patternedsacrificial release layer128. In an embodiment, stabilization layer may be sufficiently cured to sufficiently resist the sacrificial release layer release operation.

In an embodiment, thestabilization layer132 is thicker than the height ofopenings130 in the patternedsacrificial release layer128. In this manner, the thickness of the stabilizationlayer filling openings130 will become stabilization posts134, and the remainder of the thickness of thestabilization layer132 over the filledopenings130 can function to adhesively bond the patterned bulk LED substrate100 acarrier substrate140. In an embodiment, a portion of thestabilization layer132 flows into theopenings129 to form stagingcavity sidewalls136. In an embodiment illustrated inFIG. 9A, after bonding to thecarrier substrate140, the stabilization layer is thicker than the stabilization posts134. For example, a continuous portion ofstabilization layer132 remains over thecarrier substrate140. In an embodiment illustrated inFIG. 9B, the sacrificial release layer128 (or another intermediate layer) is pressed against thecarrier substrate140 during bonding such that there is not a thickness of thestabilization layer132 below the stabilization posts134. In such an embodiment, theopenings129 can function as overflow cavities for the stabilization layer during bonding. In an embodiment, theopenings129 are not completely filled with stabilization layer, which becomes thestaging cavity sidewalls136.

Following bonding of the patternedbulk LED substrate100 to thecarrier substrate140, thehandle102 substrate and optionaletch stop layer104 orbuffer layer107 are removed as illustrated inFIG. 10. Removal ofhandle substrate102 may be accomplished by a variety of methods including laser lift off (LLO), grinding, and etching depending upon the material selection of thegrowth substrate102. Upon removal of thehandle substrate102 andlayers104 or107 portions of thepassivation layer122 orsacrificial release layer128 may protrude above an exposed top surface of thep-n diode layer105 of themesa structures120.

In the particular embodiment illustrated wherehandle substrate102 is a growth substrate formed of GaAs, removal may be accomplished by etching, or a combination of grinding and selective etching, with the selective etching stopping on anetch stop layer104. For example, theGaAs growth substrate102 can be removed with a H₂SO₄+H₂O₂solution, NH₄OH+H₂O₂solution, or CH₃OH+Br₂chemistry, stopping onetch stop layer104 formed of InGaP, for example. Theetch stop layer104 may then be removed to expose thep-n diode layer105. In an embodiment where etch stop layer is formed of InGaP, the etch stop layer may be removed by wet etching in a solution of HCl+H₃PO₄.

In an embodiment where thehandle substrate102 is a growth substrate formed of sapphire, removal may be accomplished using LLO in which a102/107 interface is irradiated with an ultraviolet laser such as a Nd-YAG laser or KrF excimer laser. Absorption in theGaN buffer layer107 at the interface with thetransparent growth substrate102 results in localized heating of the interface resulting in decomposition at the interfacial GaN to liquid Ga metal and nitrogen gas. Once the desired area has been irradiated, the transparentsapphire growth substrate102 can be removed by remelting the Ga on a hotplate. Following removal of the growth substrate, theGaN buffer layer107 can be removed resulting a desired thickness for dopedlayer106. Removal ofbuffer layer107 can be performed using any of the suitable dry etching techniques described above with regard to formingtrenches116,118, as well as with CMP or a combination of both.

Referring now toFIG. 11, following the removal of the growth substrate102 a topconductive contact layer141 may be formed. Topconductive contact layer141 may be formed of a variety of electrically conductive materials including metals, conductive oxides, and conductive polymers. In an embodiment,conductive contact layer141 is formed using a suitable technique such as evaporation or sputtering. In an embodiment,conductive contact layer141 is formed of a transparent electrode material.Conductive contact layer141 may include BeAu metal alloy, or a metal stack of Au/GeAu/Ni/Au layers.Conductive contact layer141 may also be a transparent conductive oxide (TCO) such as indium-tin-oxide (ITO).Conductive contact layer141 can also be a combination of one or more metal layers and a conductive oxide. In an embodiment,conductive contact layer141 is approximately 600 angstroms thick ITO. In an embodiment, after forming theconductive contact layer141, the substrate stack is annealed to generate an ohmic contact between the conductive contact layer and the array ofmesa structures120. Where thestabilization layer132 is formed of BCB, the annealing temperature may be below approximately 350° C., at which point BCB degrades. In an embodiment, annealing is performed between 200° C. and 350° C., or more particularly at approximately 320° C. for approximately 10 minutes.

In an embodiment, prior to forming the topconductive contact layer141 anohmic contact layer143 can optionally be formed to make ohmic contact with theLED mesa structures120. In an embodiment,ohmic contact layer143 may be a metallic layer. In an embodiment,ohmic contact layer143 is a thin GeAu layer for a GaAs or AlGaInP system. In an embodiment,ohmic contact layer143 is a thin NiAu or NiAl layer for a GaN system. For example, theohmic contact layer143 may be 50 angstroms thick. In the particular embodiment illustrated, theohmic contact layer143 is not formed over the interior portion152 (seeFIGS. 16A-16B) of thequantum well layer108 so as to not reflect light back into the LED device and potentially reduce light emission. In some embodiments,ohmic contact layer143 forms a ring around theinterior portion152 of thequantum well layer108. For example,ohmic contact layer143 may be formed over theconfinement trench118 and surroundingportion154 of thequantum well layer108.

Referring now toFIG. 12, in an embodiment a patterning layer such as a photoresist is applied over the topconductive contact layer141. In an embodiment, aphotoresist layer144 is spun on such that it a top surface of thephotoresist layer144 fully covers raised portions ofconductive contact layer141 andpassivation layer122 at the filled mesa trench116 locations. Referring now toFIG. 13, in an embodiment, thephotoresist layer144 is stripped using a suitable wet solvent or plasma ashing technique until theconductive contact layer141 andpassivation layer122 are removed over the filled mesa trench116 locations, exposing thesacrificial release layer128 between the mesa structures12, resulting in the formation of an array of topconductive contacts142. The remainingphotoresist layer144 may then be fully stripped as illustrated inFIG. 14, resulting in an array of laterallyseparate LED devices150 supported by an array ofstabilization posts134 and embedded in asacrificial release layer128. At this point, the resultant structure still robust for handling and cleaning operations to prepare the substrate for subsequent sacrificial release layer removal and electrostatic pick up.

Still referring toFIG. 14, the topconductive contacts142 on eachLED device150 are substantially planar and cover substantially the entiretop surface162 of eachLED device150. In such a configuration, the topconductive contacts142 cover substantially the maximum available surface area to provide a large, planar surface for contact with the electrostatic transfer head, as described in more detail inFIGS. 17A-17E. This may allow for some alignment tolerance of the electrostatic transfer head assembly.

Following the formation of discrete and laterallyseparate LED devices150, thesacrificial release layer128 may be removed.FIGS. 15A-15B are cross-sectional side view illustrations of an array ofLED devices150 supported by an array ofstabilization posts134 after removal of the sacrificial release layer in accordance with embodiments of the invention. In the embodiments illustrated,sacrificial release layer128 is completely removed resulting in an open space below eachLED device150. A suitable etching chemistry such as HF vapor, or CF₄or SF₆plasma may used to etch the SiO₂or SiN_xsacrificial release layer128. In an embodiment, the array ofLED devices150 is on the array ofstabilization posts134, and supported only by the array of stabilization posts134. In an embodiment, stagingcavity sidewalls136 may further aid in keeping the array ofLED devices150 in place should an adhesive bond be broken between any of theLED devices150 and stabilization posts134.

In the embodiments illustrated inFIGS. 15A-15B,passivation layer122 is not removed during removal of thesacrificial release layer128. In an embodiment,passivation layer122 is formed of Al₂O₃, and a SiO₂or SiN_xsacrificial release layer128 is selectively removed with vapor HF.

FIG. 16A is a cross-sectional side-view illustration of anexemplary LED device150 in accordance with an embodiment of the invention. As illustrated, theLED device150 includes ap-n diode layer105 including atop surface162, abottom surface164,166,external sidewalls168 extending between thetop surface162 and the surroundingbottom surface164, and aquantum well layer108 between an n-dopedlayer106 or108 and a p-dopedlayer106 or108. Aconfinement trench118 extends from thebottom surface164,166 of the p-n diode layer through thequantum well layer108 and physically isolates aninterior portion152 of thequantum well layer108 from a surroundingportion154 of the quantum well layer adjacent theexternal sidewalls168. In an embodiment, theinner portion152 of thequantum well layer108 corresponds to the confined current injection area of theLED device150. A bottom electricallyconductive contact112 is on an in electrical contact with theinterior bottom surface166 of the p-n diode layer, and is not in electrical contact with the surroundingbottom surface164 of the p-n diode layer.

FIG. 16B is a top-bottom combination schematic view illustration of anexemplary LED device150 in accordance with an embodiment of the invention. As illustrated,FIG. 16B combines certain features from both top and bottom views. Referring toFIG. 16B, in an embodiment, theconfinement trench118 surrounds theinterior portion152 of thequantum well layer108. As shown, theinterior portion152 of thequantum well layer108 is laterally separated from the surroundingportion154 of the quantum well layer byconfinement trench118 so that theinner portion152 of thequantum well layer108 corresponds to the confined current injection area of theLED device150. In an embodiment,top surface162 of the p-n diode layer has asurface area156 that is larger than asurface area158 of theinterior bottom surface166 of the p-n diode layer surrounded by theconfinement trench118. As shown inFIGS. 15A-15B, in an embodiment, theLED device150 is supported by apost134 including a post surface area at a top surface of the post that is less than thesurface area158 of theinterior bottom surface166 of the p-n diode layer surrounded by theconfinement trench158.

Referring again toFIG. 16A, in an embodiment themirror layer126 spans along theinterior bottom surface166 of the p-n diode layer and along confinement trench sidewalls119 within theconfinement trench118. In an embodiment themirror layer126 does not span along theexternal sidewalls168 of the p-n diode layer. Apassivation layer122 may be located between themirror layer126 and theconfinement trench sidewalls119. In an embodiment, thepassivation layer122 spans along theexternal sidewalls168 of the p-n diode layer. An opening may be formed in the passivation layer on theinterior bottom surface166 of the p-n diode layer. This may allow electrical connection to the bottom electricallyconductive contact112 and theinterior bottom surface166 of the p-n diode layer without allowing electrical connection to the surroundingbottom surface164 of the p-n diode layer. Themirror layer126, which may also be conductive, may be formed within the opening in thepassivation layer122 on theinterior bottom surface166 of the p-n diode layer.

In accordance with embodiments of the invention theLED devices150 may be micro LED devices. In an embodiment, anLED device150 has a maximum width or length at thetop surface162 of 300 μm or less, or more specifically approximately 100 μm or less. The active area within theLED device150 may be smaller than thetop surface162 due to location of theconfinement trenches118. In an embodiment, thetop surface162 has a maximum dimension of 1 to 100 μm, or more specifically 3 to 20 μm. In an embodiment, a pitch of the array ofLED devices150 on the carrier substrate may be (1 to 300 μm) by (1 to 300 μm), or more specifically (1 to 100 μm) by (1 to 100 μm), for example, 20 μm by 20 μm, 10 μm by 10 μm, or 5 μm by 5 μm. In an exemplary embodiment, a pitch of the array ofLED devices150 on the carrier substrate is 11 μm by 11 μm. In such an exemplary embodiment, the width/length of thetop surface162 is approximately 9-10 μm, and spacing betweenadjacent LED devices150 is approximately 1-2 μm. Theinterior bottom surface166 may be approximately 3-4 μm, theconfinement trench118 surrounding theinterior bottom surface166 is approximately 1 μm, and each surroundingbottom surface164 is approximately 2 μm. In such an embodiment thepost134 width/length is approximately 1-2 μm. It is to be appreciated that these dimensions are exemplary, and embodiments of the invention may be used to form LED devices of a variety of size scales.

FIGS. 16C-16E are top-bottom combination schematic view illustrations ofexemplary LED devices150 in accordance with an embodiment of the invention.FIG. 16C is similar toFIG. 16B, with theconfinement trenches118 rotated 45 degrees with respect to theexternal sidewalls168 of the p-n diode layer, though any rotational angle could be used.FIG. 16D illustrates an embodiment where unlike the square orrectangular confinement trench118 pattern ofFIGS. 16B-16C acircular confinement trench118 pattern is used. It is believed a circular confinement trench pattern may result in less stress in theLED device150. A circular confinement trench may additionally provide a higher current density due to smaller interior confinement area inside the confinement trench.FIG. 16E illustrates an embodiment with atriangular confinement trench118 pattern. It is believed a triangular confinement trench pattern may provide a geometry for increased light extraction from side emission where the angles of the triangle may result in less internal reflection of light prior to exiting theLED device150. In each of the embodiments illustrated inFIGS. 16B-16E a square or rectangulartop surface162 is maintained to match a square or rectangular electrostatic transfer head, however other geometries are possible.

In interests of clarity and conciseness, the above description ofFIGS. 16A-16E was made with regard to the structure ofFIG. 15A. Separate description and illustration is not provided with regard to the structure ofFIG. 15B, though it is to be appreciated that similar processing sequences and structures are contemplated.

FIGS. 17A-17E are cross-sectional side view illustrations of an array of electrostatic transfer heads204 transferringLED devices150, which may be micro LED devices, fromcarrier substrate140 to a receivingsubstrate300 in accordance with an embodiment of the invention.FIG. 17A is a cross-sectional side view illustration of an array of micro device transfer heads204 supported bysubstrate200 and positioned over an array ofLED devices150 stabilized onstabilization posts134 ofstabilization layer132 oncarrier substrate140. The array ofLED devices150 is then contacted with the array of transfer heads204 as illustrated inFIG. 17B. As illustrated, the pitch of the array of transfer heads204 is an integer multiple of the pitch of the array ofLED devices150. A voltage is applied to the array of transfer heads204. The voltage may be applied from the working circuitry within atransfer head assembly206 in electrical connection with the array of transfer heads throughvias207. The array ofLED devices150 is then picked up with the array of transfer heads204 as illustrated inFIG. 17C. The array ofLED devices150 is then placed in contact with contact pads302 (e.g. gold, indium, tin, etc.) on a receivingsubstrate300, as illustrated inFIG. 17D. The array ofLED devices150 is then released ontocontact pads302 on receivingsubstrate300 as illustrated inFIG. 17E. For example, the receiving substrate may be, but is not limited to, a display substrate, a lighting substrate, a substrate with functional devices such as transistors or ICs, or a substrate with metal redistribution lines.

In accordance with embodiments of the invention, heat may be applied to the carrier substrate, transfer head assembly, or receiving substrate during the pickup, transfer, and bonding operations. For example, heat can be applied through the transfer head assembly during the pick up and transfer operations, in which the heat may or may not liquefy LED device bonding layers. The transfer head assembly may additionally apply heat during the bonding operation on the receiving substrate that may or may not liquefy one of the bonding layers on the LED device or receiving substrate to cause diffusion between the bonding layers.

The operation of applying the voltage to create a grip pressure on the array of LED devices can be performed in various orders. For example, the voltage can be applied prior to contacting the array of LED devices with the array of transfer heads, while contacting the LED devices with the array of transfer heads, or after contacting the LED devices with the array of transfer heads. The voltage may also be applied prior to, while, or after applying heat to the bonding layers.

Where the transfer heads204 include bipolar electrodes, an alternating voltage may be applied across a the pair of electrodes in eachtransfer head204 so that at a particular point in time when a negative voltage is applied to one electrode, a positive voltage is applied to the other electrode in the pair, and vice versa to create the pickup pressure. Releasing the array of LED devices from the transfer heads204 may be accomplished with a varied of methods including turning off the voltage sources, lower the voltage across the pair of electrodes, changing a waveform of the AC voltage, and grounding the voltage sources.

Referring now toFIGS. 18A-18B, in an embodiment, an array of LED devices is transferred and bonded to a display substrate. For example, thedisplay substrate302 may be a thin film transistor (TFT) display substrate (i.e. backplane) similar to those used in active matrix OLED display panels.FIG. 18A is a top view illustration of adisplay panel1800 in accordance with an embodiment of the invention.FIG. 18B is a side-view illustration of thedisplay panel1800 ofFIG. 18A taken along lines X-X and Y-Y in accordance with an embodiment of the invention. In such an embodiment, theunderlying TFT substrate300 may include working circuitry (e.g. transistors, capacitors, etc.) to independently drive eachsubpixel328.Substrate300 may include a non-pixel area and apixel area304 includingsubpixels328 arranged into pixels. The non-pixel area may include adata driver circuit310 connected to a data line of each subpixel to enable data signals (Vdata) to be transmitted to the subpixels, ascan driver circuit312 connected to scan lines of the subpixels to enable scan signals (Vscan) to be transmitted to the subpixels, apower supply line314 to transmit a power signal (Vdd) to the TFTs, and aground ring316 to transmit a ground signal (Vss) to the array of subpixels. As shown, the data driver circuit, scan driver circuit, power supply line, and ground ring are all connected to a flexible circuit board (FCB)313 which includes a power source for supplying power to thepower supply line314 and a power source ground line electrically connected to theground ring316. It is to be appreciated, that this is one exemplary embodiment for a display panel, and alternative configurations are possible. For example, any of the driver circuits can be located off thedisplay substrate300, or alternatively on a back surface of thedisplay substrate300. Likewise, the working circuitry (e.g. transistors, capacitors, etc.) formed within thesubstrate300 can be replaced with micro chips bonded to the top surface of thesubstrate300.

In the particular embodiment illustrated, theTFT substrate300 includes a switching transistor T1 connected to a data line from thedriver circuit310 and a driving transistor T2 connected to a power line connected to thepower supply line314. The gate of the switching transistor T1 may also be connected to a scan line from thescan driver circuit312. A patternedbank layer326 includingbank openings327 is formed over thesubstrate300. In an embodiment,bank openings327 correspond tosubpixels328.Bank layer326 may be formed by a variety of techniques such as ink jet printing, screen printing, lamination, spin coating, CVD, PVD and may be formed of opaque, transparent, or semitransparent materials. In an embodiment,bank layer326 is formed of an insulating material. In an embodiment, bank layer is formed of a black matrix material to absorb emitted or ambient light. Thickness of thebank layer326 and width of thebank openings327 may depend upon the height of theLED devices150 transferred to and bonded within the openings, height of the electrostatic transfer heads, and resolution of the display panel. In an embodiment, exemplary thickness of thebank layer326 is between 1 μm-50 μm.

Electrically conductivebottom electrodes342,ground tie lines344 andground ring316 may optionally be formed over thedisplay substrate300. In the embodiments illustrated an arrangement ofground tie lines344 run betweenbank openings328 in thepixel area304 of thedisplay panel1800.Ground tie lines344 may be formed on thebank layer326 or alternative,openings332 may be formed in thebank layer326 to exposeground tie lines344 beneathbank layer326. In an embodiment,ground tie liens344 are formed between thebank openings327 in the pixel area and are electrically connected to theground ring316 or a ground line in the non-display area. In this manner, the Vss signal may be more uniformly applied to the matrix of subpixels resulting in more uniform brightness across thedisplay panel1800.

Apassivation layer348 formed around theLED devices150 within thebank openings327 may perform functions such as preventing electrical shorting between the top and bottom electrode layers318,342 and providing for adequate step coverage oftop electrode layer318 between the topconductive contacts142 and ground tie lines344. Thepassivation layer348 may also cover any portions of thebottom electrode layer342 to prevent possible shorting with thetop electrode layer318. In accordance with embodiments of the invention, thepassivation layer348 may be formed of a bariety of materials such as, but not limited to epoxy, acrylic (polyacrylate) such as poly(methyl methacrylate) (PMMA), benzocyclobutene (BCB), polymide, and polyester. In an embodiment,passivation layer348 is formed by ink jet printing or screen printing around theLED devices150 to fill the subpixel areas defined bybank openings327. In accordance with embodiments of the invention, thepassivation layer348 may be a black matrix material since the mirror is embedded within theLED device150.

Top electrode layer318 may be opaque, reflective, transparent, or semi-transparent depending upon the particular application. In top emission display panels thetop electrode layer318 may be a transparent conductive material such as amorphous silicon, transparent conductive polymer, or transparent conductive oxide. Following the formation oftop electrode layer318 andencapsulation layer346 is formed oversubstrate300. For example,encapsulation layer346 may be a flexible encapsulation layer or rigid layer. In accordance with some embodiments of the invention, a circular polarizer may not be required to suppress ambient light reflection. As a result,display panels1800 in accordance with embodiments of the invention may be packaged without a circular polarizer, resulting in increased luminance of the display panel.

In an embodiment, one ormore LED devices150 are arranged in a subpixel circuit. A first terminal (e.g. bottom conductive contact) of theLED device150 is coupled with a driving transistor. For example, theLED device150 can be bonded to a bonding pad coupled with the driving transistor. In an embodiment, a redundant pair ofLED devices150 are bonded to thebottom electrode342 that is coupled with the driving transistor T2. The one ormore LED devices150 may be any of the LED devices described herein including a confined current injection area, embedded mirror, and/or passivation layer. A ground line is electrically coupled with a second terminal (e.g. top conductive contact) for the one or more LED devices.

A current can be driven through the one or more LED devices, for example, from the driving transistor T2. In a high side drive configuration the one or more LED devices may be on the drain side of a PMOS driver transistor or a source side of an NMOS driver transistor so that the subpixel circuit pushes current through the p-terminal of the LED device. Alternatively, the subpixel circuit can be arranged in a low side drive configuration in which case the ground line becomes the power line and current is pulled through the n-terminal of the LED device.

In accordance with embodiments of the invention, the subpixel circuit may operate at comparatively low currents or current densities in the pre-droop range of the characteristic efficiency curve of the LED devices, or near a maximum efficiency value past the pre-droop range. Thus, rather than increasing the size of the LED devices to increase efficiency, the effective size of the current injection area is confined in order to increase the current density within the LED device. In embodiments where the LED devices are utilized in display applications, as opposed to high-powered applications, the LED devices can operate at comparatively lower current ranges, where a slight increase in current density may result in a significant improvement in IQE and EQE of the LED devices.

In an embodiment, a subpixel circuit comprises a driving transistor, a first terminal (e.g. bottom electrically conductive contact) of an LED device with confined current injection area is coupled with the driving transistor, and a ground line is coupled with a second terminal (e.g. top electrically conductive contact) of the LED device. In an embodiment, the LED device is operated by driving a current through the LED device in response to sending a control signal to the driving transistor. In some embodiments, the current may range from 1 nA-400 nA. In an embodiment, the current ranges from 1 nA-30 nA. In an embodiment, an LED device is operated with a current from 1 nA-30 nA in a display having a 400 pixel per inch (PPI) resolution. In an embodiment, the current ranges from 200 nA-400 nA. In an embodiment, an LED device is operated with a current from 200 nA-400 nA in a display having a 100 PPI resolution. In some embodiments, an LED device is operated with a confined current density from 0.001 A/cm²to 40 A/cm². In an embodiment, the current density ranges from 0.001 A/cm²to 3 A/cm². In an embodiment, such a current density range may be applicable to a display having a 400 PPI resolution. In an embodiment, the current density ranges from 0.2 A/cm²to 4 A/cm². In an embodiment, such a current density range may be applicable to a display having a 100 PPI resolution.

The following examples are provided to illustrate the effect of current confinement, and the relationship of efficiency, current and current density for LED devices in accordance with embodiments of the invention. In accordance with embodiments of the invention, a designer may select a desired efficiency and luminance of an LED device with a characteristic efficiency curve, such as the exemplary efficiency curve illustrated inFIG. 21. Upon selecting the desired efficiency and luminance, the designer may tune the operating current and size of the confined current injection area within the LED device to achieve the desired efficiency.

Example 1

In one embodiment, a display panel is a 5.5 inch full high definition display with 1920×1800 resolution, and 400 pixels per inch (PPI) including a 63.5 μm RGB pixel size. To achieve a 300 Nit output (white) with LED devices having a 10% EQE, the display panel uses approximately 10 nA-30 nA of current per LED, assuming one LED per subpixel. For an LED device with a 10 μm×10 μm confined current injection area this corresponds to a current density of 0.01 A/cm²-0.03 A/cm². This is well below the normal or designed operating conditions for standard LEDs.

Example 2

In an embodiment, the parameters of Example 1 are the same, with a smaller 1 μm×1 μm confined current injection area. With this reduced current injection area the corresponding current density increases to 1 A/cm²-3 A/cm². Thus, Example 2 illustrates that at operating currents of 10 nA-30 nA, small changes in current injection area from 10 μm×10 μm to 1 μm×1 μm can have a significant effect on current density. In turn, the change in current density may affect efficiency of the LED device.

Example 3

In one embodiment, a display panel is a 5.5 inch full high definition display with 1920×1800 resolution, and 400 pixels per inch (PPI) including a 63.5 μm RGB pixel size. Each subpixel includes an LED device with a 10 μm×10 μm confined current injection area. Luminance is maintained at 300 Nit output (white). In this example, it is desired to achieve a 40% EQE. With this increased efficiency, lower operating currents may be used. In an embodiment, an operating current of 3 nA-6 nA per LED is selected. With these parameters an LED device with a 10 μm×10 μm confined current injection area operates at 0.003 A/cm²-0.006 A/cm², and an LED device with a 1 μm×1 μm confined current injection area operates at 0.3 A/cm²-0.6 A/cm².

Example 4

In one embodiment, a display panel is a 5.5 inch display with a lower resolution of 100 PPI including a 254 μm RGB pixel size. To achieve a 300 Nit output (white) with LED devices having a 10% EQE, the display panel uses a higher operating current of approximately 200 nA-400 nA of current per LED, assuming one LED per subpixel. For an LED device with a 10 μm×10 μm confined current injection area this corresponds to a current density of 0.2 A/cm²-0.4 A/cm². A 1 μm×1 μm confined current injection area corresponds to a current density of 20 A/cm²-40 A/cm², and a 3 μm×3 μm confined current injection area corresponds to a current density of 2 A/cm²-4 A/cm². Thus, Example 4 illustrates that with lower resolution displays, there is a smaller density of LED devices, and higher operating currents are used to achieve a similar brightness (300 Nit) as higher resolution displays.

Example 5

In one embodiment, a display panel has 716 PPI including a 35 μm RGB pixel size. To achieve a 300 Nit output (white) with LED devices having a 10% EQE, the display panel uses an operating current of approximately 4-7 nA. With these parameters an LED device with a 10 μm×10 μm confined current injection area operates at 0.004 A/cm²-0.007 A/cm², and an LED device with a 1 μm×1 μm confined current injection area operates at 0.4 A/cm²-0.7 A/cm².

Example 6

In another embodiment the required brightness of the display is increased to 3000 Nit. In all examples above the required current would increase about 10× if the same EQE is targeted. Subsequently, the current density would also increase 10× for the above examples. In one embodiment the required operating brightness is a range from 300 Nit to 3000 Nit. The current and subsequently the current density would span a range of 1-10× the 300 Nit range. In the case of Examples 1 and 2 (above) where now 300 Nit to 3000 Nit is required, an LED device with a 10 μm×10 μm confined current injection area operates at a current density of 0.01 A/cm²-0.3 A/cm²and an LED device with a 1 μm×1 μm confined current injection area operates at 1 A/cm²-30 A/cm².

In each of the above exemplary embodiments, the brightness of the display is such that the LED devices are operating at very low current densities that are not typical of standard LEDs. The typical performance of standard LEDs show low IQEs at current densities below 1 A/cm². In accordance with embodiments of the invention, the current injection area is confined such that the current density can be increased to allow operation of the LED devices in a current density regime where IQE, and EQE, are optimized.

FIG. 19 illustrates adisplay system1900 in accordance with an embodiment. The display system houses aprocessor1910,data receiver1920, adisplay1930, and one or moredisplay driver ICs1940, which may be scan driver ICs and data driver ICs. Thedata receiver1920 may be configured to receive data wirelessly or wired. Wireless may be implemented in any of a number of wireless standards or protocols including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The one or moredisplay driver ICs1940 may be physically and electrically coupled to thedisplay1930.

In some embodiments, thedisplay1930 includes one ormore LED devices150 that are formed in accordance with embodiments of the invention described above. Depending on its applications, thedisplay system1900 may include other components. These other components include, but are not limited to, memory, a touch-screen controller, and a battery. In various implementations, thedisplay system1900 may be a television, tablet, phone, laptop, computer monitor, kiosk, digital camera, handheld game console, media display, ebook display, or large area signage display.

FIG. 20 illustrates alighting system2000 in accordance with an embodiment. The lighting system houses apower supply2010, which may include a receivinginterface2020 for receiving power, and apower control unit2030 for controlling power to be supplied to thelight source2040. Power may be supplied from outside thelighting system2000 or from a battery optionally included in thelighting system2000. In some embodiments, thelight source2040 includes one ormore LED devices150 that are formed in accordance with embodiments of the invention described above. In various implementations, thelighting system2000 may be interior or exterior lighting applications, such as billboard lighting, building lighting, street lighting, light bulbs, and lamps.

In utilizing the various aspects of this invention, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for forming an LED device including any one of a confined current injection area, embedded mirror, or passivation layer. Although the present invention has been described in language specific to structural features and/or methodological acts, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as particularly graceful implementations of the claimed invention useful for illustrating the present invention.

Claims (9)

What is claimed is:

1. An LED device comprising:

a p-n diode layer comprising:

a top surface with a maximum dimension of 3 to 20 μm,

a bottom surface comprising an interior bottom surface and a surrounding bottom surface;

external sidewalls extending between the top surface and the surrounding bottom surface;

a quantum well layer between an n-doped layer and a p-doped layer;

a confinement trench that extends from the bottom surface of the p-n diode layer through the quantum well layer and physically isolates an interior portion of the quantum well layer from a surrounding portion of the quantum well layer adjacent the external sidewalls, and the confinement trench physically isolates an interior bottom surface of the p-n diode layer from a surrounding bottom surface of the p-n diode layer adjacent the external sidewalls, wherein the surrounding bottom surface of the p-n diode completely surrounds the interior bottom surface of the p-n diode layer;

a bottom electrically conductive contact on and in electrical contact with the interior bottom surface of the p-n diode layer, wherein the bottom electrically conductive contact that is on and in electrical contact with the interior bottom surface of the p-n diode layer is not in electrical contact with the surrounding bottom surface of the p-n diode layer that completely surrounds the interior bottom surface of the p-n diode layer;

wherein the LED device is bonded to a bottom electrode of a subpixel within a display area of a display substrate, and the bottom electrically conductive contact is in electrical contact with the bottom electrode; and

a top electrode that is on and in electrical contact with the top surface, and the top electrode completely covers the top surface.

2. The LED device ofclaim 1, further comprising a mirror layer spanning along the interior bottom surface and along confinement trench sidewalls within the confinement trench.

3. The LED device ofclaim 2, wherein the mirror layer does not span along the external sidewalls of the p-n diode layer.

4. The LED device ofclaim 2, further comprising a passivation layer between the mirror layer and the confinement trench sidewalls.

5. The LED device ofclaim 4, wherein the passivation layer spans along the external sidewalls of the p-n diode layer.

6. The LED device ofclaim 4, further comprising an opening in the passivation layer on the interior bottom surface of the p-n diode layer.

7. The LED device ofclaim 6, wherein the mirror layer is formed within the opening of the passivation layer on the interior bottom surface of the p-n diode layer.

8. The LED device ofclaim 1, wherein a top surface area of the top surface of the p-n diode layer is larger than a surface area of the interior bottom surface of the p-n-diode layer surrounded by the confinement trench.

9. The LED device ofclaim 1, wherein the display substrate is incorporated within portable electronic device.

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