US9581978B1

Movatterモバイル変換

Info

Publication number: US9581978B1
Application number: US14/574,339
Authority: US
Inventors: Lance Flake
Original assignee: Western Digital Technologies Inc
Current assignee: Western Digital Technologies Inc
Priority date: 2014-12-17
Filing date: 2014-12-17
Publication date: 2017-02-28

Abstract

An apparatus includes: a media; a head over the media; a head actuation motor (HAM) coupled to the head; control circuitry, coupled to the head actuation motor, including: a system-on-chip (SOC) configured to manage a control of the head actuation motor, a pulse width modulation (PWM) code bus, coupled to the SOC, configured to communicate the control of the HAM, and a power integrated circuit (PIC), coupled to the PWM code bus, configured to drive a HAM control signal.

Description

TECHNICAL FIELD

An embodiment relates generally to an electronic system, and more particularly to a system for servo data management.

BACKGROUND

Modern consumer and industrial electronic devices require storage of information, such as digital photographs, electronic mail, calendar, or contacts. These devices can be electronic systems, such as notebook computers, desktop computers, servers, televisions, and projectors, and are providing increasing levels of functionality to support modern life. Preserving the user data stored in the storage devices is of the utmost importance.

As recording technologies advance in hard disk drives, the performance and capacity has increased while the size has decreased. The pressure to produce smaller storage devices has led to the combining of integrated functions that can reside in a compatible technology. Many functions of the storage devices require analog control and sensitivity that cannot be provided by digital logic processes. The control interface between the digital functions and the analog control mechanisms continues to grow based on features and performance of the storage devices. The number of control bits in the control interface can increase the size of the packages and increase cost of the storage device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A, 1B, and 1C show an operational diagram of an electronic system with servo management according to an embodiment.

FIG. 2 shows a servo control system, of the electronic system, for controlling a head actuation motor and a media motor in accordance with an embodiment.

FIG. 3 shows a functional block diagram of a receiver interface for a power integrated circuit (PIC) in an embodiment.

FIG. 4 shows a functional block diagram of a transmitter interface for a system on chip (SOC) in an embodiment.

FIG. 5 shows an exemplary timing diagram of the PWM code bus in an embodiment.

DETAILED DESCRIPTION

Storage systems can include storage devices, such as hard disk drives (HDD) and hybrid drives utilizing magnetic recording heads in combination with non-volatile memory devices, that must manage analog control functions through pulse-width modulation (PWM). In order to control the media motor and position the heads correctly a number of analog controls must be subject to the manipulation by the controller. The response to the control of an analog circuit can be significantly longer than the response to digital logic because the analog circuitry is used to drive the movement of mechanical structures, such as the media motor and the and the head actuation motor (HAM), which can respond slowly.

Some embodiments can group sets of analog controls, that when activated can work together in a coordinated switching process. The control of the media motor can be grouped as pairs of transistors are managed in order to drive, sink, and sense the location of the media motor as it windings are manipulated to control the media speed.

It is understood that the control of the media motor can include passing current through three sets of coils used to create torque around the central hub of the media motor. By grouping the controls, the control of the media motor is simplified and can operate in a smoother and more tightly controlled process. During operation of the storage system, both the HAM and the media motor must be controlled in real-time.

A need still remains for an electronic system as an embodiment with servo management mechanism for managing the real-time controls of the media motor and the HAM during the operation of the data storage and retrieval tasks. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is increasingly critical that answers be found to these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.

Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.

Certain embodiments have other steps or elements in addition to or in place of those mentioned above. The steps or elements will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.

The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the various embodiments. It is to be understood that other embodiments would be evident based on the present disclosure, and that system, process, or mechanical changes may be made without departing from the scope of an embodiment.

In the following description, numerous specific details are given to provide a thorough understanding of the various embodiments. However, it will be apparent that the various embodiments can be practiced without these specific details. In order to avoid obscuring an embodiment, some well-known circuits, system configurations, and process steps are not disclosed in detail.

The drawings showing embodiments of the system are semi-diagrammatic, and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown exaggerated in the drawing figures. Similarly, although the views in the drawings for ease of description generally show similar orientations, this depiction in the figures is arbitrary for the most part. Generally, the various embodiments can be operated in any orientation. The various embodiments have been numbered first embodiment, second embodiment, etc. as a matter of descriptive convenience and are not intended to have any other significance or provide limitations for an embodiment.

Referring now toFIGS. 1A, 1B, and 1C, therein are shown an operational diagram of anelectronic system100 according to an embodiment. Theelectronic system100 can represent an apparatus for one of the various embodiments. Various embodiments can include the embodiment depicted inFIGS. 1A, 1B, and 1C which by way of an example is shown as a hard disk drive although it is understood that theelectronic system100 can be a tape drive, a solid-state hybrid disk drive, or other magnetic media-based storage device. Further for example, theelectronic system100 can represent a desktop computer, a notebook computer, a server, a tablet, a television, a household appliance, or other electronic systems utilizing magnetic media storage.

Theelectronic system100 including ahead102 actuated over amedia104. Thehead102 can be mounted to aflex arm118 attached to anactuator arm122. The head102 (FIG. 1B) can optionally include alaser106 for heating themedia104 during part of a write process (e.g., the head is part of an Energy-Assisted Magnetic Recording (EAMR) drive). Theflying height108 can be adjusted (e.g., by use of a heater element in the head not shown inFIG. 1B) while writing data to themedia104 or as an error recovery process during reading from themedia104. Also in an embodiment ofFIG. 1B, thehead102 comprises a write element110 (e.g., an inductive coil) and a read element112 (e.g., a magnetoresistive read element).

Themedia104 is a structure for storing information ondata tracks124. For example, themedia104 can be made of an aluminum alloy, ceramic/glass, or a similar non-magnetic material. The top and bottom surfaces of themedia104 can be covered with magnetic material deposited on one or both sides of themedia104 to form a coating layer capable of magnetization. As an example, themedia104 can be a disk platter for one embodiment of theelectronic system100 as a rotating storage system, such as a hard disk drive (HDD). As a further example, themedia104 can be a linear magnetic strip for one embodiment of theelectronic system100 as a linear storage system, such as a tape drive or a magnetic card reader.

Thelaser106, as an example, can be a laser diode or other solid-state based lasers. In addition, embodiments can employ any suitable techniques for focusing thelaser106 on themedia104, such as a suitable waveguide, magnifying lens, or other suitable optics. Thelaser106 is increased to a write power in order to heat the disk, thereby decreasing the coercivity of themedia104 so that the data is written more reliably on thedata tracks124.

Amedia motor116 can rotate themedia104, about a center of themedia104, at constant orvarying speed107. For illustrative purposes, themedia motor116 is described as a motor for a rotation, although it is understood that themedia motor116 can be other actuating motors for a tape drive, as an example.

As examples, ahead actuation motor130 can be a voice coil motor assembly, a stepper motor assembly, or a combination thereof. Thehead actuation motor130 can generate a torque or force for positioning thehead102. The positional feedback for thehead102 can be provided to controlcircuitry138 by readingservo sectors114 from themedia104. Theservo sectors114 are distributed around themedia104 at intervals sufficient to allow proper positioning of thehead102 within the data tracks124.

A tapered end of theflex arm118 can support thehead102. Theflex arm118 can be mounted to theactuator arm122, which is pivoted around a bearingassembly126 by the torque generated by thehead actuation motor130. Thehead102 can include a single instance of thewrite element110 and a single instance of the readelement112 that is narrower than thewrite element110. Thehead102 can fly over themedia104 at a dynamically adjustable span of the flyingheight108, which represents a vertical displacement between thehead102 and themedia104. Thehead102 can be positioned by theflex arm118 and theactuator arm122 and can have the flyingheight108 adjusted by thecontrol circuitry138. Thecontrol circuitry138 can measure a magnitude of the environmental disturbance, through the environmental sensor136, and calculate a feed forward adjustment for thehead actuation motor130. Thecontrol circuitry138 can control a head actuation motor (HAM)control signal120 in order to manage the position of thehead actuation motor130.

Thehead102 can be positioned over themedia104 along an arc shaped path between an inner diameter of themedia104 and outer diameter of themedia104. For illustrative purposes, theactuator arm122 and thehead actuation motor130 are configured for rotary movement of thehead102. Theactuator arm122 and thehead actuation motor130 can be configured to have a different movement. For example, theactuator arm122 and thehead actuation motor130 could be configured to have a linear movement resulting in thehead102 traveling along a radius of themedia104.

Thehead102 can be positioned over themedia104 to create magnetic transitions or detect magnetic transitions from the data tracks124 recorded in the coating layer that can be used to representing written data or read data, respectively. The position of thehead102 and thespeed107 of themedia104 can be controlled by thecontrol circuitry138. Examples of thecontrol circuitry138 can include a processor, an application specific integrated circuit (ASIC) an embedded processor, a microprocessor, a hardware control logic, a hardware finite state machine (FSM), a digital signal processor (DSP), digital circuitry, analog circuitry, optical circuitry, or a combination thereof. Thecontrol circuitry138 can also include memory devices, such as a volatile memory, a nonvolatile memory, or a combination thereof. For example, the nonvolatile storage can be non-volatile random access memory (NVRAM) or Flash memory and a volatile storage can be static random access memory (SRAM) or dynamic random access memory (DRAM).

Asystem interface140 can couple thecontrol circuitry138 to a host electronics (not shown). Thesystem interface140 can transfer host commands142 between the host electronics and thecontrol circuitry138. The host commands142 can be encoded or decoded by thecontrol circuitry138 in preparation for transfer to or from themedia104.

Thecontrol circuitry138 can be configured to control themedia motor116 for adjusting thespeed107 of themedia104. Thecontrol circuitry138 can be configured to cause thehead102 to move relative to themedia104, or vice versa. Thecontrol circuitry138 can be configured to control thespeed107 of themedia104 by sensing the back electro-motive force (EMF) of themedia motor116 and the position of thehead102 by reading theservo sectors114 strategically placed on themedia104. Theservo sectors114 can be recorded on themedia104 during a manufacturing process. Thecontrol circuitry138 can also be configured to control the flow of information to thehead102 for writing to themedia104. The information sent to thehead102 can include the preconditioning pattern, direct current erase signals, user data, or a combination thereof. Thecontrol circuitry138 can retrieve the recorded information and monitor theservo sectors114 through aread signal128 provided by thehead102.

In an embodiment, theelectronic system100 further comprisescontrol circuitry138 configured to execute the flow diagrams ofFIG. 1C. As an example,actions144 to148 can represent the flow diagram where an embodiment is employing a data management mechanism for maintaining data integrity.

In anaction144, thecontrol circuitry138 can manage the head actuation motor (HAM)130 through a system on a chip (SOC) when thehead102 is flown over themedia104 during execution by theelectronic system100, such as a manufacturing test fixture, a hard disk drive, a tape drive, or a hybrid drive.

In anaction146, the SOC can generate a pulse-width modulation (PWM) code bus reflecting the operations required to communicate the control of the HAM. The bits in the PWM code bus can be coded to reflect a single operational step or a group of coordinated operational steps.

In anaction148, the HAM control signals are driven by a power integrated circuit (PIC) based on the PWM code bus. The PWM code bus can meet the performance requirements for all of the analog control functions in theelectronic system100, while reducing the pin count and package size required by thecontrol circuitry138.

It has been discovered that various embodiments of theelectronic system100 can improve the overall performance while reducing system cost and size. Theelectronic system100 can manage the analog control requirements without adding additional package size or complicating the interconnect structure of the printed circuit board assembly of thecontrol circuitry138.

Referring now toFIG. 2, therein is shown aservo control system201, of theelectronic system100, for controlling ahead actuation motor130 and amedia motor116 in accordance with an embodiment. Theservo control system201 controls thehead actuation motor130 in order to position thehead assembly102 radially over themedia104. A read/write channel202 demodulates the readsignal128, from theservo sectors114, into an estimatedposition204 for thehead assembly102 relative to thedata track124 ofFIG. 1A on themedia104. The estimatedposition204 is applied to afirst adder206 for subtracting areference position208 in order to generate a position error signal (PES)210. Thecontrol circuitry138 can monitor thePES210 in order to generate theHAM control signal120.

As an example, thecontrol circuitry138 can include a system-on-a-chip (SOC)212 that includes the digital functions supported by theelectronic system100. A power integrated circuit (PIC)214 can be driven by theSOC212 through a pulse-width modulation (PWM)code bus216. ThePIC214 can drive a mediamotor control bus218 for managing the commutation of themedia motor116. By allowing theSOC212 to manage the switching of analog control signals in the mediamotor control bus218, thePIC214 is greatly simplified and can be further reduced in size and cost. TheSOC212 can implement the commutation logic for driving themedia motor116 in very small and high speed Complementary Metal Oxide Semiconductor (CMOS) digital logic dedicated to that purpose.

ThePIC214 can concurrently provide theHAM control signal120 and the mediamotor control bus218. The functional management of theHAM control signal120 and the mediamotor control bus218 can remain in theSOC212 while the analog signal drive capability is provided by thePIC214. This combination can dramatically reduce the cost of thePIC214, which can be produced in a bipolar technology, such as Silicon Germanium (SiGe), Gallium Arsenide (GaAs), or Bipolar Complementary Metal Oxide Semiconductor (BiCMOS). By reducing the function as well as the size of thePIC214, the overall system cost can be reduced.

Thecontrol circuitry138 can receive feedback on the position of thehead102 by way of thePES210. TheSOC212 can interpret thePES210 in order to determine the response required by theHAM control signal120 in order to correctly position thehead102. The control of themedia motor116 can be monitored by detecting the frequency of the servo related fields in theservo sectors114 as well as the time interval between theservo sectors114.

The communication between theSOC212 and thePIC214, across thePWM code bus216, can operate at digital speeds, while the analog control signals from thePIC214 have much longer durations. The difference in the speed of the control requirements allows theSOC212 to toggle the control lines of theHAM control signal120 and the mediamotor control bus218 to assert and negate the individual controls or groups of controls.

It has been discovered that thePWM code bus216 can reduce the amount of control logic required in thePIC214, which allows a reduction in the physical size of the integrated circuit of thePIC214 and reduces the pin count which can further reduce the package geometry of thePIC214. The additional digital logic required in theSOC212 can have little or no impact on the size of the die of theSOC212 while also reducing the pin count of the package theSOC212 requires. The overall reduction in cost of theSOC212 and thePIC214 also provides a smaller package size for both.

Referring now toFIG. 3, therein is shown a functional block diagram of areceiver interface301 for a power integrated circuit (PIC)214 ofFIG. 2 in an embodiment. The functional block diagram of thereceiver interface301 depicts thePWM code bus216, which includes aPWM signal code302 and an activate (ACT)line304.

ThePWM signal code302 can be a multi-bit bus having a number of bits to control a plurality of PWM controls306. By way of an example thePWM signal code302 can be 5 bits wide in order to activate up to 32 (2⁵) of the PWM controls306. The addition of a single additional bit in thePWM signal code302 can activate up to 64 (2⁶) of the PWM controls306.

ThePWM signal code302 can be coupled to anactivation decoder308. Theactivation decoder308 can assert a selectedenable310 based on the content of thePWM signal code302. As an example, the selected enable310 is only asserted during the period that thePWM signal code302 is stable. Each of the selected enable310 can be coupled to an enable input of astorage element312, such as a toggle flip-flop314 or a data flip-flop316. A clock input of thestorage element312 can be coupled to theACT line304.

In one embodiment, each of thestorage elements312 can only respond to the activation of theACT line304 if the selected enable310 is present during the negative to positive transition of theACT line304. In one embodiment, since theactivation decoder308 only enables one or grouped lines of the selected enable310, the PWM controls306 can be managed through thePWM code bus216.

The PWM controls306 can be segregated into PWM single controls318 and PWM group controls320. The PWM single controls318 can be utilized to activate a light emitting diode (LED), a flying height control of thehead102 ofFIG. 1A, an environmental sensor or the like. The PWM group controls320 can be used for controlling an H-bridge of thehead actuation motor130 ofFIG. 1A or themedia motor116 ofFIG. 1A.

The PWM group controls320 can utilize a pair of thestorage element312. The first of the pair of thestorage element312 can be the toggle flip-flop314. The second of the pair of thestorage element312 can be the data flip-flop316 coupled to the toggle flip-flop314 as a source of the data input. By way of an example, the toggle flip-flop314 can be asserted then the data flip-flop316 can be activated to assert thePWM group control320. The toggle flip-flop314 can be enabled a second time to negate the output. ThePWM group control320 will remain asserted until the data flip-flop316 is once again enabled when the toggle flip-flop314 is negated.

The nature of the PWM controls306 is a long duration between transitions. As an example, some of the PWM controls can be asserted for 10 to 40 micro-seconds while others of the PWM controls306 can be asserted for several seconds.

It is understood that the activation period of thePWM signal code302 can be offset from theACT line304 by at least half of the cycle time of theACT line304. This assures that the data set-up and hold time requirements of thestorage elements312 are met. It is further understood that the number of the PWM single controls318 and the PWM group controls320 is an example only and any combination can be implemented.

Referring now toFIG. 4, therein is shown a functional block diagram of atransmitter interface401 for a system on chip (SOC)212 ofFIG. 2 in an embodiment. The functional block diagram of thetransmitter interface401 depicts thePWM signal code302 and theACT line304 sourced from digital logic in theSOC212. Thetransmitter interface401 can be implemented in high speed digital logic within theSOC212.

Digital PWM requests402 are optionally coupled to request synchronizing flip-flops404. The output of the request synchronizing flip-flops404 can provide an input to a onecycle pulse circuit406, including a data flip-flop408 coupled to an exclusive ORgate410. When a synchronized request is asserted by the request synchronizing flip-flops404, arequest pulse412 at the output of the exclusive ORgate410 is asserted. On the subsequent system clock cycle, the data flip-flop408 will pass the synchronized request and negate therequest pulse412 of the exclusive ORgate410. The one cycle of therequest pulse412 is assured because the request synchronizing flip-flops404 and the data flip-flop408 are both clocked by the same cycle of a PWM clock (PCLK)414. In one embodiment, thePCLK414 is a derivative of the clock used throughout thecontrol circuitry138 ofFIG. 1A. ThePCLK414 can be divided to produce a lower frequency than clock used throughout thecontrol circuitry138.

As an example, therequest pulse412 can be coupled to acounter element416, such as a multi-bit counter with increment and decrement controls. Thecounter element416 is also clocked by thePCLK414. In one embodiment, the distribution of thePCLK414 assures that only a single increment is detected for a separate occurrence of therequest pulse412 but multiple occurrences of therequest pulse412 can be captured. The output of thecounter element416 can be a pendingPWM request418.

In order to manage multiple concurrent instances of the pendingPWM request418, anarbiter circuit420 can prioritize allowing the pendingPWM request418. When thearbiter circuit420 allows the pendingPWM request418, aPWM code422 can be represented on thePWM signal code302. The value of thePWM code422 can be fixed to represent a single operation on thePWM signal code302. As an example, thearbiter circuit420 can be clocked by the falling edge of theACT line304. The timing of the switch in value on thePWM signal code302 and theACT line304 provides ample set-up and hold timing in thePIC214 ofFIG. 2.

When the requested value of thePWM code422 is gated to thePWM signal code302, acomparator circuit424 can detect the match and provide a decrement to thecounter element416. For example, if only one of therequest pulses412 had been detected by thecounter element416, the pendingPWM request418 is negated. If multiples of therequest pulses412 had been detected by thecounter element416, the number of the pendingPWM request418 is reduced by one, but the pending PWM request(s)418 remains asserted at thearbiter circuit420.

Any of the pending PWM requests418 can initiate a cycle of theACT line304 through acycle generator426. Thecycle generator426 is clocked by thePCLK414, which will assert theACT line304 on a rising edge of thePCLK414 and negate theACT line304 on the subsequent rising edge of thePCLK414. If additional lines of the pending PWM requests418 are present, theACT line304 will once again be asserted. This cycle will repeat until the pending PWM requests418 are satisfied, which will leave theACT line304 in the negated state.

It is understood that the number of thePWM code422 is an example and any number of the pendingPWM request418 can be accommodated by changing the number of bits in thePWM signal code302. The value of thePWM code422 is coordinated with thePIC214, but there are no restrictions on the interpretation of thePWM code422. It is also understood that all of the request synchronizing flip-flops404, the data flip-flop408, thecounter element416, and thecycle generator426 are clocked by thePCLK414, though for clarity not all of the connections are shown. Thearbiter circuit420 can be switched by the falling edge of theACT line304 reflected by the negative output of thecycle generator426.

Referring now toFIG. 5, therein is shown an exemplary timing diagram501 of thePWM code bus216 in an embodiment. The exemplary timing diagram501 of thePWM code bus216 depicts thePWM signal code302 and theACT line304 as they relate to thePCLK414.

The pendingPWM request418 ofFIG. 4 can be asserted on an N^thrising edge502 of thePCLK414. Thearbiter circuit420 ofFIG. 4 can pass thePWM code422 to thePWM signal code302. By way of an example thePWM signal code302 is a five bit bus and the pendingPWM request422 can have the code of “00110”.

At an N+1^thrisingedge504 of thePCLK414, theACT line304 can be asserted. Since thePWM signal code302 can propagate into thePIC214 ofFIG. 2 and provide the appropriate value of the selected enable310 ofFIG. 3, the assertion of theACT line304 can switch theappropriate storage element312 ofFIG. 3 for asserting or removing the PWM controls306 ofFIG. 3.

By way of an example, at an N+2^thrisingedge506 of thePCLK414, theACT line304 can be negated and thearbiter circuit420 can propagate thePWM code422 of the pendingPWM request418 that is the next priority. In this example, thePWM code422 having the highest priority is shown to generate thePWM signal code302 value of “01001”. The transfer of thePWM code bus216 between theSOC212 ofFIG. 2 and thePIC214 can continue as long as there are any of the pending PWM requests418. If all of the pending PWM requests418 have been serviced, the code bus can be forced to a known value, such as “00000” and theACT line304 remains negated.

The resulting method, process, apparatus, device, product, and/or system is straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive, and effective, and can be implemented by adapting known components for ready, efficient, and economical manufacturing, application, and utilization.

These and other valuable aspects of an embodiment consequently further the state of the technology to at least the next level.

While the various embodiments have been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims. All matters set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.

Claims

What is claimed is:

1. An apparatus comprising:

media;

a head over the media;

a head actuation motor (HAM) coupled to the head; and

control circuitry, coupled to the head actuation motor, including:

a system-on-chip (SOC) configured to manage a control of the head actuation motor,

a pulse width modulation (PWM) code bus, coupled to the SOC, configured to communicate the control of the HAM, the PWM code bus including a PWM signal code and an activation signal, and

a power integrated circuit (PIC), coupled to the PWM code bus, configured to drive a HAM control signal that controls the HAM based on the control of the HAM communicated by the PWM code signal code and the activation signal,

wherein an activation period of the PWM signal code is offset from the activation signal by at least one-half of a cycle time of the activation signal.

2. The apparatus as claimed inclaim 1 wherein the SOC is further configured to manage control of a media motor.

3. The apparatus as claimed inclaim 1 wherein the SOC is further configured to generate a PWM code to adjust the HAM in response to a position error signal (PES).

4. The apparatus as claimed inclaim 1 wherein the SOC is further configured to generate a PWM group code for control of a media motor.

5. The apparatus as claimed inclaim 1 wherein the PIC is further configured to generate a PWM control to position the HAM.

6. The apparatus as claimed inclaim 1 wherein the PIC is further configured to generate a group PWM control to rotate a media motor.

7. The apparatus as claimed inclaim 6 wherein the group PWM control further includes PWM control to control a head height of the head.

8. The apparatus according toclaim 6 wherein the SOC includes an arbitration circuit to prioritize PWM control requests used to generate the group PWM control.

9. The apparatus as claimed inclaim 1 wherein the PIC is further configured to concurrently control a media motor and the HAM.

10. The apparatus as claimed inclaim 1 wherein the SOC is further configured to generate a stream of PWM signal codes to control the HAM and a media motor.

11. A method of operating an apparatus, the method comprising:

managing a head actuation motor (HAM) by a system-on-chip (SOC);

communicating the control of the HAM through a pulse width modulation (PWM) code bus, the PWM code bus including a PWM signal code and an activation signal; and

driving a HAM control signal that controls the HAM, from a power integrated circuit (PIC), coupled to the PWM code bus based on the control of the HAM communicated by the PWM code signal code and the activation signal,

12. The method as claimed inclaim 11 further comprising managing a media motor by the SOC.

13. The method as claimed inclaim 11 further comprising generating a PWM code, by the SOC, for responding to a position error signal (PES) by adjusting the HAM.

14. The method as claimed inclaim 11 further comprising generating a PWM group code, by the SOC, for controlling a media motor.

15. The method as claimed inclaim 14 wherein the PWM group control further includes PWM control to control a height of a head coupled to the HAM.

16. The method as claimed inclaim 14 wherein the method further comprises prioritizing PWM control requests used to generate the PWM group control.

17. The method as claimed inclaim 11 further comprising generating a PWM control, by the PIC, for positioning the HAM.

18. The method as claimed inclaim 11 further comprising generating a group PWM control, by the PIC, for rotating a media motor.

19. The method as claimed inclaim 11 further comprising concurrently controlling a media motor and the HAM by the PIC.

20. The method as claimed inclaim 11 further comprising generating a stream of PCM signal codes for controlling the HAM and a media motor.

21. An apparatus comprising:

control circuitry, coupled to a head actuation motor (HAM), including:

a system-on-chip (SOC) configured to manage a control of the HAM coupled to a head over a media,

22. The apparatus as claimed inclaim 21 wherein the SOC is further configured to generate a PWM code to adjust the HAM in response to a position error signal (PES).

23. The apparatus as claimed inclaim 21 wherein the SOC is further configured to generate a PWM group code for control of a media motor.

24. The apparatus as claimed inclaim 21 wherein the PIC is further configured to generate a PWM control to position the HAM.

25. The apparatus as claimed inclaim 21 wherein the PIC is further configured to generate a group PWM control to rotate a media motor.

26. The apparatus as claimed inclaim 21 wherein the PIC is further configured to control a media motor and the HAM.

27. The apparatus as claimed inclaim 21 wherein the SOC is further configured to generate a stream of PWM signal codes to control the HAM and a media motor.