US9478704B2 - Semiconductor display device - Google Patents

Abstract

In the case where a still image is displayed on a pixel portion having a pixel, for example, a driver circuit for controlling writing of an image signal having image data to the pixel portion stops by stopping supply of power supply voltage to the driver circuit, and writing of an image signal to the pixel portion is stopped. After the driver circuit stops, supply of power supply voltage to a panel controller for controlling the operation of the driver circuit and an image memory for storing the image data is stopped, and supply of power supply voltage to a CPU for collectively controlling the operation of the panel controller, the image memory, and a power supply controller for controlling supply of power supply voltage to a variety of circuits in a semiconductor display device is stopped.

Description

TECHNICAL FIELD

The present invention relates to an active-matrix semiconductor display device including a transistor in a pixel.

BACKGROUND ART

In recent years, a metal oxide having semiconductor characteristics called an oxide semiconductor has attracted attention as a novel semiconductor having high mobility provided by crystalline silicon and uniform element characteristics provided by amorphous silicon. The metal oxide is used for various applications. For example, indium oxide, which is a well-known metal oxide, is used for a light-transmitting pixel electrode in a liquid crystal display device, a light-emitting device, or the like. Examples of such a metal oxide having semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, and zinc oxide. Transistors each including such a metal oxide having semiconductor characteristics in a channel formation region have been known (Patent Documents 1 and 2).

REFERENCE

• Patent Document 1: Japanese Published Patent Application No. 2007-123861
• Patent Document 2: Japanese Published Patent Application No. 2007-096055

DISCLOSURE OF INVENTION

Low power consumption is one of the important points in evaluating the performance of a semiconductor display device. In particular, in a portable electronic device such as a cellular phone, a semiconductor display device needs to consume less power because high power consumption of the semiconductor display device leads to a disadvantage of short continuous operating time.

In view of the above technical background, it is an object of the present invention to propose a semiconductor display device capable of consuming less power.

A semiconductor display device according to one embodiment of the present invention includes a pixel portion having a pixel; a driver circuit for controlling writing of an image signal having image data to the pixel portion; a panel controller for controlling the operation of the driver circuit; an image memory for storing the image data; a power supply controller for controlling supply of power supply voltage to a variety of circuits in the semiconductor display device; and a CPU for collectively controlling the operation of the panel controller, the image memory, and the power supply controller. In one embodiment of the present invention, in the case where one image is continuously displayed on the pixel portion, the driver circuit stops by stopping supply of power supply voltage to the driver circuit, and writing of an image signal to the pixel portion is stopped. After the driver circuit stops, supply of power supply voltage to the panel controller and the image memory is stopped, and supply of power supply voltage to the CPU is stopped.

In one embodiment of the present invention, an insulated gate field-effect transistor (hereinafter simply referred to as a transistor) whose off-state current is extremely low is provided in a pixel in order to continuously display an image on the pixel portion after writing of an image signal to the pixel portion is stopped. With the use of the transistor as an element for controlling supply of current or voltage to a display element included in the pixel, a period during which voltage or current is continuously supplied to the display element can be lengthened. Thus, for example, in the case where image signals having the same image data are repeatedly written to the pixel portion for some consecutive frame periods, as in a still image, an image can be continuously displayed even when drive frequency is lowered by temporarily stopping writing of an image signal to the pixel portion, that is, the writing number of an image signal for a certain period is reduced.

The transistor includes a semiconductor whose bandgap is wider than that of a silicon semiconductor in a channel formation region. With a channel formation region including a semiconductor having the above characteristics, a transistor whose off-state current is extremely low can be obtained. Such a semiconductor can be, for example, an oxide semiconductor whose bandgap is approximately 2 or more times that of silicon. With the use of a transistor having the above structure as a switching element for holding voltage applied to a display element, leakage of an electric charge from the display element can be prevented.

Note that in a volatile storage device used as a register, a cache memory, or the like in the CPU, when supply of power supply voltage to the CPU is stopped, data retained is lost. Thus, before the supply of power supply voltage to the CPU is stopped, it is necessary to back up data retained in a storage device such as a register or a cache memory to a nonvolatile external storage device such as a flash memory. However, it takes time to recover the data from the external storage device to the storage device in the CPU. Thus, in a short period during which a still image is displayed, it is difficult to back up data to an external storage device such as a hard disk or a flash memory in order to stop supply of power supply voltage for the purpose of reducing power consumption.

Thus, in one embodiment of the present invention, a storage device having the following structure is provided in the CPU. The storage device includes a first memory circuit and a second memory circuit for storing data in the first memory circuit. The second memory circuit includes a storage for storing data by accumulation of an electric charge, and a transistor for holding the electric charge accumulated in the storage. The storage includes a capacitor or a transistor, and the electric charge is accumulated in the capacitor or gate capacitance of the transistor. Further, in one embodiment of the present invention, as the transistor for holding an electric charge, the above transistor whose off-state current is extremely low is used. Note that the first memory circuit can be formed using a logic element that inverts the polarity of a signal input and outputs the signal, such as an inverter or a clocked inverter.

In the CPU, a variety of data retained in the first memory circuit is backed up to the second memory circuit before supply of power supply voltage to the CPU is stopped. Specifically, the data is backed up by holding an electric charge in the storage. The electric charge is held by turning off the transistor whose off-state current is low. After the supply of power supply voltage to the CPU is restarted, the backup data is recovered to the first memory circuit. With the above structure, the data in the storage device can be prevented from being lost even when the supply of power supply voltage is stopped. Thus, before the supply of power supply voltage to the CPU is stopped, it is not necessary to back up data to an external memory circuit. Accordingly, in the CPU, supply of power supply voltage can be stopped even on the millisecond time scale. Consequently, the semiconductor display device can consume less power.

In one embodiment of the present invention, with the above structure, a low-power semiconductor display device can be obtained.

BRIEF DESCRIPTION OF DRAWINGS

In the accompanying drawings:

FIG. 1 is a block diagram illustrating the structure of a semiconductor display device;

FIGS. 2A and 2B illustrate the operation of the semiconductor display device;

FIGS. 3A and 3B illustrate the operation of the semiconductor display device;

FIGS. 4A to 4C illustrate time changes in power;

FIG. 5A illustrates the structure of a pixel portion, andFIG. 5B is a circuit diagram of a pixel;

FIG. 6 is a timing chart illustrating the operation of the semiconductor display device;

FIGS. 7A to 7C each illustrate the structure of a memory cell;

FIG. 8 is a circuit diagram of a memory element;

FIG. 9 is a timing chart illustrating the operation of a memory element;

FIGS. 10A and 10B each illustrate the structure of a storage device;

FIGS. 11A and 11B each illustrate the structure of a shift register;

FIGS. 12A and 12B are timing charts each illustrating the operation of a shift register;

FIG. 13 is a block diagram illustrating the structure of a CPU;

FIGS. 14A and 14B are a top view and a cross-sectional view of a pixel;

FIGS. 15A to 15E illustrate electronic devices; and

FIG. 16 is a circuit diagram of a memory element.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described in detail below with reference to the drawings. Note that the present invention is not limited to the following description. It will be readily appreciated by those skilled in the art that modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. The present invention therefore should not be construed as being limited to the following description of the embodiments.

Note that the category of semiconductor display devices of the present invention includes liquid crystal display devices, light-emitting devices in which a light-emitting element typified by an organic light-emitting element (OLED) is provided for each pixel, electronic paper, digital micromirror devices (DMDs), plasma display panels (PDPs), field emission displays (FEDs), and other semiconductor display devices in which transistors are included in pixel portions.

Embodiment 1

FIG. 1 illustrates a block diagram of a semiconductor display device according to one embodiment of the present invention. Note that in this specification, in a block diagram, circuits are classified by their functions and independent blocks are illustrated. However, it is difficult to classify actual circuits by their functions completely and, in some cases, one circuit has a plurality of functions.

As illustrated inFIG. 1, asemiconductor display device100 according to one embodiment of the present invention includes aCPU101, apower supply controller102, apanel controller103, animage memory104, and apanel105. Further, thepanel105 includes apixel portion106 having a display element in each pixel and adriver circuit107 for controlling the operation of thepixel portion106. Thedriver circuit107 includes a signalline driver circuit108, a scanline driver circuit109, and the like.

TheCPU101 has a function of collectively controlling the operation of thepower supply controller102, thepanel controller103, and theimage memory104. Further, theCPU101 includes astorage device110 functioning as a buffer storage device such as a register or a cache memory. Thestorage device110 stores frequently used data or a frequently used program that is needed for theCPU101 to operate.

Thepower supply controller102 has a function of determining whether to supply power supply voltage and drive signals to theCPU101, thepanel controller103, and theimage memory104 in response to an instruction from theCPU101.

Image data is stored in theimage memory104. A volatile or nonvolatile storage device can be used as theimage memory104. For example, a volatile storage device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM) can be used as theimage memory104. Note that in the case where the storage device used as theimage memory104 is nonvolatile, the image data is retained even when supply of power supply voltage is stopped. Thus, in the case where images to be displayed are the same before the stop of supply of power supply voltage and after the restart of supply of power supply voltage, it is not necessary to read image data again after the restart of the supply of power supply voltage. Accordingly, power consumption can be reduced.

For example, as the nonvolatile storage device, it is possible to use a storage device that has a transistor functioning as a switching element in each memory cell. The transistor has a semiconductor whose bandgap is wider than that of silicon and whose intrinsic carrier density is lower than that of silicon in a channel formation region. The storage device has higher speed of image data writing and image data reading than a general nonvolatile storage device such as a flash memory; thus, the storage device is suited for theimage memory104 that needs to operate at high speed.

Thepanel controller103 reads image data from theimage memory104 in response to an instruction from theCPU101 and generates an image signal containing the image data. Further, thepanel controller103 generates a drive signal that is synchronized with an image signal in response to an instruction from theCPU101. Thepanel controller103 has a function of supplying an image signal and a drive signal to thepanel105. Further, thepanel controller103 has a function of determining whether to supply power supply voltage from thepower supply controller102 to thedriver circuit107 in response to an instruction from theCPU101.

An image signal from thepanel controller103 is supplied to the signalline driver circuit108. In addition, drive signals from thepanel controller103 are supplied to the signalline driver circuit108 and the scanline driver circuit109.

Note that theCPU101 may have a function of performing image processing on image data stored in theimage memory104.

Although the drive signal is a signal for controlling the operation of a variety of circuits by a pulse, the kind of drive signal needed for the operation varies depending on the structure of the circuit. Examples of a drive signal of thedriver circuit107 include a signal line driver circuit start pulse signal (SSP) and a signal line driver circuit clock signal (SCK) that control the operation of the signalline driver circuit108 and a scan line driver circuit start pulse signal (GSP) and a scan line driver circuit clock signal (GCK) that control the operation of the scanline driver circuit109. The signalline driver circuit108 and the scanline driver circuit109 operate by supply of power supply voltage and drive signals from thepanel controller103.

Examples of drive signals of theCPU101 and thepanel controller103 include a clock signal CK. TheCPU101 and thepanel controller103 operate by supply of power supply voltage and drive signals from thepower supply controller102.

Next, an operation example of thesemiconductor display device100 according to one embodiment of the present invention is described taking the semiconductor display device inFIG. 1 as an example.

Thesemiconductor display device100 can employ a driving method by which theCPU101, thepanel controller103, theimage memory104, and thedriver circuit107 continuously operate (hereinafter this driving method is referred to as a first driving method) and a driving method by which theCPU101, thepanel controller103, theimage memory104, and thedriver circuit107 intermittently operate by provision of a period during which theCPU101, thepanel controller103, theimage memory104, and thedriver circuit107 stop (hereinafter this driving method is referred to as a second driving method). In the first driving method, theCPU101, thepanel controller103, theimage memory104, and thedriver circuit107 operate after an image signal is written to thepixel portion106 before another image signal is written to thepixel portion106. Thus, as illustrated inFIG. 2A, in the first driving method, power supply voltage is continuously supplied to theCPU101, thepanel controller103, and theimage memory104 from thepower supply controller102.

In addition, in the case where an image to be displayed on thepixel portion106 is a still image, for example, thesemiconductor display device100 can employ the second driving method. In the second driving method, the drive frequency of the signalline driver circuit108 and the scanline driver circuit109 can be lowered as compared to the first driving method. Specifically, in the second driving method, theCPU101 instructs thepanel controller103 to stop supply of power supply voltage and a drive signal to thedriver circuit107.

As illustrated inFIG. 2B, when thepanel controller103 stops supplying power supply voltage and a drive signal to thedriver circuit107 in response to the instruction, thedriver circuit107 stops. Note that the supply of a drive signal to thedriver circuit107 and the supply of power supply voltage to thedriver circuit107 may be stopped at the same time or may be stopped sequentially. In the case where the supply of power supply voltage to thedriver circuit107 is stopped after the supply of a drive signal to thedriver circuit107 is stopped, thedriver circuit107 can stop without malfunctioning.

Then, after thedriver circuit107 stops, theCPU101 instructs thepower supply controller102 to stop supply of power supply voltage and drive signals to thepanel controller103 and theimage memory104. As illustrated inFIG. 3A, when thepower supply controller102 stops supplying power supply voltage and drive signals to thepanel controller103 and theimage memory104 in response to the instruction, thepanel controller103 and theimage memory104 stop.

Note that the supply of drive signals to thepanel controller103 and theimage memory104 and the supply of power supply voltage to thepanel controller103 and theimage memory104 may be stopped at the same time or may be stopped sequentially. As in thedriver circuit107, in the case where the supply of power supply voltage to thepanel controller103 and theimage memory104 is stopped after the supply of drive signals to thepanel controller103 and theimage memory104 is stopped, thepanel controller103 and theimage memory104 can stop without malfunctioning.

After thepanel controller103 andimage memory104 stop, theCPU101 instructs thepower supply controller102 to stop supply of power supply voltage and a drive signal to theCPU101. As illustrated inFIG. 3B, when thepower supply controller102 stops supplying power supply voltage and a drive signal to theCPU101 in response to the instruction, theCPU101 stops.

Note that the supply of a drive signal to theCPU101 and the supply of power supply voltage to theCPU101 may be stopped at the same time or may be stopped sequentially. As in thedriver circuit107, thepanel controller103, and theimage memory104, in the case where the supply of power supply voltage to theCPU101 is stopped after the supply of a drive signal to theCPU101 is stopped, theCPU101 can stop without malfunctioning.

With the series of operation, the supply of power supply voltage or drive signals to theCPU101, thepanel controller103, theimage memory104, and thedriver circuit107 is stopped. The supply of power supply voltage or drive signals is stopped until writing of another image signal to thepixel portion106 is started.

In the case where writing of an image signal to thepixel portion106 is restarted, a writing instruction of an image signal is input from an input device or the like to theCPU101 and thepower supply controller102. Thepower supply controller102 restarts supply of power supply voltage and drive signals to theCPU101, thepanel controller103, and theimage memory104 in response to the writing instruction of an image signal.

Specifically, first, thepower supply controller102 restarts supply of power supply voltage and a drive signal to theCPU101 in response to the writing instruction of an image signal. TheCPU101 operates again by the restart of the supply of power supply voltage. The supply of a drive signal to theCPU101 and the supply of power supply voltage to theCPU101 may be restarted at the same time or may be restarted sequentially. Note that in the case where the supply of a drive signal to theCPU101 is restarted after the supply of power supply voltage to theCPU101 is restarted, theCPU101 can operate without malfunctioning.

Then, theCPU101 instructs thepower supply controller102 to supply power supply voltage and drive signals to thepanel controller103 and theimage memory104. Thepower supply controller102 restarts supply of power supply voltage and drive signals to thepanel controller103 and theimage memory104 in response to the instruction. Thepanel controller103 and theimage memory104 operate again by the restart of the supply of power supply voltage and drive signals.

Note that the supply of drive signals to thepanel controller103 and theimage memory104 and the supply of power supply voltage to thepanel controller103 and theimage memory104 may be restarted at the same time or may be restarted sequentially. In the case where the supply of drive signals to thepanel controller103 and theimage memory104 is restarted after the supply of power supply voltage to thepanel controller103 and theimage memory104 is restarted, thepanel controller103 and theimage memory104 can operate without malfunctioning.

Then, theCPU101 instructs thepanel controller103 to supply power supply voltage and a drive signal to thedriver circuit107. Thepanel controller103 restarts supply of power supply voltage and a drive signal to thedriver circuit107 in response to the instruction, so that thedriver circuit107 operates again. The supply of a drive signal to thedriver circuit107 and the supply of power supply voltage to thedriver circuit107 may be restarted at the same time or may be restarted sequentially. Note that as in theCPU101, thepanel controller103, and theimage memory104, in the case where the supply of a drive signal to thedriver circuit107 is restarted after the supply of power supply voltage to thedriver circuit107 is restarted, thedriver circuit107 can operate without malfunctioning.

With the series of operation, the supply of power supply voltage to theCPU101, thepanel controller103, theimage memory104, and thedriver circuit107 is restarted.

Note that in one embodiment of the present invention, the second driving method is applicable not only to the case where a still image is displayed but also to the case where a moving image is displayed by regular rewriting of an image signal.

In one embodiment of the present invention, by repeating the stop and restart of supply of power supply voltage as described above, thesemiconductor display device100 can consume less power as compared to the case where power supply voltage is continuously supplied to theCPU101, thepanel controller103, theimage memory104, and thedriver circuit107.

FIG. 4A schematically illustrates time changes in consumedpower120 in thedriver circuit107, consumedpower121 in thepanel controller103 and theimage memory104, and consumedpower122 in theCPU101.FIG. 4A illustrates the case where power supply voltage is continuously supplied to theCPU101, thepanel controller103, theimage memory104, and thedriver circuit107.

In the case ofFIG. 4A, thesemiconductor display device100 continuously consumes the predetermined consumedpower120 to122.

FIG. 4B schematically illustrates time changes in the consumedpower120 in thedriver circuit107, the consumedpower121 in thepanel controller103 and theimage memory104, and the consumedpower122 in theCPU101.FIG. 4B illustrates the case where power supply voltage is intermittently supplied to theCPU101, thepanel controller103, theimage memory104, and thedriver circuit107.

As described above, in one embodiment of the present invention, supply of power supply voltage is stopped sequentially from thedriver circuit107, thepanel controller103 and theimage memory104, and theCPU101. In addition, in one embodiment of the present invention, the supply of power supply voltage is restarted sequentially from theCPU101, thepanel controller103 and theimage memory104, and thedriver circuit107. Thus, in one embodiment of the present invention, as illustrated inFIG. 4B, the predetermined consumedpower120 is intermittently consumed. In a period during which the predetermined consumedpower120 is consumed, an image signal is written. In one embodiment of the present invention, as illustrated inFIG. 4B, the predetermined consumedpower121 is intermittently consumed. The period during which the predetermined consumedpower120 is consumed is included in a period during which the predetermined consumedpower121 is consumed. In one embodiment of the present invention, as illustrated inFIG. 4B, the predetermined consumedpower122 is intermittently consumed. The period during which the predetermined consumedpower121 is consumed and the period during which the predetermined consumedpower120 is consumed are included in a period during which the predetermined consumedpower122 is consumed.

In the case ofFIG. 4B, the consumedpower120, the consumedpower121, and the consumedpower122 are intermittently consumed; thus, the total power consumption of thesemiconductor display device100 can be made lower as compared to the case ofFIG. 4A.

Note that in one embodiment of the present invention, in the case where an external device requires thesemiconductor display device100 to notify the operating state of thesemiconductor display device100, for example, only theCPU101 might operate even in a period during which an image signal in not written. In that case, the supply of power supply voltage to theCPU101 is restarted in response to an instruction from the input device or the like; however, the supply of power supply voltage to thepanel controller103 and theimage memory104 and the supply of power supply voltage to thedriver circuit107 may be continuously stopped.

FIG. 4C schematically illustrates time changes in the consumedpower120 in thedriver circuit107, the consumedpower121 in thepanel controller103 and theimage memory104, and the consumedpower122 in theCPU101.FIG. 4C illustrates the case where power supply voltage is intermittently supplied to theCPU101, thepanel controller103, theimage memory104, and thedriver circuit107, which is different from the case inFIG. 4B.

InFIG. 4C, power supply voltage is supplied to theCPU101 during a period t1. In addition, inFIG. 4C, supply of power supply voltage to thepanel controller103 and theimage memory104 and supply of power supply voltage to thedriver circuit107 are stopped during the period t1. Thus, during the period t1, the predetermined consumedpower122 is consumed. Also in the case ofFIG. 4C, the consumedpower120, the consumedpower121, and the consumedpower122 are intermittently consumed; thus, the total power consumption of thesemiconductor display device100 can be made lower as compared to the case ofFIG. 4A.

Next, a specific structure of thepixel portion106 is described taking the case where thesemiconductor display device100 is a liquid crystal display device as an example.

FIG. 5A illustrates a structure example of thepixel portion106. InFIG. 5A, y scan lines GL (GL1 to GLy) whose potentials are controlled by the scan line driver circuit and x signal lines SL (SL1 to SLx) whose potentials are controlled by the signal line driver circuit are provided in thepixel portion106.

Each scan line GL is connected to a plurality ofpixels130. Specifically, each scan line GL is connected tox pixels130 arranged in a given row among the plurality ofpixels130 arranged in matrix.

Each signal line SL is connected toy pixels130 arranged in a given column among the plurality ofpixels130 arranged in x columns and y rows in thepixel portion106.

Note that in this specification, the term “connection” means electrical connection and corresponds to a state where current, voltage, or a potential can be supplied or transmitted. Accordingly, a connection state does not always mean a direct connection state but includes an indirect connection state through a circuit element such as a wiring, a resistor, a diode, or a transistor so that current, voltage, or a potential can be supplied or transmitted.

Note that even when independent components are connected to each other in a circuit diagram, there is the case where one conductive film has functions of a plurality of components, such as the case where part of a wiring functions as an electrode. The term “connection” in this specification also means such a case where one conductive film has functions of a plurality of components.

FIG. 5B is an example of a circuit diagram of thepixel130. Thepixel130 inFIG. 5B includes atransistor131 functioning as a switching element, aliquid crystal element132 whose transmittance is controlled in response to the potential of an image signal supplied through thetransistor131, and acapacitor133.

Theliquid crystal element132 includes a pixel electrode, a common electrode, and a liquid crystal layer having a liquid crystal to which voltage across the pixel electrode and the common electrode is applied. Thecapacitor133 has a function of holding voltage across the pixel electrode and the common electrode of theliquid crystal element132.

The liquid crystal layer can be formed using, for example, a liquid crystal material classified into a thermotropic liquid crystal or a lyotropic liquid crystal. Alternatively, the liquid crystal layer can be formed using, for example, a liquid crystal material classified into a nematic liquid crystal, a smectic liquid crystal, a cholesteric liquid crystal, or a discotic liquid crystal. Alternatively, the liquid crystal layer can be formed using, for example, a liquid crystal material classified into a ferroelectric liquid crystal or an anti-ferroelectric liquid crystal. Alternatively, the liquid crystal layer can be formed using, for example, a liquid crystal material classified into a high-molecular liquid crystal such as a main-chain high-molecular liquid crystal, a side-chain high-molecular liquid crystal, or a composite-type high-molecular liquid crystal, or a low-molecular liquid crystal. Alternatively, the liquid crystal layer can be formed using, for example, a liquid crystal material classified into a polymer dispersed liquid crystal (PDLC).

Alternatively, a liquid crystal exhibiting a blue phase for which an alignment film is not used may be used for the liquid crystal layer. A blue phase is one of liquid crystal phases that is generated just before a cholesteric phase changes into an isotropic phase while the temperature of a cholesteric liquid crystal is increased. Since the blue phase is only generated within a narrow range of temperature, a chiral material or an ultraviolet curable resin is added so that the temperature range is improved. A liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral material is preferable because it has a short response time of 1 ms or less, and is optically isotropic, which makes the alignment process unneeded and viewing angle dependence small.

The following can be used as a method for driving the liquid crystal: a twisted nematic (TN) mode, a super twisted nematic (STN) mode, a vertical alignment (VA) mode, a multi-domain vertical alignment (MVA) mode, an in-plane-switching (IPS) mode, an optically compensated birefringence (OCB) mode, a fringe field switching (FFS) mode, a blue phase mode, a transverse bend alignment (TBA) mode, a VA-IPS mode, an electrically controlled birefringence (ECB) mode, a ferroelectric liquid crystal (FLC) mode, an anti-ferroelectric liquid crystal (AFLC) mode, a polymer dispersed liquid crystal (PDLC) mode, a polymer network liquid crystal (PNLC) mode, a guest-host mode, and the like.

Thepixel130 may further include another circuit element such as a transistor, a diode, a resistor, a capacitor, or an inductor as needed.

Specifically, inFIG. 5B, a gate electrode of thetransistor131 is connected to the scan line GL. One of a source terminal and a drain terminal of thetransistor131 is connected to the signal line SL. The other of the source terminal and the drain terminal of thetransistor131 is connected to the pixel electrode of theliquid crystal element132. One electrode of thecapacitor133 is connected to the pixel electrode of theliquid crystal element132. The other electrode of thecapacitor133 is connected to a node to which a specific potential is applied. Note that a specific potential is applied to the common electrode of theliquid crystal element132. The potential applied to the common electrode may be the same as the potential applied to the other electrode of thecapacitor133.

In theliquid crystal element132, the alignment of liquid crystal molecules is changed in accordance with the level of voltage across the pixel electrode and the common electrode, so that the transmittance is changed. Accordingly, when the transmittance of theliquid crystal element132 is controlled by the potential of an image signal input to the signal line SL, gradation can be expressed.

Note that a “source terminal” of a transistor means a source region that is part of an active layer or a source electrode that is connected to an active layer. Similarly, a “drain terminal” of a transistor means a drain region that is part of an active layer or a drain electrode that is connected to an active layer.

AlthoughFIG. 5B illustrates the case where onetransistor131 is used as a switching element in thepixel130, the present invention is not limited to this structure. A plurality of transistors functioning as one switching element may be used. In the case where a plurality of transistors function as one switching element, the plurality of transistors may be connected to each other in parallel, in series, or in combination of parallel connection and series connection.

In this specification, a state in which transistors are connected to each other in series means, for example, a state in which only one of a source terminal and a drain terminal of a first transistor is connected to only one of a source terminal and a drain terminal of a second transistor. In addition, a state in which transistors are connected to each other in parallel means a state in which one of a source terminal and a drain terminal of a first transistor is connected to one of a source terminal and a drain terminal of a second transistor and the other of the source terminal and the drain terminal of the first transistor is connected to the other of the source terminal and the drain terminal of the second transistor.

When thetransistor131 includes a wide bandgap semiconductor such as an oxide semiconductor in a channel formation region, thetransistor131 can have extremely low off-state current and high withstand voltage. Further, when thetransistor131 having the above structure is used as a switching element, leakage of an electric charge accumulated in theliquid crystal element132 can be prevented effectively as compared to the case where a transistor including a normal semiconductor such as silicon or germanium is used.

Note that unless otherwise specified, in this specification, off-state current of an n-channel transistor is current that flows between a source terminal and a drain terminal when the potential of the drain terminal is higher than that of the source terminal or that of a gate electrode while the potential of the gate electrode is 0 V or lower in the case of the potential of the source terminal used as a reference. Alternatively, in this specification, off-state current of a p-channel transistor is current that flows between a source terminal and a drain terminal when the potential of the drain terminal is lower than that of the source terminal or that of a gate electrode while the potential of the gate electrode is 0 V or higher in the case of the potential of the source terminal used as a reference.

An oxide semiconductor preferably contains at least indium (In) or zinc (Zn). As a stabilizer for reducing variations in electrical characteristics of a transistor including the oxide semiconductor, the oxide semiconductor preferably contains gallium (Ga) in addition to In and Zn. Tin (Sn) is preferably contained as a stabilizer. Hafnium (Hf) is preferably contained as a stabilizer. Aluminum (Al) is preferably contained as a stabilizer. Zirconium (Zr) is preferably contained as a stabilizer.

As another stabilizer, one or more kinds of lanthanoid such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu) may be contained.

For example, indium oxide, tin oxide, zinc oxide, an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, an In—Ga-based oxide, an In—Ga—Zn-based oxide (also referred to as IGZO), an In—Al—Zn-based oxide, an In—Sn—Zn-based oxide, a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, an In—Hf—Zn-based oxide, an In—La—Zn-based oxide, an In—Pr—Zn-based oxide, an In—Nd—Zn-based oxide, an In—Sm—Zn-based oxide, an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide, an In—Tb—Zn-based oxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-based oxide, an In—Er—Zn-based oxide, an In—Tm—Zn-based oxide, an In—Yb—Zn-based oxide, an In—Lu—Zn-based oxide, an In—Sn—Ga—Zn-based oxide, an In—Hf—Ga—Zn-based oxide, an In—Al—Ga—Zn-based oxide, an In—Sn—Al—Zn-based oxide, an In—Sn—Hf—Zn-based oxide, or an In—Hf—Al—Zn-based oxide can be used as an oxide semiconductor.

Note that, for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn, and there is no limitation on the ratio of In, Ga, and Zn. In addition, the In—Ga—Zn-based oxide may contain a metal element other than In, Ga, and Zn. The In—Ga—Zn-based oxide has sufficiently high resistance when no electric field is applied thereto, so that off-state current can be sufficiently reduced. Further, the In—Ga—Zn-based oxide has high mobility.

For example, an In—Ga—Zn-based oxide with an atomic ratio of In:Ga:Zn=1:1:1 (=1/3:1/3:1/3) or In:Ga:Zn=2:2:1 (=2/5:2/5:1/5), or an oxide whose composition is in the neighborhood of the above composition can be used. Alternatively, an In—Sn—Zn-based oxide with an atomic ratio of In:Sn:Zn=1:1:1 (=1/3:1/3:1/3), In:Sn:Zn=2:1:3 (=1/3:1/6:1/2), or In:Sn:Zn=2:1:5 (=1/4:1/8:5/8), or an oxide whose composition is in the neighborhood of the above composition is preferably used.

For example, with an In—Sn—Zn-based oxide, high mobility can be comparatively easily obtained. However, even with an In—Ga—Zn-based oxide, mobility can be increased by lowering defect density in a bulk.

Note that a highly-purified oxide semiconductor (a purified oxide semiconductor) obtained by reduction of impurities such as moisture or hydrogen that serve as electron donors (donors) and reduction of oxygen vacancies is an intrinsic (i-type) semiconductor or a substantially intrinsic semiconductor. Thus, a transistor including the oxide semiconductor has extremely low off-state current. Further, the band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. With the use of an oxide semiconductor film that is highly purified by a sufficient decrease in concentration of impurities such as moisture or hydrogen and reduction of oxygen vacancies, the off-state current of the transistor can be decreased.

Specifically, various experiments can prove low off-state current of a transistor including a highly-purified oxide semiconductor for a semiconductor film. For example, even when an element has a channel width of 1×10⁶μm and a channel length of 10 μm, off-state current can be lower than or equal to the measurement limit of a semiconductor parameter analyzer, i.e., lower than or equal to 1×10⁻¹³A, at a voltage (drain voltage) between a source terminal and a drain terminal of 1 to 10 V. In that case, it can be seen that off-state current standardized on the channel width of the transistor is lower than or equal to 100 zA/μm. In addition, a capacitor and a transistor were connected to each other and off-state current was measured using a circuit in which electrical charge flowing to or from the capacitor is controlled by the transistor. In the measurement, a highly-purified oxide semiconductor film was used for a channel formation region of the transistor, and the off-state current of the transistor was measured from a change in the amount of electrical charge of the capacitor per unit hour. As a result, it can be seen that, in the case where the voltage between the source terminal and the drain terminal of the transistor is 3 V, a lower off-state current of several tens of yoctoamperes per micrometer (yA/μm) is obtained. Accordingly, the transistor including the highly-purified oxide semiconductor film for a channel formation region has much lower off-state current than a crystalline silicon transistor.

In one embodiment of the present invention, by using thetransistor131 whose off-state current is extremely low, a period during which voltage applied to theliquid crystal element132 is held can be lengthened. Thus, for example, in the case where image signals having the same image data are written to thepixel portion106 for some consecutive frame periods, as in a still image, an image can be continuously displayed even when drive frequency is lowered, that is, the writing number of an image signal for a certain period is reduced. For example, by using thetransistor131 including a highly purified oxide semiconductor in the channel formation region, the write cycle of an image signal can be 10 seconds or longer, preferably 30 seconds or longer, more preferably 1 minute or longer. As the write cycle of an image signal is made longer, power consumption can be further reduced.

In addition, since the potential of an image signal can be held for a longer period, the quality of an image to be displayed can be prevented from being lowered even when thecapacitor133 for holding the potential of the image signal is not connected to theliquid crystal element132. Thus, it is possible to increase the aperture ratio by omitting thecapacitor133 or reducing the size of thecapacitor133, which leads to a reduction in power consumption of thesemiconductor display device100.

By inversion driving by which the polarity of the potential of an image signal is inverted using the potential of a common electrode as a reference, degradation of a liquid crystal material called burn—in can be prevented. However, in the inversion driving, a change in potential applied to the signal line SL is increased at the time of the change in the polarity of the image signal; thus, a potential difference between the source terminal and the drain terminal of thetransistor131 functioning as a switching element is increased. Accordingly, thetransistor131 easily causes degradation in characteristics, such as a shift in threshold voltage. Further, in order to maintain the voltage held in theliquid crystal element132, the off-state current needs to be low even when the potential difference between the source terminal and the drain terminal is large. When a semiconductor having a wider bandgap and lower intrinsic carrier density is wider than silicon or germanium, such as an oxide semiconductor, is used for thetransistor131, the withstand voltage of thetransistor131 can be increased and the off-state current can be made extremely low. Thus, as compared to the case where a transistor including a normal semiconductor such as silicon or germanium is used, degradation of thetransistor131 can be prevented and the voltage held in theliquid crystal element132 can be maintained.

An oxide semiconductor film can be single crystal, polycrystalline (also referred to as polycrystal), or amorphous, for example. The oxide semiconductor film is preferably a c-axis aligned crystalline oxide semiconductor (CAAC-OS) film.

The CAAC-OS film is not completely single crystal nor completely amorphous. The CAAC-OS film is an oxide semiconductor film with a crystal-amorphous mixed phase structure where crystal parts and amorphous parts are included in an amorphous phase. Note that in most cases, the crystal part fits into a cube whose one side is less than 100 nm. From an observation image obtained with a transmission electron microscope (TEM), a boundary between the amorphous part and the crystal part in the CAAC-OS film is not clear. Further, with the TEM, a grain boundary in the CAAC-OS film is not found. Thus, in the CAAC-OS film, a reduction in electron mobility, due to the grain boundary, is suppressed.

In each of the crystal parts included in the CAAC-OS film, a c-axis is aligned in a direction parallel to a normal vector of a surface where the CAAC-OS film is formed or a normal vector of a surface of the CAAC-OS film, triangular or hexagonal atomic order which is seen from the direction perpendicular to the a-b plane is formed, and metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis. Note that, among crystal parts, the directions of the a-axis and the b-axis of one crystal part may be different from those of another crystal part. In this specification, a simple term “perpendicular” includes a range from 85 to 95°. In addition, a simple term “parallel” includes a range from −5 to 5°.

In the CAAC-OS film, distribution of crystal parts is not necessarily uniform. For example, in the formation process of the CAAC-OS film, in the case where crystal growth occurs from a surface side of the oxide semiconductor film, the proportion of crystal parts in the vicinity of the surface of the CAAC-OS film is higher than that in the vicinity of the surface where the CAAC-OS film is formed in some cases. Further, when an impurity is added to the CAAC-OS film, the crystal part in a region to which the impurity is added becomes amorphous in some cases.

Since the c-axes of the crystal parts in the CAAC-OS film are aligned in the direction parallel to the normal vector of the surface where the CAAC-OS film is formed or the normal vector of the surface of the CAAC-OS film, the directions of the c-axes may be different from each other depending on the shape of the CAAC-OS film (the cross-sectional shape of the surface where the CAAC-OS film is formed or the cross-sectional shape of the surface of the CAAC-OS film). Note that when the CAAC-OS film is formed, the c-axis direction of the crystal part is the direction parallel to the normal vector of the surface where the CAAC-OS film is formed or the normal vector of the surface of the CAAC-OS film. The crystal part is formed by deposition or by performing treatment for crystallization such as heat treatment after deposition.

In a transistor including a CAAC-OS film, a change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. Thus, the transistor has high reliability.

For example, a CAAC-OS film is deposited by sputtering with a polycrystalline oxide semiconductor sputtering target. When ions collide with the sputtering target, a crystal region included in the sputtering target may be separated from the target along the a-b plane, and a sputtered particle having a plane parallel to the a-b plane (a flat-plate-like sputtered particle or a pellet-like sputtered particle) might be separated from the sputtering target. In that case, the flat-plate-like sputtered particle reaches a substrate while maintaining its crystal state, so that the CAAC-OS film can be deposited.

For the deposition of the CAAC-OS film, the following conditions are preferably employed.

By reducing the amount of impurities entering the CAAC-OS film during the deposition, the crystal state can be prevented from being broken by the impurities. For example, the concentration of impurities (e.g., hydrogen, water, carbon dioxide, or nitrogen) which exist in a deposition chamber may be reduced. Further, the concentration of impurities in a deposition gas may be reduced. Specifically, a deposition gas whose dew point is −80° C. or lower, preferably −100° C. or lower is used.

By increasing the substrate heating temperature during the deposition, migration of a sputtered particle occurs after the sputtered particle reaches the substrate. Specifically, the substrate heating temperature during the deposition is 100° C. or higher and 740° C. or lower, preferably 200° C. or higher and 500° C. or lower. By increasing the substrate heating temperature during the deposition, when the flat-plate-like sputtered particle reaches the substrate, migration occurs on the substrate, so that a flat plane of the sputtered particle is attached to the substrate.

Further, it is preferable to reduce plasma damage during the deposition by increasing the proportion of oxygen in the deposition gas and optimizing power. The proportion of oxygen in the deposition gas is 30 vol % or higher, preferably 100 vol %.

As an example of the sputtering target, an In—Ga—Zn-based oxide target is described below.

A polycrystalline In—Ga—Zn-based oxide target is made by mixing InO_Xpowder, GaO_Ypowder, and ZnO_Zpowder in a predetermined mole ratio, applying pressure, and performing heat treatment at 1000° C. or higher and 1500° C. or lower. Note that X, Y, and Z are each a given positive number. Here, the predetermined mole ratio of the InO_Xpowder, the GaO_Ypowder, and the ZnO_Zpowder is, for example, 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or 3:1:2. The kinds of powder and the mole ratio for mixing powder may be changed as appropriate depending on a sputtering target to be formed.

Next, operation examples of thepixel portion106 and thedriver circuit107 are described with reference toFIG. 6.FIG. 6 schematically illustrates time changes in operating states of thepixel portion106 and thedriver circuit107.

In the second driving method, a period A during which an image signal is written to thepixel portion106 and a period B during which a display element (e.g., the liquid crystal element132) continuously expresses gradation by the image signal appear alternately.FIG. 6 illustrates the case where four periods A (periods A1 to A4) and four periods B (periods B1 to B4) appear alternately. Specifically, inFIG. 6, the periods appear in the following order: the period A1, the period B1, the period A2, the period B2, the period A3, the period B3, the period A4, and the period B4.

In the period A, a drive signal and power supply voltage are supplied to thedriver circuit107, so that driver circuits (e.g., the signalline driver circuit108 and the scan line driver circuit109) operate. InFIG. 6, a state in which thedriver circuit107 operates is denoted by SST.

When the scanline driver circuit109 operates, thepixels130 that are connected to the scan lines GL of thepixel portion106 are sequentially selected by the scanline driver circuit109. Specifically, in the case of thepixels130 inFIG. 5B, thetransistors131 that are connected to the scan lines GL are turned on. When the signalline driver circuit108 operates, an image signal is input from the signalline driver circuit108 to thepixel130 selected by the scanline driver circuit109. Specifically, in the case of thepixel130 inFIG. 5B, the potential of an image signal is applied to the pixel electrode of theliquid crystal element132 through thetransistor131 that is on.

The input of an image signal to thepixel portion106 is similarly performed on theother pixels130. A display state is set in all thepixels130, and an image based on the image data of the image signal is displayed on theentire pixel portion106. A state in which the image signal is written topixel portion106 and a display state is set is denoted by W inFIG. 6.

Next, in the period B, the supply of a drive signal and power supply voltage to thedriver circuit107 is stopped, so that the driver circuits (e.g., the signalline driver circuit108 and the scan line driver circuit109) stop. InFIG. 6, a state in which thedriver circuit107 stops operation is denoted by SSTP. When the signalline driver circuit108 stops, the input of an image signal to thepixel portion106 is stopped.

In addition, when the scanline driver circuit109 stops, the selection of thepixel portion106 by the scanline driver circuit109 is stopped. Thus, the display element included in thepixel portion106 holds a display state set in the previous period A. A state in which gradation is continuously expressed by the display element is denoted by H inFIG. 6.

Specifically, inFIG. 6, a display state set in the period A1 is held in the period B1. A display state set in the period A2 is held in the period B2. A display state set in the period A3 is held in the period B3. A display state set in the period A4 is held in the period B4.

In one embodiment of the present invention, as described above, thetransistor131 whose off-state current is extremely low is used; thus, the display state in each period B can be held for 10 seconds or longer, preferably 30 seconds or longer, more preferably 1 minute or longer.

In one embodiment of the present invention, the length of the period B can be changed as appropriate in response to a rewriting instruction of an image from the input device or the like. For example,FIG. 6 illustrates the case where timing of the end of the period B2 is set by a rewriting instruction of an image. InFIG. 6, the period B2 is forcibly ended by the rewriting instruction of an image, and then, the period A3 is started. Accordingly, in the case ofFIG. 6, the period B2 is shorter than the period B that is automatically ended regardless of the rewriting instruction of an image, for example, the period B1 or the period B3.

Note that there is a limitation on a period during which the display element can maintain a display state. Accordingly, in consideration of the period during which the display element can maintain a display state, the maximum length of the period B in a period during which a rewriting instruction of an image is not input is set in advance. In other words, in the case where a period during which a still image is displayed is longer than the maximum length of the period B, the period B is automatically ended even when there is no input of a rewriting instruction of an image. Then, the same image signal is rewritten to thepixel portion106 in the next period A, and the image held in the previous period B is displayed again on thepixel portion106.

In one embodiment of the present invention, in the second driving method, the writing number of an image signal to thepixel portion106 can be greatly reduced while the image is continuously displayed. Accordingly, the drive frequency of the driver circuit can be greatly reduced, and thesemiconductor display device100 can consume less power.

Note that as in the second driving method, in the first driving method, an image signal is written to thepixel portion106. Then, the display element expresses gradation in response to the image signal. However, unlike in the second driving method, after image signals are written to theentire pixel portion106 and a display state is set, thedriver circuit107 does not necessarily stop.

Next, drive signals and power supply voltage transmitted from thepanel controller103 to thedriver circuit107 in the second driving method in thesemiconductor display device100 inFIG. 1 are described.

Power supply voltage Vp is supplied from thepower supply controller102 to thepanel controller103. Further, a drive signal such as a clock signal CK is input from thepower supply controller102 to thepanel controller103. Thepanel controller103 has a function of generating a variety of power supply voltages and drive signals with the use of the input clock signal CK and power supply voltage Vp and supplying the power supply voltages and drive signals to the scanline driver circuit109 or the signalline driver circuit108.

Note that among drive signals generated in thepanel controller103, a start signal SP input to the scanline driver circuit109 is a start signal GSP, and a start signal SP input to the signalline driver circuit108 is a start signal SSP. In addition, among the drive signals generated in thepanel controller103, a clock signal CK input to the scanline driver circuit109 is a clock signal GCK, and a clock signal CK input to the signalline driver circuit108 is a clock signal SCK. Further, among power supply voltages generated in thepanel controller103, a power supply voltage Vp input to the scanline driver circuit109 is a power supply voltage GVp, and a power supply voltage Vp input to the signalline driver circuit108 is a power supply voltage SVp.

Note that the start signal GSP is a pulse signal based on vertical synchronous frequency, and the start signal SSP is a pulse signal based on a selection period of one scan line GL.

Further, the clock signal GCK is not limited to one clock signal, and a plurality of clock signals having different phases may be used as the clock signal GCK. When a plurality of clock signals are used as the clock signal GCK, the operation speed of the scanline driver circuit109 can be improved. Further, the clock signal SCK is not limited to one clock signal, and a plurality of clock signals having different phases may be used as the clock signal SCK. When a plurality of clock signals having different phases are used as the clock signal SCK, the operation speed of the signalline driver circuit108 can be improved. Note that a common clock signal CK may be used as the clock signal GCK and the clock signal SCK.

In a frame period during which theCPU101, thepanel controller103, theimage memory104, and thedriver circuit107 continuously operate (hereinafter this frame period is referred to as a first frame period), when the clock signal CK and the power supply voltage Vp are input, thepanel controller103 starts to supply the power supply voltage GVp, the start signal GSP, and the clock signal GCK to the scanline driver circuit109. Specifically, first, thepanel controller103 starts to supply the power supply potential GVp. When the supply of the power supply voltage GVp is stabilized, thepanel controller103 starts to supply the clock signal GCK. Then, thepanel controller103 starts to supply the start signal GSP. Note that the potential of a wiring to which the clock signal GCK is input is preferably stabilized by application of a high potential of the clock signal GCK to the wiring just before thepanel controller103 starts to supply the clock signal GCK. By this method, the scanline driver circuit109 can be prevented from malfunctioning at the time of starting operation.

In the first frame period, when the clock signal CK and the power supply voltage Vp are input, thepanel controller103 starts to supply the power supply voltage SVp, the start signal SSP, and the clock signal SCK to the signalline driver circuit108. Specifically, first, thepanel controller103 starts to supply the power supply potential SVp. When the supply of the power supply voltage SVp is stabilized, thepanel controller103 starts to supply the clock signal SCK. Then, thepanel controller103 starts to supply the start signal SSP. Note that the potential of a wiring to which the clock signal SCK is input is preferably stabilized by application of a high potential of the clock signal SCK to the wiring just before thepanel controller103 starts to supply the clock signal SCK. By this method, the signalline driver circuit108 can be prevented from malfunctioning at the time of starting operation.

When the scanline driver circuit109 starts operation, a scan signal SCN having a pulse is input from the scanline driver circuit109 to the scan line GL, so that thepixels130 in thepixel portion106 are sequentially selected. Then, when the signalline driver circuit108 starts operation, an image signal is input from the signalline driver circuit108 to the selectedpixel130 through the signal line SL. In thepixel130 to which the image signal is input, the display element (e.g., the liquid crystal element132) expresses gradation in response to the image signal.

Next, in a frame period during which theCPU101, thepanel controller103, theimage memory104, and thedriver circuit107 stop (hereinafter this frame period is referred to as a second frame period), thepanel controller103 stops supplying the power supply voltage GVp and the clock signal GCK. Specifically, first, thepanel controller103 stops supplying the clock signal GCK, stops supplying the scan signal SCN in the scanline driver circuit109, and ends the selection operation of all the scan lines GL. After that, thepanel controller103 stops supplying the power supply potential GVp. Note that to stop supplying means, for example, to set a wiring to which a signal or voltage is input in a floating state, or to apply a low potential to a wiring to which a signal or voltage is input. By this method, the scanline driver circuit109 can be prevented from malfunctioning at the time of stopping the operation.

In the second frame period, thepanel controller103 stops supplying the power supply voltage SVp and the clock signal SCK. Specifically, first, thepanel controller103 stops supplying the clock signal SCK, stops supplying the image signal in the signalline driver circuit108, and ends the input operation of all the signal lines SL. After that, thepanel controller103 stops supplying the power supply potential SVp. By this method, the signalline driver circuit108 can be prevented from malfunctioning at the time of stopping the operation.

In the second frame period, the display element included in thepixel130 continuously expresses predetermined gradation in accordance with image data in the image signal written in the first frame period. For example, in the case where theliquid crystal element132 is used as a display element, the pixel electrode of theliquid crystal element132 is set in a floating state; thus, theliquid crystal element132 holds transmittance set in accordance with the data in the image signal written in the first frame period. Thus, in the second frame period, thepixel portion106 holds an image based on the data in the image signal written in the first frame period as a still image for a certain period.

Next, in the first frame period, thepanel controller103 starts to supply the drive signals and the power supply voltages to thedriver circuit107, so that the signalline driver circuit108 and the scanline driver circuit109 start operation.

As described in the above example, in thesemiconductor display device100 according to one aspect of this embodiment, in the second driving method, the supply of drive signals and power supply voltages to thedriver circuit107 can be stopped, and an image can be continuously displayed on thepixel portion106 for a certain period. With the above structure, thesemiconductor display device100 according to one aspect of this embodiment can consume less power.

Note that in this embodiment, input of a variety of drive signals to thepanel controller103 is controlled by thepower supply controller102. However, in one embodiment of the present invention, the input of some or all of the variety of drive signals to thepanel controller103 may be controlled by theCPU101.

Next, the structure of thestorage device110 included in theCPU101 in one embodiment of the present invention is described. In one embodiment of the present invention, thestorage device110 includes a plurality of memory elements.FIG. 8 is an example of a circuit diagram of amemory element200.

Thememory element200 includes afirst memory circuit201, asecond memory circuit202, aswitch203, aswitch204, aswitch205, alogic element206, and acapacitor207. Thefirst memory circuit201 retains data only in a period during which power supply voltage is supplied. Thesecond memory circuit202 includes acapacitor208 and atransistor210 that correspond to a storage, and atransistor209 for controlling supply, holding, and release of an electric charge in the storage.

Note that thememory element200 may further include another circuit element such as a diode, a resistor, or an inductor as needed.

Thetransistor209 includes an oxide semiconductor in a channel formation region.

FIG. 8 illustrates an example in which theswitch203 is atransistor213 having conductivity (e.g., an n-channel transistor) and theswitch204 is a transistor214 having another conductivity (e.g., a p-channel transistor).

A first terminal of theswitch203 corresponds to one of a source terminal and a drain terminal of thetransistor213. A second terminal of theswitch203 corresponds to the other of the source terminal and the drain terminal of thetransistor213. Conduction or non-conduction between the first terminal and the second terminal of the switch203 (i.e., an on state or an off state of the transistor213) is selected by a control signal S2 input to a gate electrode of thetransistor213.

A first terminal of theswitch204 corresponds to one of a source terminal and a drain terminal of the transistor214. A second terminal of theswitch204 corresponds to the other of the source terminal and the drain terminal of the transistor214. Conduction or non-conduction between the first terminal and the second terminal of the switch204 (i.e., an on state or an off state of the transistor214) is selected by the control signal S2 input to a gate electrode of the transistor214.

One of a source terminal and a drain terminal of thetransistor209 is electrically connected to one of a pair of electrodes of thecapacitor208 and a gate electrode of thetransistor210. The gate electrode of thetransistor210 is referred to as a node M2.

One of a source terminal and a drain terminal of thetransistor210 is connected to a wiring to which a potential V1 is applied. The other of the source terminal and the drain terminal of thetransistor210 is connected to the first terminal of theswitch203. The second terminal of theswitch203 is connected to the first terminal of theswitch204. The second terminal of theswitch204 is connected to a wiring to which a potential V2 is applied. The second terminal of theswitch203, the first terminal of theswitch204, an input terminal of thelogic element206, and one of a pair of electrodes of thecapacitor207 are connected to each other. The second terminal of theswitch203 and the first terminal of theswitch204 are referred to as a node M1.

Note that a constant potential can be applied to the other of the pair of electrodes of thecapacitor207. For example, a low power supply potential (e.g., a ground potential) or a high power supply potential can be applied to the other of the pair of electrodes of thecapacitor207. The other of the pair of electrodes of thecapacitor207 may be connected to the wiring to which the potential V1 is applied. A constant potential can be applied to the other of the pair of electrodes of thecapacitor208. For example, a low power supply potential (e.g., a ground potential) or a high power supply potential can be applied to the other of the pair of electrodes of thecapacitor208. The other of the pair of electrodes of thecapacitor208 may be connected to the wiring to which the potential V1 is applied.FIG. 8 illustrates an example in which the other of the pair of electrodes of thecapacitor207 and the other of the pair of electrodes of thecapacitor208 are connected to the wiring to which the potential V1 is applied.

It is possible not to provide thecapacitor207 by positively utilizing parasitic capacitance or the like. It is possible not to provide thecapacitor208 by positively utilizing gate capacitance of thetransistor210 or the like. Note that gate capacitance corresponds to capacitance formed between a gate electrode and an active layer.

A control signal S1 is input to a gate electrode of thetransistor209. In each of theswitch203 and theswitch204, conduction or non-conduction between the first terminal and the second terminal is selected by the control signal S2 that is different from the control signal S1. When the first terminal and the second terminal of one of the switches are in a conduction state, the first terminal and the second terminal of the other of the switches are in a non-conduction state. In theswitch205, conduction or non-conduction between a first terminal and a second terminal is selected by a control signal S3 that is different from the control signal S1 and the control signal S2.

A signal corresponding to data retained in thefirst memory circuit201 is input to the other of the source terminal and the drain terminal of thetransistor209.FIG. 8 illustrates an example in which a signal output from an output terminal OUT of thefirst memory circuit201 is input to the other of the source terminal and the drain terminal of thetransistor209. The polarity of a signal output from the second terminal of theswitch203 is inverted by thelogic element206, and the inversion signal is input to thefirst memory circuit201 through theswitch205 in which the first terminal and the second terminal are set in a conduction state by the control signal S3.

Note thatFIG. 8 illustrates an example in which a signal output from the second terminal of theswitch203 is input to an input terminal (denoted by IN inFIG. 8) of thefirst memory circuit201 through thelogic element206 and theswitch205; however, one embodiment of the present invention is not limited this structure. A signal output from the second terminal of theswitch203 may be input to thefirst memory circuit201 without its polarity being inverted. For example, in the case where thefirst memory circuit201 has a node in which a signal obtained by inversion of the polarity of a signal input from the input terminal is held, a signal output from the second terminal of theswitch203 can be input to the node.

InFIG. 8, voltage corresponding to a difference between the potential V1 and the potential V2 is supplied to thememory element200 as power supply voltage. The voltage corresponding to the difference between the potential V1 and the potential V2 may be supplied to thefirst memory circuit201 as power supply voltage. In a period during which power supply voltage is not supplied to thefirst memory circuit201, the potential V1 and the potential V2 are substantially equal.

Note that theswitch205 can be a transistor. The transistor may be an n-channel transistor or a p-channel transistor. Alternatively, an n-channel transistor and a p-channel transistor may be used in combination. For example, an analog switch can be used as theswitch205.

InFIG. 8, thetransistor209 can have two gate electrodes above and below a semiconductor film including an oxide semiconductor. The control signal S1 can be input to one of the gate electrodes, and a control signal S4 can be input to the other of the gate electrodes. The control signal S4 may be a signal having a constant potential. The constant potential may be the potential V1 or the potential V2. Note that the two gate electrodes provided above and below the semiconductor film may be connected to each other, and the control signal S1 may be input to the gate electrodes. The threshold voltage of thetransistor209 can be controlled by a signal input to the other of the gate electrodes of thetransistor209. The off-state current of thetransistor209 can be reduced by controlling the threshold voltage.

InFIG. 8, among the transistors used in thememory element200, a transistor whose channel formation region includes a semiconductor other than an oxide semiconductor may be used as any of the transistors except thetransistor209. For example, any of the transistors except thetransistor209 may be a transistor whose channel formation region is formed in a semiconductor film including silicon or a silicon substrate.

Thefirst memory circuit201 inFIG. 8 includes a first logic element and a second logic element. An input terminal of the first logic element is connected to an output terminal of the second logic element. An input terminal of the second logic element is connected to an output terminal of the first logic element. The first logic element and the second logic element each output a signal corresponding to a signal input only in a period during which power supply voltage is supplied.

For example, an inverter or a clocked inverter can be used as the logic element.

Next, a method for driving thememory element200 inFIG. 8 is described with reference to a timing chart inFIG. 9.

In the timing chart inFIG. 9,reference numeral220 denotes data retained in thefirst memory circuit201; reference symbol S1 denotes the potential of the control signal S1; reference symbol S2 denotes the potential of the control signal S2; reference symbol S3 denotes the potential of the control signal S3; reference symbol V1 denotes the potential V1; and reference symbol V2 denotes the potential V2. When power supply voltage is not supplied to thememory element200, a difference V between the potential V1 and the potential V2 is approximately 0. Reference symbol M1 denotes the potential of the node M1, and reference symbol M2 denotes the potential of the node M2.

Note that in the driving method described below, in the structure illustrated inFIG. 8, an n-channel transistor is used as theswitch203 and a p-channel transistor is used as theswitch204. The first terminal and the second terminal of theswitch203 are brought into conduction and the first terminal and the second terminal of theswitch204 are brought out of conduction when the potential of the control signal S2 is a high potential. The first terminal and the second terminal of theswitch203 are brought out of conduction and the first terminal and the second terminal of theswitch204 are brought into conduction when the potential of the control signal S2 is a low potential. Further, the first terminal and the second terminal of theswitch205 are brought into conduction when the potential of the control signal S3 is a high potential, and the first terminal and the second terminal of theswitch205 are brought out of conduction when the potential of the control signal S3 is a low potential. Furthermore, an n-channel transistor is used as thetransistor209, thetransistor209 is turned on when the potential of the control signal S1 is a high potential, and thetransistor209 is turned off when the potential of the control signal S1 is a low potential.

However, a driving method of the present invention is not limited thereto, and as described below, the potential of each control signal can be determined so that theswitch203, theswitch204, theswitch205, and thetransistor209 are in the same state.

The potential V1 is a low power supply potential VSS and the potential V2 switches between a high power supply potential VDD and the power supply potential VSS. The power supply potential VSS may be, for example, a ground potential. Note that one embodiment of the present invention is not limited this structure, and the potential V2 may be the power supply potential VSS and the potential V1 may switch between the power supply potential VDD and the power supply potential VSS.

(Normal Operation)

Operation in aperiod1 inFIG. 9 is described. In theperiod1, power supply voltage is supplied to thememory element200. In theperiod1, the potential V2 is the power supply potential VDD. In a period during which power supply voltage is supplied to thememory element200, data (indicated by data X inFIG. 9) is retained in thefirst memory circuit201. At this time, the potential of the control signal S3 is set to a low potential so that the first terminal and the second terminal of theswitch205 are brought out of conduction. Note that the first terminal and the second terminal of each of theswitch203 and theswitch204 may be in a conduction state or a non-conduction state. In other words, the potential of the control signal S2 may be a high potential or a low potential (the potential is indicated by A inFIG. 9). Further, thetransistor209 may be on or off. In other words, the potential of the control signal S1 may be a high potential or a low potential (the potential is indicated by A inFIG. 9). In theperiod1, the potential of the node M1 may be a high potential or a low potential (the potential is indicated by A inFIG. 9). In theperiod1, the potential of the node M2 may be a high potential or a low potential (the potential is indicated by A inFIG. 9). The operation in theperiod1 is referred to as normal operation.

(Operation Before Stop of Supply of Power Supply Voltage)

Operation in aperiod2 inFIG. 9 is described. Before the supply of power supply voltage to thememory element200 is stopped, the potential of the control signal S1 is set to a high potential so that thetransistor209 is turned on. Thus, a signal corresponding to the data (the data X) retained in thefirst memory circuit201 is input to the gate electrode of thetransistor210 through thetransistor209. The signal input to the gate electrode of thetransistor210 is held in thecapacitor208 or the gate capacitance of thetransistor210. Accordingly, the potential of the node M2 becomes a signal potential corresponding to the data retained in the first memory circuit201 (the potential is indicated by VX inFIG. 9). After that, the potential of the control signal S1 is set to a low potential so that thetransistor209 is turned off. Thus, the signal corresponding to the data retained in thefirst memory circuit201 is held in thesecond memory circuit202. Also in theperiod2, the first terminal and the second terminal of theswitch205 are brought out of conduction by the control signal S3. The first terminal and the second terminal of each of theswitch203 and theswitch204 may be in a conduction state or a non-conduction state. In other words, the potential of the control signal S2 may be a high potential or a low potential (the potential is indicated by A inFIG. 9). In theperiod2, the potential of the node M1 may be a high potential or a low potential (the potential is indicated by A inFIG. 9). The operation in theperiod2 is referred to as operation before the stop of supply of power supply voltage.

Operation in aperiod3 inFIG. 9 is described. After the operation before the stop of supply of power supply voltage is performed, the potential V2 is set to the power supply potential VSS at the beginning of theperiod3, and the supply of power supply voltage to thememory element200 is stopped. When the supply of power supply voltage is stopped, the data retained in the first memory circuit201 (the data X) is lost. However, even after the supply of power supply voltage to thememory element200 is stopped, the signal potential VX corresponding to the data retained in the first memory circuit201 (the data X) is held in the node M2 by thecapacitor208 or the gate capacitance of thetransistor210. Since thetransistor209 has extremely low off-state current, the potential held in thecapacitor208 or the gate capacitance of the transistor210 (the potential VX of the node M2) can be held for a long time. Thus, even after the supply of power supply voltage to thememory element200 is stopped, the data (the data X) is retained. Theperiod3 corresponds to a period during which the supply of power supply voltage to thememory element200 is stopped.

(Restart of Supply of Power Supply Voltage)

Operation in aperiod4 inFIG. 9 is described. After the supply of power supply voltage to thememory element200 is restarted by setting the potential V2 to the power supply potential VDD, the potential of the control signal S2 is set to a low potential so that the first terminal and the second terminal of theswitch204 are brought into conduction and the first terminal and the second terminal of theswitch203 are brought out of conduction. At this time, the potential of the control signal S1 is a low potential, and thetransistor209 is kept off. The potential of the control signal S3 is a low potential, and the first terminal and the second terminal of theswitch205 are in a non-conduction state. Thus, the power supply potential VDD that is a constant potential can be applied to the second terminal of theswitch203 and the first terminal of the switch204 (the node M1) (hereinafter, this operation is referred to as precharge operation). The potential of the node M1 is held in thecapacitor207.

After the precharge operation, in aperiod5, the potential of the control signal S2 is set to a high potential so that the first terminal and the second terminal of theswitch203 are brought into conduction and the first terminal and the second terminal of theswitch204 are brought out of conduction. At this time, the potential of the control signal S1 remains the low potential, and thetransistor209 is kept off. The potential of the control signal S3 is a low potential, and the first terminal and the second terminal of theswitch205 are in a non-conduction state. Depending on a signal held in thecapacitor208 or the gate capacitance of the transistor210 (the potential VX of the node M2), the on state or the off state of thetransistor210 is selected, so that the potential of the second terminal of theswitch203 and the first terminal of theswitch204, i.e., the potential of the node M1 is determined. Specifically, in the case where thetransistor210 is on, the potential V1 (e.g., the power supply potential VSS) is applied to the node M1. On the other hand, in the case where thetransistor210 is off, the potential of the node M1 remains the constant potential (e.g., the power supply potential VDD) that is determined by the precharge operation. In this manner, depending on the on state or the off state of thetransistor210, the potential of the node M1 becomes the power supply potential VDD or the power supply potential VSS.

For example, in the case where the signal held in thefirst memory circuit201 corresponds to a digital value “1”, the potential of a signal output from the output terminal OUT of thefirst memory circuit201 is a high potential. In that case, the potential of the node M1 becomes the low power supply potential VSS corresponding to a signal of a digital value “0”. On the other hand, in the case where the signal held in thefirst memory circuit201 corresponds to a digital value “0”, the potential of a signal output from the output terminal OUT of thefirst memory circuit201 is a low potential. In that case, the potential of the node M1 becomes the high power supply potential VDD corresponding to a signal of a digital value “1”. In other words, a potential corresponding to a digital value that is different from the digital value of the signal stored in thefirst memory circuit201 is held in the node M1. This potential is indicated by VXb inFIG. 9. In other words, the potential of a signal corresponding to the data (data X) input from thefirst memory circuit201 in theperiod2 is converted into the potential VXb of the node M1.

After that, in aperiod6, the potential of the control signal S3 is set to a high potential so that the first terminal and the second terminal of theswitch205 are brought into conduction. At this time, the potential of the control signal S2 remains the high potential. The potential of the control signal S1 remains the low potential, and thetransistor209 is kept off. Thus, a signal corresponding to the potential of the second terminal of theswitch203 and the first terminal of the switch204 (the potential VXb of the node M1) is inverted by thelogic element206 to be an inversion signal corresponding to the data (the data X). The inversion signal is input to thefirst memory circuit201. Thus, the data (the data X) that has been retained before the stop of the supply of power supply voltage to thememory element200 can be retained in thefirst memory circuit201 again.

In thememory element200 inFIG. 8, after the potential of the node M1 is set to the constant potential (the power supply potential VDD inFIG. 9) by the precharge operation in theperiod4, the potential of the node M1 is set to the potential VXb corresponding to the data (the data X) in theperiod5; thus, it takes a shorter time to set the potential of the node M1 to the predetermined potential VXb. In other words, in thememory element200 inFIG. 8, theswitch203 and theswitch204 enable precharge operation, so that it takes a shorter time to retain the original data in thefirst memory circuit201 after the supply of power supply voltage is restarted.

In one embodiment of the present invention, in a period during which power supply voltage is not supplied to eachmemory element200 included in the storage device, data stored in thefirst memory circuit201 that corresponds to a volatile memory can be retained in thecapacitor208 or the gate capacitance of thetransistor210 provided in thesecond memory circuit202.

Thetransistor209 has extremely low off-state current because an oxide semiconductor is included in a channel formation region. Thus, by using thetransistor209, even when power supply voltage is not supplied to thememory element200, an electric charge held in thecapacitor208 or the gate capacitance of thetransistor210 is held for a long time. Thus, thememory element200 can retain data even in a period during which the supply of power supply voltage is stopped.

In thesecond memory circuit202, the signal held in thecapacitor208 or the gate capacitance of thetransistor210 is converted into the state (the on state or the off state) of thetransistor210 after the supply of power supply voltage to thememory element200 is restarted; thus, the signal can be read from thesecond memory circuit202 by the drain current of thetransistor210. Consequently, the original signal can be accurately read even when a potential corresponding to the signal held in thecapacitor208 or the gate capacitance of thetransistor210 fluctuates to some degree.

When thememory element200 is used in a storage device such as a register or a cache memory included in theCPU101, data in the storage device can be prevented from being lost due to the stop of the supply of power supply voltage. Further, the state before the stop of the supply of power supply voltage can be backed up in a short time, and the storage device can return to the state before the stop of the supply of power supply voltage in a short time after the supply of power supply voltage is restarted. Thus, in theCPU101, moreover, in thesemiconductor display device100, even when time from completion of writing of an image signal to thepixel portion106 to the start of writing of another image signal is long, for example, 60 seconds, or short, for example, several milliseconds, the supply of power supply voltage can be stopped. Thus, thesemiconductor display device100 capable of consuming less power can be provided.

Note that in one embodiment of the present invention, eachmemory element200 included in theCPU101 includes a second memory circuit for storing data in the first memory circuit. The second memory circuit may include a storage for storing data by accumulation of an electric charge, and a transistor controlling supply, holding, and release of the electric charge in the storage and having extremely low off-state current. Thememory element200 with the structure inFIG. 8 corresponds to one embodiment of the present invention, and each memory element of the storage device included in theCPU101 may have a structure that is different from the structure inFIG. 8.

Next, an example of a structure of thememory element200 according to one embodiment of the present invention that is different from the structure inFIG. 8 is described with reference toFIG. 16.

Amemory element250 inFIG. 16 includes afirst memory circuit251 and asecond memory circuit252. Thefirst memory circuit251 includes afirst logic element253aand asecond logic element253bthat invert the polarity of a signal input and output the inversion signal, atransistor254, and atransistor255. Thesecond memory circuit252 includes atransistor257 and acapacitor256 corresponding to a storage.

A signal Din including data input to thememory element250 is supplied to an input terminal of thefirst logic element253athrough thetransistor254. An output terminal of thefirst logic element253ais connected to an input terminal of thesecond logic element253b. An output terminal of thesecond logic element253bis connected to the input terminal of thefirst logic element253athrough thetransistor255. The potential of the output terminal of thefirst logic element253aor the input terminal of thesecond logic element253bis output to thenext memory element250 or another circuit as a signal Dout.

Note that inFIG. 16, inverters are used as thefirst logic element253aand thesecond logic element253b; however, instead of the inverter, a clocked inverter can be used as thefirst logic element253aor thesecond logic element253b.

Thecapacitor256 is connected to an input terminal of thememory element250, i.e., a node to which the potential of the signal Din is applied, through thetransistor254 and thetransistor257 so that the data of the signal Din that is input to thememory element250 can be stored as needed. Specifically, one of a pair of electrodes of thecapacitor256 is connected to the input terminal of thefirst logic element253athrough thetransistor257. The other of the pair of electrodes of thecapacitor256 is connected to a node to which the low power supply potential VSS (e.g., a ground potential) is applied.

Thetransistor257 has much lower off-state current than a transistor including a normal semiconductor such as silicon or germanium because thetransistor257 includes an oxide semiconductor in a channel formation region. The length of a data retention period of thecapacitor256 depends on the amount of leakage of electric charge accumulated in thecapacitor256 through thetransistor257. Accordingly, when the electric charge accumulated in thecapacitor256 is held by thetransistor257 having extremely low off-state current, leakage of the electric charge from thecapacitor256 can be prevented, so that the data retention period can be made longer.

Note that althoughFIG. 16 illustrates the case where thetransistor257 has a single-gate structure, thetransistor257 may have a multi-gate structure in which a plurality of electrically connected gate electrodes are included so that a plurality of channel formation regions are included.

AlthoughFIG. 16 illustrates the case where one transistor is thetransistor257, the present invention is not limited to this structure. In one embodiment of the present invention, a plurality of transistors may be thetransistor257. In the case where a plurality of transistors which function as switching elements are thetransistor257, the plurality of transistors may be connected to each other in parallel, in series, or in combination of parallel connection and series connection.

Thememory element250 may further include another circuit element such as a diode, a resistor, or an inductor as needed.

Thefirst logic element253ahas a structure in which a p-channel transistor258 and an n-channel transistor259 whose gate electrodes are connected to each other are connected in series between a first node to which the high power supply potential VDD is applied and a second node to which the low power supply potential VSS is applied. Specifically, a source terminal of the p-channel transistor258 is connected to the first node to which the power supply potential VDD is applied, and a source terminal of the n-channel transistor259 is connected to the second node to which the power supply potential VSS is applied. In addition, a drain terminal of the p-channel transistor258 is connected to a drain terminal of the n-channel transistor259, and the potentials of the two drain terminals can be regarded as the potential of the output terminal of thefirst logic element253a. Further, the potentials of the gate electrode of the p-channel transistor258 and the gate electrode of the n-channel transistor259 can be regarded as the potential of the input terminal of thefirst logic element253a.

Thesecond logic element253bhas a structure in which a p-channel transistor260 and an n-channel transistor261 whose gate electrodes are connected to each other are connected in series between the first node to which the high power supply potential VDD is applied and the second node to which the low power supply potential VSS is applied. Specifically, a source terminal of the p-channel transistor260 is connected to the first node to which the power supply potential VDD is applied, and a source terminal of the n-channel transistor261 is connected to the second node to which the power supply potential VSS is applied. In addition, a drain terminal of the p-channel transistor260 is connected to a drain terminal of the n-channel transistor261, and the potentials of the two drain terminals can be regarded as the potential of the output terminal of thesecond logic element253b. Further, the potentials of the gate electrode of the p-channel transistor260 and the gate electrode of the n-channel transistor261 can be regarded as the potential of the input terminal of thesecond logic element253b.

An on state or an off state of thetransistor254 is selected by a signal Sig1 supplied to a gate electrode of thetransistor254. An on state or an off state of thetransistor255 is selected by a signal Sig2 supplied to a gate electrode of thetransistor255. An on state or an off state of thetransistor257 is selected by a control signal Sig3 supplied to a gate electrode of thetransistor257.

Note that thefirst logic element253aand thesecond logic element253bneed to operate at high speed. Thus, a transistor including crystalline silicon or germanium in a channel formation region is preferably used as the n-channel transistor259 or the p-channel transistor259 included in thefirst logic element253aor the n-channel transistor261 or the p-channel transistor260 included in thesecond logic element253b.

Note that thetransistor254 or thetransistor255 may include crystalline silicon or germanium in a channel formation region.

Next, an operation example of thememory element250 inFIG. 16 is described.

First, at the time of writing data, thetransistor254 is turned on, and thetransistor255 and thetransistor257 are turned off. Then, the power supply potential VDD is applied to the first node and the power supply potential VSS is applied to the second node, so that the power supply voltage is applied to thefirst memory circuit251. The potential of the signal Din supplied to thememory element250 is applied to the input terminal of thefirst logic element253athrough thetransistor254, so that the potential of the output terminal of thefirst logic element253ais a potential of the signal Din whose polarity is inverted. Then, thetransistor255 is turned on to connect the input terminal of thefirst logic element253ato the output terminal of thesecond logic element253b, so that data is written to thefirst logic element253aand thesecond logic element253b.

Next, in the case where the data input is retained in thefirst logic element253aand thesecond logic element253b, thetransistor255 is kept on, thetransistor257 is kept off, and thetransistor254 is turned off. By turning off thetransistor254, the data input is retained in thefirst logic element253aand thesecond logic element253b. At this time, the power supply potential VDD is applied to the first node and the power supply potential VSS is applied to the second node, so that the state in which the power supply voltage is applied between the first node and the second node is maintained.

The potential of the output terminal of thefirst logic element253areflects the data retained in thefirst logic element253aand thesecond logic element253b. Thus, by reading the potential, the data can be read from thememory element250.

Note that in the case where the supply of power supply voltage is stopped at the time of retaining data, the data is retained in thecapacitor256 before the supply of power supply voltage is stopped. In the case where the data is retained in thecapacitor256, first, thetransistor254 is turned off and thetransistor255 and thetransistor257 are turned on. Then, through thetransistor257, an electric charge with an amount corresponding to the value of the data retained in thefirst logic element253aand thesecond logic element253bis accumulated in thecapacitor256, so that the data is written to thecapacitor256. After the data is stored in thecapacitor256, thetransistor257 is turned off, so that the data stored in thecapacitor256 is retained. After thetransistor257 is turned off, for example, the power supply potential VSS is applied to the first node and the second node so that the nodes have equal potentials, and the application of power supply voltage between the first node and the second node is stopped. Note that after the data is stored in thecapacitor256, thetransistor255 may be turned off.

In this manner, in the case where the data input is retained in thecapacitor256, the application of power supply voltage between the first node and the second node is not needed; thus, off-state current flowing between the first node and the second node through the p-channel transistor258 and the n-channel transistor259 included in thefirst logic element253aor the p-channel transistor260 and the n-channel transistor261 included in thesecond logic element253bcan be as close to zero as possible. Consequently, power consumption due to the off-state current of thefirst memory circuit251 at the time of retaining the data can be greatly reduced, and the storage device and the semiconductor display device including the storage device can consume less power.

As described above, thetransistor257 has extremely low off-state current. Thus, when thetransistor257 is off, the electric charge accumulated in thecapacitor256 does not easily leak, so that the data is retained.

In the case where the data stored in thecapacitor256 is read, thetransistor254 is turned off. Then, the power supply potential VDD is applied again to the first node and the power supply potential VSS is applied again to the second node, so that power supply voltage is applied between the first node and the second node. Then, by turning on thetransistor257, the signal Dout having a potential that reflects the data can be read from thememory element250.

Next,FIG. 10A illustrates a structure example of a storage device included in theCPU101. The storage device inFIG. 10A includes aswitching element221 and amemory element group222 including the plurality ofmemory elements200. The high power supply potential VDD is applied to eachmemory element200 included in thememory element group222 through the switchingelement221. Further, the potential of a signal IN and the low power supply potential VSS are applied to eachmemory element200 included in thememory element group222.

InFIG. 10A, a transistor is used as the switchingelement221, and switching of the transistor is controlled by a control signal SigA supplied to a gate electrode of the transistor.

AlthoughFIG. 10A illustrates the case where one transistor is the switchingelement221, the present invention is not limited to this structure. In one embodiment of the present invention, a plurality of transistors may be the switchingelement221. In the case where a plurality of transistors which function as switching elements are the switchingelement221, the plurality of transistors may be connected to each other in parallel, in series, or in combination of parallel connection and series connection.

Although theswitching element221 controls the supply of the high power supply potential VDD to eachmemory element200 included in thememory element group222 inFIG. 10A, the switchingelement221 may control the supply of the low power supply potential VSS.FIG. 10B illustrates an example of a storage device in which the low power supply potential VSS is applied to eachmemory element200 included in thememory element group222 through the switchingelement221. The switchingelement221 can control the supply of the low power supply potential VSS to eachmemory element200 included in thememory element group222.

This embodiment can be combined with any of the other embodiments as appropriate.

Embodiment 2

In this embodiment, an example of a shift register applicable to the scanline driver circuit109 and the signalline driver circuit108 of thesemiconductor display device100 described in the above embodiment is described.

FIGS. 11A and 11B illustrate a structure example of the shift register in this embodiment.

The shift register inFIG. 11A is formed using P sequential logic units10 (P is a natural number of 3 or more). InFIG. 11A, the Psequential logic units10 are illustrated as sequential logic units FF_1 to FF_P.

A start signal ST and a reset signal Res are input to each of the sequential logic units FF_1 to FF_P.

Further, a clock signal CK1, a clock signal CK2, and a clock signal CK3 are input to each of the sequential logic units FF_1 to FF_P. As the clock signal CK1, the clock signal CK2, and the clock signal CK3, for example, any three of a first clock signal (also referred to as CLK1), a second clock signal (also referred to as CLK2), a third clock signal (also referred to as CLK3), and a fourth clock signal (also referred to as CLK4) can be used. The first to fourth clock signals are each a digital signal whose potential repeatedly switches between a high level and a low level. Note that different combinations of the clock signals are input to the adjacentsequential logic units10. The shift register inFIG. 11A controls the operation of thesequential logic units10 by the first to fourth clock signals. With the above structure, operation speed can be improved.

FIG. 11B illustrates an example of a specific circuit structure of thesequential logic unit10 inFIG. 11A.

The sequential logic unit inFIG. 11B includes atransistor31, atransistor32, atransistor33, atransistor34, atransistor35, atransistor36, atransistor37, atransistor38, atransistor39, atransistor40, and atransistor41. The case where all the transistors are n-channel transistors is given as an example, and a specific connection relation is described below.

Note that in this embodiment, the structure of the sequential logic unit is described referring to one of a source terminal and a drain terminal of the transistor as a first terminal and the other of the source terminal and the drain terminal of the transistor as a second terminal.

A power supply potential Va is input to a first terminal of thetransistor31, and the start signal ST is input to a gate electrode of thetransistor31. A power supply potential Vb is input to a first terminal of thetransistor32, and a second terminal of thetransistor32 is connected to a second terminal of thetransistor31.

Note that one of the power supply potential Va and the power supply potential Vb is a high potential Vdd, and the other is a low potential Vss. In the case where all the transistors are p-channel transistors, the values of the power supply potential Va and the power supply potential Vb interchange with each other. In addition, a difference between the power supply potential Va and the power supply potential Vb corresponds to power supply voltage.

A first terminal of thetransistor33 is connected to the second terminal of thetransistor31, and the power supply potential Va is input to a gate electrode of thetransistor33.

The power supply potential Va is input to a first terminal of thetransistor34, and the clock signal CK3 is input to a gate electrode of thetransistor34.

A first terminal of thetransistor35 is connected to a second terminal of thetransistor34. A second terminal of thetransistor35 is connected to a gate electrode of thetransistor32. The clock signal CK2 is input to a gate electrode of thetransistor35.

The power supply potential Va is input to a first terminal of thetransistor36, and the reset signal Res is input to a gate electrode of thetransistor36.

The power supply potential Vb is input to a first terminal of thetransistor37. A second terminal of thetransistor37 is connected to the gate electrode of thetransistor32 and a second terminal of thetransistor36. The start signal ST is input to a gate electrode of thetransistor37.

The clock signal CK1 is input to a first terminal of thetransistor38, and a gate electrode of thetransistor38 is connected to a second terminal of thetransistor33.

The power supply potential Vb is input to a first terminal of thetransistor39. A second terminal of thetransistor39 is connected to a second terminal of thetransistor38. A gate electrode of thetransistor39 is connected to the gate electrode of thetransistor32.

The clock signal CK1 is input to a first terminal of thetransistor40, and a gate electrode of thetransistor40 is connected to the second terminal of thetransistor33.

The power supply potential Vb is input to a first terminal of thetransistor41. A second terminal of thetransistor41 is connected to a second terminal of thetransistor40. A gate electrode of thetransistor41 is connected to the gate electrode of thetransistor32.

Note that inFIG. 11B, a point at which the second terminal of thetransistor33, the gate electrode of thetransistor38, and the gate electrode of thetransistor40 are connected to each other is referred to as a node NA. A point at which the gate electrode of thetransistor32, the second terminal of thetransistor35, the second terminal of thetransistor36, the second terminal of thetransistor37, the gate electrode of thetransistor39, and the gate electrode of thetransistor41 are connected to each other is referred to as a node NB. A point at which the second terminal of thetransistor38 and the second terminal of thetransistor39 are connected to each other is referred to as a node NC. A point at which the second terminal of thetransistor40 and the second terminal of thetransistor41 are connected to each other is referred to as a node ND.

The sequential logic unit inFIG. 11B outputs the potential of the node NC as a first output signal OUT1 and outputs the potential of the node ND as a second output signal OUT2. For example, the second output signal OUT2 can be used as the scan signal SCN for selecting thepixel130 in the scanline driver circuit109 and can be used as a signal for outputting an image signal to the selectedpixel130 in the signalline driver circuit108.

Note that as the start signal ST input to the first sequential logic unit FF_1, for example, the start signal GSP, a start signal STP, or the like in thesemiconductor display device100 described in the above embodiment is used. Further, in each of the second to P-th sequential logic units FF_2 to FF_P, the first output signal OUT1 in the previous sequential logic unit is used as the start signal ST.

In each of the sequential logic units FF_1 to FF_P−2, the first output signal OUT1 in the sequential logic unit after the next sequential logic unit is used as the reset signal Res. In each of the sequential logic unit FF_P−1 and the sequential logic unit FF_P, a signal which is separately generated can be used as the reset signal Res, for example. Note that the (P−1)th sequential logic unit FF_P−1 and the P-th sequential logic unit FF_P are each used as a dummy sequential logic unit.

Next, an operation example of the shift register inFIG. 11A is described with reference toFIGS. 12A and 12B.

FIG. 12A is a timing chart illustrating an operation example of the sequential logic unit inFIG. 11B, andFIG. 12B is a timing chart illustrating an operation example of the shift register inFIG. 11A.

Note thatFIG. 12A is a timing chart of the case where each of thesequential logic units10 inFIG. 11A has the structure inFIG. 11B. The following description is made taking the case where the potential Vdd is input as the power supply potential Va and the potential Vss is input as the power supply potential Vb when all thetransistors31 to41 in thesequential logic unit10 inFIG. 11B are n-channel transistors, as an example.

As illustrated inFIG. 12A, by the input of the pulse of the start signal ST to eachsequential logic unit10 in aselection period61, thetransistor31 is turned on. Then, the potential of the node NA becomes equal to or higher than the potential Vdd by bootstrap operation, so that thetransistor38 and thetransistor40 are turned on. In addition, when thetransistor37 is turned on by the input of the pulse of the start signal ST, the potential of the node NB becomes low, so that thetransistor39 and thetransistor41 are turned off. Accordingly, the potential of the first output signal OUT1 and the potential of the second output signal OUT2 become high.

Further, when thetransistor36 is turned on by the input of the pulse of the reset signal Res in anon-selection period62, the potential of the node NB becomes high, so that thetransistor32, thetransistor39, and thetransistor41 are turned on. In addition, when thetransistor32 is turned on, the potential of the node NA becomes low, so that thetransistor38 and thetransistor40 are turned off. Accordingly, the potentials of the first output signal OUT1 and the second output signal OUT2 remain low.

The above operation is performed sequentially in thesequential logic units10 in response to the first clock signal CLK1 to the fourth clock signal CLK4, so that the first output signal OUT1 and the second output signal OUT2 whose pulses are sequentially shifted can be output from eachsequential logic unit10, as illustrated inFIG. 12B.

In the case where the shift register described in this embodiment is applied to the scanline driver circuit109 or the signalline driver circuit108 included in thesemiconductor display device100 described in the above embodiment, the supply of the power supply voltage input to eachsequential logic unit10, the drive signal (e.g., the clock signal CLK), and the drive signal (e.g., the start signal SP) input to the first sequential logic unit is stopped, so that the operation of the scanline driver circuit109 and the signalline driver circuit108 can be stopped.

This embodiment can be combined with any of the other embodiments as appropriate.

Embodiment 3

In this embodiment, a specific embodiment of a CPU is described.FIG. 13 is a block diagram illustrating a structure example of a CPU.

ACPU600 includes acontroller601, an arithmetic logic unit (ALU)602 corresponding to an arithmetic unit, adata cache603, aninstruction cache604, aprogram counter605, aninstruction register606, amain storage device607, and aregister file608.

Thecontroller601 has a function of decoding and executing an instruction input. TheALU602 has a function of performing a variety of arithmetic processing such as four arithmetic operations and logic operations. Thedata cache603 is a buffer storage device that temporarily stores frequently used data. Theinstruction cache604 is a buffer storage device that temporarily stores a frequently used instruction of instructions (programs) sent to thecontroller601. Theprogram counter605 is a register that stores an address of an instruction to be executed next. Theinstruction register606 is a register that stores an instruction to be executed next. Data used for the arithmetic processing in theALU602 and an instruction that is executed in thecontroller601 are stored in themain storage device607. Theregister file608 has a plurality of registers including a general-purpose register and can store data read from themain storage device607, data which is obtained during the arithmetic processing in theALU602, data which is obtained as a result of the arithmetic processing in theALU602, and the like.

Next, the operation of theCPU600 is described.

In response to an address of an instruction to be executed next that is stored in theprogram counter605, thecontroller601 reads the instruction from the corresponding address of theinstruction cache604, and stores the instruction in theinstruction register606. When the instruction is not stored in the corresponding address of theinstruction cache604, thecontroller601 accesses a corresponding address of themain storage device607, reads the instruction from themain storage device607, and stores the instruction in theinstruction register606. In that case, the instruction is also stored in theinstruction cache604.

Thecontroller601 decodes the instruction stored in theinstruction register606 and executes the instruction. Specifically, thecontroller601 generates a variety of signals for controlling the operation of theALU602 in response to the instruction.

When the instruction which is to be executed is an arithmetic instruction, thecontroller601 makes theALU602 perform arithmetic processing using the data stored in theregister file608, and stores the arithmetic processing result in theregister file608.

When the instruction which is to be executed is a loading instruction, thecontroller601, first, accesses a corresponding address of thedata cache603, and checks whether corresponding data exists in thedata cache603. When the corresponding data exists in thedata cache603, the data is copied from the corresponding address of thedata cache603 to theregister file608. When the corresponding data does not exist in thedata cache603, the data is copied from a corresponding address of themain storage device607 to the corresponding address of thedata cache603, and then the data is copied from the corresponding address of thedata cache603 to theregister file608. Note that in the case where the corresponding data does not exist, since it is necessary to access the low-speedmain storage device607 as described above, it takes a longer time to execute the instruction as compared to the case where thecontroller601 accesses only the buffer storage device (e.g., the data cache603). However, when not only the data but also the address of the data and data of addresses of the vicinities of the data in themain storage device607 are copied to the buffer storage device, second and subsequent accesses to the address of the data and the addresses of the vicinities of the data in themain storage device607 can be performed at high speed.

When the instruction which is to be executed is a store instruction, thecontroller601 stores data in theregister file608 in a corresponding address of thedata cache603. In that case, thecontroller601, first, accesses the corresponding address of thedata cache603 and checks whether the corresponding data can be stored in thedata cache603. When the data can be stored in thedata cache603, the data is copied from theregister file608 to the corresponding address of thedata cache603. When the data cannot be stored, another corresponding address is assigned in part of thedata cache603, and the data is copied from theregister file608 to the corresponding address of thedata cache603. Note that the data can be copied to themain storage device607 just after the data is copied to thedata cache603. Alternatively, after some pieces of data are copied to thedata cache603, the pieces of data can be collectively copied to themain storage device607.

Then, after thecontroller601 executes the instruction, thecontroller601 accesses theprogram counter605 again, and repeats the operation in which an instruction read from theinstruction register606 is decoded and executed.

In one embodiment of the present invention, when the storage device described in the above embodiment is applied to the buffer storage device (e.g., thedata cache603 or the instruction cache604), data in the buffer storage device can be prevented from being lost due to the stop of the supply of power supply voltage. Further, the state before the stop of the supply of power supply voltage can be backed up in a short time, and the buffer storage device can return to the state before the stop of the supply of power supply voltage in a short time after the supply of power supply voltage is restarted. Thus, in theentire CPU600 or the logic circuit (e.g., thecontroller601 or the ALU602) included in theCPU600, even when time from completion of writing of an image signal to thepixel portion106 to the start of writing of another image signal is long, for example, 60 seconds, or short, for example, several milliseconds, the supply of power supply voltage can be stopped. Thus, theCPU600 can consume less power.

This embodiment can be combined with any of the other embodiments as appropriate.

Embodiment 4

In this embodiment, the structure of a pixel in a semiconductor display device according to one embodiment of the present invention is described taking thepixel130 inFIG. 5B as an example.

FIG. 14A is an example of a top view of a pixel.FIG. 14B is a cross-sectional view taken along dashed line A1-A2 inFIG. 14A.

The pixel inFIGS. 14A and 14B includes aconductive film501 functioning as the scan line GL, aconductive film502 functioning as the signal line SL, aconductive film503 functioning as a wiring COM, and aconductive film504 functioning as a second terminal of thetransistor131. Theconductive film501 also functions as the gate electrode of thetransistor131 inFIG. 5B. In addition, theconductive film502 also functions as a first terminal of thetransistor131.

A base film550 is formed over asubstrate500. As the base film550, for example, a single layer of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or an aluminum oxide film or a stack of a plurality of these films can be used. In particular, when an insulating film having a high barrier property, for example, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, an aluminum oxide film, or an aluminum nitride oxide film is used for the base film, impurities in an atmosphere, such as moisture or hydrogen or impurities included in thesubstrate500, such as an alkali metal or a heavy metal, can be prevented from entering anactive layer507 or agate insulating film506 to be formed later, or an interface between theactive layer507 and another insulating film and the vicinity thereof. Note that in order to prevent hydrogen, which serves as an electron donor, from entering theactive layer507, the concentration of hydrogen in the base film550 is preferably as low as possible. Specifically, the concentration of hydrogen in the base film550 is preferably 7.2×10²⁰cm⁻³or lower.

Note that in this specification, an oxynitride is a substance which includes more oxygen than nitrogen, and a nitride oxide is a substance which includes more nitrogen than oxygen.

Theconductive film501 and theconductive film503 can be formed by processing one conductive film formed over the base film550 into a desired shape. Thegate insulating film506 is formed over theconductive film501 and theconductive film503. Further, theconductive film502 and theconductive film504 can be formed by processing one conductive film formed over thegate insulating film506 into a desired shape.

Theactive layer507 of thetransistor131 is formed over thegate insulating film506 to overlap with theconductive film501. As illustrated inFIGS. 14A and 14B, theactive layer507 preferably completely overlaps with theconductive film501 functioning as a gate electrode. With such a structure, an oxide semiconductor in theactive layer507 can be prevented from being degraded by incident light from thesubstrate500 side; thus, degradation in characteristics of thetransistor131, such as a shift in threshold voltage of thetransistor131, can be prevented.

In the pixel inFIGS. 14A and 14B, an insulating film512 and an insulatingfilm513 are sequentially formed to cover theactive layer507, theconductive film502, and theconductive film504. In addition, apixel electrode505 is formed over the insulatingfilm513, and theconductive film504 is connected to thepixel electrode505 through a contact hole formed in the insulating film512 and the insulatingfilm513.

A portion where theconductive film503 functioning as the wiring COM overlaps with theconductive film504 with thegate insulating film506 provided therebetween functions as thecapacitor133.

In this embodiment, an insulatingfilm508 is formed between theconductive film501 and thegate insulating film506. The insulatingfilm508 is provided between theconductive film501 and theconductive film502; thus, parasitic capacitance generated between theconductive film501 and theconductive film502 can be reduced by the insulatingfilm508.

In this embodiment, an insulatingfilm509 is formed between theconductive film503 and thegate insulating film506. In addition, aspacer510 is formed over thepixel electrode505 to overlap with the insulatingfilm509.

FIG. 14A is a top view of the pixel provided with thespacer510. InFIG. 14B, asubstrate514 is provided to face thesubstrate500 provided with thespacer510.

Acommon electrode515 is provided for thesubstrate514, and aliquid crystal layer516 containing a liquid crystal is provided between thepixel electrode505 and thecommon electrode515. Theliquid crystal element132 is formed in a portion where thepixel electrode505, thecommon electrode515, and theliquid crystal layer516 overlap with each other.

In the case of a transmissive liquid crystal display device, thepixel electrode505 and thecommon electrode515 are each preferably formed using a light-transmitting conductive material. In the case of a reflective liquid crystal display device, it is preferable that thecommon electrode515 be formed using a light-transmitting conductive material and that thepixel electrode505 be formed using a light-reflecting conductive material.

Specifically, for thepixel electrode505 and thecommon electrode515, any of indium oxide, indium oxide-tin oxide (indium tin oxide (ITO)), indium oxide-tin oxide containing silicon or silicon oxide, indium oxide-zinc oxide (indium zinc oxide), indium oxide containing tungsten oxide and zinc oxide, an Al—Zn-based oxide semiconductor containing nitrogen, a Zn-based oxide semiconductor containing nitrogen, a Sn—Zn-based oxide semiconductor containing nitrogen, gold (Au), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu), palladium (Pd), and titanium (Ti) can be used. Other examples are elements that belong toGroup 1 or 2 in the periodic table, for example, an alkali metal such as lithium (Li) or cesium (Cs) and an alkaline earth metal such as magnesium (Mg), calcium (Ca), or strontium (Sr), an alloy containing such an element (e.g., MgAg or AlLi), a rare earth metal such as europium (Eu) or ytterbium (Yb), and an alloy containing such an element. Note that each of thepixel electrode505 and thecommon electrode515 can be formed in such a manner that, for example, a conductive film is formed using the above material by sputtering, vapor deposition (including vacuum vapor deposition), or the like, and then the conductive film is processed into a desired shape by etching through a photolithography process.

An alignment film may be provided as appropriate between thepixel electrode505 and theliquid crystal layer516 or between thecommon electrode515 and theliquid crystal layer516. The alignment film can be formed using an organic resin such as polyimide or poly(vinyl alcohol). Alignment treatment for aligning liquid crystal molecules in a certain direction, such as rubbing, is performed on a surface of the alignment film. A roller wrapped with cloth of nylon or the like is rolled while being in contact with the alignment film so that the surface of the alignment film can be rubbed in a certain direction. Note that it is also possible to form the alignment film that has alignment characteristics with the use of an inorganic material such as silicon oxide by vapor deposition, without alignment treatment.

Injection of liquid crystals for formation of theliquid crystal layer516 may be performed by a dispenser method (a dripping method) or a dipping method (a pumping method).

Note that thesubstrate514 is provided with a light-blockingfilm517 capable of blocking light so that disclination caused by disorder of alignment of the liquid crystal between pixels is prevented from being observed or dispersed light is prevented from entering a plurality of adjacent pixels. The light-blockingfilm517 can be formed using an organic resin containing a black pigment such as a carbon black or low-valent titanium oxide. Alternatively, the light-blockingfilm517 can be formed using a film including chromium.

When the light-blockingfilm517 is provided to overlap with theactive layer507 of thetransistor131, the oxide semiconductor in theactive layer507 can be prevented from being degraded by incident light from thesubstrate514 side; thus, degradation in characteristics of thetransistor131, such as a shift in threshold voltage of thetransistor131, can be prevented.

AlthoughFIGS. 14A and 14B illustrate theliquid crystal element132 in which theliquid crystal layer516 is provided between thepixel electrode505 and thecommon electrode515, a liquid crystal display device according to one embodiment of the present invention is not limited to this structure. A pair of electrodes may be formed over one substrate as in an IPS liquid crystal element or a liquid crystal element exhibiting a blue phase.

Note that in the case where a driver circuit is formed on a panel, also by blocking a transistor used in the driver circuit from light with the use of a gate electrode or a light-blocking film, degradation in characteristics, such as a shift in threshold voltage of the transistor, can be prevented.

This embodiment can be combined with any of the other embodiments as appropriate.

Embodiment 5

A semiconductor display device according to one embodiment of the present invention can be used for display devices, personal computers, or image reproducing devices provided with recording media (typically, devices that reproduce the content of recording media such as digital versatile discs (DVDs) and have displays for displaying the reproduced images). Further, as electronic devices that can include the semiconductor display device according to one embodiment of the present invention, cellular phones, game machines (including portable game machines), personal digital assistants, e-book readers, cameras such as video cameras and digital still cameras, goggle-type displays (head mounted displays), navigation systems, audio reproducing devices (e.g., car audio systems and digital audio players), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATMs), vending machines, and the like can be given.FIGS. 15A to 15E illustrate specific examples of these electronic devices.

FIG. 15A illustrates a portable game machine, which includes ahousing5001, ahousing5002, adisplay portion5003, adisplay portion5004, amicrophone5005,speakers5006, anoperation key5007, astylus5008, and the like. It is possible to provide a low-power portable game machine with the use of the semiconductor display device according to one embodiment of the present invention as thedisplay portion5003 or5004. Note that although the portable game machine illustrated inFIG. 15A has the twodisplay portions5003 and5004, the number of display portions included in the portable game machine is not limited thereto.

FIG. 15B illustrates a display device, which includes ahousing5201, adisplay portion5202, asupport5203, and the like. It is possible to provide a low-power display device with the use of the semiconductor display device according to one embodiment of the present invention as thedisplay portion5202. Note that the display device means all display devices for displaying information, such as display devices for personal computers, for receiving TV broadcast, and for displaying advertisements.

FIG. 15C illustrates a laptop, which includes ahousing5401, adisplay portion5402, akeyboard5403, a pointing device5404, and the like. It is possible to provide a low-power laptop with the use of the semiconductor display device according to one embodiment of the present invention as thedisplay portion5402.

FIG. 15D illustrates a personal digital assistant, which includes afirst housing5601, asecond housing5602, afirst display portion5603, asecond display portion5604, a joint5605, anoperation key5606, and the like. Thefirst display portion5603 is provided in thefirst housing5601, and thesecond display portion5604 is provided in thesecond housing5602. Thefirst housing5601 and thesecond housing5602 are connected to each other with the joint5605, and an angle between thefirst housing5601 and thesecond housing5602 can be changed with the joint5605. An image on thefirst display portion5603 may be switched depending on the angle between thefirst housing5601 and thesecond housing5602 at the joint5605. A semiconductor display device with a position input function may be used as at least one of thefirst display portion5603 and thesecond display portion5604. Note that the position input function can be added by provision of a touch panel in a semiconductor display device. Alternatively, the position input function can be added by provision of a photoelectric conversion element called a photosensor in a pixel portion of a semiconductor display device. It is possible to provide a low-power personal digital assistant with the use of the semiconductor display device according to one embodiment of the present invention as thefirst display portion5603 or thesecond display portion5604.

FIG. 15E illustrates a video camera, which includes afirst housing5801, asecond housing5802, adisplay portion5803,operation keys5804, alens5805, a joint5806, and the like. Theoperation keys5804 and thelens5805 are provided in thefirst housing5801, and thedisplay portion5803 is provided in thesecond housing5802. Thefirst housing5801 and thesecond housing5802 are connected to each other with the joint5806, and an angle between thefirst housing5801 and thesecond housing5802 can be changed with the joint5806. An image on thedisplay portion5803 may be switched depending on the angle between thefirst housing5801 and thesecond housing5802 at the joint5806. It is possible to provide a low-power video camera with the use of the semiconductor display device according to one embodiment of the present invention as thedisplay portion5803.

This embodiment can be combined with any of the other embodiments as appropriate.

Embodiment 6

In this embodiment, structures of a storage device that is suited for an image memory are described.FIGS. 7A to 7C illustrate specific structure examples of amemory cell701 included in a storage device.

Note that in this embodiment, the structure of thememory cell701 is described referring to one of a source terminal and a drain terminal of a transistor as a first terminal and the other of the source terminal and the drain terminal of the transistor as a second terminal.

Thememory cell701 inFIG. 7A includes atransistor703 functioning as a switching element and acapacitor720. A gate electrode of thetransistor703 is connected to a word line WL. A first terminal of thetransistor703 is connected to a data line DL. A second terminal of thetransistor703 is connected to one electrode of thecapacitor720. The other electrode of thecapacitor720 is connected to a node to which a constant potential such as a ground potential is applied.

In thememory cell701 inFIG. 7A, at the time of writing image data, thetransistor703 is turned on, so that the potential of a signal including image data is applied from the data line DL to one electrode of thecapacitor720 through thetransistor703. The amount of electric charge accumulated in thecapacitor720 is controlled in response to the potential of the signal, so that the image data is written to thememory cell701.

Next, at the time of retaining the image data, thetransistor703 is turned off, so that the electric charge is held in thecapacitor720. Since thetransistor703 includes a wide-bandgap semiconductor such as an oxide semiconductor, thetransistor703 has extremely low off-state current. Thus, the electric charge accumulated in thecapacitor720 hardly leaks, and the image data can be retained for a longer period as compared to the case where a semiconductor such as silicon is used for thetransistor703.

At the time of reading the image data, thetransistor703 is turned on, so that the electric charge accumulated in thecapacitor720 is taken out through the data line DL. Then, by reading a difference in the amount of electric charge, the image data can be read.

Thememory cell701 inFIG. 7B includes thetransistor703 functioning as a switching element, atransistor721, and acapacitor722. The gate electrode of thetransistor703 is connected to a first word line WLa. The first terminal of thetransistor703 is connected to a first data line DLa. The second terminal of thetransistor703 is connected to a gate electrode of thetransistor721. A first terminal of thetransistor721 is connected to a second data line DLb. A second terminal of thetransistor721 is connected to a node to which a predetermined potential is applied. One of a pair of electrodes of thecapacitor722 is connected to the gate electrode of thetransistor721. The other of the pair of electrodes of thecapacitor722 is connected to a second word line WLb.

In thememory cell701 inFIG. 7B, at the time of writing image data, thetransistor703 is turned on, so that the potential of a signal including image data is applied from the first data line DLa to the gate electrode of thetransistor721 through thetransistor703. The amount of electric charge accumulated in gate capacitance of thetransistor721 and thecapacitor722 is controlled in response to the potential of the signal, so that the image data is written to thememory cell701.

Next, at the time of retaining the image data, thetransistor703 is turned off, so that the electric charge accumulated in the gate capacitance of thetransistor721 and thecapacitor722 is held. Since thetransistor703 includes a wide-bandgap semiconductor such as an oxide semiconductor as described above, thetransistor703 has extremely low off-state current. Thus, the accumulated electric charge hardly leaks, and the image data can be retained for a longer period as compared to the case where a semiconductor such as silicon is used for thetransistor703.

At the time of reading the image data, the potential of the second word line WLb is changed. A potential difference between the pair of electrodes of thecapacitor722 is held in accordance with the principle of conservation of charge; thus, a change in potential of the second word line WLb is given to the gate electrode of thetransistor721. The threshold voltage of thetransistor721 is changed in accordance with the amount of electric charge accumulated in the gate capacitance of thetransistor721. Thus, by reading a difference in the amount of accumulated electric charge from the amount of drain current of thetransistor721 which is obtained through the change in the potential of the gate electrode of thetransistor721, the image data can be read.

Note that a wide-bandgap semiconductor such as an oxide semiconductor may be used for an active layer of thetransistor721. Alternatively, for the active layer of thetransistor721, any of the following semiconductors may be used: amorphous silicon, microcrystalline silicon, polycrystalline silicon, single crystal silicon, amorphous germanium, microcrystalline germanium, polycrystalline germanium, and single crystal germanium. When oxide semiconductor films are used for active layers of all the transistors in thememory cell701, a process can be simplified. Further, for example, when the active layer of thetransistor721 functioning as a memory element is formed using a semiconductor which provides higher mobility than an oxide semiconductor, such as polycrystalline silicon or single crystal silicon, image data can be read from thememory cell701 at high speed.

Thememory cell701 inFIG. 7C differs from thememory cell701 inFIG. 7B in that one data line DL has functions of the first data line DLa and the second data line DLb. Specifically, thememory cell701 inFIG. 7C includes thetransistor703 functioning as a switching element, atransistor723, and acapacitor724. The gate electrode of thetransistor703 is connected to the first word line WLa. The first terminal of thetransistor703 is connected to the data line DL. The second terminal of thetransistor703 is connected to a gate electrode of thetransistor723. A first terminal of thetransistor723 is connected to the data line DL. A second terminal of thetransistor723 is connected to a node to which a predetermined potential is applied. One of a pair of electrodes of thecapacitor724 is connected to the gate electrode of thetransistor723. The other of the pair of electrodes of thecapacitor724 is connected to the second word line WLb.

Thememory cell701 inFIG. 7C can perform operation such as writing, retention, and reading of image data in a manner similar to that of thememory cell701 inFIG. 7B.

A wide-bandgap semiconductor such as an oxide semiconductor may be used for an active layer of thetransistor723. Alternatively, for the active layer of thetransistor723, any of the following semiconductors may be used: amorphous silicon, microcrystalline silicon, polycrystalline silicon, single crystal silicon, amorphous germanium, microcrystalline germanium, polycrystalline germanium, and single crystal germanium. When oxide semiconductor films are used for active layers of all the transistors in thememory cell701, a process can be simplified. Further, for example, when the active layer of thetransistor723 is formed using a semiconductor which provides higher mobility than an oxide semiconductor, such as polycrystalline silicon or single crystal silicon, image data can be read from thememory cell701 at high speed.

The storage device including any of thememory cells701 inFIGS. 7A to 7C has higher speed of writing and reading image data than a general nonvolatile storage device such as a flash memory; thus, the storage device is suited for an image memory that needs to operate at high speed.

Further, the storage device including any of thememory cells701 inFIGS. 7A to 7C can retain image data for a long period. Thus, in the case where the storage device is used as an image memory, image data in the image memory is not easily lost even when supply of power supply voltage to a semiconductor display device is stopped. Thus, in the case where images to be displayed are the same before the stop of supply of power supply voltage and after the restart of supply of power supply voltage, it is not necessary to read image data again after the restart of supply of power supply voltage. Accordingly, power consumption can be reduced.

This embodiment can be combined with any of the other embodiments as appropriate.

REFERENCE NUMERALS

10: sequential logic unit,31: transistor,32: transistor,33: transistor,34: transistor,35: transistor,36: transistor,37: transistor,38: transistor,39: transistor,40: transistor,41: transistor,61: selection period,62: non-selection period,100: semiconductor display device,101: CPU,102: power supply controller,103: panel controller,104: image memory,105: panel,106: pixel portion,107: driver circuit,108: signal line driver circuit,109: scan line driver circuit,110: storage device,120: consumed power,121: consumed power,122: consumed power,130: pixel,131: transistor,132: liquid crystal element,133: capacitor,200: memory element,201: memory circuit,202: memory circuit,203: switch,204: switch,205: switch,206: logic element,207: capacitor,208: capacitor,209: transistor,210: transistor,213: transistor,214: transistor,221: switching element,222: memory element group,250: memory element,251: memory circuit,252: memory circuit,253a: logic element,253b: logic element,254: transistor,255: transistor,256: capacitor,257: transistor,258: p-channel transistor,259: n-channel transistor,260: p-channel transistor,261: n-channel transistor,500: substrate,501: conductive film,502: conductive film,503: conductive film,504: conductive film,505: pixel electrode,506: gate insulating film,507: active layer,508: insulating film,509: insulating film,510: spacer,512: insulating film,513: insulating film,514: substrate,515: common electrode,516: liquid crystal layer,517: light-blocking film,600: CPU,601: controller,602: ALU,603: data cache,604: instruction cache,605: program counter,606: instruction register,607: main storage device,608: register file,701: memory cell,703: transistor,720: capacitor,721: transistor,722: capacitor,723: transistor,724: capacitor,5001: housing,5002: housing,5003: display portion,5004: display portion,5005: microphone,5006: speaker,5007: operation key,5008: stylus,5201: housing,5202: display portion,5203: support,5401: housing,5402: display portion,5403: keyboard,5404: pointing device,5601: housing,5602: housing,5603: display portion,5604: display portion,5605: hinge,5606: operation key,5801: housing,5802: housing,5803: display portion,5804: operation key,5805: lens, and5806: hinge.

This application is based on Japanese Patent Application serial No. 2011-261970 filed with Japan Patent Office on Nov. 30, 2011, the entire contents of which are hereby incorporated by reference.

Claims (12)

The invention claimed is:

1. A semiconductor display device comprising:

a pixel portion comprising a display element and a first transistor;

a driver circuit; and

a CPU comprising:

a first memory circuit comprising a first volatile memory, and

a second memory circuit comprising a first nonvolatile memory, the first nonvolatile memory comprising a second transistor and a first capacitor,

wherein one of a source terminal and a drain terminal of the second transistor is electrically connected to an output terminal of the first memory circuit,

wherein the other of the source terminal and the drain terminal of the second transistor is electrically connected to one electrode of the first capacitor,

wherein the pixel portion is configured to display a still image after the driver circuit stops supplying an image signal to the pixel portion,

wherein the second memory circuit is configured to store data stored in the first memory circuit before the CPU stops, and

wherein each of the first transistor and the second transistor comprises a semiconductor whose bandgap is wider than bandgap of silicon in a channel formation region.

2. The semiconductor display device according toclaim 1, wherein the semiconductor is an oxide semiconductor.

3. The semiconductor display device according toclaim 2, wherein the oxide semiconductor comprises at least one of In, Ga, and Zn.

4. The semiconductor display device according toclaim 1, further comprising:

a third memory circuit comprising a second volatile memory, and

a fourth memory circuit comprising a second nonvolatile memory, the second nonvolatile memory comprising a third transistor and a second capacitor,

wherein one of a source terminal and a drain terminal of the third transistor is electrically connected to an output terminal of the third memory circuit,

wherein the other of the source terminal and the drain terminal of the third transistor is electrically connected to one electrode of the second capacitor, and

wherein the output terminal of the first memory circuit is electrically connected to an input terminal of the third memory circuit.

5. A semiconductor display device comprising:

a pixel portion comprising a display element and a first transistor;

a driver circuit; and

a CPU comprising:

a first memory circuit comprising a first volatile memory, and

a second memory circuit comprising a first nonvolatile memory, the first nonvolatile memory comprising a second transistor and a first capacitor,

wherein one of a source terminal and a drain terminal of the second transistor is electrically connected to an output terminal of the first memory circuit,

wherein the other of the source terminal and the drain terminal of the second transistor is electrically connected to one electrode of the first capacitor,

wherein the pixel portion is configured to display a still image after the driver circuit stops supplying an image signal to the pixel portion,

wherein the second memory circuit is configured to store data stored in the first memory circuit before the CPU stops,

wherein the second memory circuit is configured to retain the data while the CPU stops, respectively, and

wherein each of the first transistor and the second transistor comprises a semiconductor whose bandgap is wider than bandgap of silicon in a channel formation region.

6. The semiconductor display device according toclaim 5, wherein the semiconductor is an oxide semiconductor.

7. The semiconductor display device according toclaim 6, wherein the oxide semiconductor comprises at least one of In, Ga, and Zn.

8. The semiconductor display device according toclaim 5, further comprising:

a third memory circuit comprising a second volatile memory, and

a fourth memory circuit comprising a second nonvolatile memory, the second nonvolatile memory comprising a third transistor and a second capacitor,

wherein one of a source terminal and a drain terminal of the third transistor is electrically connected to an output terminal of the third memory circuit,

wherein the other of the source terminal and the drain terminal of the third transistor is electrically connected to one electrode of the second capacitor, and

wherein the output terminal of the first memory circuit is electrically connected to an input terminal of the third memory circuit.

9. A semiconductor display device comprising:

a pixel portion comprising a display element and a first transistor;

a driver circuit; and

a CPU comprising:

a first memory circuit comprising a first volatile memory, and

a second memory circuit comprising a first nonvolatile memory, the first nonvolatile memory comprising a second transistor and a first capacitor,

wherein one of a source terminal and a drain terminal of the second transistor is electrically connected to an output terminal of the first memory circuit,

wherein the other of the source terminal and the drain terminal of the second transistor is electrically connected to one electrode of the first capacitor,

wherein the pixel portion is configured to display a still image after the driver circuit stops supplying an image signal to the pixel portion,

wherein the second memory circuit is configured to store data stored in the first memory circuit before the CPU stops, and to recover the data to the first memory circuit after the CPU restarts, and

wherein each of the first transistor and the second transistor comprises a semiconductor whose bandgap is wider than bandgap of silicon in a channel formation region.

10. The semiconductor display device according toclaim 9, wherein the semiconductor is an oxide semiconductor.

11. The semiconductor display device according toclaim 10, wherein the oxide semiconductor comprises at least one of In, Ga, and Zn.

12. The semiconductor display device according toclaim 9, further comprising:

a third memory circuit comprising a second volatile memory, and

a fourth memory circuit comprising a second nonvolatile memory, the second nonvolatile memory comprising a third transistor and a second capacitor,

wherein one of a source terminal and a drain terminal of the third transistor is electrically connected to an output terminal of the third memory circuit,

wherein the other of the source terminal and the drain terminal of the third transistor is electrically connected to one electrode of the second capacitor, and

wherein the output terminal of the first memory circuit is electrically connected to an input terminal of the third memory circuit.

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