CLAIM OF PRIORITYThis patent application is a continuation of U.S. patent application Ser. No. 13/755,972 filed Jun. 19, 2013 now U.S. Pat. No. 8,744,003, which makes reference to, claims priority to and claims benefit from:
- U.S. Provisional Patent Application Ser. No. 61/662,085 entitled “Apparatus and Method for Efficient Utilization of Bandwidth” and filed on Jun. 20, 2012, now expired;
- U.S. Provisional Patent Application Ser. No. 61/726,099 entitled “Modulation Scheme Based on Partial Response” and filed on Nov. 14, 2012, now expired;
- U.S. Provisional Patent Application Ser. No. 61/729,774 entitled “Modulation Scheme Based on Partial Response” and filed on Nov. 26, 2012, now expired; and
- U.S. Provisional Patent Application Ser. No. 61/747,132 entitled “Modulation Scheme Based on Partial Response” and filed on Dec. 28, 2012, now expired.
Each of the above-identified applications is hereby incorporated herein by reference in its entirety.
INCORPORATION BY REFERENCEThis patent application also makes reference to:
- U.S. Pat. No. 8,582,637, titled “Low-Complexity, Highly-Spectrally-Efficient Communications,” and filed on Jan. 31, 2013; and
- U.S. patent application Ser. No. 13/756,010, titled “Multi-Mode Receiver for Highly-Spectrally-Efficient Communications,” and filed on Jan. 31, 2013.
Each of the above stated applications is hereby incorporated herein by reference in its entirety.
TECHNICAL FIELDAspects of the present application relate to electronic communications.
BACKGROUNDExisting communications methods and systems are overly power hungry and/or spectrally inefficient. Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such approaches with some aspects of the present method and system set forth in the remainder of this disclosure with reference to the drawings.
BRIEF SUMMARYMethods and systems are provided for low-complexity, highly-spectrally efficient communications, substantially as illustrated by and/or described in connection with at least one of the figures, as set forth more completely in the claims.
BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1A is a block diagram depicting an example system configured for low-complexity, highly-spectrally-efficient communications.
FIG. 1B is a block diagram illustrating a multi-mode transmitter operable to support low-complexity, highly-spectrally-efficient communications.
FIG. 1C is a block diagram illustrating a multi-mode receiver operable to support low-complexity, highly-spectrally-efficient communications.
FIG. 2 is a block diagram depicting an example equalization and sequence estimation circuit for use in a system configured for low-complexity, highly-spectrally-efficient communications.
FIG. 3 is a block diagram depicting an example sequence estimation circuit for use in a system configured for low-complexity, highly-spectrally-efficient communications.
FIG. 4 is a block diagram depicting an example metric calculation circuit for use in a system configured for low-complexity, highly-spectrally-efficient communications.
FIGS. 5A-5D depict portions of an example sequence estimation process performed by a system configured for low-complexity, highly-spectrally-efficient communications.
FIGS. 6A and 6B depict an example survivor selection process that is an alternative to the process depicted inFIG. 5D.
FIG. 7 is a diagram illustrating initialization of the sequence estimation process.
FIG. 8A depicts an example implementation of the phase buffer shown inFIG. 3.
FIG. 8B depicts an example implementation of the symbol buffer shown inFIG. 3.
FIG. 8C depicts contents of an example symbol buffer over a plurality of iterations of a sequence estimation process.
FIG. 8D depicts generated signals corresponding to the symbol buffer contents shown inFIG. 8C.
FIG. 9 is a flowchart illustrating dynamic configuration of a multi-mode transmitter.
FIG. 10 compares between Symbol Error Rate (SER) vs. SNR of the receiver configured intomode 1 of table 2 and configured intomode 2 of table 2.
DETAILED DESCRIPTIONAs utilized herein the terms “circuits” and “circuitry” refer to physical electronic components (i.e. hardware) and any software and/or firmware (“code”) which may configure the hardware, be executed by the hardware, and or otherwise be associated with the hardware. As used herein, for example, a particular processor and memory may comprise a first “circuit” when executing a first one or more lines of code and may comprise a second “circuit” when executing a second one or more lines of code. As utilized herein, “and/or” means any one or more of the items in the list joined by “and/or”. As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. As utilized herein, the term “exemplary” means serving as a non-limiting example, instance, or illustration. As utilized herein, the terms “e.g.,” and “for example” set off lists of one or more non-limiting examples, instances, or illustrations. As utilized herein, circuitry is “operable” to perform a function whenever the circuitry comprises the necessary hardware and code (if any is necessary) to perform the function, regardless of whether performance of the function is disabled, or not enabled, by some user-configurable setting.
FIG. 1A is a block diagram depicting an example system configured for low-complexity, highly-spectrally-efficient communications. Thesystem100 comprises amapper circuit102, a pulse shapingfilter circuit104, a timingpilot insertion circuit105, a transmitter front-end circuit106, achannel107, a receiver front-end108, afilter circuit109, a timingpilot removal circuit110, an equalization andsequence estimation circuit112, and ade-mapping circuit114. Thecomponents102,104,105, and106 may be part of a transmitter (e.g., a base station or access point, a router, a gateway, a mobile device, a server, a computer, a computer peripheral device, a table, a modem, a set-top box, etc.), thecomponents108,109,110,112, and114 may be part of a receiver (e.g., a base station or access point, a router, a gateway, a mobile device, a server, a computer, a computer peripheral device, a table, a modem, a set-top box, etc.), and the transmitter and receiver may communicate via thechannel107.
Themapper102 may be operable to map bits of the Tx_bitstream to be transmitted to symbols according to a selected modulation scheme. The symbols may be output viasignal103. For example, for an quadrature amplitude modulation scheme having a symbol alphabet of N (N-QAM), the mapper may map each Log2(N) bits of the Tx_bitstream to single symbol represented as a complex number and/or as in-phase (I) and quadrature-phase (Q) components. Although N-QAM is used for illustration in this disclosure, aspects of this disclosure are applicable to any modulation scheme (e.g., amplitude shift keying (ASK), phase shift keying (PSK), frequency shift keying (FSK), etc.). Additionally, points of the N-QAM constellation may be regularly spaced (“on-grid”) or irregularly spaced (“off-grid”). Furthermore, the symbol constellation used by the mapper may be optimized for best bit-error rate performance that is related to log-likelihood ratio (LLR) and to optimizing mean mutual information bit (MMIB). The Tx_bitstream may, for example, be the result of bits of data passing through a forward error correction (FEC) encoder and/or an interleaver. Additionally, or alternatively, the symbols out of themapper102 may pass through an interleaver.
Thepulse shaper104 may be operable to adjust the waveform of thesignal103 such that the waveform of the resultingsignal113 complies with the spectral requirements of the channel over which thesignal113 is to be transmitted. The spectral requirements may be referred to as the “spectral mask” and may be established by a regulatory body (e.g., the Federal Communications Commission in the United States or the European Telecommunications Standards Institute) and/or a standards body (e.g., Third Generation Partnership Project) that governs the communication channel(s) and/or standard(s) in use. Thepulse shaper104 may comprise, for example, an infinite impulse response (IIR) and/or a finite impulse response (FIR) filter. The number of taps, or “length,” of thepulse shaper104 is denoted herein as LTx, which is an integer. The impulse response of thepulse shaper104 is denoted herein as hTx. Thepulse shaper104 may be configured such that itsoutput signal113 intentionally has a substantial amount of inter-symbol interference (ISI). Accordingly, thepulse shaper104 may be referred to as a partial response pulse shaping filter, and thesignal113 may be referred to as a partial response signal or as residing in the partial response domain, whereas thesignal103 may be referred to as residing in the symbol domain. The number of taps and/or the values of the tap coefficients of thepulse shaper104 may be designed such that thepulse shaper104 is intentionally non-optimal for additive white Gaussian noise (AWGN) in order to improve tolerance of non-linearity in the signal path. In this regard, thepulse shaper104 may offer superior performance in the presence of non-linearity as compared to, for example, a conventional near zero positive ISI pulse shaping filter (e.g., root raised cosine (RRC) pulse shaping filter). Thepulse shaper104 may be designed as described in one or more of: the United States patent application titled “Design and Optimization of Partial Response Pulse Shape Filter,” the United States patent application titled “Constellation Map Optimization For Highly Spectrally Efficient Communications,” and the United States patent application titled “Dynamic Filter Adjustment For Highly-Spectrally-Efficient Communications,” each of which is incorporated herein by reference, as set forth above.
It should be noted that a partial response signal (or signals in the “partial response domain”) is just one example of a type of signal for which there is correlation among symbols of the signal (referred to herein as “inter-symbol-correlated (ISC) signals”). Such ISC signals are in contrast to zero (or near-zero) ISI signals generated by, for example, raised-cosine (RC) or root-raised-cosine (RRC) filtering. For simplicity of illustration, this disclosure focuses on partial response signals generated via partial response filtering. Nevertheless, aspects of this disclosure are applicable to other ISC signals such as, for example, signals generated via matrix multiplication (e.g., lattice coding), and signals generated via decimation below the Nyquist frequency.
The timingpilot insertion circuit105 may insert a pilot signal which may be utilized by the receiver for timing synchronization. Theoutput signal115 of the timingpilot insertion circuit105 may thus comprise thesignal113 plus an inserted pilot signal (e.g., a sine wave at ¼×fbaud, where fbaud is the symbol rate). An example implementation of thepilot insertion circuit105 is described in the United States patent application titled “Timing Synchronization for Reception of Highly-Spectrally-Efficient Communications,” which is incorporated herein by reference, as set forth above.
The transmitter front-end106 may be operable to amplify and/or upconvert thesignal115 to generate thesignal116. Thus, the transmitter front-end106 may comprise, for example, a power amplifier and/or a mixer. The front-end may introduce non-linear distortion and/or phase noise (and/or other non-idealities) to thesignal116. The non-linearity of thecircuit106 may be represented as FnlTx which may be, for example, a polynomial, or an exponential (e.g., Rapp model). The non-linearity may incorporate memory (e.g., Voltera series).
Thechannel107 may comprise a wired, wireless, and/or optical communication medium. Thesignal116 may propagate through thechannel107 and arrive at the receive front-end108 assignal118.Signal118 may be noisier than signal116 (e.g., as a result of thermal noise in the channel) and may have higher or different ISI than signal116 (e.g., as a result of multi-path).
The receiver front-end108 may be operable to amplify and/or downconvert thesignal118 to generate thesignal119. Thus, the receiver front-end may comprise, for example, a low-noise amplifier and/or a mixer. The receiver front-end may introduce non-linear distortion and/or phase noise to thesignal119. The non-linearity of thecircuit108 may be represented as FnlRx which may be, for example, a polynomial, or an exponential (e.g., Rapp model). The non-linearity may incorporate memory (e.g., Voltera series).
The timing pilot recovery andremoval circuit110 may be operable to lock to the timing pilot signal inserted by thepilot insertion circuit105 in order to recover the symbol timing of the received signal. Theoutput122 may thus comprise thesignal120 minus (i.e., without) the timing pilot signal. An example implementation of the timing pilot recovery andremoval circuit110 is described in the United States patent application titled “Timing Synchronization for Reception of Highly-Spectrally-Efficient Communications,” which is incorporated herein by reference, as set forth above.
The input filter
109 may be operable to adjust the waveform of the partial response signal
119 to generate partial response signal
120. The input filter
109 may comprise, for example, an infinite impulse response (IIR) and/or a finite impulse response (FIR) filter. The number of taps, or “length,” of the input filter
109 is denoted herein as LRx, an integer. The impulse response of the input filter
109 is denoted herein as hRx. The number of taps, and/or tap coefficients of the input filter
109 may be configured based on: a non-linearity model,
, signal-to-noise ratio (SNR) of
signal120, the number of taps and/or tap coefficients of the Tx
partial response filter104, and/or other parameters. The number of taps and/or the values of the tap coefficients of the
input filter109 may be configured such that noise rejection is intentionally compromised (relative to a perfect match filter) in order to improve performance in the presence of non-linearity. As a result, the
input filter109 may offer superior performance in the presence of non-linearity as compared to, for example, a conventional near zero positive ISI matching filter (e.g., root raised cosine (RRC) matched filter). The
input filter109 may be designed as described in one or more of: the United States patent application titled “Design and Optimization of Partial Response Pulse Shape Filter,” the United States patent application titled “Constellation Map Optimization For Highly Spectrally Efficient Communications,” and the United States patent application titled “Dynamic Filter Adjustment For Highly-Spectrally-Efficient Communications,” each of which is incorporated herein by reference, as set forth above.
As utilized herein, the “total partial response (h)” may be equal to the convolution of hTx and hRx, and, thus, the “total partial response length (L)” may be equal to LTx+LRx−1. L may, however, be chosen to be less than LTx+LRx−1 where, for example, one or more taps of theTx pulse shaper104 and/or theRx input filter109 are below a determined level. Reducing L may reduce decoding complexity of the sequence estimation. This tradeoff may be optimized during the design of thesystem100.
The equalizer andsequence estimator112 may be operable to perform an equalization process and a sequence estimation process. Details of an example implementation of the equalizer andsequence estimator112 are described below with respect toFIG. 2. Theoutput signal132 of the equalizer andsequence estimator112 may be in the symbol domain and may carry estimated values of corresponding transmitted symbols (and/or estimated values of the corresponding transmitted information bits of the Tx_bitstream) ofsignal103. Although not depicted, thesignal132 may pass through an interleaver en route to the de-mapper114. The estimated values may comprise soft-decision estimates, hard-decision estimates, or both.
The de-mapper114 may be operable to map symbols to bit sequences according to a selected modulation scheme. For example, for an N-QAM modulation scheme, the mapper may map each symbol to Log2(N) bits of the Rx_bitstream. The Rx_bitstream may, for example, be output to a de-interleaver and/or an FEC decoder. Alternatively, or additionally, the de-mapper114 may generate a soft output for each bit, referred as LLR (Log-Likelihood Ratio). The soft output bits may be used by a soft-decoding forward error corrector (e.g. a low-density parity check (LDPC) dedecoder). The soft output bits may be generated using, for example, a Soft Output Viterbi Algorithm (SOVA) or similar. Such algorithms may use additional information of the sequence decoding process including metrics levels of dropped paths and/or estimated bit probabilities for generating the LLR, where
where Pbis the probability that bit b=1.
In an example implementation, components of the system upstream of thepulse shaper104 in the transmitter and downstream of the equalizer andsequence estimator112 in the receiver may be as found in a conventional N-QAM system. Thus, through modification of the transmit side physical layer and the receive side physical layer, aspects of the invention may be implemented in an otherwise conventional N-QAM system in order to improve performance of the system in the presence of non-linearity as compared, for example, to use of RRC filters and an N-QAM slicer.
FIG. 1B is a block diagram illustrating a multi-mode transmitter operable to support low-complexity, highly-spectrally-efficient communications. Shown inFIG. 1B, are a forward error correction (FEC)encoder156, themapper102, an inter-symbol correlation (ISC)generation circuit158, the timingpilot insertion circuit105, the transmitter front-end circuit106, a clocksignal generation circuit152, and acontrol circuit154.
The clocksignal generation circuit152 may comprise, for example, one or more oscillators (e.g., a crystal oscillator) and one or more phase locked loops (PLLs) for generating aclock signal156 whose frequency determines the rate at which symbols are generated and transmitted by the transmitter (the “symbol rate” or “baud rate”). The frequency of theclock signal156 may be based on the mode of operation of the transmitter (e.g., as indicated by control signal158).
Thecontrol circuit154 may comprise, for example, an application specific integrated circuit (ASIC), a programmable interrupt controller (PIC), an ARM-based processor, an x86-based processor, and/or any other suitable circuitry operable to control a configuration of the transmitter based on one or more parameters. The parameters on which the configuration of the transmitter may be based may include, for example, input from a user of, and/or software application running on, a device (e.g., a mobile phone, laptop, base station, or the like) in which the transmitter resides. The parameters on which the configuration of the transmitter may be based may include performance indicators measured by circuitry of the transmitter such as, for example, measured noise levels, temperature, battery charge level, etc. The parameters on which the configuration of the transmitter may be based may include, for example, characteristics of data to be transmitted. Such characteristics may include, for example, quality of service parameters (e.g., latency and/or throughput requirements) and/or a model of non-linear distortion that the data will experience en route to a receiver. The parameters on which the configuration of the transmitter may be based may include performance indicators measured by and fed back from a receiver. Such performance indicators may include, for example, symbol error rate (SER), bit error rate (BER), signal-to-noise ratio (SNR), metrics calculated by a sequence estimation circuit, a phase error measured by the receiver, a measurement indicative of multipath present in the channel, and/or any other relevant performance indicator. Thecontrol circuit154 may indicate a mode of operation of the transmitter and/or control configuration of the various components of the transmitter via thecontrol signal158.
Thecontrol circuit154 may also be operable to generate control messages that indicate a configuration of the transmitter. Such control messages may be, for example, inserted into the transmitted datastream and/or transmitted on a control channel of beacon signal, to inform the receiver of the configuration of the receiver. Such control messages may be used by a multi-mode receiver for configuration of its circuitry.
TheFEC encoder156 may be perform FEC encoding according to one or more algorithms such as Reed-Solomon, or low-density parity check (LDPC) algorithms. The FEC code rate and/or the encoding algorithm used may be determined based on the mode of operation of the transmitter (e.g., as indicated by control signal158). For example, FEC type (e.g., LDPC, RS, etc.) may be switched to match the modulation type and FEC rate may be optimized to increase capacity based on the mode of operation of the transmitter. In some cases of iterative FEC codes (e.g., LDPC, turbo), the code structure may vary to utilize the statistical characteristics of the partial response signal errors. FEC decoding performance may be improved through dynamic selection of the appropriate error model.
Themapper102 may be as described above with reference toFIG. 1A, for example. A symbol constellation in use by themapper102 may be determined based on the mode of operation of the transmitter (e.g., as indicated by control signal158). The rate at which bits are mapped to symbols may be determined based on theclock signal156. In an example embodiment of the disclosure, themapper102 may be operable to insert one or more pilot symbols (e.g., a particular pattern of pilot symbols) into a generated symbol sequence. In an example embodiment, the pilot symbol(s) may be inserted in a deterministic manner (e.g., periodically and/or on an event-driven basis) such that a receiver of the signal may know, or be able to autonomously determine, that the symbols are pilot symbols and not information symbols (information symbols being symbols generated from data bits input to the mapper102). In an example implementation, a common symbol constellation may be used for both the pilot symbols and the information symbols. In another example implementation, a first symbol constellation (e.g., a 32QAM-based PR10 constellation) may be used for information symbols and a second symbol constellation (e.g., a BPSK or QPSK constellation) may be used for pilot symbols.
The pilot overhead (POH) (i.e., the percentage of all transmitted symbols that are pilot symbols) and pattern of pilot symbols may be adapted dynamically (e.g., at or near real-time, based on recent measurements and/or feedback and/or user input) according to one or more performance indicators (e.g., SNR, SER, metrics levels calculated bymodule204, amount of multipath, etc.) of thechannel108. When the transmitter is configured for near zero positive ISI, pilot symbols may be spread in time such that a single pilot is inserted for every N information symbols. In this manner, the pilot symbols may support the carrier recovery loop in the presence of phase noise and may prevent cycle slips by providing side information on the phase error present at the time of transmission of the pilot symbol. However, when the transmitter is configured in a mode that generates ISC signals whose values are, at any given time, based on a plurality of symbols, it may be advantageous to use several adjacent (or closely distributed) pilot symbols in order to provide efficient side information for the phase. Thus, symbol pilots when the transmitter is in a ISC mode, may be use a pattern of inserting group of M pilot symbols for every N information symbols, where the M symbols may be perfectly cascaded (i.e., no information symbol in between pilots) or, information symbol(s) may be inserted between some of the pilot symbols consisting the group of M. For example, the transmitter may insert 1 pilot symbol between every N information symbols when configured in a first mode of operation, andinsert 2 or more consecutive pilot symbols between every N information symbols when configured in a second mode of operation.
A configuration of theISC generation circuit158 may be determined based on the mode of operation of the transmitter (e.g., as indicated by control signal158). In a first configuration, theISC generation circuit158 may be configured to generate ISC signals. For example, in a first configuration theISC generation circuit158 may correspond to, and operate as, thepulse shaper104 described herein with reference to FIGS.1A and2-8D. In a second configuration, theISC generation circuit158 may be configured as a near zero positive ISI pulse shaping filter (e.g., may be configured based on, or to approximate, a root raised cosine (RRC) pulse shaping filter). The first configuration may correspond to a first number of filter taps and/or a first set of tap coefficients. The second configuration may correspond to a second number of filter taps and/or a second set of tap coefficients. As another example, the first configuration of theISC generation circuit158 may be one in which it perform decimation below the Nyquist frequency such that aliasing results in an ISC signal. As another example, the first configuration of the ISC generation circuit158 may be one in which it performs lattice coding resulting in an ISC signal.
The timingpilot insertion circuit105 may be as described above with reference toFIG. 1A, for example. In an example implementation, the sub-harmonic of the symbol frequency at which the pilot is inserted may be determined based on the mode of operation of the transmitter (e.g., as indicated by control signal158). That is, if the timing pilot is inserted at Fbaud/D, the value of D may be controlled based on the mode of operation of the transmitter (e.g., as indicated by control signal158). Additionally, the power of the inserted pilot signal may be controlled based on the mode of operation of the transmitter (e.g., as indicated by control signal158). Relatedly, the timingpilot insert circuit105 may be enabled and disabled based on the mode of operation of the transmitter (e.g., as indicated by control signal158).
The Tx front-end106 may be as described above with reference toFIG. 1A. Different configurations of the front-end106 may correspond, for example, to different power back-off settings of an amplifier of the front-end106. A larger power back-off may correspond to an operating point further away from a reference point (e.g., 1-dB compression point) than an operating point corresponding to a smaller power back-off. Consequently, a larger power back-off setting may correspond to increased linearity at the expense of decreased transmitted power and energy efficiency.
In operation, the transmitter may support a plurality of modes, with each of the modes corresponding to a particular configuration of each of themapper102,ISC generation circuit158, timingpilot insert circuit105, Tx Front-End circuit106, andclock152. The transmitter may be configured dynamically (e.g., at or near real-time, based on recent measurements and/or feedback and/or user input). In an example implementation, the transmitter may support the two modes characterized by the parameters shown in table 1,
| TABLE 1 | 
|  | 
|  | Mapper | ISC generation | Clock | Pilot insert | Front-end | 
| Mode | 
|  | 102 | circuit 158 | 152 | 105 | 106 | 
|  | 
| 1 | N-QAM | RRC, BW1 | Fb1 | Fb1/D | P1> PBO1 > P2 | 
| 2 | M-QAM | PR, BW2 | Fb2 | Fb2/D | P1> PBO2 > P3 | 
|  | 
where N and M are integers; D is a real number; F
b1is baud rate in
mode 1; F
b2is the baud rate in
mode 2; PBO1 is the power back-off setting of an amplifier of the front-
end106 in
mode 1; PBO2 is the power back-off setting of the amplifier of the front-
end106 in
mode 2; and P
1, P
2and P
3are three back-off limits where P
1>P
2>P
3such that P
1corresponds to an operating point that is further from a reference point than an operating point corresponding to P
2, and P
2corresponds to an operating point that is further from the reference point than an operating point corresponding to P
3(i.e., P
3results in higher transmitted power and more non-linear distortion than P
2, and P
2results in higher transmitted power and more non-linear distortion than P
1). In such an implementation, the
mapper102,
ISC generation circuit158,
clock152,
pilot insert circuit105, and front-
end106 may be configured such that the two modes in table 1 achieve the same throughput in the same bandwidth (i.e., same spectral efficiency) but with different symbol constellations. That is,
mode 1 may achieve a particular throughput using an N-QAM constellation, RRC pulse shape filtering with an effective bandwidth of BW1, a first baud rate F
b1, and an amplifier setting with lower non-linear distortion, whereas
mode 2 may achieve the throughput using a M-QAM symbol constellation (N>M), partial response (PR) pulse shape filtering with effective bandwidth of BW2=BW1, a second baud rate F
b2=log 2(N)/log 2(M)×F
b1, and an amplifier setting with higher non-linear distortion.
In an example implementation, M=N (i.e., the two modes use the same constellation), BW2=BW1/X, Fb1=Fb2(i.e., the two modes use the same baud rate), and PBO1=PBO2 (i.e., the two modes use the same power back-off setting of an amplifier), andmode 2 achieves the same throughput asmode 1, but using a factor of X less bandwidth, as a result of the increased spectral efficiency ofmode 2.
FIG. 1C is a block diagram illustrating a multi-mode receiver operable to support low-complexity, highly-spectrally-efficient communications. Shown inFIG. 1C, are the Rx Front-end108, theRx filter109, the timingpilot removal circuit110, the equalization andsequence estimation circuit112, acontrol circuit174, and anFEC decoder circuit176.
Thecontrol circuit174 may comprise, for example, an application specific integrated circuit (ASIC), a programmable interrupt controller (PIC), an ARM-based processor, an x86-based processor, and/or any other suitable circuitry operable to control a configuration of the receiver based on one or more parameters. The parameters on which the configuration of the receiver may be based may include, for example, input from a user of, and/or software application running on, a device (e.g., a mobile phone, laptop, base station, or the like) in which the receiver resides. The parameters on which the configuration of the receiver may be based may include performance indicators measured by circuitry of the receiver such as, for example, measured noise levels, temperature, battery charge level, symbol error rate (SER), bit error rate (BER), signal-to-noise ratio (SNR), metrics calculated by a sequence estimation circuit, a non-linear model in use by the receiver, a phase error measured by the receiver, a measurement indicative of an amount of multipath in the channel, and/or any other relevant performance indicator. The parameters on which the configuration of the receiver may be based may include characteristics of data to be received. Such characteristics may include, for example, quality of service parameters (e.g., latency and/or throughput requirements) and/or a model of non-linear distortion experienced by the data during transmission, propagation over the channel, and/or reception by the receiver. The parameters on which the configuration of the receiver may be parameters communicated (e.g., in a beacon signal) by a transmitter from which the receiver desires to receive communications. Such parameters may include, for example, power back-off (and/or other indications of non-linearity) symbol constellation in use, type of pulse shape filtering in use, baud rate, etc. The parameters on which the configuration of the receiver may be based may include a mode of operation of a transmitter from which the receiver desires to receive communications. Such mode of operation may, for example, be communicated to the receiver in a control message (e.g., in a beacon signal) and relayed to thecontrol circuit174.
Thecontrol circuit174 may also be operable to generate control messages that indicate a configuration of the receiver. Such control messages may be, for example, inserted into the transmitted datastream and/or transmitted on a control channel of beacon signal, to provide feedback to a transmitter. Such control messages may be used by a multi-mode transmitter for configuration of its circuitry.
The timingpilot removal circuit110 may be as described above and may, for example, comprise one or more phase locked loops (PLLs) for recovering the symbol timing of received signals and outputting a clock signal determined by the recovered symbol timing.
The Rx front-end108 may be as described above with reference toFIG. 1A, for example. Different configurations of the front-end108 may correspond, for example, to different combination of power back-off settings of amplifiers and/or attenuators of the front-end108. A larger power back-off may correspond to an operating point further away from a reference point (e.g., 1-dB compression point) than an operating point corresponding to a smaller power back-off. Consequently, a larger power back-off setting may correspond to increased linearity at the expense of decreased energy efficiency and/or increased noise figure.
A configuration of theRx filter109 may be determined based on the mode of operation of the receiver (e.g., as indicated by the control signal178). In a first configuration, theRx filter109 may operate as described herein with reference to FIGS.1A and2-8D. That is, in a first configuration, theRx filter109 may be configured to achieve a desired total partial response. In a second configuration, however, theRx filter109 may be configured as a near zero positive ISI pulse shaping filter (e.g., root raised cosine (RRC) pulse shaping filter). The first configuration may correspond to a first number of filter taps and/or a first set of tap coefficients. The second configuration may correspond to a second number of filter taps and/or a second set of tap coefficients.
A configuration of the equalization andsequence estimation circuit112 may be determined based on the mode of operation of the receiver (e.g., as indicated by the control signal178). In a first configuration, the equalization andsequence estimation circuit112 may operate as described herein with reference to FIGS.1A and2-8D, for example. That is, in a first configuration, the equalization andsequence estimation circuit112 may detect/estimate sequences of ISC symbols. In a second configuration, however, the equalization andsequence estimation circuit112 may detect/estimate individual symbols (i.e., sequences only one symbol in length). Accordingly, in the second configuration, the equalization andsequence estimation circuit112 may perform slicing and each estimate/decision (hard or soft) may depend only on the current symbol. Thus, configuration of the equalization andsequence estimation circuit112 may be based, for example, on an indication of inter symbol correlation in a received signal. In case of severe channel multipath and/or phase noise that create a correlation between received symbols,circuit112 may be configured for decoding symbols by sequence estimation method to improve decoding performance comparing to symbol-by-symbol slicing/decision.
TheFEC decoder176 may be perform FEC decoding according to one or more algorithms such as Reed-Solomon, or low-density parity check (LDPC) algorithms. The FEC code rate and/or the decoding algorithm used may be determined based on the mode of operation of the transmitter (e.g., as indicated by control signal178). For example, FEC type (e.g., LDPC, RS, etc.) may be switched to match the modulation type and FEC rate may be optimized to increase capacity based on the mode of operation of the transmitter. In some cases of iterative FEC codes (e.g., LDPC, turbo), the code structure may vary to utilize the statistical characteristics of the partial response signal errors. FEC decoding performance may be improved through dynamic selection of the appropriate error model.
In operation, the receiver may support a plurality of modes, with each of the modes corresponding to a particular configuration of each of the Rx Front-end108, theRx filter109, the timingpilot removal circuit110, the equalization andsequence estimation circuit112, and acontrol circuit174. The receiver may be configured dynamically (e.g., at or near real-time, based on recent measurements and/or feedback). In an example implementation, the receiver may support the two modes characterized by the parameters shown in table 2,
| TABLE 2 | 
|  | 
|  | Rx Filter | Clock | Front-end | EQ &Seq | 
| Mode | 
|  | 109 | 152 | 108 | Est. 112 | 
|  | 
| 1 | RRC, BW1 | Fb1 | P4> PBO3 > P5 | Slice | 
| 2 | PR,BW2 | 2 × Fb1 | P4> PBO4 > P6 | Seq. est. | 
|  | 
where F
b1is the baud rate for
mode 1; PBO3 is the power back-off setting of an amplifier of the front-
end108 in
mode 1; PBO4 is the power back-off setting of an amplifier of the front-
end108 in
mode 2; and P
4, P
5and P
6are three back-off limits where P
4>P
5>P
6such that P
4corresponds to an operating point that is further from a reference point than an operating point corresponding to P
5, and P
5corresponds to an operating point that is further from the reference point than an operating point corresponding to P
6(i.e., P
6results in more non-linear distortion than P
5, and P
5results in more non-linear distortion than P
4). In the receiver, there is a tradeoff between linearity and noise figure performance. Allowing high non-linear distortion may enable improving the overall noise figure which, in turn, may improve demodulator sensitivity. Thus, a receiver capable of tolerating severe non-linear distortion may permit configuring that receiver for optimal noise figure.
In such an implementation, the Rx front-end108,Rx filter109, and equalization andsequence estimation circuit112 may be configured such thatmode 2 provides better reception (e.g., lower SER) around the operating SNR (e.g., 30 dB SNR) thanmode 1 for the same throughput and same spectral efficiency. For a given received signal level (RSL), the system atmode 2 may improve SNR comparing tomode 1 due to the ability to tolerate larger non-linear distortion originating at the receiver front-end and consequently decrease the noise figure which increase observed SNR.FIG. 10 depicts SER vs. SNR formodes 1 and 2 under example constraints.
FIG. 2 is a block diagram depicting an example equalization and sequence estimation circuit for use in a system configured for low-complexity, highly-spectrally-efficient communications. Shown are anequalizer circuit202, asignal combiner circuit204, a phase adjustcircuit206, asequence estimation circuit210, andnon-linearity modeling circuits236aand236b.
Theequalizer202 may be operable to process thesignal122 to reduce ISI caused by thechannel107. Theoutput222 of theequalizer202 is a partial response domain signal. The ISI of thesignal222 is primarily the result of thepulse shaper104 and the input filter109 (there may be some residual ISI from multipath, for example, due to use of the least means square (LMS) approach in the equalizer202). The error signal,201, fed back to theequalizer202 is also in the partial response domain. Thesignal201 is the difference, calculated bycombiner204, between222 and apartial response signal203 that is output bynon-linearity modeling circuit236a. An example implementation of the equalizer is described in the United States patent application titled “Feed Forward Equalization for Highly-Spectrally-Efficient Communications,” which is incorporated herein by reference, as set forth above.
Thecarrier recovery circuit208 may be operable to generate asignal228 based on a phase difference between thesignal222 and apartial response signal207 output by thenon-linearity modeling circuit236b. Thecarrier recovery circuit208 may be as described in the United States patent application titled “Coarse Phase Estimation for Highly-Spectrally-Efficient Communications,” which is incorporated herein by reference, as set forth above.
The phase adjustcircuit206 may be operable to adjust the phase of thesignal222 to generate thesignal226. The amount and direction of the phase adjustment may be determined by thesignal228 output by thecarrier recovery circuit208. Thesignal226 is a partial response signal that approximates (up to an equalization error caused by finite length of theequalizer202, a residual phase error not corrected by the phase adjustcircuit206, non-linearities, and/or other non-idealities) the total partial response signal resulting from corresponding symbols ofsignal103 passing throughpulse shaper104 andinput filter109.
Thebuffer212 buffers samples of thesignal226 and outputs a plurality of samples of thesignal226 viasignal232. Thesignal232 is denoted PR1, where the underlining indicates that it is a vector (in this case each element of the vector corresponds to a sample of a partial response signal). In an example implementation, the length of the vector PR1 may be Q samples.
Input to thesequence estimation circuit210 are thesignal232, thesignal228, and a response ĥ. Response ĥ is based on h (the total partial response, discussed above). For example, response ĥ may represent a compromise between h (described above) and a filter response that compensates for channel non-idealities such as multi-path. The response ĥ may be conveyed and/or stored in the form of LTx+LRx−1 tap coefficients resulting from convolution of the LTx tap coefficients of thepulse shaper104 and the LRx tap coefficients of theinput filter109. Alternatively, response h may be conveyed and/or stored in the form of fewer than LTx+LRx−1 tap coefficients—for example, where one or more taps of the LTx and LRx is ignored due to being below a determined threshold. Thesequence estimation circuit210 may output partial response feedback signals205 and209, asignal234 that corresponds to the finely determined phase error of thesignal120, and signal132 (which carries hard and/or soft estimates of transmitted symbols and/or transmitted bits). An example implementation of thesequence estimation circuit210 is described below with reference toFIG. 3.
The
non-linear modeling circuit236amay apply a non-linearity function
 (a model of the non-linearity seen by the received signal en route to the circuit
210) to the
signal205 resulting in the
signal203. Similarly, the
non-linear modeling circuit236bmay apply the non-linearity function
 to the
signal209 resulting in the
signal207.
 may be, for example, a third-order or fifth-order polynomial. Increased accuracy resulting from the use of a higher-order polynomial for
 may tradeoff with increased complexity of implementing a higher-order polynomial. Where FnlTx is the dominant non-linearity of the communication system
100,
 modeling only FnlTx may be sufficient. Where degradation in receiver performance is above a threshold due to other non-linearities in the system (e.g., non-linearity of the receiver front-end
108) the model
 may take into account such other non-linearities
FIG. 3 is a block diagram depicting an example sequence estimation circuit for use in a system configured for low-complexity, highly-spectrally-efficient communications. Shown are acandidate generation circuit302, ametrics calculation circuit304, acandidate selection circuit306, acombiner circuit308, abuffer circuit310, abuffer circuit312, a phase adjustcircuit314, andconvolution circuits316aand316b. The sequence estimation process described with respect toFIG. 3 is an example only. Many variations of the sequence estimation process are also possible. For example, although the implementation described here uses one phase survivor per symbol survivor, another implementation may have PSu (e.g., PSu<Su) phase survivors that will be used commonly for each symbol survivor.
For each symbol candidate at time n, themetrics calculation circuit304 may be operable to generate a metric vector Dn1. . . DnM×Su×Pbased on the partial response signal PR1, thesignal303aconveying the phase candidate vectors PCn1. . . PCnM×Su×Pand thesignal303bconveying the symbol candidate vectors SCn1. . . SCnM×Su×Pwhere underlining indicates a vector, subscript n indicates that it is the candidate vectors for time n, M is an integer equal to the size of the symbol alphabet (e.g., for N-QAM, M is equal to N), Su is an integer equal to the number of symbol survivor vectors retained for each iteration of the sequence estimation process, and P is an integer equal to the size of the phase alphabet. In an example implementation, the size of phase alphabet is three, with each of the three symbols corresponding to one of: a positive shift, a negative phase shift, or zero phase shift, as further described below with respect toFIGS. 5A-5D and in the United States patent application titled “Fine Phase Estimation for Highly Spectrally Efficient Communications,” which is incorporated herein by reference, as set forth above. In an example implementation, each phase candidate vector may comprise Q phase values and each symbol candidate vector may comprise Q symbols. An example implementation of the metrics calculation block is described below with reference toFIG. 4.
Thecandidate selection circuit306 may be operable to select Su of the symbol candidates SCn1. . . SCnM×Su×Pand Su of the phase candidates PCn1. . . PCnM×Su×Pbased on the metrics Dn1. . . DnM×Su×P. The selected phase candidates are referred to as the phase survivors PSn1. . . PSnSu. Each element of each phase survivors PSn1. . . PSnSumay correspond to an estimate of residual phase error in thesignal232. That is, the phase error remaining in the signal after coarse phase error correction via the phase adjustcircuit206. The best phase survivor PSn1is conveyed viasignal307a. The Su phase survivors are retained for the next iteration of the sequence estimation process (at which time they are conveyed viasignal301b). The selected symbol candidates are referred to SSn1. . . SSnSuas the symbol survivors SSn1. . . SSnSu. Each element of each symbol survivors may comprise a soft-decision estimate and/or a hard-decision estimate of a symbol of thesignal232. The best symbol survivor SSn1is conveyed to symbol buffer310 via thesignal307b. The Su symbol survivors are retained for the next iteration of the sequence estimation process (at which time they are conveyed viasignal301a). Although, the example implementation described selects the same number, Su, of phase survivors and symbol survivors, such is not necessarily the case. Operation of examplecandidate selection circuits306 are described below with reference to FIGS.5D and6A-6B.
Thecandidate generation circuit302 may be operable to generate phase candidates PCn1. . . PCnM×Su×Pand symbol candidates SCn1. . . SCnM×Su×Pfrom phase survivors PSn−11. . . PSn−1Suand symbol survivors SSn−11. . . SSn−1Su, wherein the index n−1 indicates that they are survivors from time n−1 are used for generating the candidates for time n. In an example implementation, generation of the phase and/or symbol candidates may be as, for example, described below with reference toFIGS. 5A and 5B and/or in the United States patent application titled “Joint Sequence Estimation of Symbol and Phase with High Tolerance of Nonlinearity,” which is incorporated herein by reference, as set forth above.
Thesymbol buffer circuit310 may comprise a plurality of memory elements operable to store one or more symbol survivor elements of one or more symbol survivor vectors. Thephase buffer circuit312 may comprise a plurality of memory elements operable to store one or more phase survivor vectors. Example implementations of thebuffers310 and312 are described below with reference toFIGS. 8A and 8B, respectively.
Thecombiner circuit308 may be operable to combine the best phase survivor, PSn1, conveyed viasignal307a, with thesignal228 generated by the carrier recovery circuit208 (FIG. 2) to generate fine phase error vector FPEn1, conveyed viasignal309, which corresponds to the finely estimated phase error of the signal222 (FIG. 2). At each time n, fine phase error vector FPEn−11stored inphase buffer312 may be overwritten by FPEn1.
The phase adjustcircuit314 may be operable to adjust the phase of thesignal315aby an amount determined by thesignal234 output byphase buffer312, to generate thesignal205.
Thecircuit316a, which performs a convolution, may comprise a FIR filter or IIR filter, for example. Thecircuit316amay be operable to convolve thesignal132 with responseh, resulting in the partial response signal315a. Similarly, theconvolution circuit316bmay be operable to convolve thesignal317 with response ĥ, resulting in thepartial response signal209. As noted above, response ĥ may be stored by, and/or conveyed to, thesequence estimation circuit210 in the form of one or more tap coefficients, which may be determined based on the tap coefficients of thepulse shaper104 and/orinput filter109 and/or based on an adaptation algorithm of a decision feedback equalizer (DFE). Response ĥ may thus represent a compromise between attempting to perfectly reconstruct the total partial response signal (103 as modified bypulse shaper104 and input filter109) on the one hand, and compensating for multipath and/or other non-idealities of thechannel107 on the other hand. In this regard, thesystem100 may comprise one or more DFEs as described in one or more of: the United States patent application titled “Decision Feedback Equalizer for Highly-Spectrally-Efficient Communications,” the United States patent application titled “Decision Feedback Equalizer with Multiple Cores for Highly-Spectrally-Efficient Communications,” and the United States patent application titled “Decision Feedback Equalizer Utilizing Symbol Error Rate Biased Adaptation Function for Highly-Spectrally-Efficient Communications,” each of which is incorporated herein by reference, as set forth above.
Thus, signal203 is generated by taking a first estimate of transmitted symbols, (an element of symbol survivor SSn1), converting the first estimate of transmitted symbols to the partial response domain viacircuit316a, and then compensating for non-linearity in thecommunication system100 viacircuit236a(FIG. 2). Similarly, signal207 is generated from a second estimate of transmitted symbols (an element of symbol survivor SSn1) that is converted to the partial response domain bycircuit316bto generatesignal209, and then applying a non-linear model to the signal209bto compensate for non-linearity in the signal path.
FIG. 4 is a block diagram depicting an example metric calculation circuit for use in a system configured for low-complexity, highly-spectrally-efficient communications. Shown is a phase adjustcircuit402, aconvolution circuit404, and a costfunction calculation circuit406. The phase adjustcircuit402 may phase shift one or more elements of the vector PR1 (conveyed via signal232) by a corresponding one or more values of the phase candidate vectors PCn1. . . PCnM×Su×PThesignal403 output by the phase adjustcircuit402 thus conveys a plurality of partial response vectors PR2n1. . . PR2nM×Su×P, each of which comprises a plurality of phase-adjusted versions of PR1.
Thecircuit404, which performs a convolution, may comprise a FIR filter or IIR filter, for example. Thecircuit404 may be operable to convolve the symbol candidate vectors SCn1. . . SCnM×Su×Pwith ĥ. Thesignal405 output by thecircuit404 thus conveys vectors SCPRn1. . . SCPRnM×Su×Peach of which is a candidate partial response vector.
Thecost function circuit406 may be operable to generate metrics indicating the similarity between one or more of the partial response vectors PR2n1. . . PR2nM×Su×Pand one or more of the vectors SCPRn1. . . SCPRnM×Su×Pto generate error metrics Dn1. . . DnM×Su×P. In an example implementation, the error metrics may be Euclidean distances calculated as shown below inequation 1.
Dni=|(SCPRni)−(PR2ni)|2  EQ. 1
for 1≦i≦M×Su×P.
FIGS. 5A-5D depict portions of an example sequence estimation process performed by a system configured for low-complexity, highly-spectrally-efficient communications. InFIGS. 5A-5D it is assumed, for purposes of illustration, that M=4 (a symbol alphabet of α, β, χ, δ), Su=3 (three symbol survivors are selected each iteration), Psu=Su (three phase survivors are selected each iteration), P=3 (a phase alphabet of plus, minus, and zero), and that Q (vector length) is 4.
Referring toFIG. 5A, there is shown phase and symbol survivors from time n−1 on the left side of the figure. The first step in generating symbol candidates and phase candidates from the survivors is to duplicate the survivors and shift the contents to free up an element in each of the resulting vectors called out as502 on the right side ofFIG. 5A. In the example implementation depicted, the survivors are duplicated M*P−1 times and shifted one element.
Referring toFIG. 5B, the next step in generating the candidates is inserting symbols in the vacant elements of the symbol vectors and phase values in the vacant elements of the phase vectors, resulting in the symbol candidates and phase candidate for time n (called out as504 inFIG. 5B). In the example implementation depicted, each of the M possible symbol values is inserted into Su*P symbol candidates, and each of the P phase values may be inserted into M*Su candidates. In the example implementation depicted, θ5 is a reference phase value calculated based on phase survivor PSn−11. For example, θ5 may be the average (or a weighted average) of the last two or more elements of the phase survivor PSn−11(in the example shown, the average over the last two elements would be (θ5+0)/2). In the example implementation depicted, θ4=θ5−Δθ, and θ6=θ5+Δθ, where Δθ is based on: the amount of phase noise insignal226, slope (derivative) of the phase noise insignal226, signal-to-noise ratio (SNR) ofsignal226, and/or capacity of thechannel107. Similarly, in the example implementation shown, θθ is a reference phase value calculated based on phase survivor PSn−1n, θ7=θ8−Δθ, θ9=θ8+Δθ, θ11 is a reference phase value calculated based on phase survivor PSn−13, θ10=θ11−Δθ, and θ12==θ11+Δθ.
Referring toFIG. 5C, as described above with reference toFIG. 4, the symbol candidates are transformed to the partial response domain via a convolution, the reference signal PR1 is phase adjusted, and then the metrics Dn1. . . DnM×Su×Pare calculated based on the partial response signals PR2n1. . . PR2nM×Su×Pand SCPRn1. . . SCPRnM×Su×P.
Referring toFIG. 5D, the metrics calculated inFIG. 5C are used to select which of the candidates generated inFIG. 5B are selected to be the survivors for the next iteration of the sequence estimation process.FIG. 5D depicts an example implementation in which the survivors are selected in a single step by simply selecting Su candidates corresponding to the Su best metrics. In the example implementation depicted, it is assumed that metric Dn4is the best metric, that Dn16is the second best metric, and that Dn30is the third-best metric. Accordingly, symbol candidate SCn14is selected as the best symbol survivor, PCn14is selected as the best phase survivor, symbol candidate SCn16is selected as the second-best symbol survivor, PCn16is selected as the second-best phase survivor, symbol candidate SCn30is selected as the third-best symbol survivor, and PCn30is selected as the third-best phase survivor. The survivor selection process ofFIG. 5D may result in selecting identical symbol candidates which may be undesirable. A survivor selection process that prevents redundant symbol survivors is described below with reference toFIGS. 6A and 6B.
FIGS. 6A and 6B depict an example survivor selection process that is an alternative to the process depicted inFIG. 5D. InFIG. 6A, the candidates generated inFIG. 5B and the metrics calculated inFIG. 5C are used to select the best phase candidate for each symbol candidate (selected candidates are called out by reference designator602). InFIG. 6B, the best Su of the candidates selected inFIG. 6A are selected as the survivors for the next iteration of the sequence estimation process. In the example implementation depicted, it is assumed that metric Dn6is the best metric, that Dn5, is the second-best metric, and that Dn25is the third-best metric. Accordingly, symbol candidate SCn6is selected as the best symbol survivor, PCn6is selected as the best phase survivor, symbol candidate SCn5, is selected as the second-best symbol survivor, PCn5is selected as the second-best phase survivor, symbol candidate SCn25is selected as the third-best symbol survivor, and PCn25is selected as the third-best phase survivor.
Although the implementations described with reference toFIGS. 5A-6B use one phase survivor per symbol survivor. Other example implementations may use PSu (e.g., PSu<Su) phase survivors that are used commonly for each symbol survivor. In such an implementation, each of the phase survivors PSn−11. . . PSn−1PSumay be duplicated P times to generate phase successors, and then duplicated M*Su times to be associated with corresponding symbols successors. The number of symbol candidates in such an implementation would be M*Su*PSu*P.
FIG. 7 is a diagram illustrating initialization of the sequence estimation process. InFIG. 7 it is again assumed, for illustration, that M=4 (a symbol alphabet of α, β, χ, δ), Su=3 (three symbol survivors are selected each iteration), Psu=Su (three phase survivors are selected each iteration), P=3 (a phase alphabet of plus, minus, and zero), and that Q (vector length) is 4. On the far left ofFIG. 7 is shownsymbol survivors702 after receipt of a preamble sequence. Because the preamble is a deterministic sequence, all symbol survivors are forced to the same values. From thesurvivors702 are generated thecandidates704 andmetrics706 are calculated based on thecandidates704. In the example implementation shown, since the survivors were all the same, there are only four unique symbol candidates. The metrics for the four candidates are, respectively, D1, D2, D3, and D4. Accordingly, if the three candidates corresponding to the best three metrics were chosen, then the three candidates corresponding to D1 would all be chosen and the survivors for the next iteration would again all be identical. Accordingly, the three best, non-redundant symbol candidates are selected (as indicated by the heavy lines). Consequently, one of the candidates having the metric value D1 is selected, one of the candidates having the metric value D2 is selected, and one of the candidates having metric value D3 is selected, such that three non-redundant survivors are used for the next iteration.
FIG. 8A depicts an example implementation of the phase buffer shown inFIG. 3. In the example implementation depicted, the depth of thephase buffer312 is Q and the phase value stored at element q is represented as Zq, for q from 1 to Q. In the example implementation depicted, the value stored in element q3 is output as thesignal234. For each iteration of the sequence estimation process, Q elements of thephase buffer312 storing Q values of PSn−11may be overwritten with Q values of PSn1.
FIG. 8B depicts an example implementation of the symbol buffer shown inFIG. 3. In the example implementation depicted, the value(s) stored in one or more elements starting with index q1 (e.g., values stored in elements q1 through q1+L) is/are output as thesignal317 and the value(s) stored in one or more elements starting with index q2 (e.g., values stored in elements q2 through q2+L) is/are output as thesignal132. Because the value(s) output as thesignal317 start from a lower-indexed element of the symbol buffer, the delay between receiving a signal sample and outputting the corresponding value ofsignal317 is shorter than the delay between receiving a signal sample and outputting the corresponding value of thesignal132. Because the value(s) output as thesignal132 start from a higher-indexed element, however, it/they is/are likely to be less error-prone. These concepts are further illustrated with reference to inFIGS. 8C and 8D. In an example implementation, q2 is equal to q3.
FIG. 8C depicts contents of an example symbol buffer over a plurality of iterations of a sequence estimation process. In the example implementation shown inFIG. 8C, thesymbol buffer310 comprises four elements with thesignal317 corresponding to the contents of the first element (for simplicity of illustration, inFIGS. 8C and 8D, it is assumed only one element is output assignal317 on each iteration) and thesignal132 corresponding to the fourth element (for simplicity of illustration, inFIGS. 8C and 8D, it is assumed only one element is output assignal132 on each iteration). In the example implementation depicted, during each iteration of the sequence estimation process, candidates are generated by duplicating the survivors from the previous iteration, shifting the values by one element, and the appending a new value into the vacated element. Accordingly, ideally each survivor would differ from the previous survivor only in the lowest-indexed element (corresponding to the most-recent symbol). Where other elements of the most-recent survivor differ from corresponding elements of the previous survivor, such difference indicates that there is an error in those elements (either in the most-recent survivor or in the previous survivor). Given the convolutional nature of the partial response signal, symbols at higher indexes in the buffer are more reliable. Thus the symbol values will tend to converge as they move toward the right inFIG. 8C.
Shown are the contents ofexample symbol buffer310 at times n−3, n−2, n−1, and n. At time n−3, a symbol survivor having values α, β, χ, δ is stored in thesymbol buffer310. Accordingly, as shown inFIG. 8D, the value ofsignal317 at time n−3 is ‘α’ and the value ofsignal132 is ‘δ.’ At time n−2, a new symbol survivor having values δ, β, β, χ is stored in thesymbol buffer310. Accordingly, as shown inFIG. 8D, the value ofsignal317 at time n−2 is ‘δ’ and the value ofsignal132 is ‘χ.’ At time n−1, a new symbol survivor having values χ, δ, β, β is stored in thesymbol buffer310. Accordingly, as shown inFIG. 8D, the value ofsignal317 at time n−1 is ‘χ’ and the value ofsignal132 is ‘β.’ At time n, a new symbol survivor having values β, χ, δ, β is stored in thesymbol buffer310. Accordingly, as shown inFIG. 8D, the value ofsignal317 at time n is ‘β’ and the value ofsignal132 is ‘β.’ Thus, in the example scenario depicted inFIG. 8C, the value in the first element of thesymbol buffer310 at time n−3 was erroneous and the symbol did not converge until it reached the second element (q=2) of thebuffer310. That is, at time n−2 the symbol changed from α to β and then remained β at times n−1 and n. This illustrates the consequence of takingsignal317 from the first element of thesymbol buffer310 and taking thesignal132 from the fourth element of thesymbol buffer312. Namely, thesignal317 has less delay than thesignal132 but is also more error prone than thesignal132.
InFIG. 8D, the values of the signals are shown for times n−3 totime n+3. The dashed lines illustrate the delay between thesignal317 and thesignal132.
FIG. 9 is a flowchart illustrating dynamic configuration of a multi-mode transmitter. Inblock902, the transmitter powers up. In block904 a user and/or application layer of a device (e.g., mobile phone) in which the transmitter resides issues a command for the transmitter to be configured into a first mode of operation. Such a command may be, for example, in response to a need or desire to communicate with a first receiver that supports a first physical layer protocol/standard. Additionally or alternatively, such a command may be in response to a request sent on behalf of the first receiver (e.g., from a transmitter residing in the first device along with the first receiver). Inblock906, the transmitter is configured into the first mode of operation (e.g.,mode 1 of table 1, above). The first mode of operation may use, for example, RRC pulse shaping. Inblock908, information is transmitted, intended for the first receiver, by the transmitter configured in the first mode. The first receiver may receive the transmission and process it to recover the transmitted information.
Inblock910, a user and/or application layer of a device (e.g., mobile phone) in which the transmitter resides issues a command for the transmitter to be configured into a second mode of operation. Such a command may be, for example, in response to a need or desire to communicate with a second receiver that supports a second physical layer protocol/standard. Additionally or alternatively, such a command may be in response to a request sent on behalf of the second receiver (e.g., from a transmitter residing in a second device along with a second receiver). In an example implementation, the transmitter may, for example, acknowledge therequest using mode 1 communications prior to switching tomode 2. The transmitter may, for example, be operable to switch between modes on a frame-by-frame basis. Inblock906, the transmitter is configured into the first mode of operation (e.g.,mode 1 In block912, the transmitter is configured into the second mode of operation (e.g.,mode 2 of table 1, above). The second mode of operation may use, for example, partial response pulse shaping. Inblock914, information is transmitted, intended for the second receiver, by the transmitter configured in the second mode. Inblock916, the transmitter powers down.
FIG. 10 compares between Symbol Error Rate (SER) vs. SNR of the receiver configured intomode 1 of table 2 and configured intomode 2 of table 2. For purpose ofFIG. 10, gross spectral efficiency has been set to 10 bits/sec/Hz.Line1002 represents ideal performance of mode 1 (QAM1024 at Fb1) andline1004 represents ideal performance of mode 2 (PR10, which uses a QAM32 constellation, at 2×Fb1) without phase noise nor non-linear distortion.Line1006 represents performance ofmode 1, andline1008 represents performance ofmode 2 with SSB phase noise of −90 dBc/Hz at frequency offset of 100 KHz. The phase noise model has a fixed slope of −20 dB/dec.Line1010 represents performance ofmode 1, andLine1012 represents performance ofmode 2, under combined phase noise and non-linear distortion. The non-linear distortion model is saturated 3rdorder, without memory, where φ was selected to be 30° to create the polynomial saddle point, which is the clipping (saturation) point:
and r is set according to the desired distortion level (backoff).
In ideal conditions,mode 2 as shown performs 3.5 dB better thanmode 1 as shown around SER of 3×10-2, which is a practical reference for BER of 10-6 with FEC rate around 0.95. Bothmode 2 andmode 1 as shown are using symbols Pilot Over Head (POH) of 5%.Mode 2 as shown is estimating phase noise using the HPSE but themode 1 shown is using perfect decisions for carrier recovery loop (for all other demodulating purposes it uses the symbol pilots and tentative decisions). The phase noise degrades themode 1 by 1 dB butmode 2 by only 0.4 dB. The transmitted power ofmode 2 shown is higher by 4.5 dB than for themode 1 shown. Nevertheless, the combined phase noise and non-linear distortion degradesmode 1 shown by 2.2 dB while it affectsmode 2 shown by only 0.6 dB. The overall SER improvement ofmode 2 shown is around 5.3 dB butmode 2 shown has error correlation due to the nature of partial response (memory) hence, the FEC gain formode 2 shown is 1 dB below the FEC gain ofmode 1 shown. Therefore the practical sensitivity benefit is limited to 4.3 dB. Tx power benefit ofmode 2 shown relative tomode 1 shown is 4.5 dB, thus the total contribution to the system gain by usingmode 2 shown instead ofmode 1 shown is 8.8 dB. But due to spectral mask limitations the Tx power must be below P1 dB-4.5 dB so that the spectral re-growth will not exceed the applicable spectral mask, therefore the practical benefit in Tx power ofmode 2 shown vs.mode 1 shown is 3 dB and the overall system gain benefit of usingmode 2 instead ofmode 1 shown is 7.3 dB. With the use of crest factor reduction (CFR) and pre-distortion methods the Tx power formode 2 shown may increase without violating the applicable spectral mask and the system gain benefit resulting from use ofmode 2 shown instead ofmode 1 shown may approach 8.8 dB.
The present method and/or system may be realized in hardware, software, or a combination of hardware and software. The present method and/or system may be realized in a centralized fashion in at least one computing system, or in a distributed fashion where different elements are spread across several interconnected computing systems. Any kind of computing system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computing system with a program or other code that, when being loaded and executed, controls the computing system such that it carries out the methods described herein. Another typical implementation may comprise an application specific integrated circuit or chip.
The present method and/or system may also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form.
While the present method and/or system has been described with reference to certain implementations, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present method and/or system. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present disclosure without departing from its scope. Therefore, it is intended that the present method and/or system not be limited to the particular implementations disclosed, but that the present method and/or system will include all implementations falling within the scope of the appended claims.