US9229806B2 - Block closure techniques for a data storage device - Google Patents

Abstract

A data storage device includes a non-volatile memory and a controller. A method includes initiating a write operation to write first data to a first word line of a multi-level cell (MLC) block of the non-volatile memory. The method further includes compensating, in response to an event that interrupts programming at the first word line, for incompletion of a write disturb effect at the MLC block due to the event by copying second data from a second word line of the MLC block to a second block of the non-volatile memory or by writing dummy data to the second word line.

Description

CROSS-REFERENCE TO RELATED APPLICATION

The present application is related to U.S. patent application Ser. No. 14/080,655, filed concurrently herewith and entitled “DATA RETENTION DETECTION TECHNIQUES FOR A DATA STORAGE DEVICE,” the disclosure of which is incorporated herein by reference.

FIELD OF THE DISCLOSURE

The present application is generally related to data storage devices and more particularly to block closure techniques for data storage devices.

BACKGROUND

Non-volatile data storage devices, such as embedded memory devices and removable memory devices, have enabled increased portability of data and software applications. For example, multi-level cell (MLC) storage elements of a flash memory device may each store multiple bits of data, enhancing data storage density as compared to single-level cell (SLC) flash memory devices. As a result, flash memory devices may enable users to store and access a large amount of data.

Data stored at a flash memory data storage device may become less reliable over time. For example, a threshold voltage stored at a flash memory storage element may “shift” or lose charge over time due to charge leakage. The flash memory data storage device may track the length of time data has been stored at the flash memory storage element and may access the data in a manner determined by the length of time the data has been stored at the flash memory storage element. For example, if threshold voltages stored at the data storage device shift after a certain length of time, the data storage device may compensate for the shifting when accessing the data by adjusting one or more read thresholds used to sense the data.

SUMMARY

Techniques are disclosed for managing closure of multi-level cell (MLC) blocks in a data storage device, such as by maintaining a common set of parameters for a closed MLC block of the data storage device that is no longer available for write operations. For example, a block closure technique may enable a common set of cell voltage distribution (CVD) tracking parameters to be maintained for each word line of the closed MLC block storing valid data. The block closure technique may increase performance of the data storage device as compared to conventional devices in which word lines of a closed block are associated with multiple sets of CVD tracking parameters. For example, the block closure technique may enable a data storage device to access data at the closed MLC block using a common set of threshold voltages and/or a common set of error correcting code (ECC) control data instead of using multiple sets of threshold voltages and ECC control data. The data storage device may access data at each word line of the closed MLC block using the common set of threshold voltages instead of adjusting read circuitry to use different sets of threshold voltages to sense word lines of the closed MLC block. The data storage device may access data at each word line of the closed MLC block using the common set of ECC control data instead of re-calibrating an ECC decoder to use different ECC control data to decode data from word lines of the closed MLC block. Accessing data from each word line of the closed MLC block without re-adjusting the read circuitry and without re-adjusting the ECC decoder may reduce latency associated with read operations at the closed MLC block.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a particular illustrative embodiment of a system including a data storage device;

FIG. 2 is a diagram illustrating certain example operations of the data storage device ofFIG. 1;

FIG. 3 is a flow diagram of a particular illustrative embodiment of a method of operation of the data storage device ofFIG. 1;

FIG. 4 is a flow diagram of another particular illustrative embodiment of a method of operation of the data storage device ofFIG. 1; and

FIG. 5 is a flow diagram of another particular illustrative embodiment of a method of operation of the data storage device ofFIG. 1.

DETAILED DESCRIPTION

FIG. 1 is a block diagram of a particular illustrative embodiment of anelectronic device100 including adata storage device102 and ahost device150. Thedata storage device102 may be embedded within thehost device150, such as in accordance with an embedded MultiMedia Card (eMMC®) (trademark of Joint Electron Devices Engineering Council (JEDEC) Solid State Technology Association, Arlington, Va.) configuration. Alternatively, thedata storage device102 may be removable from (i.e., “removably” coupled to) thehost device150. For example, thedata storage device102 may be removably coupled to thehost device150 in accordance with a removable universal serial bus (USB) configuration.

To further illustrate, thedata storage device102 may be configured to be coupled to thehost device150 as embedded memory, such as in connection with an eMMC configuration, as an illustrative example. Thedata storage device102 may correspond to an eMMC device. As another example, thedata storage device102 may correspond to a memory card, such as a Secure Digital (SD®) card, a microSD® card, a miniSD™ card (trademarks of SD-3C LLC, Wilmington, Del.), a MultiMediaCard™ (MMC™) card (trademark of JEDEC Solid State Technology Association, Arlington, Va.), or a CompactFlash® (CF) card (trademark of SanDisk Corporation, Milpitas, Calif.). Thedata storage device102 may operate in compliance with a JEDEC industry specification. For example, thedata storage device102 may operate in compliance with a JEDEC eMMC specification, a JEDEC Universal Flash Storage (UFS) specification, one or more other specifications, or a combination thereof.

Thedata storage device102 includes anon-volatile memory104 and acontroller122. In a particular illustrative embodiment, the non-volatilememory104 may include a flash memory (e.g., a NAND flash memory or a NOR flash memory). In other implementations, thenon-volatile memory104 may include an erasable programmable read-only memory (EPROM), an electrically-erasable programmable read-only memory (EEPROM), a read-only memory (ROM), a one-time programmable memory (OTP), another type of memory, or a combination thereof. Thenon-volatile memory104 and thecontroller122 may be coupled via a bus, an interface, another structure, or a combination thereof.

Thenon-volatile memory104 may include multiple blocks of word lines (also referred to herein as “physical pages”). In the example ofFIG. 1, thenon-volatile memory104 includes ablock106 and ablock120. In a particular embodiment, theblock106 is of a multi-level cell (MLC) configuration, and theblock120 is of a single-level cell (SLC) configuration. For example, theblock106 may include storage elements that are each configured to store any of three or more logical values, and theblock120 may include storage elements that are each configured to store either of two logical values (e.g., a logical “0” or a logical “1”). Theblock120 may correspond to a recovery block that is reserved for data recovery at thedata storage device102.

Theblocks106,120 may each include multiple word lines. In the example ofFIG. 1, theblock106 includes aword line110 and aword line118. It should be appreciated thatFIG. 1 is illustrative and that thedata storage device102 may include a different number and/or configuration of blocks and/or word lines. As described further below, theword lines110,118 may have a multi-level cell (MLC) configuration that enables each of theword lines110,118 to store multiple logical pages of data. To illustrate, if theword lines110,118 have a two-level (“X2”) configuration, theword lines110,118 may each be configured to store two logical pages of data. As another example, if theword lines110,118 have a three-level (“X3”) configuration, theword lines110,118 may each be configured to store three logical pages of data. Alternatively, one or both of theword lines110,118 may have another configuration.

In the example ofFIG. 1, theword line110 stores error correcting code (ECC)codewords112,114. TheECC codewords112,114 may correspond to logical pages that can be stored simultaneously at an MLC word line. As an example, theECC codewords112,114 may respectively correspond to lower page data and upper page data, as described further below.

Thecontroller122 may include amemory124, an error correcting code (ECC)engine146, ahost interface148, and readcircuitry149. Although the example ofFIG. 1 depicts thememory124 as a single memory component, it should be appreciated that thememory124 may correspond to multiple distinct memory components and/or multiple different types of memory components. For example, all or part of thememory124 may correspond to a random access memory (RAM). As another example, a portion of thememory124 may correspond to a high-speed cache that is configured to store one or more control parameters, as described further below. All or part of thememory124 may correspond to another type of memory, such as a non-volatile memory included in thecontroller122.

Thehost device150 may correspond to a mobile telephone, a music player, a video player, a gaming console, an electronic book reader, a personal digital assistant (PDA), a computer, such as a laptop computer, tablet, or notebook computer, another electronic device, or a combination thereof. Thehost device150 may communicate via a host controller, which may enable thehost device150 to read data from thenon-volatile memory104 and to write data to thenon-volatile memory104. Thehost device150 may operate in compliance with a JEDEC Solid State Technology Association industry specification, such as an embedded MultiMedia Card (eMMC) specification or a Universal Flash Storage (UFS) Host Controller Interface specification. Thehost device150 may operate in compliance with one or more other specifications, such as a Secure Digital (SD) Host Controller specification as an illustrative example. Thehost device150 may communicate with thenon-volatile memory104 in accordance with another suitable communication protocol.

In operation, thecontroller122 may receive data and instructions from thehost device150 and may send data to thehost device150. Thecontroller122 may send data and commands to thenon-volatile memory104 and may receive data from thenon-volatile memory104. As a particular example, thecontroller122 may receivedata126 from thehost device150 via thehost interface148. Thecontroller122 may store (e.g., buffer) thedata126 at thememory124. Thedata126 may correspond to user data (e.g., a file or a portion of a file) that is to be stored at thenon-volatile memory104.

TheECC engine146 may be configured to receive thedata126 and to generate a codeword based on thedata126. For example, theECC engine146 may include an encoder configured to encode thedata126 using an ECC encoding technique. TheECC engine146 may include a Reed-Solomon encoder, a Bose-Chaudhuri-Hocquenghem (BCH) encoder, a low-density parity check (LDPC) encoder, a turbo encoder, an encoder configured to encode thedata126 according to one or more other ECC techniques, or a combination thereof. TheECC engine146 may include a decoder configured to decode data read from thenon-volatile memory104 to detect and correct, up to an error correction capability of an ECC technique used by theECC engine146, bit errors that may be present in the data. As a particular example, theECC engine146 may receive thedata126 from thememory124. TheECC engine146 may generate one or more ECC codewords based on thedata126. For example, theECC engine146 may generate theECC codewords112,114 based on thedata126.

Thecontroller122 is configured to send data and a write command to cause thenon-volatile memory104 to store the data to a specified address of thenon-volatile memory104. As a particular example, thecontroller122 may send theECC codewords112,114 to thenon-volatile memory104. The example ofFIG. 1 indicates that thecontroller122 may write theECC codewords112,114 at theword line110 of thenon-volatile memory104.

Thecontroller122 is configured to send a read command to read data from a specified address of thenon-volatile memory104. As an example, thecontroller122 may send a read command to sense threshold voltages stored at theword line110. Theread circuitry149 may compare the sensed threshold voltages to reference voltage levels (e.g., read thresholds) to generate theECC codewords112,114. TheECC engine146 may be configured to receive theECC codewords112,114 (e.g., upon a sense operation by thecontroller122 to sense theECC codewords112,114 from the non-volatile memory104) and to decode theECC codewords112,114 to generate the data126 (or a portion thereof).

A write operation at thenon-volatile memory104 may be interrupted by an event. To illustrate, if thecontroller122 initiates a write operation to write one of theECC codewords112,114 at thenon-volatile memory104 but the write operation is “interrupted” or “stalled” due to an event (e.g., a power-down event), then thenon-volatile memory104 stores “partially-written” data. As an example, if thecontroller122 initiates writing theECC codeword112 to theword line110 and a power down event occurs while writing theECC codeword112 to theword line110, then thenon-volatile memory104 may store a portion of theECC codeword112. As another example, if a power-down event occurs after thecontroller122 completes writing theECC codeword112 to theword line110 and while the ECC codeword114 is being written to theword line110, then thenon-volatile memory104 may store a portion of the ECC codeword114. In such cases, theword line110 may store “partially-written” data.

A block closure technique in accordance with the present disclosure may close theblock106 in response to a word line of theblock106 storing partially-written data (e.g., in response to an event causing one of theECC codewords112,114 to be partially-written to the word line110). Closing theblock106 may include inhibiting further write operations to theblock106 by the controller122 (and by the host device150). For example, thecontroller122 may be configured to update a management table128 to indicate that theblock106 is unavailable for write operations, such as updating the management table128 to indicate that theblock106 does not include a word line having an address that may be targeted by a subsequent write operation.

The block closure technique may copy data from word lines of theblock106 affected by the event. As a particular illustrative example, if a write abort event occurs while writing data (e.g., one of theECC codewords112,114) at theword line110, theECC codewords112,114 may be copied to another portion of thenon-volatile memory104, such as to theblock120.

Thecontroller122 may be configured to update the management table128 to indicate that theECC codewords112,114 have been copied to theblock120. The management table128 may include a file allocation table (FAT). The management table128 may be further updated to indicate that the data stored at theword line110 has been invalided and/or that the data stored at theblock120 is valid.

Data of one or more other word lines of theblock106 likely to be affected by the write abort event (or “indirectly affected” by the write abort event) may be copied to theblock120. As a particular example, if theword line118 is adjacent to theword line110, data stored at theword line118 may also be affected by the write abort event, as described further with reference toFIG. 2. Data from theword line118 may be copied to theblock120, and theblock106 may be closed to further write operations. According to further examples, dummy data (e.g., invalid data) may be written to theblock106 to adjust threshold voltages stored at the word line110 (e.g., via a write disturb effect), as described further with reference toFIG. 2.

Closing theblock106 in accordance with the block closure technique may enablecommon parameters140 to be used to read from theblock106 data written prior to the write abort event. To illustrate, in certain conventional devices, data written at a block before a write abort event and data written at the block after the write abort event may be associated with different parameters, such as different cell voltage distribution (CVD) tracking parameters indicated by different time tags. By closing theblock106 in response to the write abort event, writing of “new” data after the write abort event may be avoided, thus enabling use of thecommon parameters140 to read data from theblock106.

Thecommon parameters140 may include CVD tracking parameters that are common to each word line of theblock106. Thecommon parameters140 may indicateECC control data142 that is common to theblock106. For example, theECC control data142 may indicate a type of encoding technique used to encode data stored at theblock106. Thecommon parameters140 may indicatethreshold voltages144 common to theblock106. For example, as data is retained at theblock106, threshold voltages of storage elements of theblock106 may “drift” (e.g., due to charge leakage). The threshold voltages144 may indicate suitable threshold voltages for reading data stored at theblock106. Further, a common time tag, such as atime tag136, may be associated with the common parameters140 (instead of multiple time tags, such as thetime tag136 and a time tag138).

The block closure technique described with reference toFIG. 1 may enable improved efficiency and operation of thedata storage device102. For example, by associating thetime tag136 with thecommon parameters140 for theblock106, operation of thedata storage device102 is simplified compared to conventional devices that access multiple time tags and/or multiple sets of parameters to sense and/or decode data from a block. To illustrate, by using thethreshold voltages144 that are common to theblock106, thecontroller122 may sense each word line of theblock106 that stores valid data without re-adjusting theread circuitry149 based on multiple sets of threshold voltages (e.g., without re-configuring theread circuitry149 from a first set of threshold voltages used to sense theword line110 to a second set of threshold voltages used to sense the word line118). By using theECC control data142 that is common to theblock106, thecontroller122 may sense each word line of theblock106 that stores valid data without re-adjusting theECC engine146 based on multiple sets of ECC parameters (e.g., without re-configuring theECC engine146 from a first set of ECC parameters used to decode data sensed from theword line110 to a second set of ECC parameters used to decode data sensed from the word line118). Accessing data from each word line of theblock106 that stores valid data without re-adjusting theread circuitry149 and without re-adjusting theECC engine146 may reduce latency associated with read operations at theblock106.

Further, thecommon parameters140 may be stored at a high-speed cache portion of thememory124 and used to sense and/or decode data from each word line of theblock106 that stores valid data. Because the high-speed cache portion may be associated with high production cost and/or large device area, caching multiple sets of read thresholds and multiple sets of ECC parameters for each block of thenon-volatile memory104 may be infeasible or may consume cache area reserved for other information. Thus, conventional devices may store multiple sets of read thresholds and multiple sets of ECC parameters at a location other than a high-speed cache portion (e.g., a portion associated with lower production cost and/or device size). Because thecommon parameters140 may include a single set of threshold voltages and a single set of ECC parameters, thecommon parameters140 may be stored at the high-speed cache portion, thus improving performance of thedata storage device102, such as by reducing latency associated with read operations.

Alternatively or in addition to triggering the block closure technique in response to a write abort event, thecontroller122 may be configured to trigger the block closure technique in connection with a data retention detection technique implemented by thecontroller122. To illustrate, in a particular embodiment, thecontroller122 is configured to select a “reference word line” of a block of thenon-volatile memory104. Thecontroller122 may be configured to use the reference word line to estimate data retention of the block (e.g., ability of the block to retain data without a large amount of errors). Thecontroller122 may close the block in response to determining that the data retention of the block is below a threshold data retention.

As an illustrative example, thecontroller122 may select theword line118 as the reference word line. In a particular embodiment, theword line118 is a “middle” word line of theblock106. For example, if theblock106 includes a positive integer number L of word lines and if theword line118 is the (L/2)th word line of theblock106, thecontroller122 may select theword line118 as the reference word line.

Upon selecting theword line118 as the reference word line, thecontroller122 may store a referenceerror rate indication134 at thememory124. The referenceerror rate indication134 may indicate a first error rate associated with data stored at theword line118 at a first time. For example, the referenceerror rate indication134 may indicate a decoded error rate and/or a bare estimation bit error rate (BER) associated with the data at a particular time. To illustrate, thecontroller122 may estimate the bare estimation BER by determining a likely number of bit errors of the data without decoding through the errors to determine an actual error rate (e.g., decoded error rate) of the data. For example, in ECC configurations in which a “hard” number of bit errors can be determined by thecontroller122 only upon decoding the data, the bare estimation BER may correspond to a “soft” number of bit errors of the data (e.g., an estimated number of bit errors estimated by the controller122).

Although the example ofFIG. 1 depicts that the referenceerror rate indication134 is stored at thememory124 of thecontroller122, the reference error rate indication134 (and/or other data stored at the memory124) may be stored at thenon-volatile memory104 alternatively or in addition to being stored at thememory124. For example, the referenceerror rate indication134 may be copied from thememory124 to thenon-volatile memory104 prior to a power-down event at thedata storage device102. In a particular embodiment, theECC engine146 is configured to determine error rates of data stored at thenon-volatile memory104, such as the first error rate.

After a power-up event at thedata storage device102, thecontroller122 may sense data from theword line118 and may determine a second error rate associated with the data sensed from theword line118. Thecontroller122 may determine a difference between the second error rate and the first error rate indicated by the referenceerror rate indication134. Thecontroller122 may compare the difference to a data retention threshold indicated by athreshold indication130. If thecontroller122 determines that the difference satisfies (e.g., is greater than or equal to) the data retention threshold indicated by thethreshold indication130, thecontroller122 may update the referenceerror rate indication134 to indicate the second error rate.

If thecontroller122 determines that the difference does not satisfy (e.g., is less than) the data retention threshold indicated by thethreshold indication130, thecontroller122 may trigger the block closure technique. As a particular example, thecontroller122 may set (e.g., assert) adata retention flag132. Thedata retention flag132 may indicate that open blocks of thenon-volatile memory104 are to be closed. The open blocks may include theblock106, theblock120, one or more other blocks of thenon-volatile memory104, or a combination thereof.

Setting thedata retention flag132 may trigger the block closure technique described above. For example, thecontroller122 may be configured to check thedata retention flag132 in response to each power-up event at thedata storage device102. If thedata retention flag132 is asserted, thecontroller122 may close one or more open blocks of thenon-volatile memory104 in accordance with the block closure technique. For example, data from a partially-written word line may be copied to a recovery block that is reserved for data recovery, and data stored at a second word line that may be affected by write operations at the partially-written word line may also be copied to the recovery block, as described further with reference toFIG. 2.

The data retention detection technique described with reference toFIG. 1 may enable improved performance of thedata storage device102. For example, by closing a block to write operations once data retention of the block is less than an acceptable threshold, data loss can be avoided (or reduced). In particular, data can be read and copied from the block before data retention at the block is low enough to cause bit errors that prevent successful sensing and/or decoding of the data. In a particular illustrative embodiment, the data retention detection technique triggers closure of a block when a particular measured error rate associated with the block increases by 25 percent or more. The data retention detection technique may be applied during assembly of theelectronic device100, such as during an infrared reflow (IR) operation, as described further with reference toFIG. 5.

FIG. 2 is a diagram illustrating certain example operations of thedata storage device102 ofFIG. 1.FIG. 2 depicts operation states204,208,212, and216. Each of the operation states204,208,212, and216 indicates states of word lines (WL) 0, 1, 2, 3, 4, 5, and 6. The word lines 0-6 may correspond to word lines of a block of thenon-volatile memory104. For convenience of description, the word lines 0-6 are described as being included in theblock106, though it should be appreciated that the word lines 0-6 may be included in another block of the non-volatile memory104 (e.g., theblock120, or another block of the non-volatile memory104).

Each of the word lines 0-6 may be programmed to store a lower page and an upper page. For example, a lower page and an upper page may correspond to theECC codewords112,114, respectively. In the example ofFIG. 2, numerals included in the lower page (LP) column and the upper page (UP) column indicate an order of write operations at theblock106. For example, referring to theoperation state204, a lower page may be written to the word line 0 (indicated by “0” in the LP column), followed by a lower page written to the word line 1 (indicated by “1” in the LP column), followed by an upper page written to the word line 0 (indicated by “2” in the UP column), followed by a lower page written to the word line 2 (indicated by “3” in the LP column), etc. InFIG. 2, numerals in parentheses indicate pages that are scheduled to be written but have not yet been written (e.g., due to interruption of a write process).

In theoperation state204, theword lines 0, 1, 2, 3, and 4 each store a lower page and an upper page. The word lines 5 and 6 each store a lower page. An event may occur at thedata storage device102 while writing an upper page to theword line 5. The event may cause a write abort at theword line 5. The event may interrupt or stall writing the upper page to theword line 5. For example, the event may include a power-down event, a power droop event, a power drop event, a program failure event, a sanitization event (e.g., receiving an eMMC sanitize command from thehost device150 by the controller122), or receiving by the controller122 a host command from thehost device150 to close one or more open blocks of the non-volatile memory104 (e.g., an eMMC halt command), as illustrative examples.

Because theword lines 4 and 6 are adjacent to theword line 5, the event may affect data written at theword lines 4 and 6 in addition to affecting data (e.g., the lower page) stored at theword line 5. As an example, in some configurations, data may be written to theword lines 4 and 6 assuming that writing the upper page at theword line 5 will affect the data stored at theword lines 4 and 6, such as by affecting threshold voltages of storage elements of theword lines 4 and 6 via a write disturb effect, such as a cross-coupling effect or a “Yupin effect.” Certain conventional devices may create multiple sets of read parameters for word lines in response to such an event. For example, a conventional technique may associate a first set of read parameters with theword lines 0, 1, 2, and 3 and a second set of read parameters with theword lines 4 and 6 (e.g., in order to compensate for incompletion of the write disturb effect on theword lines 4 and 6 that would occur if the writing of the upper page were completed at the word line 5).

As used herein, theword line 5 may be “directly” affected by an event that interrupts programming at theword line 5, and theword lines 4, 6 may be “indirectly” affected by the event. For example, theword line 4 may be indirectly affected by the event because the lower page stored at theword line 4 is not affected by a complete write disturb effect that would result from completing writing of the lower page at theword line 5. As another example, theword line 6 may be indirectly affected by the event because the event interrupts writing of the upper page to theword line 5, resulting in incompletion of the write disturb effect at theword line 6. As used herein, a “critical region” includes any word lines directly affected or indirectly affected by an event that interrupts writing of data at thenon-volatile memory104.

To further illustrate,FIG. 2 depicts ahistogram209 that includes aset210 of threshold voltages and aset211 of threshold voltages. Thesets210,211 may each correspond to a group of threshold voltage distributions stored at a word line of the non-volatile memory104 (e.g., an “A” state distribution, a “B” state distribution, and a “C” state distribution). Theset211 includes greater threshold voltages due to completion of a write disturb effect as compared to theset210. In a particular example, theset211 corresponds to threshold voltages stored at theword line 2 in theoperation state204, and theset210 corresponds to threshold voltages stored at theword line 3 in theoperation state204.

To compensate for incompletion of the write disturb effect (e.g., to compensate for theset210 including lower threshold voltages than the set211), thecontroller122 may copy data from theword lines 4, 5, and 6 to theblock120. Accordingly,FIG. 2 illustrates an example in which data is copied from theword lines 4, 5, and 6 in response to an event occurring while programming upper page data to theword line 5. Theblock120 may correspond to a recovery block (e.g., an SLC recovery block) of thenon-volatile memory104. In the particular example ofFIG. 2, lower pages of theword lines 4, 5, and 6 and upper pages of theword lines 4 and 5 may be copied to theblock120. The upper page ofword line 5 may be copied from the word line 5 (if recoverable), or from a data buffer of thecontroller122. Upon copying the data to theblock120, theblock106 may be closed to further write operations.

As a result of closing theblock106, data stored at theword lines 0, 1, 2, and 3 may be associated with a common time tag indicating common parameters for reading data from theword lines 0, 1, 2, and 3. For example, subsequent write operations to theblock106 may be inhibited by closing theblock106, thus avoiding association of another time tag with theblock106 that would occur upon storing of data at theblock106 at a subsequent time. The common time tag may correspond to thetime tag136, and the common parameters may correspond to thecommon parameters140. In response to closing theblock106, the management table128 may be updated to indicate memory locations of the copied data at the non-volatile memory104 (e.g., memory locations of the block120). Thecontroller122 may update the management table128 to indicate that theword lines 4, 5, and 6 store invalid data and/or that theblock120 stores valid data.

In theoperation state208, theword lines 0, 1, 2, and 3 each store a lower page and an upper page. Theword line 4 stores a lower page. An event may occur at thedata storage device102 while programming a lower page to theword line 5. The event may interrupt or stall writing of the lower page to theword line 5. For example, the event may include a power-down event, a power droop event, a power drop event, a program failure event, a sanitization event (e.g., receiving an eMMC sanitize command from thehost device150 by the controller122), or receiving by the controller122 a host command from thehost device150 to close one or more open blocks of the non-volatile memory104 (e.g., an eMMC halt command), as illustrative examples.

In response to the event, thecontroller122 may copy data from theword lines 3, 4, and 5 to theblock120. For example, because theword line 4 is adjacent to theword line 5, the lower page stored at theword line 4 may be affected by the event due to incompletion of a write disturb effect that would occur if programming at theword line 5 were completed. Theoperation state208 further indicates that an upper page is scheduled to be written to theword line 4 after writing the lower page to theword line 5. Accordingly, because theword line 3 is adjacent to theword line 4, data stored at theword line 3 may be affected by the event due to incompletion of a write disturb effect that would occur if the upper page were programmed at the word line 4 (after successfully completing programming of the lower page at the word line 5). Therefore,FIG. 2 illustrates an example in which data is copied from theword lines 3, 4, and 5 in response to an event occurring while programming lower page data to theword line 5.

Upon copying data from theword lines 3, 4, and 5 to theblock120, theblock106 may be closed to further write operations. In response to closing theblock106, thecontroller122 may update the management table128 to indicate memory locations of the copied data at the non-volatile memory104 (e.g., memory locations of the block120). Thecontroller122 may update the management table128 to indicate that theword lines 3, 4, and 5 store invalid data and/or that theblock120 stores valid data.

In theoperation state212, theword lines 0, 1, 2, 3, and 4 each store a lower page. The word lines 0, 1, 2, and 3 each store an upper page. An event may occur at thedata storage device102 while programming a lower page to theword line 5. The event may interrupt or stall writing of the lower page to theword line 5. For example, the event may include a power-down event, a power droop event, a power drop event, a program failure event, a sanitization event (e.g., receiving an eMMC sanitize command from thehost device150 by the controller122), or receiving by the controller122 a host command from thehost device150 to close one or more open blocks of the non-volatile memory104 (e.g., an eMMC halt command), as illustrative examples. At the time the event occurs, theword line 4 may be partially-written (e.g., may store a lower page but not an upper page) and theword line 6 may be unwritten (e.g., does not store a lower page or an upper page).

In response to the event, thecontroller122 may re-write the lower page to theword line 5 and may write dummy data (e.g., invalid data, such as a sequence of random or pseudo-random bits) to theword lines 4, 5, and 6. The dummy data written to theword lines 4, 5, and 6 may include a dummy lower page written to theword line 6 and dummy upper pages written to theword lines 4, 5, and 6, as illustrated. Thecontroller122 may close theblock106 to further write operations. Thecontroller122 may update the management table128 to indicate that theword lines 4, 5, and 6 store invalid data. For example, thecontroller122 may update the management table128 to indicate that theword lines 4 and 5 each store a valid lower page, theword line 6 stores an invalid lower page (i.e., dummy data), and theword lines 4, 5, and 6 each store invalid upper pages (i.e., dummy data).

The dummy data written to theword lines 4, 5, and 6 may compensate for incompletion of a write disturb effect caused by interruption of writing of data at theword line 5. For example, writing the dummy upper page to theword line 4 may increase threshold voltages stored at theword line 3 via the write disturb effect, since theword line 3 is adjacent to theword line 4. Therefore,FIG. 2 illustrates an example in which lower page data is re-written to theword line 5, dummy lower page data is written to theword line 6, and dummy upper page data is written to theword lines 4, 5, and 6 in response to an event occurring while programming lower page data to theword line 5.

In theoperation state216, theword lines 0, 1, 2, and 3 each store a lower page and an upper page. Theword line 4 stores a lower page. In the particular example of theoperation state216, the upper page of theword line 3 corresponds to a “last written” page, and an event occurs at thedata storage device102 after completing writing the upper page to theword line 3 but prior to writing a lower page to theword line 5. The event may include a sanitization event (e.g., receiving an eMMC sanitize command from thehost device150 by the controller122) or receiving by the controller122 a host command from thehost device150 to close one or more open blocks of the non-volatile memory104 (e.g., an eMMC halt command), as illustrative examples.

In response to the event, thecontroller122 may write a dummy lower page to theword line 5 and dummy upper pages to theword lines 4 and 5. Therefore,FIG. 2 illustrates an example in which dummy lower page data is written to theword line 5 and dummy upper page data is written to theword lines 4 and 5 in response to an event occurring after programming upper page data to theword line 3. Thecontroller122 may close theblock106 to further write operations. Thecontroller122 may update the management table128 to indicate that theword lines 4, 5, and 6 store invalid data. For example, thecontroller122 may update the management table128 to indicate that theword lines 4 and 5 each store an invalid upper page (i.e., dummy data) and that theword line 5 further stores an invalid lower page.

The examples described with reference toFIG. 2 illustrate block closure techniques that enable improved operation of a data storage device. For example, the block closure techniques ofFIG. 2 enable each word line of theblock106 storing valid data to be associated with a common time tag. That is, instead of resuming an interrupted write operation after an event (e.g., after a power cycle) and then assigning distinct time tags to data written before and after the event, thecontroller122 may close theblock106, enabling use of a common time tag for each word line of theblock106 storing valid data. Accordingly, subsequent write operations to theblock106 may be inhibited by closing theblock106, thus avoiding association of another time tag with theblock106 that would occur upon storing of data at theblock106 at a subsequent time. Use of a common time tag for each word line of theblock106 storing valid data may improve operation of a data storage device by enabling use of thecommon parameters140 for theblock106, such theECC control data142 and/or thethreshold voltages144. Using thecommon parameters140 may avoid re-adjustment of theread circuitry149 and theECC engine146 in order to access data stored at different word lines of theblock106.

Referring toFIG. 3, a particular illustrative embodiment of a method is depicted and generally designated300. Themethod300 may be performed in thedata storage device102, such as by thecontroller122.

Themethod300 may include initiating a write operation to write first data to a first word line of a multi-level cell (MLC) block of a non-volatile memory, such as thenon-volatile memory104, at304. The MLC block may correspond to theblock106. The word line may correspond to any of the word lines described with reference toFIGS. 1 and 2, such as theword line110. The first data may correspond to theECC codeword112 and/or to a lower page, such as one of the lower pages described with reference toFIG. 2.

Themethod300 may further include compensating for incompletion of a write disturb effect at the MLC block in response to an event that interrupts programming at the first word line, at308. Compensating for incompletion of the write disturb effect includes copying second data from a second word line of the MLC block to a second block of the non-volatile memory104 (e.g., from theword line118 to the block120) or writing dummy data to the second word line (e.g., writing invalid data to the word line118). The event may correspond to any of the events described with reference toFIG. 2. The second word line may be configured to be disturbed by data writes to the first word line via the write disturb effect, such as to adjust voltage thresholds at the second word line to correspond to the set211 (e.g., to “shift” the voltage thresholds from theset210 to the set211).

As an example, referring to theoperation state204, if the event occurs while programming an upper page at theword line 5, compensating for incompletion of the write disturb effect may include copying data from theword lines 4, 5, and 6 to a second block of thenon-volatile memory104. For example, thecontroller122 may copy lower pages from theword lines 4, 5, and 6 and upper pages from theword lines 4 and 5 to theblock120. In this case, the second word line may correspond to theword line 4 and/or to the word line 6 (each of which are adjacent to the word line 5).

As another example, referring to theoperation state208, if the event occurs while programming a lower page at theword line 5, compensating for incompletion of the write disturb effect may include copying data from theword lines 3, 4, and 5 to a second block of thenon-volatile memory104. For example, thecontroller122 may copy lower pages from theword lines 3, 4, and 5 and an upper page from theword line 3 to theblock120. In this case, the second word line may correspond to theword line 3 and/or to theword line 4. Theword line 4 is adjacent to theword line 3 and to theword line 5. That is, theword line 4 is between theword lines 3, 5.

As another example, referring to theoperation state212, if the event occurs while programming a lower page at theword line 5, compensating for incompletion of the write disturb effect may include writing dummy data to theword lines 4, 5, and 6. For example, thecontroller122 may re-write the lower page to theword line 5 and may write dummy upper pages to theword lines 4, 5, and 6 and a dummy lower page to theword line 6. The dummy pages may correspond to invalid data, and the management table128 may indicate that the dummy pages are invalid. In this case, the second word line may correspond to theword line 4 and/or theword line 6. The word lines 4, 6 are each adjacent to theword line 5.

As another example, referring to theoperation state216, if the event occurs after programming an upper page at theword line 3 and prior to programming a lower page at theword line 5, compensating for incompletion of the write disturb effect may include writing dummy data to theword lines 4 and 5. For example, thecontroller122 may write a dummy lower page to theword line 5 and dummy upper pages to theword lines 4 and 5. In this case, the second word line may correspond to theword line 5. Theword line 5 is adjacent to theword line 4.

Themethod300 may further include closing the MLC block to further write operations, at312. A common time tag may be associated with each word line of the MLC block that stores valid data. The common time tag may correspond to thetime tag136. The common time tag may enable reading of data from each word line of the MLC block storing valid data using a common set of parameters. For example, themethod300 may further include reading each word line of the MLC block that stores valid data using common parameters, at316. The common parameters may correspond to thecommon parameters140. The common parameters may include theECC control data142, thethreshold voltages144, or a combination thereof.

By compensating for incompletion of the write disturb effect, word lines of the MLC block storing valid data may be accessed using the common parameters instead of separately treating word lines affected and not affected by incompletion of the write disturb effect. To illustrate, in the examples described with reference toFIG. 3, word lines storing threshold voltages corresponding to theset210 may be data-copied to theblock120 or may be programmed with dummy data. Accordingly, each word line of the MLC block storing valid data may be programmed to store data that is illustrated by theset211. In this manner, each word line of the MLC block storing valid data may be read using common read threshold voltages and/or common ECC control data, which may avoid accessing multiple sets of read threshold voltages and/or multiple sets of ECC control data, simplifying operation of a data storage device. Accordingly, themethod300 illustrates example block closure techniques that enable improved operation of a data storage device.

The block closure techniques illustrated with reference toFIG. 3 may be used in connection with a data retention detection technique. For example, a data retention detection technique may correspond to one or more of the events described with reference toFIG. 3 and may trigger the block closure technique ofFIG. 3. In a particular embodiment, thecontroller122 triggers the block closure technique ofFIG. 3 in response to determining that a data retention status of thenon-volatile memory104 is below a threshold data retention, as described further with reference toFIG. 4.

Referring toFIG. 4, a particular illustrative embodiment of a method is depicted and generally designated400. Themethod400 may be performed in thedata storage device102, such as by thecontroller122.

Themethod400 may include selecting a word line of a block of a non-volatile memory, such as thenon-volatile memory104, as a reference word line, at404. As a particular example, thecontroller122 may determine a most recently accessed time tag of thedata storage device102 and may select a block associated with the time tag (e.g., by accessing thememory124 to determine a most recently created time tag or a most recently accessed time tag). The block may correspond to theblock106, and the time tag may correspond to one of the time tags136,138. Thecontroller122 may select a middle word line of the block as the reference word line. For example, if the block includes a positive integer number L of word lines, thecontroller122 may select the (L/2)th word line as the reference word line. The reference word line may be included in a closed block of the non-volatile memory104 (e.g., a block of thenon-volatile memory104 where no further data writes by thecontroller122 are scheduled or expected).

Themethod400 may further include writing to thenon-volatile memory104 an indication of a first error rate of a first set of bits sensed from the word line, at408. For example, if thecontroller122 selects theword line110 as the reference word line, thecontroller122 may sense a set of bits from the word line110 (e.g., one or both of theECC codewords112,114) and determine an error rate associated with the set of bits. The set of bits may include a predefined bit pattern that thecontroller122 can check for bit errors. The set of bits may correspond to a reference page, such as a reference upper page, programmed to the reference word line. Thecontroller122 may store an indication of the error rate anywhere at the non-volatile memory104 (e.g., at theblock106, at theblock120, or at another block of the non-volatile memory104). The indication may correspond to the referenceerror rate indication134.

The error rate of the first set of bits may be determined according to a suitable technique. According to a first technique, the first error rate is a bit error rate (BER) indicating a percentage of bit errors associated with the set of bits. For example, the first error rate may be a “bare” BER that is determined by thecontroller122 prior to (or without) theECC engine146 decoding the set of bits. For example, if the set of bits is a predefined bit pattern, thecontroller122 may determine a number of bits of the set of bits that differs from the predefined bit pattern. Alternatively, the error rate can be determined in connection with a decoding operation performed by theECC engine146, such as by determining a number of bits that are corrected while decoding the set of bits.

Themethod400 may further include sensing the word line to generate a second set of bits, at412. The word line may be sensed in response to a power-on event being initiated at thedata storage device102 and after writing the indication of the first error rate to thenon-volatile memory104. The second set of bits may differ from the first set of bits due to one or more bit errors. The second set of bits may be generated independently of a host command from thehost device150 to read data from the word line. For example, thedata storage device102 may be configured to sense the word line in response to each power-on event detected at thedata storage device102.

Themethod400 may further include comparing the first error rate (e.g., by accessing the indication of the first error rate) and a second error rate associated with the second set of bits to determine a difference between the first error rate and the second error rate, at416. The second error rate may be determined in a manner illustrated by any of the examples described with reference to the first error rate. As a particular example, the second error rate may correspond to a bare estimation BER.

Themethod400 may include determining whether the difference satisfies a threshold, at420. For example, thecontroller122 may compare the difference to a data retention threshold indicated by thethreshold indication130. In a particular illustrative embodiment, the threshold is satisfied when the second error rate exceeds the first error rate by 25 percent or more. Alternatively, the threshold may be a different number, depending on the particular application (e.g., depending on an error correction capability of the ECC engine146).

If the difference does not satisfy the threshold (e.g., if the difference is less than the data retention threshold), themethod400 may terminate, at424. For example, one or more open blocks of thenon-volatile memory104 may remain open if the difference does not satisfy the threshold. If the difference satisfies the threshold (e.g., if the difference is greater than or equal to the data retention threshold), themethod400 includes closing a block of the non-volatile memory104 (e.g., any of theblocks106,120) to further write operations, at428. The block may be closed in a manner illustrated by the block closure technique described with reference toFIG. 3.

In a particular illustrative embodiment, closing the block includes setting (e.g., asserting) a data retention flag, such as thedata retention flag132. Setting the data retention flag may cause thecontroller122 to close one or more (e.g., all) open blocks of thenon-volatile memory104. As an example, thecontroller122 may be configured to check thedata retention flag132 in response to each power-up event at thedata storage device102. If thecontroller122 determines (e.g., after a second power-up event) that thedata retention flag132 is asserted, thecontroller122 may close one or more open blocks of thenon-volatile memory104 to write operations after the second power-up event.

The open blocks may be closed using one or more operations described with reference toFIGS. 2 and 3. For example, a “critical region” of an open block may be data-copied to a second block of thenon-volatile memory104 or written with dummy data, as described with reference toFIGS. 2 and 3.

Themethod400 ofFIG. 4 illustrates a data retention detection technique that may reduce or prevent data corruption and improve performance at thedata storage device102. For example, by closing one or more open blocks of thenon-volatile memory104 based on the data retention status of thenon-volatile memory104, such as when a difference between the first error rate and the second error rate satisfies a threshold, “stress” effects on the one or more open blocks (e.g., due to repetitive programming and erasure) can be managed before data at the one or more open blocks becomes unrecoverable (e.g., un-decodable by the ECC engine146). Further, by closing a block of thenon-volatile memory104 based on the data retention status, a common time tag may be associated each word line of the block storing valid data (instead of writing additional data to the block and associating the additional data with another time tag), which may avoid accessing multiple sets of read threshold voltages and/or multiple sets of ECC control data, simplifying operation of thedata storage device102. Further, by selecting a representative page stored at a representative word line of a block (e.g., a representative upper page stored at a middle word line of a block), the data retention detection technique ofFIG. 4 may be applied “system-wide,” instead of repeating a data retention operation on a block-by-block basis for each block of thenon-volatile memory104.

The data retention detection technique illustrated with reference toFIG. 4 may be utilized during operation of thedata storage device102. Alternatively or in addition, the data retention detection technique ofFIG. 4 may be used in connection with a production process associated with thedata storage device102. As an example, the data retention detection technique may be utilized in connection with an infrared (IR) reflow process that attaches thenon-volatile memory104 and/or thecontroller122 to a printed circuit board (PCB) (or to another component) during an assembly process. For example, thedata storage device102 may be soldered to a PCB of thehost device150 during assembly of thehost device150 and in connection with an embedded configuration of thedata storage device102. In a particular embodiment, the data retention detection technique is used to determine that the IR reflow process is completed and that data stored at thenon-volatile memory104 should be copied from an SLC memory portion of thenon-volatile memory104 to an MLC memory portion of thenon-volatile memory104, as described further with reference toFIG. 5. The IR reflow detection technique illustrated with reference toFIG. 5 may be used in connection with the data retention detection technique ofFIG. 4.

Referring toFIG. 5, a particular illustrative embodiment of a method is depicted and generally designated500. Themethod500 may be performed in thedata storage device102, such as by thecontroller122. In a particular embodiment, themethod500 is performed during assembly of the host device150 (e.g., while thedata storage device102 is being embedded within the host device150).

Themethod500 may include initiating a power-on event at thedata storage device102, at504. The power-on event may occur during an assembly process associated with thehost device150, such as during an assembly process that embeds components within thehost device150.

Themethod500 may further include sensing a reference word line of a non-volatile memory of thedata storage device102, such as thenon-volatile memory104, to generate a set of bits, at508. The reference word line may be the reference word line described with reference toFIG. 4. For example, the reference word line may be a middle word line of an MLC block of thenon-volatile memory104. The set of bits may include a predefined bit pattern that thecontroller122 can check for bit errors. In a particular embodiment, the set of bits is programmed to thedata storage device102 by a manufacturer of thedata storage device102. The set of bits may correspond to a reference page, such as a reference upper page, programmed to the reference word line.

Themethod500 may further include determining an error rate associated with the set of bits, at512. The error rate may be determined according to one or more of the techniques described with reference toFIG. 4. For example, the error rate may indicate a bare BER of the set of bits.

Themethod500 may include determining whether the error rate satisfies a threshold, at516. In a particular embodiment, the error rate ofFIG. 5 corresponds to the second error rate described with reference toFIG. 4. For example, thecontroller122 may compare the error rate ofFIG. 5 with the first error rate ofFIG. 4 to determine a difference, and to determine whether the difference satisfies the threshold, as described with reference toFIG. 4. In other embodiments, thecontroller122 may be configured to compare the error rate ofFIG. 5 to the threshold to determine whether the error rate satisfies the threshold.

If the error rate fails to satisfy the threshold, themethod500 may terminate, at520. For example, a determination may be made that the IR reflow operation is not completed. Upon completion of the IR reflow operation, data that is pre-loaded to thenon-volatile memory104 may be relocated from an SLC portion of thenon-volatile memory104 to an MLC portion of thenon-volatile memory104.

To illustrate, data may be pre-loaded to thenon-volatile memory104 prior to thedata storage device102 being integrated within an electronic device, such as prior to embedding thedata storage device102 within the host device150 (in connection with an illustrative embedded configuration). Such “preloaded” data may be subject to one or more corrupting events that may cause errors to occur in the data. In some circumstances, a number of errors introduced in the preloaded data may exceed an error correction capability of an ECC technique used by theECC engine146 to protect the preloaded data. To illustrate, attaching a first die that includes thenon-volatile memory104 to a PCB or to a second die that includes thecontroller122 may heat the first die. Heating the first die may cause threshold voltage shifting of storage elements that store the preloaded data, causing errors in the preloaded data. To improve data integrity, the preloaded data may be stored at an SLC portion of thenon-volatile memory104 during the IR reflow process and copied to an MLC portion of thenon-volatile memory104 after the IR reflow process is completed.

Themethod500 may further include determining that the IR reflow operation is completed based on the error rate satisfying the threshold, at524. For example, the error rate may be sufficient to cause threshold voltage shifting of storage elements that store the preloaded data, causing errors in the preloaded data. In the example ofFIG. 5, the errors may be utilized to determine that the IR reflow operation is completed.

Themethod500 may further include copying data from a first block of thenon-volatile memory104 to a second block of thenon-volatile memory104, such as to relocate the pre-loaded data in response to determining that the IR reflow operation is completed, at528. The first block and the second block may correspond to SLC and MLC blocks of thenon-volatile memory104, respectively. In a particular illustrative example, the first block and the second block respectively correspond to theblocks120,106, and preloaded data is copied from theblock120 to theblock106. The second block may include the reference word line, or the second block may correspond to another block of thenon-volatile memory104.

Themethod500 illustrates an IR reflow detection technique that may reduce time and cost associated with production of an electronic device that includes thedata storage device102. For example, customers may charge certain production time to suppliers of data storage devices, and manually instructing each data storage device to relocate pre-loaded data after assembly would consume time and resources. Accordingly, by configuring thedata storage device102 to relocate pre-loaded data in response to “recognizing” that an IR reflow operation is completed, production time and expense can be reduced.

One or more techniques described herein may be applicable to data storage devices that include multiple memory dies. To illustrate, thenon-volatile memory104 may correspond to a first memory die of thedata storage device102, and thedata storage device102 may further include a second memory die including a second non-volatile memory (not shown inFIG. 1). In a particular embodiment, thecontroller122 implements the data retention detection technique illustrated with reference toFIG. 4 for each memory die of the data storage device102 (e.g., for the first memory die and for the second memory die). That is, thecontroller122 may utilize a first reference portion (e.g., page, word line, or block) of the first memory die to determine a data retention status of the first memory die, and thecontroller122 may utilize a second reference portion (e.g., page, word line, or block) of the second memory die to determine a data retention status of the second memory die. Thecontroller122 may be configured to assert multiple data retention flags to indicate respective data retention statuses of the multiple memory dies. Those of skill in the art will recognize that one or more other techniques described herein may be applicable to multi-die devices.

Although certain operations are described herein separately for convenience of illustration, one of skill in the art will appreciate that such operations can be selectively applied (e.g., combined) depending on the particular application. To illustrate, in a particular embodiment, one or more techniques described herein may be applied during production of theelectronic device100 and during operation of theelectronic device100. For example, the IR reflow detection technique illustrated in connection with themethod500 and the data retention detection technique described with reference to themethod400 may be utilized during production of theelectronic device100. Alternatively or in addition, the data retention detection technique described with reference to themethod400 and the block closure technique described in accordance with themethod300 may be used during operation of theelectronic device100. Those of skill in the art will recognize that further applications of the techniques described herein are within the scope of the disclosure.

Although one or more components described herein are illustrated as block components and described in general terms, such components may include one or more microprocessors, state machines, or other circuits configured to enable the controller122 (or one or more components thereof) to perform operations described herein. For example, one or more components described herein may correspond to one or more physical components, such as hardware controllers, state machines, logic circuits, one or more other structures, or a combination thereof, to enable thecontroller122 to perform one or more operations described herein. One or more aspects of thecontroller122 may be implemented using a microprocessor or microcontroller programmed to perform operations described herein, such as one or more operations of themethods300,400, and500. In a particular embodiment, thecontroller122 includes a processor executing instructions that are stored at thenon-volatile memory104. Alternatively or in addition, executable instructions that are executed by the processor may be stored at a separate memory location that is not part of thenon-volatile memory104, such as at a read-only memory (ROM).

To further illustrate, thecontroller122 may be configured to initiate a write operation to write first data to a first word line of an MLC block of thenon-volatile memory104, such as by issuing a write command to thenon-volatile memory104 that targets (e.g., identifies within an operand of the write command) an address of the first word line. An event may interrupt programming at the first word line. For example, one or more commands may be received by thecontroller122 from thehost device150 via thehost interface148 instructing thedata storage device102 to close one or more open blocks of thenon-volatile memory104. Thecontroller122 may execute one or more instructions to respond to such commands from thehost device150.

As another example, a power detector circuit of thedata storage device102 may be configured to detect a power down event, a power droop event, a power drop event, or a combination thereof. In response to the event, thecontroller122 may compensate for incompletion of a write disturb effect at the MLC block due to the event by copying second data from a second word line of the MLC block to a second block of the non-volatile memory (e.g., by issuing one or more sense commands to thenon-volatile memory104 targeting an address of the MLC block and by issuing one or more write commands to thenon-volatile memory104 targeting an address of the second block). Thecontroller122 may compensate for incompletion of the write disturb effect by writing dummy data to the second word line (e.g., by generating random or pseudo-random data by a pseudo-random number generator of thedata storage device102 to generate the dummy data and by issuing the dummy data and a write command targeting the MLC block to the non-volatile memory104).

To further illustrate, thecontroller122 may be configured to write an indication of a first error rate of a first set of bits to the non-volatile memory104 (e.g., using a write command targeting an address of the non-volatile memory104). The first set of bits is sensed from a word line of the non-volatile memory (e.g., using a sense command targeting an address of the word line). In response to a first power-on event being initiated at the data storage device after writing the indication of the first error rate to the non-volatile memory, thecontroller122 may sense the word line to generate a second set of bits, such as by issuing to the non-volatile memory104 a sense command targeting the address of the word line. Thecontroller122 may determine whether a difference between the first error rate and a second error rate associated with the second set of bits satisfies a threshold, such as by executing a compare instruction. In response to the difference satisfying the threshold, thecontroller122 may set a data retention flag, such as by issuing a write command to thenon-volatile memory104 to copy thedata retention flag132 from thememory124 to the non-volatile memory104 (e.g., to assert the data retention flag132). The data retention flag indicates a data retention status of the non-volatile memory.

In a particular embodiment, thedata storage device102 may be attached to or embedded within one or more host devices, such as within a housing of a host communication device, which may correspond to thehost device150. For example, thedata storage device102 may be integrated within a packaged apparatus such as a wireless telephone, a personal digital assistant (PDA), a gaming device or console, a portable navigation device, or other device that uses internal non-volatile memory. However, in other embodiments, thedata storage device102 may be implemented in a portable device configured to be selectively coupled to one or more external devices, such as thehost device150. In a particular embodiment, thedata storage device102 may include a non-volatile memory, such as a three-dimensional (3D) memory, a flash memory (e.g., a NAND memory, a NOR memory, an MLC flash memory, a divided bit-line NOR (DINOR) memory, an AND memory, a high capacitive coupling ratio (HiCR) device, an asymmetrical contactless transistor (ACT) device, or other flash memories), an erasable programmable read-only memory (EPROM), an electrically-erasable programmable read-only memory (EEPROM), a read-only memory (ROM), a one-time programmable memory (OTP), or any other type of memory.

The illustrations of the embodiments described herein are intended to provide a general understanding of the various embodiments. Other embodiments may be utilized and derived from the disclosure, such that structural and logical substitutions and changes may be made without departing from the scope of the disclosure. This disclosure is intended to cover any and all subsequent adaptations or variations of various embodiments. Those of skill in the art will recognize that such modifications are within the scope of the present disclosure.

The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, that fall within the scope of the present disclosure. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims (20)

What is claimed is:

1. A method comprising:

in a data storage device including a non-volatile memory and a controller, performing by the controller:

initiating a write operation to write first data to a first word line of a multi-level cell (MLC) block of the non-volatile memory; and

in response to an event that interrupts programming at the first word line, compensating for incompletion of a write disturb effect at the MLC block due to the event by copying second data from a second word line of the MLC block to a second block of the non-volatile memory or by writing dummy data to the second word line.

2. The method ofclaim 1, further comprising closing the MLC block to further write operations after compensating for incompletion of the write disturb effect.

3. The method ofclaim 1, further comprising maintaining at least one common parameter that is common to each word line of the MLC block that stores valid data after compensating for incompletion of the write disturb effect.

4. The method ofclaim 3, wherein the at least one common parameter indicates threshold voltages used to read data from each word line of the MLC block that stores valid data.

5. The method ofclaim 3, wherein the at least one common parameter indicates error correcting code (ECC) control data used by an ECC engine of the controller to decode data from each word line of the MLC block storing valid data.

6. The method ofclaim 3, wherein the at least one common parameter is a time tag.

7. The method ofclaim 1, wherein the first data corresponds to a lower page, wherein the event occurs while writing the lower page to the first word line, and wherein the second word line is adjacent to the first word line.

8. The method ofclaim 1, wherein the first data corresponds to an upper page, wherein the event occurs while writing the upper page to the first word line, and wherein a third word line of the MLC block is between the first word line and the second word line.

9. The method ofclaim 1, wherein the second block is a single-level cell (SLC) block.

10. The method ofclaim 1, wherein the event includes one or more of a power-down event, a power droop event, a program failure event, a sanitization event, or receiving a host command to close one or more open blocks of the non-volatile memory.

11. A data storage device comprising:

a non-volatile memory that includes a multi-level cell (MLC) block and a second block, wherein the MLC block includes a first word line and a second word line; and

a controller coupled to the non-volatile memory, wherein the controller is configured to initiate a write operation to write first data to the first word line and to compensate, in response to an event that interrupts programming at the first word line, for incompletion of a write disturb effect at the MLC block due to the event by copying second data from the second word line to the second block or by writing dummy data to the second word line.

12. The data storage device ofclaim 11, wherein the controller is further configured to close the MLC block to further write operations after compensating for incompletion of the write disturb effect.

13. The data storage device ofclaim 11, wherein the second word line is adjacent to the first word line.

14. The data storage device ofclaim 11, wherein the MLC block further includes a third word line, and wherein the third word line is between the first word line and the second word line.

15. The data storage device ofclaim 14, wherein the third word line is adjacent to the first word line.

16. The data storage device ofclaim 11, wherein the second word line is configured to be disturbed by data writes to the first word line via the write disturb effect.

17. The data storage device ofclaim 11, wherein the controller is further configured to maintain at least one common parameter that is common to each word line of the MLC block that stores valid data and to operate according to a block closure technique after compensating for incompletion of the write disturb effect.

18. The data storage device ofclaim 11, wherein the controller is further configured to close the MLC block to further write operations after compensating for incompletion of the write disturb effect and to maintain at least one common parameter that is common to each word line of the MLC block that stores valid data after closing the MLC block.

19. The data storage device ofclaim 11, wherein the second block is a recovery block reserved for data recovery.

20. The data storage device ofclaim 11, wherein the second block is a single-level cell (SLC) block.

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