US9129822B2 - High voltage field balance metal oxide field effect transistor (FBM) - Google Patents

Abstract

A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Description

CLAIM OF PRIORITY

This application is a divisional of commonly-assigned, co-pending application Ser. No. 13/561,523, filed Jul. 30, 2012, the entire disclosures of which are incorporated herein by reference.

CROSS-REFERENCE TO RELATED APPLICATION

This application is related to commonly-assigned, co-pending application Ser. No. 13/199,381, filed Oct. 25, 2011, the entire disclosures of which are incorporated herein by reference.

This application is related to commonly-assigned, co-pending application Ser. No. 13/561,300, entitled “TERMINATION DESIGN FOR HIGH VOLTAGE DEVICE” to Lingpeng Guan et al filed Jul. 30, 2012, the entire disclosures of which are incorporated herein by reference.

This application is related to commonly-assigned, co-pending application Ser. No. 13/561,500, entitled “CORNER LAYOUT FOR HIGH VOLTAGE SEMICONDUCTOR DEVICE” to Lingpeng Guan et al., filed Jul. 30, 2012, the entire disclosures of which are incorporated herein by reference.

FIELD OF THE INVENTION

Embodiments of the present invention are related to semiconductor power devices. More particularly, this invention relates to new configurations and methods for manufacturing improved power device structures with field balance metal oxide field effect transistors (FBMs) for sustaining high breakdown voltage while achieving low drain to source resistance R_dsA.

BACKGROUND OF THE INVENTION

Conventional technologies to configure and manufacture high voltage semiconductor power devices are still confronted with difficulties and limitations to further improve the performances due to different tradeoffs. In vertical semiconductor power devices, there is a tradeoff between the drain to source resistance, i.e., on-state resistance, commonly represented by R_dsA (i.e., drain-source resistance X Active Area) as a performance characteristic, and the breakdown voltage sustainable by the power device. A commonly recognized relationship between the breakdown voltage (BV) and the R_dsA is expressed as: R_dsA is directly proportional to BV^2.5. For the purpose of reducing the R_dsA, an epitaxial layer is formed with a higher dopant concentration. However, a heavily doped epitaxial layer also reduces the breakdown voltage sustainable by the semiconductor power device.

Several device configurations have been explored in order to resolve the difficulties and limitations caused by these performance tradeoffs. An early attempt to improve breakdown voltage was disclosed in U.S. Pat. No. 4,941,026 to Temple. The Temple device uses a deep trench filled with a gate electrode and lined with a thick oxide. This type of structure allows for greater depletion and therefore the doping concentration of the drift region can be increased. With a higher doping concentration, a lower R_dsA can be achieved. However, this structure shifts the burden of supporting nearly all of the voltage to the oxide layer that lines the trench. Increasing the thickness of the oxide in order to support more voltage also increases the stress in the device. Therefore, the BV is limited to lower voltage devices such as those rated below 200V.

FIG. 1 shows the cross section of a conventional floating island and thick bottom trench oxide metal oxide semiconductor (FITMOS) field effect transistor (FET) implemented with thick bottom oxide in the trench gate and floating P-dopant islands under the trench gate to improve the electrical field shape. The charge compensation of the P-dopant in the floating islands allows for the N-epitaxial doping concentration to be increased, thus reduce the R_dsA. In addition, the thick bottom oxide in the trench gate lowers the gate to drain coupling, thus lowering the gate to drain charge Q_gd. The device further has the advantage of supporting a higher breakdown voltage on both the top epitaxial layer and the lower layer near the floating islands. However, the presence of floating P-region causes higher dynamic on resistance during switching.

In U.S. Pat. No. 7,291,894, Sapp et al. disclose a power transistor that maintains a high BV, while reducing the gate to drain capacitance (C_gd). In the Sapp transistor C_gdis decreased by replacing the trench electrode with an oxide. In order to compensate for the decrease in BV resulting from the removal of the electrode, the walls of the trenches are doped with a P-type dopant before the oxide is formed. This P-doped area provides a charge balancing mechanism that allows for the recovery of some of the BV that was lost by removing the trench electrode, but it is necessary to achieve accurate charge balance to sustain the high breakdown. Similarly, the device described in U.S. Pat. No. 6,762,455 to Oppermann et al also employs a trench filled with oxide. In the Oppermann device the trench sidewall can be doped like that of Sapp, but Oppermann further describes a lower P-doped region being formed below the trench. However, this too suffers from the same limitations as the Sapp device. The absence of an electrode within the trenches places a stringent burden on accurate charge balance to achieve high breakdown.

In U.S. Pat. No. 5,637,898, Baliga discloses a power transistor designed with the specific goal of providing a high breakdown voltage and low on-state resistance. The Baliga power transistor is a vertical field effect transistor in a semiconductor substrate that includes a trench having a bottom in the drift region and an insulated gate electrode for modulating the conductivity of the channel and drift regions in response to the application of a turn-on gate bias. The insulated gate electrode includes an electrically conductive gate in the trench and an insulating region which lines a sidewall of the trench adjacent the channel and drift regions. The insulating region has a non-uniform cross-sectional area between the trench sidewall and the gate. This enhances the forward voltage blocking capability of the transistor by inhibiting the occurrence of high electric field crowding at the bottom of the trench. The thickness of the insulating region is greater along the portion of the sidewall which extends adjacent the drift region and less along the portion of the sidewall which extends adjacent the channel region. The drift region is also non-uniformly doped to have a linearly graded doping profile that decreases in a direction from the drain region to the channel region to provide low on-state resistance. The charge compensation in this device is achieved by the gate electrode. However, the presence of a large gate electrode significantly increases the gate to drain capacitance of this structure, resulting in higher switching losses. In addition, the Baliga device presents the additional manufacturing complexity of having a linearly graded doping profile in the drift region.

In U.S. Pat. No. 7,335,944, Banerjee et al. disclose a type of transistor that includes first and second trenches defining a mesa in a semiconductor substrate. The first and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members separated from the mesa by a thick dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section, i.e., the doping profile gradient in the drift region varies as a function of the vertical depth of the drift region. Each field plate is electrically connected to the source electrode. In this device, the charge compensation is achieved by the field plate connected to the source. However, the manufacturing of this structure requires complex fabrication processes that include deep trenches, thick liner oxide, and a doping concentration gradient.

U.S. Pat. No. 7,649,223 to Kawashima discloses a partial superjunction device-. Superjunction transistors provide a way to achieve low R_dsA while maintaining a high BV. Superjunction devices include alternating P-type and N-type doped columns formed in the drift region. In the OFF-state of the MOSFET, the columns completely deplete at relatively low voltage and thus can sustain a high breakdown voltage. In the Kawashima device, the P-doped columns are formed part way into the depth of an N-doped epitaxial layer in which MOSFET device structures are formed. For a superjunction, the R_dsA increases in direct proportion to the BV, which is a much less dramatic increase than in the conventional semiconductor structure. However, superjunction devices require complex processing and many additional masking steps, and therefore are expensive to produce.

For the above reasons, there is a need to provide new device configurations and new manufacturing methods for the semiconductor power devices which reduce the on-state resistance and in the meantime increasing the breakdown voltage sustainable by the power device such that the above discussed difficulties and limitations can be resolved.

BRIEF DESCRIPTION OF THE DRAWINGS

The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross-sectional schematic diagram of a prior art field effect transistor device.

FIG. 2A is a cross sectional view of a field balanced MOSFET (FBM) device according to an embodiment of the present invention.

FIG. 2B is a cross sectional view of an FBM device according to an embodiment of the present invention and demonstrates how the P-link functions.

FIG. 2C is an overhead view of an FBM device according to an embodiment of the present invention showing locations where links between the body regions and buried doped regions may be formed.

FIGS. 2D-2E are cross sectional views of FBM devices according to two additional embodiments of the present invention.

FIGS. 3A-3D are charts that demonstrate a relationship between different design variables of FBM devices.

FIGS. 4A-4B are cross sectional views of an FBM device according to an embodiment of the present invention and illustrating why the device is less susceptible to high current avalanche mode failures.

FIGS. 5A-5H are a series of cross sectional views for illustrating the manufacturing processes to form the FBM device ofFIG. 2A.

FIGS. 6A-6G are a series of cross sectional views for illustrating the manufacturing process to form the FBM device ofFIG. 2D.

FIGS. 7A-7D are a series of cross sectional views for illustrating the manufacturing process to form an FBM device according to an embodiment of the present invention.

SUMMARY OF THE INVENTION

The disadvantages associated with the prior art are overcome by embodiments of the present invention relating to a new and improved semiconductor power device configuration and method for manufacturing a semiconductor power device with reduced R_dsA and a high sustainable breakdown voltage.

Specifically, it is an aspect of the present invention to provide a new and improved device configuration and manufacturing method for providing a semiconductor power device with reduced R_dsA by forming a highly doped epitaxial layer near the top surface of a semiconductor substrate and then forming trenches lined with oxides and filled with conductive material, within the highly doped epitaxial layer. The conductive material within the trenches are connected to a source electrode with buried P-regions formed underneath each source trench to function as charge compensating layers for the highly doped drift region to enable it to sustain high voltage while maintaining low series resistance.

Another aspect of the present invention is to provide a new and improved device configuration and manufacturing method for providing a semiconductor power device that includes a top structure functioning as a MOSFET with a charge compensated drift region and further provided with trenches filled with electrically conductive material (e.g., polysilicon) connected to source electrode and including buried P-regions with some conductive trenches having P-doped regions surround the trench sidewalls to allow for the buried P-regions to discharge.

Another aspect of the present invention is to provide a new and improved device configuration and manufacturing method for manufacturing a semiconductor power device that includes a top structure functioning as a MOSFET with a charge compensated drift region and further provided with trenches filled with electrically conductive material connected to source electrode and including buried P-regions with conductive trenches having P-doped regions surround every trench sidewall.

Briefly, according to a preferred embodiment, a semiconductor power device may be formed in a semiconductor substrate having a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises a source region and a gate region disposed near the top surface of the semiconductor substrate and a drain region disposed at a bottom surface of the semiconductor substrate. The semiconductor power device further comprises source trenches opened into the highly doped region lined with a dielectric and then filled with a conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed at the bottom of the source trenches and doped with dopants of opposite conductivity from the highly doped region.

In a preferred embodiment, the semiconductor power device further comprises doped regions surrounded the sidewalls of the source trenches and doped with a dopant of a same conductivity type of the buried P-regions to allow for the buried P-regions to discharge.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

Although the following detailed description contains many specific details for the purposes of illustration, anyone of ordinary skill in the art will appreciate that many variations and alterations to the following details are within the scope of the invention. Accordingly, the exemplary embodiments of the invention described below are set forth without any loss of generality to, and without imposing limitations upon, the claimed invention.

In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. In the following discussion, a device with an N-type substrate is described for purposes of illustration. Substrates that are P-type may be fabricated using a similar process but with opposite conductivity types. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

FIG. 2A is a cross sectional view of a Field Balance MOSFET (FBM) according to an embodiment of the present invention.FBM200 is formed in a semiconductor substrate having a heavily dopedregion202 of a first conductivity type, e.g., an N-type substrate of a concentration of about 2-4e19/cm³. A lightly dopedvoltage blocking region203 of the first conductivity type, e.g., N-type, of a concentration of about 1e14/cm³to 1e15/cm³, is supported on top of the heavily dopedregion202. A highly doped surface shieldedregion204, which is also of the first conductivity type of a concentration of about 1e15/cm³to 5e16/cm³, is supported on top of thevoltage blocking region203. By way of example and not by way of limitation, the surface shieldedregion204 may have a doping concentration 5-100 times greater than that of the voltage blocking region. TheFBM200 is a vertical device with a drain (or collector)electrode205 disposed on a bottom surface of the substrate and a source (or emitter)electrode214 disposed on a top surface. TheFBM200 further includes a plurality oftrenches225 lined with adielectric layer207 such as an oxide layer and filled with an electrically conductive trench filling material that forms ashield electrode211. By way of example, and not by way of limitation, theshield electrode211 may be made of polysilicon. By way of example and not by way of limitation, thedielectric layer207 may have a substantially uniform thickness throughout the depth of the trench, it may be somewhat thinner at the bottom of the trench, it may be made thicker at the trench bottom, or it may be tapered higher near the trench bottom. Theshield electrode211 is electrically connected to thesource electrode214. A lightly doped depletable region of thesecond conductivity type209, e.g., P-type, is formed at the bottom of thetrench225. The lightly-doped depletable region of thesecond conductivity type209 may also be referred to as the buried P-region209. By way of example and not by way of limitation, the surface shieldedregion204 may be shallower than or substantially the same depth as the cumulative depth of thetrench225 plus the buried P-region209. As used herein, the term “substantially the same depth” means that the depth of the surface shieldedregion204 is within ±10% of the cumulative depth of thetrench225 plus the buried P-region209.

Asource region208 of the first conductivity type is formed near the top surface of the surface shieldedregion204. The source region is electrically connected to thesource electrode214. Surrounding thesource region208 is anupper body region206 of the second conductivity type. Also proximate the source region is a highly dopedP contact206′. Aplanar gate electrode212 is formed on the top surface covering an area adjacent to thesource electrode214 and the top surface of thesource region208.

The buried P-region209 creates a P-N junction capacitor when it is not connected to the body region. This potentially creates problems with switching, because the presence of floating P-regions causes higher dynamic on resistance during switching. Therefore, a suitablydoped link219, e.g., a P-doped link (P-link) for an N-type device200, may be formed between the buried P-region209 and theupper body region206 at selected locations in order to allow an electrical path for the buried P-regions209 to discharge.FIG. 2A provides an illustration of the P-link219 between the two regions. The doping concentration of the P-link219 can be chosen such that the region significantly depletes under reverse bias as shown inFIG. 2B. The equipotential lines shown near the top of the device are at a lower voltage than those at the bottom of the device. Additionally, the darker shading indicates a lower potential. In order for the P-link219 to significantly deplete, the doping concentration of the P-link219 can be made lighter than that of theupper body region206.

According to one embodiment the P-links219 are only made at select locations. Not everytrench225 connects the buried P-region209 to theupper body region206 because it would either decrease the BV of the device or worsen its on-resistance. But every buried P-region209 is connected back the source at some location via the P-link. Additionally, selectively distributing P-links219 throughout the active area of the device allows for the buried P-region209 to sufficiently discharge. By way of example and not by way of limitation,FIG. 2C provides a plan view of possible locations for the P-links219. In this example, the P-links219 are formed at the end of thedevice trenches225 by opening up asmall window229 in a mask layer and allowing a deep diffusion to connect the buried P-region and theupper body region206.

According to another embodiment of the present invention, in every location the buried P-region209 is electrically connected to theupper body region206 with a P-link219.FIG. 2D is a cross sectional view of anFBM device201 according to this embodiment. While the BV of the device may be decreased, this embodiment requires one less mask during fabrication. Instead of being forced to open a window in a mask layer for implanting the P-link219, a blanket angled implant can be used without a mask.

According to yet another embodiment of the present invention, the switching speed of the FBM device may be controlled by connecting thetrench filling material211 in thetrench225 to gate potential instead of the source.FIG. 2E depicts anFBM device200 that has this connection made in the leftmost trench. This connection will cause an increase in the gate to drain capacitance C_gdwhich will then reduce the switching speed ofFBM device201. By selecting the percentage oftrenches225 that will be connected to the gate instead of the source, the increase in the C_gdcan be controlled. This is beneficial because at high switching speeds excessive electromagnetic interference (EMI) problems occur.

Embodiments of the present invention maintain a high BV while minimizing R_dsA. According to embodiments of the present invention, the BV is split between the surface shieldedregion204 and thevoltage blocking region203. By way of example and not by way of limitation, an FBM device designed to have a BV of 660 V may have the surface shieldedregion204 configured to support 140 V and thevoltage blocking region203 may be configured to support 520 V. Thevoltage blocking region203 functions as a traditional epi-layer and follows the relationship of R_dsA∝BV^2.5. Therefore, the proportional decrease in R_dsA of the device as a result of decreasing the voltage supported by thevoltage blocking region203 from 660 V to 520 V is: (660/520)²⁵=1.81. For example, if the R_dsA of a device was originally 82 mΩ-cm²for an epi-layer that must support the entire 660 V, then for avoltage blocking region203 that only needs to support 520 V, the reduced R_dsA would be only 45.2 mΩ-cm².

The surface shieldedregion204 is configured to support the remaining voltage, while adding only a negligible amount of resistance. In order to accomplish this, the surface shieldedregion204 is highly doped in order to minimize R_dsA. However, with a high doping concentration, the epitaxial layer alone cannot support enough voltage. Therefore, the surface shieldedregion204 needs to be charge compensated. The charge compensation is provided by two separate components: (1) a MOS capacitor created by theoxide207 surrounding theshield electrode211; and (2) the buried P-region209. Both components can be configured such that they each support the desired amount of the voltage. By way of example and not by way of limitation, the voltage supported by the surface shieldedregion204 may be half supported by the buried P-region209 and half supported by theoxide207.

If it is desired that the buried P-region209 support a larger portion of the voltage, then the buried P-region can be designed to extend deeper into the semiconductor substrate. Variation in the dopant concentration in the buried P-region does not significantly alter the BV of theFBM200.FIG. 3A shows that a variation of 60% from the targeted concentration only decreases the BV of the device by approximately 5 V. This provides an increase in the robustness of the device, because it allows for greater variation in the processing while still maintaining a high BV. However, variations in the doping concentrations of the P-link219 may decrease the BV of theFBM200. As shown inFIG. 3D, a variation of 30% from the targeted concentration can reduce the BV by approximately 30V. It is noted that the sensitivity of the breakdown voltage to the doping concentration is generally not affected by the number of P-links.

If it is desired that the oxide support more of the voltage, then the depth of thetrench225 may be increased, and/or the thickness of theoxide207 may be increased. The relationship between oxide thickness and the amount of voltage supported may be described by Equation 1:

$\begin{array}{cc}N\left(y\right)=\left[\frac{{\varepsilon }_{\mathrm{si}}}{\frac{\mathrm{qm}}{2}\left(\frac{{\varepsilon }_{\mathrm{si}}}{{\varepsilon }_{\mathrm{ox}}}{t}_{\mathrm{ox}}+\frac{m}{2}\right)}\right]\left(\frac{\mathrm{BV}}{d-t_{\mathrm{ox}}}\right)y& \mathrm{Eq}.1\end{array}$
where N(y) is the doping concentration as a function of depth y, m is the mesa width, t_oxis the trench oxide thickness, d is the trench depth, BV is the breakdown voltage, and ∈_siand ∈_oxare the permittivities of silicon and oxide respectively.FIG. 3B shows the actual relationship between the thickness of theoxide207 and the BV ofFBM200, andFIG. 3C shows the actual relationship between the depth of thetrench225 and the BV ofFBM200.

In addition to supporting a portion of the BV, the buried P-region also increases the robustness of theFBM200. MOSFETs fail in unclamped inductive switching (UIS) mode because a parasitic bipolar NPN transistor (created by the N-source region, the P-body region, and the N-epitaxial layer) turns on and cannot be turned off. The prior art tries to prevent theparasitic NPN transistor445 from turning on by reducing the resistance or by moving the avalanche region away from the NPN transistor. As shown inFIG. 4A, when theFBM400 is in the avalanche mode the current441 flows mostly in the vicinity of the trench sidewall instead of under thesource region408. This prevents the current from flowing near the parasiticbipolar NPN transistor445, and therefore the device is prevented from latching up. Additionally, the doping concentrations are chosen, such that the location of the highest concentration of electron-hole generation by impact ionization is driven deep into the device. This further improves the robustness of the device, because the temperature of the device increases at locations with a high concentration of impact ionization, and increased temperatures make it is easier for the NPN to switch445 on. As seen inFIG. 4B the highest regions of impact ionization are in the buried P-region409 (location A) and deep within the voltage blocking layer (location B). Therefore moving locations A and B far from the parasitic NPN bipolar transistor produces a more robust device.

A key benefit of the present device is the fact that the body diode behavior is far superior during reverse recovery to the behavior seen in conventional charge balance MOSFETs. In charge balance MOSFETs, the depletion of the P-N columns at low voltages leads to the removal of all the stored charge before the device can block a significant voltage. Once the stored charge is gone, the current very quickly drops to zero leading to a “snap” recovery. The high dI/dt (rate of current change) can lead to high voltage overshoots when impressed across circuit stray inductances, and lead to device failure. In the FBM structure, the lower portion of the device stores charge like a conventional power MOSFET, which is not removed until a high blocking voltage is reached. The slower charge removal as the voltage builds up is responsible for a “soft” diode recovery, a feature of great benefit in some power circuits, where it reduces voltage overshoots, minimizes device failure and EMI problems.

There are a number of different techniques for fabricating FBM devices of the types described above. By way of example,FIGS. 5A-5H are cross-sectional views of the surface shieldedregion504 illustrating a method of fabrication of FBM devices of the type depicted inFIG. 2A. This embodiment reduces manufacturing cost since it only requires 7 masks (one mask for each of the following processing steps: (1) the links, (2) trenches, (3) poly gates, (4) source, (5) contacts, (6) metal, and (7) passivation). This is a significant cost savings compared to prior art superjunction devices which typically require as many as 17 masks. As shown inFIG. 5A, a heavily doped N-typeepitaxial semiconductor layer504 is formed above the lightly dopedvoltage blocking region503. It should be noted that, for simplicity, only the very top portion of the blockingregion503 is shown inFIGS. 5A-5G. As shown inFIG. 5A, a P-link mask529 is then formed on a surface of the surface shieldedregion504, e.g., by patterning a photoresist layer. P-type dopants are then implanted into the surface shieldedregion504 at the locations where a P-link519 is desired.

As shown inFIG. 5B, atrench mask535 is then formed on a surface of the surface shieldedregion504, e.g., by patterning a photoresist layer, or by patterning a hardmask oxide formed using a low temperature oxide (LTO) deposition technique or thermal oxidation, and etched with a photoresist mask. Atrench525 is then formed in the highly doped surface shieldedregion504 through thetrench mask535 to a predetermined depth. Thetrench525 extends through the P-link519, such that the P-doped regions remain along the sidewalls. By way of example and not by way of limitation thetrenches525 may be formed by reactive ion etching (RIE). As shown inFIG. 5C, the buried P-regions509 are formed with a blanket vertical P-type dopant implant with a 0° tilt. As shown inFIG. 5D, anoxide layer507 is grown along the sidewalls and bottom surface of thetrenches525. The P-link519 and the buried P-region509 are also allowed to diffuse. This step allows the P-link519 to connect with the buried P-region509. The diffusion step and the oxide formation may also be performed at the same time. Additionally, the buried P-regions509 are diffused such that the combined depth of thetrench525 and the buried P-region509 are similar to the depth of the surface shieldedregion504. By way of example and not by way of limitation, the surface shieldedregion504 may be shallower than or substantially the same depth as the cumulative depth of thetrench525 plus the buried P-region509. As noted above substantially the same depth includes a depth within ±10% of the cumulative depth of thetrench525 plus the buried P-region509.

Thereafter, the manufacturing process continues with standard processing steps to form the finished FBM device shown inFIG. 2A.FIG. 5E shows that the trenches are then filled with atrench filling material511 and the poly and the oxide material are both etched back.FIG. 5F shows the JFET implant, the gate oxidation, and the poly gate definition.FIG. 5G shows the body implant and the drive in. Finally,FIG. 5H shows the finished FBM device500 after the source masking andimplant508, the source drive in, the self-alignedP implant contact506′, the borophosphosilicate glass (BPSG) deposition, contact formation, and metal deposition masking and etching.

According to another embodiment of the present invention, the P-links519 may be formed with selective side wall implantation. This allows for the initial P-link mask, shown inFIG. 5A to be omitted. However, there is still an additional mask needed for the selective side wall implant and as such, 7 masks are still needed. Before the trench walls are lined with an oxide, selected trenches are masked in order to allow some of the sidewalls to be implanted with a tilted implant.

According to another embodiment of the present invention, the FBM is manufactured such that every buried P-region209 is connected to thebody region206 with a P-link219 as shown inFIG. 2D. The advantage of this embodiment is that there is a reduction in the number of mask layers needed for the production of the FBM device. However, this embodiment requires a larger termination region. Since the buried P-region is connected across the entire device, a disconnection must be made in the termination region in order to prevent a short between drain and source. The termination region suitable for this embodiment of the invention is describe in commonly owned U.S. patent application Ser. No. 13/561,300, which was incorporated herein by reference above.

FIGS. 6A-6F illustrate a method of manufacturing according to this embodiment. As shown inFIG. 6A, atrench mask635 is formed on the surface of the surface shieldedregion604, e.g., by patterning a photoresist layer, or by patterning a hardmask oxide formed using a low temperature oxide (LTO) deposition technique or thermal oxidation, etched by a photoresist mask. Atrench625 is then formed in the highly doped surface shieldedregion604 to a predetermined depth. By way of example and not by way of limitation, thetrenches625 may be formed by reactive ion etching (RIE). As shown inFIG. 6B, the buried P-regions609 are formed with a blanket vertical P-type dopant implant with a 0° tilt. Also inFIG. 6B is the sidewall implant used to create the P-link619. By way of example and not by way of limitation, the side wall implant may be formed with ion implantation at a tilted angle, for e.g. at a 15-30 degree tilt. Alternatively, the sidewall implant may be formed by growing a P-type epitaxial layer along each trench's sidewalls. As shown inFIG. 6C, a layer of insulatingmaterial607, e.g., an oxide layer, is grown along the sidewalls and bottom surface of thetrenches625. The P-links619 and the buried P-regions609 are also allowed to diffuse. This step allows the P-links619 to connect with the buried P-regions609. The diffusion step and the oxide formation may also be performed at the same time. Additionally, the buried P-regions609 are diffused such that the combined depth of eachtrench625 and the buried P-regions609 are similar to the depth of the surface shieldedregion604. By way of example and not by way of limitation, the surface shieldedregion604 may be shallower than or substantially the same depth as the cumulative depth of thetrench625 plus the buried P-region609. Again, substantially the same depth includes a depth within ±10% of the cumulative depth of thetrench625 plus the buried P-region609.

Thereafter, the manufacturing process may proceed with standard processing steps to form the finished FBM device shown inFIG. 2D. Specifically,FIG. 6D shows that the trenches can be filled with an electrically conductive trench filling material611 (e.g., polyilicon) and the insulatingmaterial607 andtrench filling material611 are both etched back.FIG. 6E shows the JFET implant, the gate oxidation, and the poly gate definition.FIG. 6F shows the body implant and the drive in. Finally,FIG. 6G shows the finished FBM device600 after the source masking andimplant608, the source drive in, the self-alignedP implant606′, the borophosphosilicate glass (BPSG) deposition, contact formation, and metal deposition masking and etching.

According to another embodiment of the present invention, the P-link219 may be formed by introducing a separate buried layer about halfway between the body junction and trench bottom, and using diffusion to merge these regions. This method allows for deeper trenches to be formed in the substrate.FIGS. 7A-7D show how this method is used to produce an FBM device700. First,FIG. 7A shows a partially completed surface shieldedregion704′ formed above the lightly dopedvoltage blocking region703. It should be noted that only the very top portion of the blockingregion703 is shown inFIGS. 7A-7D. A P-link mask729 is then formed on a surface of the partially completed surface shieldedregion704′, e.g., by patterning a photoresist layer. P-type dopants are then implanted into the surface shieldedregion704′ at the locations where a P-link719 is desired.FIG. 7B then shows the remainder of the surface shieldedregion704″ being epitaxially grown above the implanted P-link719.

Next,FIG. 7C shows atrench mask735 formed on a surface of the surface shieldedregion704″, e.g., by patterning a photoresist layer, or by patterning a hardmask oxide formed using a low temperature oxide (LTO) deposition technique or thermal oxidation, etched by a photoresist mask. Atrench725 is then formed in the highly doped surface shieldedregion704′ and704″ to a predetermined depth. Thetrench725 also extends through the P-link719, such that the P-doped regions remain along the sidewalls of thetrench725. By way of example and not by way of limitation thetrenches725 may be formed by reactive ion etching (RIE). As shown inFIG. 7C, the buried P-regions709 are formed with a blanket vertical P-type dopant implant with a 0° tilt. As shown inFIG. 7D, an oxide layer707 is grown along the sidewalls and bottom surface of thetrenches725. The P-link719 and the buried P-region709 are also allowed to diffuse. This allows the P-link719 to connect with the buried P-region709. The diffusion step and the oxide formation may also be performed at the same time. Additionally, the buried P-regions709 are diffused such that the combined depth of thetrench725 and the buried P-region709 are similar to the depth of the surface shieldedregion704. By way of example and not by way of limitation, the surface shieldedregion704 may be shallower than or substantially the same depth as the cumulative depth of thetrench725 plus the buried P-region709. Substantially the same depth includes ±10% the cumulative depth of thetrench725 plus the buried P-region709. The remaining processing steps are the same as those performed for the previous embodiment and the resulting FBM device700 is substantially the same as FBM device500 except that thetrenches725 are deeper. As discussed above, the deeper trenches allow for more voltage to be supported by the surface shieldedregion704. Additionally, this embodiment may also be altered to provide a P-link719 for every buried P-region709 in the device.

While the above is a complete description of the preferred embodiments of the present invention, it is possible to use various alternatives, modifications, and equivalents. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claims, along with their full scope of equivalents. The order of recitation of steps in a method is not intended to limit a claim to a particular order of performing the corresponding steps. Any feature, whether preferred or not, may be combined with any other feature, whether preferred or not. In the claims that follow, the indefinite article “A” or “An” refers to a quantity of one or more of the item following the article, except where expressly stated otherwise. The appended claims are not to be interpreted as including means-plus-function limitations, unless such a limitation is explicitly recited in a given claim using the phrase “means for”. Any element in a claim that does not explicitly state “means for” performing a specified function, is not to be interpreted as a “means” or “step” clause as specified in 35 USC §112, 116.

Claims (12)

What is claimed is:

1. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type;

an epitaxial layer of the first conductivity type disposed on a top surface of the semiconductor substrate, wherein the epitaxial layer includes a surface shielded region that is heavily doped positioned above a voltage blocking region that is lightly doped;

a body region of a second conductivity type that is opposite of the first conductivity type, a source region of the first conductivity type and a gate disposed near the top surface of the surface shielded region and a drain disposed at a bottom surface of the semiconductor substrate;

a plurality of trenches formed in the surface shielded region, wherein the trenches are lined with a trench insulation material and filled with an electrically conductive trench filling material configured to be in electrical contact with a source electrode on top of the surface shielded region and in electrical contact with the source region;

a plurality of buried doped regions of the second conductivity type, wherein each is positioned below one of the plurality of trenches, and wherein the buried doped regions extend to a depth substantially the same as the bottom surface of the surface shielded region; and

one or more charge linking paths of the second conductivity type positioned along one or more trench walls of the plurality of trenches and configured to electrically connect a buried doped region to the body region.

2. The device ofclaim 1, wherein the surface shielded region is configured to support approximately one-third of the breakdown voltage (BV) and the voltage blocking region is configured to support approximately two-thirds of the BV.

3. The device ofclaim 2, wherein the buried doped region is configured to support approximately one-half of the BV supported by the surface shielded region and the trench insulation material supports the remainder of the BV supported by the surface shielded region.

4. The device ofclaim 1, wherein the trench filling material in some of the trenches is insulated from the source electrode and is electrically connected to the gate electrode.

5. The device ofclaim 1, wherein a doping concentration of the surface shielded region is between 5 and 100 times greater than a doping concentration of the voltage blocking region.

6. The device ofclaim 1, whereby each of the plurality of buried doped regions is connected to the source region by one of the one or more charge linking paths.

7. The device ofclaim 1, wherein the trench filling material includes polysilicon.

8. The device ofclaim 1, wherein the trench insulation material is an oxide material.

9. The device ofclaim 1, wherein a doping concentration of the charge linking region is lower than the doping concentration of the body region.

10. The device ofclaim 1, wherein the trench insulation material is of substantially uniform thickness.

11. The device ofclaim 1, wherein the trench insulation material is thicker at the bottom of the trenches.

12. The device ofclaim 1, wherein the trench insulation material is thickness is tapered higher near the trench bottom.

Images