US8987898B2 - Semiconductor wafer with reduced thickness variation and method for fabricating same - Google Patents

Abstract

According to one embodiment, a semiconductor wafer comprises a plurality of solder bumps for providing device contacts formed over a functional region of the semiconductor wafer, and one or more support rings surrounding the functional region. The one or more support rings and the plurality of solder bumps are formed so as to have substantially matching heights. The presence of the one or more support rings causes the semiconductor wafer to have a substantially uniform thickness in the functional region after a thinning process is performed on the semiconductor wafer. A method for fabricating the semiconductor wafer comprises forming the plurality of solder bumps over the functional region, and forming the one or more support rings surrounding the functional region before performing the thinning process on the semiconductor wafer.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is generally in the field of semiconductor fabrication. More specifically, the present invention is in the field of semiconductor wafer fabrication.

2. Background Art

On-resistance can be an important operating parameter for semiconductor devices. The on-resistance of a power metal-oxide-semiconductor field-effect transistor (MOSFET), for example, is typically recognized to include resistance contributions from the semiconductor wafer substrate, the epitaxial semiconductor channel, and contributions from packaging. One approach to improving on-resistance includes reducing the wafer substrate resistance contribution by reducing the thickness of the wafer. However, care must be taken when thinning the wafer substrate to avoid variation in substrate thickness across the wafer, because a substantially uniform wafer thickness facilitates a desirably uniform on-resistance distribution for the power MOSFET devices fabricated on the wafer.

The manufacturing process that typically defines wafer thickness is backgrind. A backgrind process utilizes abrasives on grinding wheels to remove semiconductor substrate material from the back surface of a wafer and thereby reduce its initial thickness to a desirable thickness for improving device on-resistance. The backgrind processes typically in use are designed to minimize substrate thickness variation for wafers having a smooth front surface. Normally, wafer front surfaces are laminated with a polymeric tape (known as backgrind tape) that both protects the front surface of the wafer from debris on the grinding chuck and also has the capability to absorb a limited amount of surface irregularity on the front surface of the wafer, so that those irregularities are not transferred to the back surface during backgrind.

However, in some fabrication processes it may be desirable to perform the backgrind operation on wafers after solder bumps have been formed on the front surface. The solder bumps are typically disposed on device pads across the wafer front surface. The application of backgrind tape under these conditions may absorb the topography produced by the solder bumps to some extent, but transfer of irregularities remaining on the front surface often still occurs due to the relatively large size of the solder bumps, resulting in undesirable variation in substrate thickness after backgrind.

Thus, there is a need to overcome the drawbacks and deficiencies in the art by enabling a semiconductor wafer with solder bumps formed thereon to undergo a backgrind or other thinning process without suffering substantial substrate thickness variation as a result.

SUMMARY OF THE INVENTION

The present invention is directed to a semiconductor wafer with reduced thickness variation and method for fabricating same, substantially as shown in and/or described in connection with at least one of the figures, and as set forth more completely in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a cross-sectional view of a peripheral region of a conventional semiconductor wafer during a thinning process.

FIG. 1B shows a cross-sectional view of the semiconductor wafer peripheral region ofFIG. 1A after the thinning process.

FIG. 2A shows a top view of a semiconductor wafer including a support ring, according to one embodiment of the present invention.

FIG. 2B shows an enlarged detailed view of a region of the semiconductor wafer shown inFIG. 2A.

FIG. 3 is a flowchart presenting a method for fabricating a semiconductor wafer including a support ring, according to one embodiment of the present invention.

FIG. 4 shows a cross-sectional view of a peripheral region of a semiconductor wafer including a support ring, according to one embodiment of the present invention, after a thinning process has been performed.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to a semiconductor wafer with reduced thickness variation and method for fabricating same. Although the invention is described with respect to specific embodiments, the principles of the invention, as defined by the claims appended herein, can obviously be applied beyond the specifically described embodiments of the invention described herein. Moreover, in the description of the present invention, certain details have been left out in order to not obscure the inventive aspects of the invention. The details left out are within the knowledge of a person of ordinary skill in the art.

The drawings in the present application and their accompanying detailed description are directed to merely example embodiments of the invention. To maintain brevity, other embodiments of the invention, which use the principles of the present invention, are not specifically described in the present application and are not specifically illustrated by the present drawings. It should be borne in mind that, unless noted otherwise, like or corresponding elements among the figures may be indicated by like or corresponding reference numerals. Moreover, the drawings and illustrations in the present application are generally not to scale, and are not intended to correspond to actual relative dimensions.

FIG. 1A shows a cross-sectional view of a peripheral region of a conventional semiconductor wafer during a thinning process.Processing environment100 showsgrinding wheel102,grinding chuck106,peripheral region111 of semiconductor wafer110, andbackgrind tape130, as semiconductor wafer110 undergoes a thinning process, which is represented inFIG. 1A as a backgrind process.Processing environment100, shows semiconductor wafer110 having a plurality ofsolder bumps120 formed overfront surface113 and havingback surface115 in contact withgrinding wheel102, which is depicted as applyinggrinding force160 againstback surface115 of semiconductor wafer110.

As explained above, backgrind is typically the manufacturing process that defines wafer thickness and thereby may be utilized to reduce the resistance contribution due to substrate thickness to the on-resistance of devices fabricated on semiconductor wafer110. As shown inFIG. 1A,front surface113 of semiconductor wafer110 has been to laminated withbackgrind tape130, e.g., normally a polymeric tape, provided to protectfront surface113 of semiconductor wafer110 from debris ongrinding chuck106, as well as to absorb minor topological irregularities onfront surface113 so that those irregularities are not transferred toback surface115 during backgrind.

However, when, as is represented inFIG. 1A, it is desirable to perform the backgrind operation on semiconductor wafer110 aftersolder bumps120 have been formed onfront surface113,backgrind tape130 may be incapable of adequately compensating for the variations in surface topology resulting from the presence ofsolder bumps120 atfront surface113. For example,backgrind tape130 appears to cover tosolder bumps120 and to present a smooth surface to grindingchuck106 on the backgrind machine (backgrind machine not shown inFIG. 1A).Grinding wheel102 is then brought into contact withback surface115 of semiconductor wafer110 andpreset grinding force160 is applied. However, the application ofgrinding force160 causescompliant backgrind tape130 to compress near the perimeter of semiconductor wafer110, where there are no solder bumps. Semiconductor wafer110 bends intogrinding chuck106 in this region, as shown by flex lines offorce116, and the grinding rate is thereby reduced in much ofperipheral region111 compared with the other portions of semiconductor wafer110 interior toperipheral region111.

The result of the conditions depicted inFIG. 1A is shown byFIG. 1B.FIG. 1B provides a cross-sectional view of semiconductor waferperipheral region111 after the backgrind process ofFIG. 1A is completed. As may be apparent fromFIG. 1B, once grindingwheel106 is withdrawn fromback surface115 of semiconductor wafer110, flex lines offorce116 are eliminated and semiconductor wafer110 can relax back to its original shape. However, due to the reduced grinding rate inperipheral region111, the resultant wafer thickness is greater in this region, as indicated bythickness variation108 atback surface115 of semiconductor wafer110. As shown inFIG. 1B,thickness variation108 extends towards the interior region of semiconductor wafer110, under solder bumps120 and their corresponding devices, e.g., power MOSFETs fabricated inperipheral region111 havingsolder bumps120 as device contacts. Consequently, the semiconductor dies harvested fromperipheral region111 will have a greater on-resistance due to the additional substrate thickness corresponding tothickness variation108, which is an undesirable outcome.

FIG. 2A show a top view offront surface213 ofsemiconductor wafer210 includingsupport ring240, according to one embodiment of the present invention, that is configured to overcome the drawbacks and deficiencies described by reference to FIGS.1A and1B.Semiconductor wafer210 comprisesfunctional region212 wherein semiconductor devices have been fabricated according to any suitable methods, as known in the art.Semiconductor wafer210 also includesperimeter zone214 occupying area at the edge ofsemiconductor wafer210. According to the embodiment ofFIG. 2A,perimeter zone214 is a device free region encirclingfunctional region212 wherein the devices ofsemiconductor wafer210 are formed. The representation ofsemiconductor wafer210further shows region250 inFIG. 2A, which is shown as enlargeddetailed region250 inFIG. 2B, andwafer notch218 inFIG. 2A.

As shown inFIG. 2A,support ring240 is formed inperimeter zone214 and surroundsfunctional region212. As further shown by enlargeddetailed region250 inFIG. 2B, in oneembodiment support ring240 may comprise a plurality of support rings. That is to say,support ring240 comprises at least one ring, but in various implementations may comprise two, or more, support rings. As may be seen fromsemiconductor wafer210,support ring240 may take the form of a circle having its center substantially co-located with the geometric center offront surface213. Moreover, wheresupport ring240 comprises more than one support ring, as shown in enlargeddetailed region250 inFIG. 2B,support ring240 may comprise two or more substantially concentric support rings.

It is noted thatsupport ring240 shown inFIG. 2A, e.g., shown surroundingfunctional region212, appears to be continuous according to that depiction, except for the break introduced bywafer notch218, while enlargeddetailed region250 inFIG. 2B shows a first support ring comprisingsupport ring segments240aseparated by respective gaps242aand a second support ring comprisingsupport ring segments240bseparated byrespective gaps242b. However, in one embodiment,support ring240 may comprise one or more support rings with no gaps, for example, a support ring or rings continuously surrounding functional region212 (except possibly for the gap produced by wafer notch218).

In other embodiments in whichwafer notch218 is omitted fromsemiconductor wafer210,support ring240 may comprise one or more substantially continuous rings surroundingfunctional region212. Alternatively, as shown by enlargeddetailed region250 inFIG. 2B, in some embodiments,support ring240 may include one or more ringed arrangements of gapped ring segments. Moreover, in those latter embodiments, adjacent support rings may be configured such that their respective gaps are not aligned. Referring to enlargeddetailed region250 ofFIG. 2B, for example, it may be seen thatgaps242aand242bare not aligned. In yet other embodiments of the present invention,support ring240 may include a combination of substantially continuous and gapped support rings. It is noted that in at least one embodiment of the present invention, as indicated for example by the representations inFIG. 2A, it is intended for support ring(s)240 to occupy less than or approximately equal to fifty percent (50%) of the area of devicefree perimeter zone214.

The advantages resulting from the semiconductor wafer structure shown inFIGS. 2A and 2B will become more apparent by reference toFIGS. 3 and 4.FIG. 3 shows a flowchart presenting a method for fabricating a semiconductor wafer including a support ring, according to one embodiment of the present invention, whileFIG. 4 shows a cross-sectional view of a semiconductor wafer including a support ring after completion of a thinning process, such as a backgrind process analogous to the process depicted byFIGS. 1A and 1B.Processing environment400, inFIG. 4, showsperipheral region411 ofsemiconductor wafer410 in combination with grindingchuck406 andbackgrind tape430.Semiconductor wafer410 includesfunctional region412 extending beyond the border ofperipheral region411, and devicefree perimeter zone414.Semiconductor wafer410 further includes solder bumps420 formed overfunctional region412 and support rings440aand440b(shown in cross-section) formed over devicefree perimeter zone414. Also shown inFIG. 4 are back surface415 ofsemiconductor wafer410 andthickness variation408 resulting from backgrind ofsemiconductor wafer410.

Turning toFIG. 3,flowchart300 sets forth a method, according to one embodiment of the present invention, for fabricating a semiconductor wafer including a solder ring and having a substantially uniform thickness across its functional region. Certain details and features have been left out offlowchart300 that are apparent to a person of ordinary skill in the art. For example, a step may comprise one or more substeps or may involve specialized equipment or materials, as known in the art. Whilesteps310 through330 indicated inflowchart300 are sufficient to describe one embodiment of the present invention, other embodiments of the invention may utilize steps different from those shown inflowchart300, or may comprise more, or fewer, steps.

Step310 offlowchart300 comprises forming a plurality of solder bumps for providing device contacts over a functional region of a semiconductor wafer. Referring toFIG. 4, step310 may be seen to correspond to formation of solder bumps420 overfunctional region412. As may be further understood from the top view ofsemiconductor wafer210, inFIG. 2A, solder bumps corresponding to solderbumps420, inFIG. 4, may be formed over thefunctional region212 in order to provide device contacts for the semiconductor device fabricated infunctional region212. Formation of solder bumps may be performed according to any suitable technique as known in the art.

Continuing withstep320, inFIG. 3, and continuing to refer tosemiconductor wafer210 inFIG. 2A, step320 offlowchart300 comprises forming one or more support rings240 surroundingfunctional region212. As explained in relation toFIGS. 2A and 2B,support ring240 may comprise one or more support rings, and may include substantially continuous support rings, support rings including at least one gap, and/or support rings formed from multiple support ring segments separated by gaps. For example, as shown by enlargeddetailed region250 inFIG. 2B,support ring240 may comprise two substantially concentric support rings that together occupy less than or approximately equal to fifty percent (50%) of the area of devicefree perimeter zone214.

Step320 may comprise forming support ring(s)240 comprising solder, for example, and may proceed according to techniques analogous to those employed for formation of solder bumps instep310. Moreover, as shown byFIG. 4, in the present embodiment, support rings440aand440bare characterized by a height that substantially matches the height of solder bumps420. As shown inFIG. 4, support rings440aand440bmay extenddistance444 abovefront surface413 ofsemiconductor wafer410, while solder bumps420 extend adistance424 abovefront surface413. According to some embodiments of the present invention, distances444 and424 may be substantially equal. Alternatively,distance444 may vary fromdistance424, but fall within a specified range ofdistance424, such as within plus-or-minus approximately twenty percent (20%) ofdistance424.

Moving to step330 inFIG. 3, and continuing to refer toprocessing environment400 inFIG. 4, step330 offlowchart300 comprises thinningsemiconductor wafer410. Step330 may be performed using a backgrind process, as described above by reference toFIG. 1A. Unlike the process described inFIG. 1A, however, backgrind ofsemiconductor wafer410 including support rings440aand440bresults in a substantially reducedthickness variation408 when compared to more conventional thickness variation108 (shown inFIG. 1B), and advantageously results in substantial elimination ofthickness variation408 underfunctional region412. Consequently, the substrate thickness acrossfunctional region412 is substantially uniform after thinning, thereby enabling fabrication of devices, such as power MOSFET devices, that concurrently display reduced on-resistance and a desirably uniform on-resistance distribution.

In addition to enabling consistent and reduced on-resistances for the devices fabricated onsemiconductor wafer410, the presence of support rings440aand440binperimeter zone414 may also enable more consistent adhesion ofbackgrind tape430. As result, the presence of support rings440aand440bmay make it less likely forbackgrind tape430 to delaminate around the periphery ofsemiconductor wafer410. Because such delamination may permit ingress of water or grinding chemicals underbackgrind tape430 during the backgrind process, and/or permit ingress of etchants during subsequent stress relief etching processes, including support rings440aand440bonsemiconductor wafer410 provides advantageous additional protections to the devices fabricated on the semiconductor wafer.

Thus, by providing one or more support rings surrounding a functional region of a semiconductor wafer, embodiments of the present invention disclose a structure and related method configured to facilitate wafer substrate thinning and thereby improve semiconductor device performance. Moreover, by forming one or more support rings having heights substantially matching the heights of solder bumps providing device contacts over the functional region, embodiments of the present invention enable a significant reduction in, or substantial elimination of, substrate thickness variation across the functional region, thereby advantageously achieving uniform on-resistance distribution in devices fabricated on the semiconductor wafer.

From the above description of the invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would recognize that changes can be made in form and detail without departing from the spirit and the scope of the invention. The described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular embodiments described herein, but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.

Claims (20)

The invention claimed is:

1. A semiconductor wafer comprising:

a plurality of solder bumps for providing device contacts over a functional region of said semiconductor wafer;

at least two support rings surrounding said functional region;

said at least two support rings and said plurality of solder bumps being situated on one surface of said semiconductor wafer;

said at least two support rings formed in a device free perimeter zone of said semiconductor wafer and said plurality of solder bumps situated on said functional region of said semiconductor wafer substantially matching in height;

said at least two support rings causing said semiconductor wafer to have a substantially uniform thickness in said functional region after a thinning process is performed on said semiconductor wafer.

2. The semiconductor wafer ofclaim 1, wherein said at least two support rings are substantially continuous.

3. The semiconductor wafer ofclaim 1, wherein said at least two support rings comprise at least one gap.

4. The semiconductor wafer ofclaim 1, wherein said at least two support rings comprise support ring segments surrounding said functional region, said support ring segments being spaced apart by gaps.

5. The semiconductor wafer ofclaim 1, wherein said at least two support rings comprise several substantially concentric support rings.

6. The semiconductor wafer ofclaim 5, wherein said several substantially concentric support rings each comprise support ring segments spaced apart by gaps.

7. The semiconductor wafer ofclaim 1, wherein said at least two support rings comprise two substantially concentric support rings.

8. The semiconductor wafer ofclaim 1, wherein said at least two support rings extend a first distance above said one surface of said semiconductor wafer and said plurality of solder bumps extend a second distance above said one surface, and wherein said first distance is within plus-or-minus approximately twenty percent (20%) of said second distance.

9. The semiconductor wafer ofclaim 1, wherein said at least two support rings occupy less than or equal to approximately fifty percent (50%) of said device free perimeter zone.

10. The semiconductor wafer ofclaim 1, wherein said at least two support rings comprise a solder ring.

11. A method for fabricating a semiconductor wafer, said method comprising:

forming a plurality of solder bumps on one surface of said semiconductor wafer, said plurality of solder bumps for providing device contacts over a functional region of said semiconductor wafer;

forming at least two support rings on said one surface of said semiconductor wafer and surrounding said functional region, said at least two support rings formed in a device free perimeter zone of said semiconductor wafer and said plurality of solder bumps situated on said functional region of said semiconductor wafer substantially matching in height;

wherein said at least two support rings cause said semiconductor wafer to have a substantially uniform thickness in said functional region after a thinning process is performed on said semiconductor wafer.

12. The method ofclaim 11, further comprising thinning said semiconductor substrate after forming said at least two support rings surrounding said functional region.

13. The method ofclaim 11, wherein forming said at least two support rings comprises forming two substantially continuous support rings.

14. The method ofclaim 11, wherein forming said at least two support rings comprises forming two support rings with each including at least one gap.

15. The method ofclaim 11, wherein forming said at least two support rings comprises forming support ring segments surrounding said functional region, said support ring segments spaced apart by gaps.

16. The method ofclaim 11, wherein forming said at least two support rings comprises forming several substantially concentric support rings.

17. The method ofclaim 16, wherein said several substantially concentric support rings comprise support ring segments spaced apart by gaps.

18. The method ofclaim 11, wherein forming said at least two support rings comprises forming two substantially concentric support rings.

19. The method ofclaim 11, wherein said at least two support rings extend a first distance above said one surface of said semiconductor wafer and said plurality of solder bumps extend a second distance above said one surface, and wherein said first distance is within plus-or-minus approximately twenty percent (20%) of said second distance.

20. The method ofclaim 11, wherein said at least two support rings occupy less than or equal to approximately fifty percent (50%) of said device free perimeter zone.

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