US8861112B1 - Two dimensional magnetic recording system head separation estimator - Google Patents

Abstract

An apparatus for estimating head separation in an array reader magnetic recording system includes an array reader with multiple read heads operable to read data from a magnetic storage medium, a first preamplifier connected to a first read head, a second preamplifier connected to a second read head, and a head separation estimation circuit connected to the first preamplifier and to the second preamplifier, operable to estimate an integer phase offset and a fractional phase offset between a first signal from the first read head and a second signal from the second read head.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

The present application claims priority to (is a non-provisional of) U.S. Pat. App. No. 61/983,425, entitled “Two Dimensional Magnetic Recording System Head Separation Estimator”, and filed Apr. 23, 2014 by Pan et al, the entirety of which is incorporated herein by reference for all purposes.

FIELD OF THE INVENTION

Various embodiments of the present invention provide systems and methods for determining head separation in a two dimensional magnetic recording system.

BACKGROUND

In a typical magnetic storage system, digital data is stored in a series of concentric circles or spiral tracks along a storage medium. Data is written to the medium by positioning a read/write head assembly over the medium at a selected location as the storage medium is rotated, and subsequently passing a modulated electric current through the head assembly such that a corresponding magnetic flux pattern is induced in the storage medium. To retrieve the stored data, the head assembly is positioned again over the track as the storage medium is rotated. In this position, the previously stored magnetic flux pattern induces a current in the head assembly that can be converted to the previously recorded digital data. In a two dimensional magnetic recording system, the read/write head assembly includes an array of multiple read heads each positioned to read the target track. The separation of the read heads can vary, altering the phase offset between signals from the different read heads, particularly as the array of read heads is moved over the magnetic storage medium.

SUMMARY

Various embodiments of the present invention provide systems and methods for determining head separation in a two dimensional magnetic recording system.

In some embodiments, an apparatus for estimating head separation in an array reader magnetic recording system includes an array reader with multiple read heads operable to read data from a magnetic storage medium, a first preamplifier connected to a first read head, a second preamplifier connected to a second read head, and a head separation estimation circuit connected to the first preamplifier and to the second preamplifier, operable to estimate an integer phase offset and a fractional phase offset between a first signal from the first read head and a second signal from the second read head.

This summary provides only a general outline of some embodiments of the invention. The phrases “in one embodiment,” “according to one embodiment,” “in various embodiments”, “in one or more embodiments”, “in particular embodiments” and the like generally mean the particular feature, structure, or characteristic following the phrase is included in at least one embodiment of the present invention, and may be included in more than one embodiment of the present invention. Importantly, such phrases do not necessarily refer to the same embodiment. This summary provides only a general outline of some embodiments of the invention. Additional embodiments are disclosed in the following detailed description, the appended claims and the accompanying drawings.

BRIEF DESCRIPTION OF THE FIGURES

A further understanding of the various embodiments of the present invention may be realized by reference to the figures which are described in remaining portions of the specification. In the figures, like reference numerals may be used throughout several drawings to refer to similar components. In the figures, like reference numerals are used throughout several figures to refer to similar components.

FIG. 1 is a diagram of a magnetic storage medium and sector data scheme that may be used with a two dimensional magnetic recording servo channel with adaptive combination in accordance with some embodiments of the present invention;

FIG. 2 depicts a storage system including a two dimensional magnetic recording read channel/servo channel with head separation estimator in accordance with some embodiments of the present invention;

FIG. 3 is a block diagram of a two dimensional magnetic recording read channel/servo channel with head separation estimator in accordance with some embodiments of the present invention; and

FIG. 4 is a flow diagram showing a method for estimating head separation in a two dimensional magnetic recording system in accordance with some embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

A head separation estimator is disclosed herein for a two dimensional magnetic recording system, also referred to as an array reader magnetic recording system. The signals from each of the multiple read heads in the array reader are phase aligned and combined, including compensating for integer phase offsets which are phase offsets that are integer multiples of the bit period, as well as compensating for fractional phase offsets which are phase offsets that are less than a single bit period. By compensating for both integer and fractional phase offsets between the signals in a two dimensional magnetic recording system, the phase aligned signals can be combined for reliable data detection. Rather than using detected syncmark location to estimate the integer phase offset, which relies on loop pulse estimation calibration, but wherein the loop pulse estimation calibration relies on correct phase alignment of the signals, the present head separation estimator breaks this cycle to provide for reliable and non-circular estimation of phase offset. This head separation estimation can be summarized according to some embodiments as follows:

Step 1: Perform phase start detection on first and second streams, and calculate fractional phase offset ΔT as difference between phase start location of first and second streams

Step 2: Calibrate loop pulse estimation LPE1 and LPE2 for the signal from each read head using known data as follows:

• • a) Train first loop pulse estimation LPE1 using digital samples for the signal from the primary read head, applying any desired loop pulse estimation constraints
  • b) Set the timing loop error combining ratio to [1 0] to consider only the signal from the primary read head in the timing loop
  • c) Interpolate the second loop pulse estimation LPE2 from the first loop pulse estimation LPE1 based on the fractional phase offset ΔT

Step 3: Calibrate integer phase offset M as follows:

• • a) Set timing loop error combining ratio to [1/2 1/2] to consider signals from the primary read head and secondary read head in the timing loop
  • b) Detect the syncmark in the two streams with the stream processing controlled based on both loop pulse estimations LPE1 and LPE2
  • c) Compute the integer phase offset M as the difference between the locations of the syncmarks in both streams

Although the head separation estimation is disclosed herein with respect to example embodiments with two read heads in the array reader, the head separation estimation can be applied to array readers with any number of read heads, by repeating the process disclosed herein to estimate the phase offset between each of the other secondary read heads with respect to the read head selected as the primary read head for the head separation estimation.

Turning toFIG. 1, a diagram of a magnetic storage medium and sector data scheme is shown that can be used with a two dimensional magnetic recording system with head separation estimation in accordance with some embodiments of the present invention. Themagnetic storage medium100 is shown with anexample data track116 and its two adjacent neighboringdata tracks118,120 ondisk platter124, indicated as dashed lines. Thetracks116,118,120 are segregated by servo data written withinservo wedges112,114. It should be noted that while threetracks116,118,120 and twoservo wedges112,114 are shown, hundreds of wedges and tens of thousands of tracks may be included on a given storage medium.

Theservo wedges112,114 includeservo data130 that is used for control and synchronization of a read/write head assembly over a desired location onstorage medium100. In particular, theservo data130 generally includes apreamble pattern132 followed by a servo address mark (SAM)134, aGray code136, aburst field138, and a repeatable run-out (RRO)field140. In some embodiments, a servo data set has two or more fields of burst information. It should be noted that different information can be included in the servo fields. Between the servodata bit patterns130aand130b, auser data region142 is provided.User data region142 can include one or more sets of data that are stored onstorage medium100. The data sets can include user synchronization information, some of which can be used as a mark to establish a point of reference from which processing of the data withinuser data region142 may begin.

In operation,storage medium100 is rotated in relation to a sensor with multiple read heads that senses information from the storage medium. In a read operation, the sensor would sense servo data from wedge112 (i.e., during a servo data period) followed by user data from a user data region betweenwedge112 and wedge114 (i.e., during a user data period) and then servo data from wedge114. In a write operation, the sensor would sense servo data from wedge112 then write data to the user data region between wedge112 and wedge114, with location information in the user data region provided by auser sync mark144 and a user preamble146.

The data processing system that processes some or all of the servo data (e.g.,130) retrieved from servo regions (e.g.,112) is referred to herein as a servo channel. As the servo data (e.g.,130) is processed by the servo channel, signals from multiple read heads in the two dimensional magnetic recording system are produced representing the servo data (e.g.,130). The phase offset of the signals due to head separation is estimated, including integer phase offset and fractional phase offset, and the signals are combined, yielding a combined signal. Values in the combined signal can then be detected and corrected in any suitable manner, such as using a Soft Output Viterbi Algorithm (SOVA) detector.

Turning toFIG. 2, astorage system200 is disclosed which includes a read channel/servo channel circuit202 with head separation estimation in accordance with some embodiments of the present invention.Storage system200 may be, for example, a hard disk drive.Storage system200 also includes apreamplifier204, aninterface controller206, ahard disk controller210, amotor controller212, aspindle motor214, adisk platter216, and a read/write head assembly220.Interface controller206 controls addressing and timing of data to/fromdisk platter216. The data ondisk platter216 consists of groups of magnetic signals that may be detected by read/write head assembly220 when the assembly is properly positioned overdisk platter216. In one embodiment,disk platter216 includes magnetic signals recorded in accordance with either a longitudinal or a perpendicular recording scheme.

In a typical read operation, read/write head assembly220 is accurately positioned bymotor controller212 over a desired data track ondisk platter216.Motor controller212 both positions read/write head assembly220 in relation todisk platter216 and drivesspindle motor214 by moving read/write head assembly220 to the proper data track ondisk platter216 under the direction ofhard disk controller210.Spindle motor214 spinsdisk platter216 at a determined spin rate (RPMs). Once read/write head assembly220 is positioned adjacent the proper data track, magnetic signals representing data ondisk platter216 are sensed by an array of read heads in read/write head assembly220 asdisk platter216 is rotated byspindle motor214. The sensed magnetic signals are provided as continuous, minute analog signals representative of the magnetic data ondisk platter216. These minute analog signals are transferred from read/write head assembly220 to readchannel circuit202 viapreamplifiers204.Preamplifiers204 are operable to amplify the minute analog signals accessed fromdisk platter216. In turn,servo channel circuit202 processes servo data to correctly position the read/write head assembly220 over thedisk platter216, and the read channel circuit digitizes and decodes the received analog signals to recreate the information originally written todisk platter216. This data is provided as readdata222 to a receiving circuit. A write operation is substantially the opposite of the preceding read operation withwrite data224 being provided to readchannel circuit202. This data is then encoded and written todisk platter216. While reading data from the array of read heads in read/write head assembly220, read channel/servo channel circuit202 estimates the phase offset of the signals from each read head caused by the separation of the read heads in read/write head assembly220, and aligns the signals before combining them. Such head separation estimation can be implemented consistent with that disclosed below in relation toFIG. 3. In some cases, the head separation estimation can be performed consistent with the flow diagram disclosed below in relation toFIG. 4.

It should be noted that in someembodiments storage system200 is integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. Such a RAID storage system increases stability and reliability through redundancy, combining multiple disks as a logical unit. Data can be spread across a number of disks included in the RAID storage system according to a variety of algorithms and accessed by an operating system as if it were a single disk. For example, data can be mirrored to multiple disks in the RAID storage system, or can be sliced and distributed across multiple disks in a number of techniques. If a small number of disks in the RAID storage system fail or become unavailable, error correction techniques can be used to recreate the missing data based on the remaining portions of the data from the other disks in the RAID storage system. The disks in the RAID storage system can be, but are not limited to, individual storage systemssuch storage system200, and can be located in close proximity to each other or distributed more widely for increased security. In a write operation, write data is provided to a controller, which stores the write data across the disks, for example by mirroring or by striping the write data. In a read operation, the controller retrieves the data from the disks. The controller then yields the resulting read data as if the RAID storage system were a single disk.

In addition, it should be noted that in someembodiments storage system200 is modified to include solid state memory that is used to store data in addition to the storage offered bydisk platter216. This solid state memory may be used in parallel todisk platter216 to provide additional storage. In such a case, the solid state memory receives and provides information directly to readchannel circuit202. Alternatively, the solid state memory may be used as a cache where it offers faster access time than that offered bydisk platter216. In such a case, the solid state memory may be disposed betweeninterface controller206 and readchannel circuit202 where it operates as a pass through todisk platter216 when requested data is not available in the solid state memory or when the solid state memory does not have sufficient storage to hold a newly written data set. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of storage systems including bothdisk platter216 and a solid state memory.

Turning toFIG. 3, a two dimensionalmagnetic recording system300 with head separation estimation is depicted in accordance with some embodiments of the present invention. An array reader or sensor includes multiple read heads such as, but not limited to, the two readheads304,305 shown inFIG. 3. The read heads304,305 are positioned over atarget track301 between side tracks302,303. In some embodiments, there is adown track separation306 between the read heads304,305, causing a phase offset between thesignals307,308 from the read heads304,305. The phase offset includes an integer phase offset M, an integer multiple of the bit period, and a fractional phase offset ΔT which is less than a single bit period. Separate read channel processing paths are provided for each of thesignals307,308 from the read heads304,305.

Preamplifiers309,319 amplify the analog signals307,308 from readheads304,305, yielding amplifiedanalog signals310,320. Analog signals307,308 may be, but are not limited to, minute analog electrical signals derived from read heads304,305 in a read/write head assembly that is disposed in relation to a storage medium (not shown). Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources from which analog signals307,308 may be derived. Analogfront end circuits311,321 receive and process the amplifiedanalog signals310,320, providing processedanalog signals312,322 to analog todigital converter circuits313,323. Analogfront end circuits311,321 may include, but are not limited to, an analog filter and an amplifier circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that may be included as part of analogfront end circuits311,321.

Analog todigital converter circuits313,323 convert processedanalog signals312,322 into corresponding series ofdigital samples314,324. Analog todigital converter circuits313,323 may be any circuits known in the art that are capable of producing digital samples corresponding to analog input signals. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converter circuits that may be used in relation to different embodiments of the present invention.

The analogfront end311,321 and analog todigital converter circuits313,323 can be controlled by afeedback signal334 from atiming loop333, for example to adjust the filtering and sampling phase to reduce or eliminate the fractional phase offset ΔT between the signal paths. Thetiming loop333 can include any suitable circuits for adjusting thefeedback signal334 to reduce or eliminate the fractional phase offset ΔT, such as, but not limited to, a frequency synthesizer and comparator to adjust the sampling clock to reduce an error signal. Notably, thetiming loop333 can scale thedigital samples316,326 before using them to adjust thefeedback signal334, so that changes in the adjusting thefeedback signal334 can reduce phase errors in bothdigital samples316,326 equally, or can focus on adjusting thefeedback signal334 to reduce phase errors in eitherdigital samples316 or326. Thedigital samples316,326 can be scaled in any suitable manner, such as using multipliers intiming loop333. For example, by applying a timing loop error combining ratio of [1 0], thetiming loop333 generatesfeedback signal334 based on thedigital samples316 and not ondigital samples326. By applying a timing loop error combining ratio of [1/2 1/2], thetiming loop333 generatesfeedback signal334 based on thedigital samples316 and326 equally.

The series ofdigital samples314,324 are provided to delay circuits such as, but not limited to, first-in first-out (FIFO)memories315,325, which remove the integer phase offset M based on a phase offsetM control signal356. For example, the earlier of the series ofdigital samples314,324 is delayed in its associatedFIFO memory315,325 by M bit periods, so that any phase offset between thedigital samples316,326 at the outputs of theFIFO memories315,325 is less than bit period. Any remaining phase offset or fractional phase offset ΔT can be corrected by thetiming loop333.

Thedigital samples316,326 are provided toequalizer circuits317,327.Equalizer circuits317,327 apply an equalization algorithm todigital samples316,326 to yield equalizedoutputs318,328. In some embodiments of the present invention,equalizer circuits317,327 are digital finite impulse response filter circuits as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of equalizer circuits that may be used in relation to different embodiments of the present invention.

Thedigital samples316,326 and/or equalizedoutputs318,328 can receive any other desired processing, such as, but not limited to, noise scaling, prior to being combined inadder circuit329 to generate combinedsignal330.

The combinedsignal330 is provided to adata detector circuit331 which applies a data detection algorithm to combinedsignal330 to yield detectedoutput332. In some embodiments, the data detection algorithm may be but is not limited to, a Soft Output Viterbi Algorithm (SOVA), or a Maximum a Posteriori detection algorithm as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detection algorithms that may be used in relation to different embodiments of the present invention.

The detectedoutput332 can be used or further processed in any desired manner, for example by decoding, de-interleaving and producing hard decisions representing the originally stored data. The detectedoutput332 can also be used, for example, to adapt filter tap coefficients forequalizer circuits317,327 and to generate an error signal for thetiming loop333.

Thedigital samples314 are also provided to a looppulse estimation circuit340 which calculates aloop pulse estimation341 for the first signal path for the first orprimary read head304. The looppulse estimation circuit340 can calculate theloop pulse estimation341 in any suitable manner, for example by applying a least mean squares algorithm to thedigital samples314 and detectedoutput332 to obtain the loop pulse estimation of the first data path. The loop pulse estimation is a partial response target representing the bit response of the first data path. The looppulse estimation circuit340 can also apply any desired constraints, such as, but not limited to, a shoulder constraint, or peek-shoulder constraint. Similarly, thedigital samples324 can also be provided to a looppulse estimation circuit344 which can calculate aloop pulse estimation345 for the second signal path for thesecondary read head305 in the same manner in some embodiments. However, according to the head separation estimation disclosed herein, theloop pulse estimation345 for the second signal path can be calculated by interpolating theloop pulse estimation341 based on the fractional phase offset ΔT.

Thedigital samples314 are also provided to async detector circuit342 that searches for sync marks or servo address mark bits indigital samples314, yielding the position orlocation343 of the sync mark in the stream of bits indigital samples314. Similarly,digital samples324 are also provided to async detector circuit346 that searches for sync marks or servo address mark bits indigital samples324, yielding the position orlocation347 of the sync mark in the stream of bits indigital samples324. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sync detector circuits that can be used in relation to different embodiments of the present invention.

Thedigital samples314,324 are also provided to a combined zeroerror phase detector352 or phase start detector which calculates the estimated startingphases353 ofdigital samples314,324. The combined zeroerror phase detector352 can calculate the estimated startingphases353 in any suitable manner, for example based on a sinusoidal pattern (e.g., 00110011) in the preamble field of the servo data. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of zero error phase detector circuits that may be used in relation to different embodiments of the present invention. Notably, the phase start detection can be performed by detecting any particular phase in thedigital samples314,324, and is not limited to detecting the zero error phase start.

Thedigital samples314,324 are also provided to a combinedsync detector350, which yields the positions orlocations351 of the syncmarks indigital samples314,324. The combinedsync detector350 and thesync detectors342,346 can be the same circuits in some embodiments.

Thedigital samples314,324 are also provided to areader separation estimator354, which calculates the integer phase offsetM356 and the fractional phase offsetΔT355. Thereader separation estimator354 calculates the integer phase offsetM356 in some embodiments by calculating the difference between thelocations351 of the syncmarks indigital samples314,324. Thereader separation estimator354 calculates the fractional phase offsetΔT355 in some embodiments by calculating the difference between the startingphases353 yielded by the combined zeroerror phase detector352. The combined zeroerror phase detector352, the combinedsync detector350 and thereader separation estimator354 are collectively referred to herein as a head separation estimation circuit.

The head separation estimation is performed in two dimensionalmagnetic recording system300 according to some embodiments as follows:

Step 1: Perform phase start detection in combined zeroerror phase detector352 based ondigital samples314,324, and calculate fractional phase offsetΔT355 inreader separation estimator354 as the difference between phase start location of first and second streams indigital samples314,324.

Step 2: Calibrate loop pulse estimation LPE1 and LPE2 for the signal from each readhead304,305 while reading known data as follows:

• • d) Train first looppulse estimation LPE1341 usingdigital samples314 for the signal from theprimary read head304, applying any desired loop pulse estimation constraints.
  • e) Set the timing loop error combining ratio to [1 0] intiming loop333 to consider only the signal from theprimary read head304 in thetiming loop333
  • f) Interpolate the second looppulse estimation LPE2345 from the first looppulse estimation LPE1341 based on the fractional phase offsetΔT355

Step 3: Calibrate integer phase offsetM356 as follows:

• • d) Set timing loop error combining ratio to [1/2 1/2] intiming loop333 to consider signals from theprimary read head304 andsecondary read head305 in thetiming loop333
  • e) Detect thesyncmarks351 in the two streams in combinedsync detector350 with the stream processing controlled based on both looppulse estimations LPE1341 andLPE2345
  • f) Compute the integer phase offsetM356 as the difference between the locations of thesyncmarks351 in both streams

By performing the calibration of the first looppulse estimation LPE1341, then interpolating from the first looppulse estimation LPE1341 to yield the second looppulse estimation LPE2345 based on the fractional phase offsetΔT355, the loop pulse estimation for both signal paths can be completed without relying on previous phase alignment of the two signal paths. The syncmark detection can then be performed using the calibrated first looppulse estimation LPE1341 and second looppulse estimation LPE2345.

Turning toFIG. 4, a flow diagram400 shows a method for estimating head separation in a two dimensional magnetic recording system in accordance with some embodiments of the present invention. Following flow diagram400, a first analog input is receives from a first read head in an array reader (block402). A second analog input is received from a second read head in an array reader (block404). The first analog input is converted to a first series of digital samples (block406). The second analog input is converted to a second series of digital samples (block408). A first phase start of the first series of digital samples is computed (block410). A second phase start of the second series of digital samples is computed (block412). The phase starts of the two signals can be computed in any suitable manner, such as in a Zero Error Phase Start (ZPS) detector circuit which calculates estimated starting phases based on a sinusoidal pattern (e.g., 00110011) in the preamble field of servo data. The phase start detection can be performed by detecting any particular phase, and is not limited to detecting the zero error phase start.

The fractional phase offset ΔT is computed as the difference of the first phase start and the second phase start (block414). The first loop pulse estimation is generated based on the first series of digital samples (block416). The combining ratio of the timing loop error for the two signals is set to [1 0] (block418). The second loop pulse estimation is generated by interpolating with the fractional phase offset ΔT (block420). The timing loop error combining ratio is set to [1/2 1/2] (block422). The syncmark is detected in the first series of digital samples using the first loop pulse estimation and is detected in the second series of digital samples using the second loop pulse estimation (block424). The loop pulse estimations can be used to configure the system in any suitable manner, such as, but not limited to, in generating feedback signals to control filtering or gain in an analog front end, equalizer, analog to digital converter, etc. The integer phase offset M is computed as the difference between sync found locations in the first series of digital samples and in the second series of digital samples (block426). The integer phase offset M and ΔT fractional phase offset are corrected in first and second signal paths (block428). In some embodiments, the integer phase offset M is corrected using a delay in the earlier of the two signal paths, for example in a first-in first-out (FIFO) memory. In some embodiments, the ΔT fractional phase offset is corrected by adjusting a synthesizer in a timing loop to adjust the sampling phase of an analog to digital converter. The aligned signal paths are combined to yield a combined signal (block430). Values in the combined signal are detected (block432). In some embodiments, values are detected by applying a data detection algorithm such as, but not limited to, a Soft Output Viterbi Algorithm (SOVA) detection process. The steps of the method can be performed in any suitable manner, either serially or at least partly in parallel.

It should be noted that the various blocks shown in the drawings and discussed herein may be implemented in integrated circuits along with other functionality. Such integrated circuits may include all of the functions of a given block, system or circuit, or a subset of the block, system or circuit. Further, elements of the blocks, systems or circuits may be implemented across multiple integrated circuits. Such integrated circuits may be any type of integrated circuit known in the art including, but are not limited to, a monolithic integrated circuit, a flip chip integrated circuit, a multichip module integrated circuit, and/or a mixed signal integrated circuit. It should also be noted that various functions of the blocks, systems or circuits discussed herein may be implemented in either software or firmware. In some such cases, the entire system, block or circuit may be implemented using its software or firmware equivalent. In other cases, the one part of a given system, block or circuit may be implemented in software or firmware, while other parts are implemented in hardware.

In conclusion, the present invention provides novel head separation estimation in a two dimensional magnetic recording servo system. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.

Claims (20)

What is claimed is:

1. An apparatus comprising:

an array reader comprising a plurality of read heads operable to read data from a magnetic storage medium;

a first preamplifier connected to a first read head in the plurality of read heads;

a second preamplifier connected to a second read head in the plurality of read heads; and

a head separation estimation circuit connected to the first preamplifier and to the second preamplifier, operable to estimate an integer phase offset and a fractional phase offset between a first signal from the first read head and a second signal from the second read head.

2. The apparatus ofclaim 1, wherein the head separation estimation circuit comprises a phase start detector operable to determine a starting phase for the first signal and a starting phase for the second signal.

3. The apparatus ofclaim 2, wherein the head separation estimation circuit further comprises a reader separation estimator operable to calculate a fractional phase offset between the first signal and the second signal based on a difference between the starting phase for the first signal and the starting phase for the second signal.

4. The apparatus ofclaim 1, wherein the head separation estimation circuit further comprises a loop pulse estimation circuit operable to calculate a loop pulse estimation for the first signal.

5. The apparatus ofclaim 4, wherein the head separation estimation circuit further comprises a second loop pulse estimation circuit operable to calculate a loop pulse estimation for the second signal by interpolating from the loop pulse estimation for the first signal by a fractional phase offset between the first signal and the second signal.

6. The apparatus ofclaim 1, wherein the head separation estimation circuit comprises a sync detector operable to detect a syncmark in the first signal and in the second signal.

7. The apparatus ofclaim 6, wherein the head separation estimation circuit further comprises a reader separation estimator operable to calculate an integer phase offset between the first signal and the second signal based on a difference between a syncmark location in the first signal detected by the sync detector and a syncmark location in the second signal detected by the sync detector, wherein the integer phase offset comprises a phase offset between the first signal and a second signal that has an integer multiple of a bit period.

8. The apparatus ofclaim 1, further comprising a first-in first-out memory connected to the first signal and a second first-in first-out memory connected to the second signal, wherein the first-in first-out memories are operable to delay an output by an integer phase offset between the first signal and the second signal such that a phase offset between the output of the first-in first-out memory and the output of the second first-in first-out memory is less than a single bit period.

9. The apparatus ofclaim 1, further comprising a timing loop connected to the first signal and to the second signal, wherein the timing loop is operable to generate a feedback signal to reduce a fractional phase difference between the first signal and the second signal.

10. The apparatus ofclaim 9, wherein the timing loop comprises at least one multiplier to scale the first signal and the second signal before generating the feedback signal to reduce a fractional phase difference between the first signal and the second signal.

11. The apparatus ofclaim 1, further comprising an adder circuit to combine the first signal and the second signal after an integer phase delay and a fractional phase delay between the first signal and the second signal have been removed, yielding a combined signal.

12. The apparatus ofclaim 11, further comprising a data detector operable to detect values of samples in the combined signal.

13. A method for estimating head separation in a two dimensional magnetic recording system, comprising:

computing a phase start of a first signal from a first read head and a phase start of a second signal from a second read head;

calculating a fractional phase offset between the first signal and the second signal as a difference between the phase start of the first signal and the phase start of the second signal;

calibrating a first loop pulse estimate for the first signal;

interpolating the first loop pulse estimate by the fractional phase offset to yield a second loop pulse estimate for the second signal;

detecting a syncmark in the first signal and in the second signal; and

calculating an integer phase offset between the first signal and the second signal as a difference between a location of the syncmark in the first signal and in the second signal.

14. The method ofclaim 13, further comprising setting a timing loop combining ratio to [1 0] for the first signal and the second signal before the interpolating.

15. The method ofclaim 13, further comprising setting a timing loop combining ratio to [1/2 1/2] for the first signal and the second signal before detecting the syncmark.

16. The method ofclaim 15, further comprising:

cancelling the fractional phase offset in a timing loop; and

cancelling the integer phase offset in a first-in first-out memory.

17. The method ofclaim 16, further comprising:

combining the first signal and the second signal to yield a combined signal; and

applying a data detection algorithm to the combined signal to yield detected values.

18. A storage device, comprising:

a magnetic storage medium operable to store data;

a head assembly disposed in relation to the storage medium and comprising an array reader with a plurality of read heads to read and write the data on the storage medium;

a first preamplifier connected to a first read head in the plurality of read heads;

a second preamplifier connected to a second read head in the plurality of read heads; and

a head separation estimation circuit connected to the first preamplifier and to the second preamplifier, operable to estimate an integer phase offset and a fractional phase offset between a first signal from the first read head and a second signal from the second read head.

19. The storage device ofclaim 18, wherein the head separation estimation circuit is operable to calculate a fractional phase offset between the first signal and the second signal based on phase start detection of the first signal and the second signal, further comprising a loop pulse estimation circuit operable to calibrate a loop pulse estimation for the first signal and to interpolate the loop pulse estimation for the first signal by the fractional phase offset to yield a second loop pulse estimation for the second signal.

20. The storage device ofclaim 19, wherein the head separation estimation circuit is further operable to detect a syncmark in the first signal and in the second signal and to calculate an integer phase offset between the first signal and the second signal as a difference between a location of the syncmark in the first signal and a location of the syncmark in the second signal.

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