US8797075B2 - Low power oversampling with reduced-architecture delay locked loop - Google Patents

Abstract

In one embodiment, an apparatus including a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.

Description

TECHNICAL FIELD

Embodiments relate to data recovery as executed by a computer system having superscalar architecture.

BACKGROUND

The International Organization for Standardization Open Systems Interconnection (ISO/OSI) model is a layered architecture that standardizes levels of service and types of interaction for systems exchanging information through a communications network. The ISO/OSI model separates computer-to-computer communications into seven layers or levels, each building upon the standards contained in the levels below it. The highest of the seven layers deals with software interactions at the application-program level. In contrast, the lowest level is the “physical layer” (PHY), which is hardware-oriented and deals with aspects of establishing and maintaining a physical link between communicating systems. Among specifications covered on the physical layer are cabling, electrical signals, and mechanical connections.

As the development of mobile device trends toward richer functionality (e.g., improved displays, cameras, peripherals, etc.) and media/content (e.g., more robust cloud-based services), mobile computing device platforms and architectures seek to accommodate greater bandwidth in the transfer of data between components. Mobile Industry Processor Interface (MIPI) Alliance is a working group that sets standards for mobile computing devices. Smart phones, personal digital assistants, laptops, tablets, and, more generally, mobile computing devices, may be designed with one or more MIPI configuration compliant components. Each component may implement a MIPI link.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a block diagram of a system in accordance with one or more embodiments.

FIG. 1B is a timing diagram of a system in accordance with one or more embodiments.

FIG. 2 is a block diagram of a system in accordance with one or more embodiments.

FIG. 3A is a block diagram of a system in accordance with one or more embodiments.

FIG. 3B is a block diagram of a system in accordance with one or more embodiments.

FIG. 3C is a timing diagram of a system in accordance with one or more embodiments.

FIG. 4 is a flow diagram of a method in accordance with one or more embodiments.

FIG. 5 is a timing diagram of a system in accordance with one or more embodiments.

FIG. 6 is a block diagram of a processor core in accordance with one or more embodiments.

FIG. 7 is a block diagram of a system in accordance with one or more embodiments.

FIG. 8 is a block diagram of a system in accordance with one or more embodiments.

FIG. 9 is a block diagram of an example system in accordance with one embodiment of the present invention.

DETAILED DESCRIPTION

The MIPI M-PHY physical layer specification (e.g., as defined by the MIPI Alliance specification for M-PHY of Feb. 8, 2011, approved Apr. 28, 2011) supports high-speed serial data rates across peripherals/components in mobile computing devices. An M-PHY link is a serial data connection between peripherals that includes two sublinks running in opposite directions. Each sublink constitutes one or more unidirectional point-to-point lanes running in the same direction. Each lane connects a transmitter and a receiver and is independent from other lanes in the same link as to operating mode and properties. Serial data is transferred over a lane using pulse width modulation signaling (PWM). The PWM signaling may operate at various data transfer speed ranges pursuant to one of the specification-defined gears (e.g., G1-G7).

Referring now toFIG. 1A, shown is a block diagram of a system in accordance with one or more embodiments. Shown is atransmitter104 and itscorresponding receiver112 as connected by twointerconnects106 and108. Although the transmitter and receiver may be implemented according to various protocols such as a given low power protocol, the transmitter and receiver as shown inFIG. 1A may be MIPI M-PHY-based devices. A differential-p point-to-point interconnect106 may be used to transmit a first differential PWM signal and the differential-n point-to-point interconnect108 may be used to transmit a second differential PWM signal, thereby constituting a differential pair of signals. Together, thetransmitter104 andreceiver112, as bridged byinterconnects106 and108, constitute alane102. While only one transmitter-receiver pair is explicitly shown, one skilled in the art will understand that many such transmitter-receiver pairs may exist to connect (e.g., via additional interconnects not shown) any two components or peripherals in a mobile computing device. The plurality of transmitter-receiver pairs is suggested by a set oftransmitters100 and a set ofreceivers110 as shown inFIG. 1A.

In accordance with one or more embodiments, the PWM signals are received by thereceiver112 and then processed. By processing the signals, thereceiver112 is able to perform a data recovery function (e.g., as indicated by116). In this manner, data is transferred from one component/peripheral to another at a high speed. A high speed, in accordance with some embodiments, means a variable speed based on PWM gear selection ranging between 3-576 MBPS (i.e., G1-G7 as described in the MIPI M-PHY specification). Specifically, in accordance with some embodiments, a delay locked loop (DLL)-based low power oversampling logic unit114 (e.g., implemented in receiver112) receives the signals from thetransmitter104 over theinterconnects106 and108 and also performs the processing steps. Signal processing by the DLL-based low poweroversampling logic unit114 is further discussed in relation to the subsequent FIGs.

Referring now toFIG. 1B, shown is a timing chart of a system in accordance with one or more embodiments. The timing chart shows an example of power states (i.e., voltage levels) of theinterconnects106 and108 (e.g., as shown inFIG. 1A) with respect to time. By serving as a means for differential PWM signal transport, these interconnects constitute a differential-p line118 and a differential-n line120. Thedifferential lines118 and120 may be sampled for a designated time period of data transfer between transmitter and receiver to determine how the transferred data (e.g., a single PWM databit) may be expressed. For example, the transferred databit may constitute a differential-p signal when the differential-p line118 is in a high power state and the differential-n line120 is in a low power state during the sampled time period. Otherwise, the transferred databit may constitute a differential-n signal when the differential-n line120 is in a high power state and the differential-p line118 is in a lower power state during the sampled time period.

Referring now toFIG. 2, shown is a block diagram of a system in accordance with one or more embodiments. In accordance with some embodiments, the system features shown inFIG. 2 may comprise the DLL-based low poweroversampling logic unit114 discussed in relation toFIG. 1. In some embodiments, the DLL-based low poweroversampling logic unit114 may include a 6-phase delay locked loops (DLL)unit204, a 12-pulsePWM clock generator208, a sample &hold unit212, a differential-to-single conversion unit214, anedge detector218, acounter222, and a decision/data recovery unit226.

In accordance with some embodiments, the 6-phase DLL unit204 may receive agear selection input202. The gear selection input may be any identifier or other selective means used to identify any one of a number of gears. In accordance with some embodiments, a gear is one of the 7 gears as defined by the MIPI Alliance's M-PHY specification. TheDLL unit204 may also receive a PWM core clock signal200 (i.e., a reference clock signal) as an input. Based on thegear selection input202 and the PWMcore clock signal200, theDLL unit204 may determine aphase delay output206. The determination of thephase delay output206 by theDLL unit204 is further discussed in relation toFIG. 3A.

In accordance with some embodiments, the 12-pulsePWM clock generator208 may receive thephase delay output206 as an input. Based on thephase delay output206, the 12-pulsePWM clock generator208 may generate an oversampledclock signal210 as an output. For example, the 12-pulsePWM clock generator208 may generate a pulse at every rising and falling edge of a PWM core clock signal200 (e.g., reference clock signal). As such, thereference clock signal200 may be amplified by the oversampling logic of thePWM clock generator208 to generate aclock signal210 with an increased frequency. The 12-pulsePWM clock generator208 may be any device or circuit that may be used to produce a timing signal for synchronizing operations.

In accordance with some embodiments, the sample &hold unit212 may receive two differential PWM signals overinterconnects106 and108 from atransmitter104. The sample &hold unit212 may also receive the oversampledclock signal210 as an input. Based on theseinputs106,108,210, the sample &hold unit212 may sampleinputs106 and108 (i.e., the differential PWM signals) for some time period (e.g., a cycle or half a cycle) based on the oversampledclock signal210 and then hold theinputs106 and108 for the like time period. After holding theinputs106 and108 for the designated time period, the sample &hold unit212 subsequently transmitsinputs106 and108 (i.e., the differential PWM signals) to the differential-to-single conversion unit214. In one or more embodiments, the sample &hold unit212 may be any device or circuit capable of sampling a series of input signals that are buffered and then released upon the completion of a specified timing period.

In accordance with some embodiments, the differential-to-single conversion unit214 receives differential PWM signals106 and108 from the sample &hold unit212. Further, the differential-to-single conversion unit214 converts the twoinput signals106 and108 to a single-endedPWM signal216. Upon conversion, the single-endedPWM signal216 is an output provided to theedge detector218.

In accordance with some embodiments, theedge detector218 receives the single-endedPWM signal216 as an input. The single-endedPWM signal216 is processed to determine the occurrence of rising and falling edges in thesignal216. For example, the detection of a rising edge results in the issue of a count-upsignal220 by theedge detector218. The detection of a falling edge results in the issue of a count-down signal220 by theedge detector218. In addition, theedge detector218 may also generate a reset signal in addition to a count-down signal220 upon detecting a falling edge for the single-endedPWM signal216.

In accordance with some embodiments, thecounter222 receives the edge detection signals220 as inputs. For example, thecounter222 may increase the count based on a received count-upsignal220 and decrease the count based on a received count-down signal220. As such, thecounter222 can determine a data output signal224 (i.e., a net count value). In some embodiments, thedata output signal224 is either a logical high value (e.g., “1”) or a logical low value (e.g., “0”) based on whether the count value is net positive or not.

In accordance with some embodiments, the decision/data recovery unit226 receives thedata output signal224 and a PWM core clock signal200 (e.g., reference clock signal). Based on theinputs224 and200, a data recovery step is performed. Said another way,data116 is transmitted at a high speed (e.g., a speed corresponding to a PWM gear selection) across the lane in accordance with the M-PHY specification.

Referring now toFIG. 3A, shown is a block diagram of a system in accordance with one or more embodiments. In accordance with some embodiments, the system features shown inFIG. 3A may comprise the 6-phase delay locked loops (DLL)unit204 discussed in relation toFIG. 2. Shown is aphase detector300, a DLL coarse &fine control unit304, a set of voltage-controlleddelay lines312, and a 12-pulsePWM clock generator208.

In accordance with some embodiments, thephase detector300 receives an inverted PWM core clock signal as an input. The PWMcore clock signal200 may be a reference clock signal in accordance with some embodiments. As such, in some embodiments, the PWMcore clock signal200 is provided from a source external to theDLL unit204. Further, in some embodiments, a phase output (i.e., ph0) from a first voltage-controlled day line is the PWM core clock signal input to thephase detector300. In all embodiments, aninverter device314 may be used in accordance with some embodiments to invert the PWMcore clock signal200.

In accordance with some embodiments, thephase detector300 receives afeedback clock signal310 as an input. In such embodiments, the feedback clock signal is received by thephase detector300 from a final voltage-controlled delay line (e.g., ph6 as shown inFIG. 3A).

In processing the inverted PWM core clock signal and thefeedback clock signal310, thephase detector300 determines a phase difference between the rising edges of the signals (i.e., the inverted PWM core clock signal/ph0 and the feedback clock signal/ph6). Based on the determination, thephase detector300 may generate and transmit an output302 indicative of which of the two signals is the first to evidence a first rising edge.

In accordance with some embodiments, the DLL coarse &fine control unit304 receives a phase detection output302 (e.g., a phase difference as determined by phase detector300), a PWM core clock signal200 (e.g., a reference clock signal), and agear selection input202. In processing these inputs, the DLL coarse &fine control unit304 determines a delay adjustment. The DLL coarse &fine control unit304 may express larger adjustments using acoarse control signal306 and smaller adjustments using afine control signal308. In some embodiments, the delay adjustment is applied to synchronize the PWMcore clock signal200 with thefeedback clock signal310.

In accordance with some embodiments, the voltage-controlleddelay lines312 receive acoarse control signal306 and/or afine control signal308. In some embodiments, the voltage-controlleddelay lines312 may be implemented as a set of delay buffers such that each delay buffer transmits one or more phase outputs (e.g., ph0-ph6 as shown inFIG. 3A). As shown inFIG. 3A, 6 phase outputs (e.g., ph0-ph5) are provided as inputs to the 12-pulsePWM clock generator208. Moreover, the phase output from each delay buffer also is provided as an input to a next delay buffer (e.g., output ph1 from the first delay buffer is provided as an input to the second delay buffer), with the two exceptions: (i) the first buffer does not receive a phase output as an input but rather receives acoarse control signal306 and/or afine control signal308; and (ii) the last buffer provides its phase output (i.e., ph6) as afeedback clock signal310 to the phase detector300 (i.e., since no subsequent delay buffer is available). In this way, the delay buffers may be said to have a cascading configuration such that delay signals306 and308 propagate through the voltage-controlled delay lines to generate 7 distinct phase outputs (e.g., ph0-ph6) at distinct times. Further detail as to the generated phase output signals is provided in relation toFIGS. 3B and 3C.

In accordance with some embodiments, the 12-pulsePWM clock generator208 receives the phase output signals (e.g., ph0-ph6 as shown inFIG. 3A) as inputs. On their own, ph1-ph6 are sufficient to generate a 6× oversampled clock signal. However, the 12-pulsePWM clock generator208 may used an edge detector to generate a 12× oversampledclock signal210 based on the 6× oversampled clock signal. As such, theDLL unit204 may take a lower-frequency PWM core clock signal200 (e.g., reference clock signal) and use it as a basis to generate a 12× oversampledclock signal210.FIGS. 3B and 3C show how this may be achieved in accordance with some embodiments.

Referring now toFIG. 3B, shown is a block diagram of a system in accordance with one or more embodiments. In some embodiments, the block diagram shown inFIG. 3B constitutes a series of logic gates that use phase output signals (e.g., ph0-ph5, as generated by the voltage-controlleddelay lines312 shown inFIG. 3A) to generate a 6× oversampled clock signal. As shown inFIG. 3B, ph0 and ph1 are inputs to a first XNOR gate to generate a first output, ph2 and ph3 are inputs to a second XNOR gate to generate a second output, and ph4 and ph5 are inputs to a third XNOR gate to generate a third output. The three outputs (e.g., from the XNOR gates) are then provided as three inputs to a NAND gate. The output of the NAND gate is inverted to generate a 6× oversampled clock signal.

Referring now toFIG. 3C, shown is a timing diagram of a system in accordance with one or more embodiments. In accordance with some embodiments,FIG. 3C shows a reference clock signal (e.g., PWMcore clock signal200 as shown inFIG. 3A) in a first row and an inverted clock signal (e.g., the PWMcore clock signal200 ofFIG. 3A as modified by an inverter314). As discussed in relation toFIG. 3A, the reference clock signal may be from a source external to theDLL unit204 in some embodiments. Further, in some embodiments, a phase output (i.e., ph0) from a first voltage-controlled day line may continue to function as the reference clock signal.

The third through eighth rows ofFIG. 3C show the reference clock signal as subject to a series of phase-shifted delays. For example, in the third row, ph1 is generated by subjecting the reference clock signal to the first voltage-controlled delay line. As such, ph1 is one delay interval later than the reference clock signal of the first row. Likewise, ph2 shown in the fourth row is one delay interval removed from ph1 in the third row (i.e., two delay intervals removed from reference clock signal/ph0 shown in the first row) and so forth as the reference clock signal is propagated through the cascaded voltage-controlleddelay lines312 shown inFIG. 3A. The result is that ph1 (third row), ph2 (fourth row), ph3 (fifth row), ph4 (sixth row), ph5 (seventh row), and ph6 (eighth row) are each shifted one delay interval later than the previous phase output signal.

Further, the 6× oversampled clock signal is the product of phase outputs ph0-ph5 as shown by the logic expressed inFIG. 3B. The products of the XNOR gates shown inFIG. 3B are shown in the ninth through eleventh rows ofFIG. 3C respectively. AsFIG. 3B shows, these XNOR gate products are then combined as inputs to a NAND gate to generate the 6× oversampled clock signal, which is shown in the twelfth row ofFIG. 3C. In some embodiments, the 6× oversampled clock signal may then be processed by an edge detector to generate a 12× oversampled clock signal as shown in the thirteenth row ofFIG. 3C. That is, the 12× oversampled clock signal includes a pulse for every rising and falling edge in the 6× oversampled clock signal.

Accordingly, as shown inFIGS. 3A-3C, aDLL unit204 may receive a reference clock signal and process it to generate a significantly more-frequent oversampled clock signal. For example, a 12× oversampled clock signal may be generated using merely 6 voltage-controlled delay lines and 6 phase outputs instead of 12 voltage-controlled delay lines and 12 phase outputs. Specifically, thePWM clock generator208 shown inFIG. 3A may: (i) receive the phase output signals (i.e., ph0-ph5); (ii) process the phase output signals using the logic shown inFIG. 3B to generate a 6× oversampled clock signal; and (iii) process the 6× oversampled clock signal using an edge detector to generate a 12× oversampled clock signal. One skilled in the art will note that generating a 12× oversampled clock signal using less than 12 voltage-controlled delay lines introduces a savings in terms of power as less architectural features are active or necessary.

Referring now toFIG. 4, shown is a flow diagram of a method in accordance with one or more embodiments. For example, the method shown inFIG. 4 may be performed by a system as described in relation toFIGS. 2 and 3. Beginning withStep400, differential input signals are received from a transmitter. In some embodiments, the differential input signals are transmitted from a MIPI M-PHY transmitter104 to a MIPI M-PHY receiver112 as shown inFIG. 1. For example, in some embodiments, the differential input signals may be received by a DLL-based low power oversampling logic unit114 (e.g., as shown inFIG. 1) or, more specifically, a sample & hold unit212 (e.g., as shown inFIG. 2) in a DLL-based low power oversampling logic unit.

InStep402, an oversampled clock signal may be generated based on a gear selection input and a reference clock signal (e.g., PWMcore clock signal200 as shown inFIGS. 2 and 3). In accordance with some embodiments, the gear selection input may be any identifier or datum indicative of an enumerated gear (e.g., G1-G7) defined by the MIPI Alliance's M-PHY specification or another specification. As discussed in relation toFIG. 3A, the oversampledclock signal210 may be generated using a 6-phase DLL unit204 in conjunction with a 12-pulsePWM clock generator208. As such, the generatedoversampled clock signal210 may function at a higher frequency (e.g., 12×) than the reference clock signal. Step402 is discussed in further detail in relation toFIG. 5.

In Step404, differential input signals (e.g., received in Step400) are converted to a single-ended PWM signal based on the oversampled clock signal. For example, in some embodiments, the differential input signals are sampled and held (e.g., by sample &hold unit212 as shown inFIG. 2) for some determined time period. Further, when a rising edge is detected in the oversampled clock signal, the differential input signals are converted to a single-ended signal (e.g., by theconversion unit214 shown inFIG. 2).

InStep406, the number of rising and falling edges is counted for the single-ended PWM signal. In some embodiments, anedge detector218 as shown in relation toFIG. 2 may be used to determine when a rising or falling edge registers in the single-endedPWM signal216. Upon edge detection, theedge detector218 may send a count-up or count-down signal to acounter222.

InStep408, a logical high or low value is determined based on the edge count and the oversampled clock signal. For example, in some embodiments, the counter222 (e.g., as shown inFIG. 2) determines abit value224 that is representative of the single-endedPWM signal216 based on all the count up/down signals provided by theedge detector218. If the count is net-positive (i.e., the count-up signals exceed the count-down signals) for a given period of the core clock signal, then the bit value may be a logical high value (e.g., “1”); otherwise, the bit value may be expressed as a logical low value (e.g., “0”). As such, a bit value (e.g., as signified by data output signal224) may be determined and transmitted for data recovery processing for each time period marked by thecore clock signal200.

InStep410, the bit value determined inStep408 is used as a basis for data recovery. For example, the bit value (e.g.,data output signal224 as shown inFIG. 2) may be transmitted from thecounter222 and provided as an input to the decision/data recovery unit226. In processing the bit value, the decision/data recovery unit226 will decide whether or not to recover data. In this manner, data may be transmitted between a MIPI M-PHY transmitter104 to a MIPI M-PHY receiver110.

Referring now toFIG. 5, shown is a flow diagram of a method in accordance with one or more embodiments. For example, the method shown inFIG. 5 may be performed by a system as described in relation toFIGS. 2 and 3. Specifically, the method shown inFIG. 5 may be performed as part ofStep402 as shown inFIG. 4. Beginning withStep500, a reference clock signal is received. In accordance with some embodiments, the reference clock signal200 (i.e., PWM core clock signal) is received by a delay lockedloop unit204 as shown inFIG. 2 (including a DLL coarse andfine control unit304 as shown inFIG. 3A).

InStep502, an inverted reference clock signal is generated. In accordance with some embodiments, an inverter device314 (e.g., as shown inFIG. 3A) is used to invert areference clock signal200 received by the delay lockedloop unit204.

In Step504, the inverted reference clock signal is compared with a feedback clock signal to determine a phase difference. In accordance with some embodiments, a phase detector300 (e.g., as shown inFIG. 3A) may be used to determine the phase difference as described herein. As such, thefeedback clock signal310 may be phase output ph6 from the final voltage-controlled delay line as shown inFIG. 3A. Further, the determined phase difference may be provided as an input to a DLL coarse andfine control unit304 as shown inFIG. 3A.

In Step506, a delay control signal is generated based on the phase difference. In accordance with some embodiments, a DLL coarse and fine control unit304 (e.g., as shown inFIG. 3A) may receive a phase difference (e.g., phase detection output302 as shown inFIG. 3A) as an input from aphase detector300. Based upon the phase difference, the DLL coarse andfine control unit304 may generate a fine control signal308 to apply a delay adjustment in a first fixed timing increment to the timing of subsequently generated phase outputs. Further, the DLL coarse andfine control unit304 may generate acoarse control signal306 to apply a delay adjustment in a second fixed timing increment to the timing of subsequently generated phase outputs. In one or more embodiments, the second fixed timing increment associated with thecoarse control signal306 is larger than the first fixed timing increment associated with thefine control signal308.

InStep508, the delay control signal is applied to a set of voltage-controlled delay lines to generate a set of phase outputs. In some embodiments, afine control signal308 and/or a coarse control signal306 (e.g., as generated by a DLL coarse and fine control unit as shown inFIG. 3A) is applied to the voltage-controlled delay lines shown inFIG. 3A to generate phase outputs ph0-ph6. In some embodiments, the phase outputs propagate through the voltage-controlled delay lines in the cascading manner previously described in relation toFIG. 3A (i.e., ph1 is the output of the first delay line and provided as an input to the second delay line, ph2 is the output of the second delay line and provided as an input to the third delay line, and so forth). Additionally, the phase outputs are also provided as inputs to aPWM clock generator208 as shown in relation toFIG. 3A.

In Step510, an oversampled clock signal is generated using the set of phase outputs. In some embodiments, aPWM clock generator208 as shown in relation toFIG. 3A receives phase outputs ph0-ph5 and generates the oversampledclock signal210 based on the received phase outputs.

Referring now toFIG. 6, shown is a timing diagram of a system in accordance with one or more embodiments. Shown is a series of square wave forms representative of the pulse-width modulated (PWM) signals involved in the previously-discussed systems and process (e.g., a MIPI M-PHY receiver architecture). In reference to the counter signal, the x-axis is time and the y-axis is a count value. In reference to all the other shown signals, the x-axis is also time but the y-axis is voltage.

The first waveform shown inFIG. 6 is the single-ended PWM signal. As discussed in relation to the previous FIGs., the single-ended PWM signal is provided when the differential to single-ended conversion unit214 (e.g., as shown inFIG. 2) processes the two differential PWM signals (e.g., Input p and Input n as shown inFIG. 2 and received in Step400).

The second and third waveforms shown inFIG. 6 are the count-down and count-upsignals220, respectively, generated by theedge detector218's processing of the single-ended PWM signal. As such, the second waveform is shown to indicate a count-down spike whenever the single-ended PWM signal evidences falling edges. Similarly, the third waveform is shown to indicate a count-up spike whenever the single-ended PWM signal evidences rising edges.

The fourth and fifth waveforms shown inFIG. 6 are the PWM core clock signal (i.e., clock reference signal) and oversampled clock signal respectively. AsFIG. 5 shows, the oversampled clock signal functions at a greater frequency than the clock reference signal.

The sixth and final waveform shown inFIG. 6 is the counter status. In some embodiments, the count is incremented, decremented, or reset on the basis of count-up and count-down/reset signals generated by theedge detector218. Accordingly, the present bit value maintained by thecounter222 at the end of each timing period marked by the reference clock signal is translated into a logical high or low value for sending to the decision/data recovery unit226. For example, the counter value is positive at the end of the first and third timing periods; as such, the bit value sent from thecounter222 to the decision/data recovery unit226 is “1” or a high logical value. Conversely, counter value is negative at the end of the second timing period; as such, the bit value sent from thecounter222 to the decision/data recovery unit226 is “0” or a low logical value. As previously discussed, the decision/data recovery unit226 performs or does not perform data recovery on the basis of the bit value received from thecounter222.

Referring now toFIG. 7, shown is a block diagram of a processor in accordance with one or more embodiments. As shown inFIG. 7,processor700 may be a multicore processor including a plurality of cores710a-710n. Each core may be associated with a corresponding voltage regulator712a-712n. The various cores may be coupled via aninterconnect715 to an uncore logic that includes various components. As seen, the uncore logic may include a sharedcache730 which may be a last level cache. In addition, the uncore logic may include anintegrated memory controller740, various interfaces750 and transmitter andreceiver logic755.

In various embodiments, transmitter andreceiver logic755 may include delay locked loop (DLL)-based lower poweroversampling receiver logic114 that in one embodiment may include hardware to execute firmware and/or software to perform the steps and functions described in relation to the previous FIGs. Specifically, the DLL-based low poweroversampling receiver logic114 shown inFIG. 7 may include features and logic as discussed in relation toFIGS. 2 and 3. In this way, the DLL-based low poweroversampling receiver logic114 can provide for high speed data transfer between components and across the physical layer of a mobile computing device.

With further reference toFIG. 7,processor700 may communicate with asystem memory760, e.g., via a memory bus. In addition, by interfaces750, connection can be made to various off-chip components such as peripheral devices, mass storage and so forth. While shown with this particular implementation in the embodiment ofFIG. 7, the scope of the various embodiments discussed herein is not limited in this regard.

Referring now toFIG. 8, shown is a block diagram of a system in accordance with one or more embodiments. As shown inFIG. 8, amultiprocessor system800 is a point-to-point interconnect system, and includes afirst processor802 and asecond processor804 coupled via a point-to-point interconnect. As shown inFIG. 8, each ofprocessors802 and804 may be multicore processors, including first and second processor cores (i.e.,processor cores814 and816), although potentially many more cores may be present in the processors.

Still referring toFIG. 8,first processor802 further includes a memory controller hub (MCH)820 and point-to-point (P-P) interfaces824 and826. Similarly,second processor804 includes aMCH822 andP-P interfaces828 and830. As shown inFIG. 8, MCH's820 and822 couple the processors to respective memories, namely amemory806 and amemory808, which may be portions of system memory (e.g., DRAM) locally attached to the respective processors.First processor802 andsecond processor804 may be coupled to achipset810 via P-P interconnects824 and830, respectively. As shown inFIG. 8,chipset810 includesP-P interfaces832 and834.

Furthermore,chipset810 includes aninterface836 tocouple chipset810 with a highperformance graphics engine812 by aP-P interconnect854. In turn,chipset810 may be coupled to afirst bus856 via aninterface838. As shown inFIG. 8, various input/output (I/O)devices842 may be coupled tofirst bus856, along with a bus bridge840 which couplesfirst bus856 to asecond bus858. Various devices may be coupled tosecond bus858 including, for example, a keyboard/mouse846,communication devices848 and adata storage unit850 such as a disk drive or other mass storage device which may includecode852, in one embodiment. The code, when executed, may provide for the execution of steps and functionality as described in relation to the earlier FIGs. Further, an audio I/O844 may be coupled tosecond bus858. Embodiments can be incorporated into other types of systems including mobile devices such as a smart cellular telephone, tablet computer, netbook, Ultrabook™, or so forth.

Embodiments may be implemented in code and may be stored on a non-transitory storage medium (e.g., machine-readable storage medium) having stored thereon instructions which can be used to program a system to perform the instructions. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, solid state drives (SSDs), compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions. Moreover, the embodiments may be implemented in code as stored in a microcontroller for a hardware device.

Referring now toFIG. 9, shown is a block diagram of anexample system900 with which embodiments can be used. As seen,system900 may be a smartphone or other wireless communicator. As shown in the block diagram ofFIG. 9,system900 may include abaseband processor910 which may be a multicore processor that can handle both baseband processing tasks as well as application processing. Thusbaseband processor910 can perform various signal processing with regard to communications, as well as perform computing operations for the device. In turn,baseband processor910 can couple to a user interface/display920 which can be realized, in some embodiments by a touch screen display. In addition,baseband processor910 may couple to a memory system including, in the embodiment ofFIG. 9 a non-volatile memory, namely aflash memory930 and a system memory, namely a dynamic random access memory (DRAM)935. As further seen,baseband processor910 can further couple to acapture device940 such as an image capture device that can record video and/or still images.

To enable communications to be transmitted and received, various circuitry may be coupled betweenbaseband processor910 and an antenna980. Specifically, a radio frequency (RF)transceiver970 and a wireless local area network (WLAN)transceiver975 may be present. In general,RF transceiver970 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as 3G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol. Other wireless communications such as receipt or transmission of radio signals, e.g., AM/FM, or global positioning satellite (GPS) signals may also be provided. In addition, viaWLAN transceiver975, local wireless signals, such as according to a Bluetooth™ standard or an IEEE 802.11 standard such as IEEE 802.11a/b/g/n can also be realized. Although shown at this high level in the embodiment ofFIG. 9, understand the scope of the present invention is not limited in this regard.

The following clauses and/or examples pertain to further embodiments:

One example embodiment may be an apparatus that includes a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal. The apparatus may further include a controller unit to generate a delay signal based on the phase difference. The apparatus may further include a set of voltage-controlled delay lines to generate a plurality of phase outputs based on the delay signal wherein each voltage-controlled delay line transmits two or more of the plurality of phase outputs. The plurality of phase outputs may be provided to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver. The controller unit may receive a gear selection input. The gear selection input may identify one of a plurality of speed ranges according to a lower power communication specification. A first delay line in the set of voltage-controlled delay lines may receive the delay signal from the controller unit and make a delay adjustment. The delay adjustment may be based on a coarse delay time period and a fine delay time period. The first delay line may provide a first phase output to both the clock generator unit and a second delay line in the set of voltage-controlled delay lines. A final delay line in the set of voltage-controlled delay lines may provide a second phase output to the phase detector. The second phase output may be the feedback clock signal. The phase difference may indicate a timing differential between the reference clock signal and the feedback clock signal. The set of voltage-controlled delay lines may be implemented using a delay-locked loop circuit. The delay-locked loop circuit may be a digital delay-locked loop circuit. The receiver may be a MIPI M-PHY receiver.

Another example embodiment may be a system comprising a system on a chip. The system on a chip may include at least one core having at least one execution unit and receiver logic. The receiver logic may include a digital delay-locked loop circuit to receive a reference pulse-width modulated (PWM) clock signal and a gear selection input. The delay-locked loop circuit may invert the reference PWM clock signal. The digital delay-locked loop circuit may determine a phase difference between the inverted reference PWM clock signal and a feedback clock signal. The digital delay-locked loop circuit may generate a plurality of phase output signals based on the phase difference. The receiver logic my further include a clock generator device to generate an oversampled clock signal based on the plurality of phase output signals. The oversampled clock signal may be used for data recovery by the receiver. The system may include a wireless device coupled to the system on a chip via an interconnect. The interconnect may be used to communicate data between the wireless device and the receiver logic of the system on a chip. The system may include a sample and hold unit to receive two differential input signals from the transmitter logic. The sample and hold unit may sample the two differential input signals for a first fixed time period. The sample and hold unit may buffer the two differential input signals for a second fixed time period. The sample and hold unit may send the two differential input signals to a conversion unit based on a frequency for the oversampled clock signal. The system may include a conversion unit to receive two differential input signals originating from the transmitter logic. The conversion unit may generate a single-ended PWM signal based on the two differential input signals. The system may include an edge detector unit to receive a single-ended PWM signal. The edge detector may generate and send a first type of signal when the single-ended PWM signal features a rising edge. The edge detector may generate an send a second type of signal when the single-ended PWM signal features a falling edge. The system may include a counter unit to receive the first type of signal and increment a bit value. The counter unit may receive the second type of signal and decrement the bit value. The counter unit may reset the bit value upon receipt of the second type of signal. The system may include a decision unit to receive the bit value. Based on the bit value, the decision unit may determine whether to recover at least one datum. The counter unit may send the bit value to the decision unit based on a frequency for the oversampled clock signal.

Another example embodiment may be a method. The method may involve determining a phase difference between an inverted reference clock signal and a feedback clock signal. The method may involve generating a delay signal based on the phase difference. The method may involve generating a plurality of phase outputs using a delay-locked loop circuit. The method may involve generating an oversampled clock signal based on the plurality of phase outputs. The oversampled clock signal may be used in performing data recovery by the receiver. The method may involve receiving differential signals from a transmitter. The method may involve sampling the differential signals for a fixed time period. The method may involve buffering the differential signals for the fixed time period. The method may involve converting the differential signals to a single-ended pulse-width modulated (PWM) signal. The method may involve processing the single-ended PWM signal to determine the number of rising and falling edges for a timing cycle based on a frequency for the oversampled clock signal. The method may involve determining a bit value for the single-ended PWM signal based on the number of rising and falling edges for the timing cycle. The method may involve performing a data recovery operation based on the bit value. The receiver may be a MIPI M-PHY receiver.

Another example embodiment may be a microcontroller executing in relation to a lower power oversampling logic unit, such that the microcontroller is arranged to perform the above-described method.

Another example embodiment may be a communication device arranged to perform the above-described method.

Another example embodiment may be at least one machine readable medium comprising a plurality of instructions that, in response to being executed on a computing device, cause the computing device to carry out the above-described method.

While a limited number of embodiments have been explicitly shown, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of the described embodiments.

Claims (21)

What is claimed is:

1. An apparatus, comprising:

a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal;

a controller unit to generate a delay signal based on the phase difference and to receive a gear selection input that identifies one of a plurality of speed ranges according to a low power communication specification; and

a set of voltage-controlled delay lines to generate a plurality of phase outputs based on the delay signal, wherein the plurality of phase outputs are provided to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.

2. The apparatus ofclaim 1, wherein a first delay line in the set of voltage-controlled delay lines is to receive the delay signal from the controller unit and make a delay adjustment, wherein the delay adjustment is based on one of a coarse delay time period and a fine delay time period.

3. The apparatus ofclaim 2, the first delay line to provide a first phase output to both the clock generator unit and a second delay line in the set of voltage-controlled delay lines.

4. The apparatus ofclaim 3, wherein a final delay line in the set of voltage-controlled delay lines is to provide a second phase output to the phase detector corresponding to the feedback clock signal.

5. The apparatus ofclaim 1, wherein the phase difference indicates a timing differential between the reference clock signal and the feedback clock signal.

6. The apparatus ofclaim 1, wherein the set of voltage-controlled delay lines is implemented using a delay-locked loop circuit.

7. The apparatus ofclaim 6, wherein the delay-locked loop circuit is a digital delay-locked loop circuit.

8. The apparatus ofclaim 1, wherein the receiver is a MIPI M-PHY receiver.

9. A system, comprising:

a system on a chip comprising at least one core having at least one execution unit and receiver logic, the receiver logic comprising:

a digital delay-locked loop circuit to:

receive a reference pulse-width modulated (PWM) clock signal and a gear selection input;

invert the reference PWM clock signal;

determine a phase difference between the inverted reference PWM clock signal and a feedback clock signal;

generate a plurality of phase output signals based on the phase difference; and

a clock generator device to generate an oversampled clock signal based on the plurality of phase output signals, the oversampled clock signal to be used for data recovery by the receiver logic; and

a wireless device coupled to the system on the chip via an interconnect, the interconnect used to communicate data between the wireless device and the receiver logic of the system on the chip.

10. The system ofclaim 9, further comprising:

a sample and hold unit to:

receive a differential input signal pair from the wireless device;

sample the differential input signal pair for a first fixed time period; and

buffer the differential input signal pair for a second fixed time period.

11. The system ofclaim 10, the sample and hold unit further to:

send the differential input signal pair to a conversion unit based on a frequency for the oversampled clock signal.

12. The system ofclaim 9, further comprising:

a conversion unit to:

receive a differential input signal pair, the differential input signal pair originating from the wireless device; and

generate a single-ended PWM signal based on the differential input signal pair.

13. The system ofclaim 9, further comprising:

an edge detector unit to:

receive a single-ended PWM signal;

generate and send a first type of signal when the single-ended PWM signal features a rising edge; and

generate and send a second type of signal when the single-ended PWM signal features a falling edge.

14. The system ofclaim 13, further comprising:

a counter unit to:

receive the first type of signal and increment a bit value; and

receive the second type of signal and decrement the bit value.

15. The system ofclaim 14, the counter unit further to:

reset the bit value upon receipt of the second type of signal.

16. The system ofclaim 15, further comprising:

a decision unit to:

receive the bit value; and

based on the bit value, determine whether to recover at least one datum;

the counter unit further to:

send the bit value to the decision unit based on a frequency for the oversampled clock signal.

17. A method, comprising:

determining, in an oversampling logic unit of a receiver, a phase difference between an inverted reference clock signal and a feedback clock signal;

generating a delay signal based on the phase difference;

receiving a gear selection input that identifies one of a plurality of speed ranges according to a low power communication specification;

generating a plurality of phase outputs using a delay-locked loop circuit of the oversampling logic unit; and

generating an oversampled clock signal based on the plurality of phase outputs, the oversampled clock signal for use in performing data recovery by the receiver.

18. The method ofclaim 17, further comprising:

receiving, in the receiver, a differential signal pair from a transmitter coupled to the receiver;

sampling the differential signal pair for a fixed time period based on the oversampled clock signal; and

buffering the differential signal pair for the fixed time period.

19. The method ofclaim 18, further comprising:

converting the differential signal pair to a single-ended pulse-width modulated (PWM) signal; and

processing the single-ended PWM signal to determine the number of rising and falling edges for a timing cycle based on a frequency for the oversampled clock signal.

20. The method ofclaim 19, further comprising:

determining a bit value for the single-ended PWM signal based on the number of rising and falling edges for the timing cycle; and

performing a data recovery operation based on the bit value.

21. The method ofclaim 17, wherein the receiver is a MIPI M-PHY receiver.

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