US8785289B2 - Integrated decoupling capacitor employing conductive through-substrate vias - Google Patents
Integrated decoupling capacitor employing conductive through-substrate viasDownload PDFInfo
- Publication number
- US8785289B2 US8785289B2US13/975,519US201313975519AUS8785289B2US 8785289 B2US8785289 B2US 8785289B2US 201313975519 AUS201313975519 AUS 201313975519AUS 8785289 B2US8785289 B2US 8785289B2
- Authority
- US
- United States
- Prior art keywords
- substrate
- conductive
- dielectric
- forming
- tsv
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
- H01L25/0657—Stacked arrangements of devices
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D88/00—Three-dimensional [3D] integrated devices
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D88/00—Three-dimensional [3D] integrated devices
- H10D88/01—Manufacture or treatment
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Definitions
- the present inventionrelates to the field of semiconductor structures, and particularly to a decoupling capacitor that employs a conductive through-substrate via and methods of manufacturing the same.
- 3DSithree dimensional silicon
- this noiseis controlled by embedding deep trench capacitors (DTC) within active silicon devices.
- DTCdeep trench capacitors
- a large array of DTC'sare required.
- the circuit density, switching activity, and power distribution structuresare enhanced in a 3DSi structure, more DTC's will be required to control the noise generation.
- VnL ⁇ ( dI/dt ), in which L is inductance, I is current, and t is time.
- Linductance
- Icurrent
- ttime
- a capacitor in a semiconductor substrateemploys a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode.
- TSVthrough-substrate via
- the capacitorprovides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSV's can be provided in the semiconductor substrate to provide electrical connection for power supplies and signal transmission therethrough.
- the capacitorhas a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips.
- a semiconductor structureincludes a semiconductor chip, which includes a semiconductor substrate; at least one capacitor embedded in the semiconductor substrate; and at least one laterally-insulated conductive through-substrate connection structure.
- Each of the at least one capacitorincludes an inner electrode including a conductive through-substrate via (TSV) structure; a node dielectric laterally contacting and laterally enclosing the inner electrode; and an outer electrode laterally contacting and laterally enclosing a portion of the node dielectric.
- TSVconductive through-substrate via
- a semiconductor structureincludes a capacitor located in a semiconductor substrate and a contact structure located on the semiconductor substrate.
- the capacitorincludes an inner electrode, a node dielectric, and an outer electrode.
- the inner electrodeincludes a conductive through-substrate via (TSV) structure that contiguously extends at least from an upper surface of the semiconductor substrate to a lower surface of the semiconductor substrate.
- TSVthrough-substrate via
- the node dielectriclaterally contacts and laterally encloses the inner electrode and contiguously extends from the upper surface to the lower surface.
- the outer electrodelaterally contacts and laterally encloses a portion of the node dielectric.
- the contact structureis conductively connected to the outer electrode.
- a method of forming a semiconductor structureincludes forming a capacitor and a laterally-insulated conductive through-substrate connection structure in a semiconductor substrate.
- the laterally-insulated conductive through-substrate connection structureis formed by forming a dielectric tubular structure around a first through-substrate cavity formed in the semiconductor substrate; and filling a cavity within the dielectric tubular structure with a conductive material.
- the capacitoris formed by forming an outer electrode by doping a portion of the semiconductor substrate around a second through-substrate cavity; forming a node dielectric on a surface of the second through-substrate cavity; and forming an inner electrode by filling the second through-substrate cavity with the conductive material.
- a method of forming a semiconductor structureincludes providing a semiconductor chip and electrically connecting the semiconductor chip to a mounting structure employing an array of solder balls.
- the semiconductor chipincludes a semiconductor substrate; at least one capacitor embedded in the semiconductor substrate; and at least one laterally-insulated conductive through-substrate connection structure.
- the at least one capacitorhas an inner electrode that includes a conductive through-substrate via (TSV) structure.
- TSVconductive through-substrate via
- FIGS. 1-18are sequential vertical cross-sectional views through various processing steps of a first exemplary structure according to a first embodiment of the present invention.
- FIG. 19is a vertical cross-sectional view of a second exemplary structure according to a second embodiment of the present invention.
- FIG. 20is a vertical cross-sectional view of a third exemplary structure according to a third embodiment of the present invention.
- FIG. 21is a graph showing results of a simulation that shows a noise reduction at high frequency provided by an exemplary structure according to an embodiment of the present invention.
- the present inventionrelates to semiconductor structures, and particularly to a decoupling capacitor that employs a conductive through-substrate via and methods of manufacturing the same, which are now described in detail with accompanying figures.
- the same reference numerals or lettersare used to designate like or equivalent elements.
- the drawingsare not necessarily drawn to scale.
- a “conductive through-substrate via (TSV) structure”is a conductive structure that extends through a substrate, i.e., at least from a top surface of the substrate to a bottom surface of the substrate.
- a “laterally-insulated conductive through-substrate connection structure”is an assembly of a conductive TSV structure and another structure that laterally surrounds the conductive TSV structure and electrically isolates the conductive TSV structure from the substrate.
- a “mounting structure”is any structure to which a semiconductor chip can be mounded by making electrical connections thereto.
- a mounting structurecan be a packaging substrate, an interposer structure, or another semiconductor chip.
- a first element“laterally contacts” a second element if there is a direct physical contact between the first element and the second element in a “lateral direction,” which is any direction perpendicular to a top surface or a bottom surface of a substrate.
- a first element“laterally encloses” a second element if an inner periphery of the first element is located on or outside an outer periphery of the second element.
- a first element“encapsulates” a second element if all outer surfaces of the second element are located within inner surfaces of the first element.
- two elementsare “conductively connected” to each other if there exists a conductive path between the two elements to allow conduction of electricity.
- a first exemplary structure according to a first embodiment of the present inventionincludes a semiconductor substrate 10 that has a semiconductor material.
- the semiconductor material of the semiconductor substrate 10can be selected from, but is not limited to, silicon, germanium, silicon-germanium alloy, silicon carbon alloy, silicon-germanium-carbon alloy, gallium arsenide, indium arsenide, indium phosphide, III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, and other compound semiconductor materials.
- the semiconductor material of the semiconductor substrate 10is a single crystalline material.
- the semiconductor substrate 10can be a single crystalline silicon layer.
- the semiconductor substrate 10can be doped with dopants of a first conductivity type, which can be p-type or n-type.
- the dopant concentration of the semiconductor substrate 10can be from 1.0 ⁇ 10 14 /cm 3 to 1.0 ⁇ 10 17 /cm 3 .
- a doped well region 12is formed in the semiconductor substrate 12 by implanting dopants of a second conductivity through a portion of the top surface of the semiconductor substrate 12 .
- the second conductivity typeis the opposite of the first conductivity type.
- the second conductivity typeis n-type if the first conductivity type is p-type, and vice versa.
- the dopant concentration of the doped well region 12can be from 1.0 ⁇ 10 18 /cm 3 to 1.0 ⁇ 10 21 /cm 3 to increase the conductivity of the doped well region 12 .
- a pad dielectric layer 16 and a first mask layer 18are formed on the top surface of the semiconductor substrate 10 .
- the pad dielectric layer 16may, or may not, be formed on the backside of the semiconductor substrate 10 .
- the pad dielectric layer 16includes a dielectric material such as silicon nitride.
- the first mask layer 18can be composed of a photoresist or a dielectric material such as silicon oxide or silicon nitride.
- the first mask layer 18is lithographically patterned, and the pattern in the first mask layer 18 is transferred through the semiconductor substrate 10 by an anisotropic etch that employs the first mask layer 18 as an etch mask.
- a first through-substrate cavity 47is formed in the semiconductor substrate 10 .
- the lateral dimensions, e.g., diameter, a major axis, a minor axis, a length of a side, of the first through-substrate cavity 47can be from 1 micron to 100 microns, and typically from 3 microns to 30 microns, although lesser and greater lateral dimensions can also be employed.
- the first mask layer 18can be removed selective to the semiconductor substrate 10 .
- a dielectric tubular structure 20is formed around the first through-substrate cavity 47 , for example, by converting exposed portions of the semiconductor substrate 10 on the sidewalls of the first through-substrate cavity 47 into a dielectric material.
- the exposed portion of the semiconductor substratecan be converted into a dielectric oxide by thermal oxidation.
- the dielectric tubular structure 20can include an oxide of the semiconductor material of the semiconductor substrate 10 .
- the dielectric tubular structure 20can include silicon oxide.
- the pad dielectric layer 16prevents conversion of other portions of the semiconductor substrate 10 into a dielectric material.
- the dielectric tubular structure 20extends from the top surface of the semiconductor substrate 10 to the bottom surface of the semiconductor substrate 10 .
- a horizontal cross-sectional area of the dielectric tubular structure 20includes a hole corresponding to the first through-substrate cavity 47 .
- the thickness of the dielectric tubular structure 20as measured laterally between an inner periphery of the dielectric tubular structure 20 and an outer periphery of the dielectric tubular structure 20 can be from 100 nm to 1 micron, although lesser and greater thicknesses can also be employed.
- the pad dielectric layer 16can be removed.
- a dielectric liner 30is deposed on the inner sidewalls of the dielectric tubular structure 20 .
- the dielectric liner 30can include, for example, a stack of a silicon oxide layer and a silicon nitride layer.
- the first through-substrate cavity 47is filled with a first disposable material to form a first disposable material layer 49 L.
- the first disposable material layer 49 Lextends through the semiconductor substrate 10 and covers both sides of the semiconductor substrate 10 , thereby encapsulating the semiconductor substrate 10 .
- the first disposable materialcan be, for example, a polycrystalline silicon-containing material such as polysilicon or an amorphous silicon-containing material such as amorphous silicon.
- the first disposable material layer 49 Lis removed from the front side and the backside of the semiconductor substrate 10 , for example, by an etch-back process or chemical mechanical planarization (CMP). Further, a portion of the first disposable material layer 49 L is recessed below the top surface of the semiconductor substrate 10 by a recess depth rd, which can be from 200 nm to 2,000 nm, although lesser and greater recess depths rd can also be employed. The remaining portion of the first disposable material layer 49 L constitutes a first disposable material portion 49 .
- CMPchemical mechanical planarization
- a dielectric cap portion 50is formed by filling a cavity above the first disposable material portion 49 with a dielectric material and removing excess dielectric material above a top surface of the dielectric liner 30 .
- a silicon nitride cap layer(not shown) can be deposited on the top surface of the dielectric cap portion 50 and the portion of the dielectric liner 30 located on the front side of the semiconductor substrate 10 .
- a second mask layer 51is formed above the top surface of the semiconductor substrate 10 .
- the second mask layer 51can be composed of a photoresist or a dielectric material such as silicon oxide or silicon nitride.
- the second mask layer 51is lithographically patterned to form an opening in an area that does not overlie the disposable material portion 49 or the dielectric tubular structure 20 .
- the opening in the second mask layer 51is formed over or in proximity to the doped well region 12 .
- the pattern in the second mask layer 51is transferred through the semiconductor substrate 10 by an anisotropic etch that employs the second mask layer 51 as an etch mask.
- a second through-substrate cavity 67is formed in the semiconductor substrate 10 .
- the lateral dimensions, e.g., diameter, a major axis, a minor axis, a length of a side, of the second through-substrate cavity 67can be from 1 micron to 100 microns, and typically from 3 microns to 30 microns, although lesser and greater lateral dimensions can also be employed.
- a doped material layer 52is deposited on the exposed surfaces of the first exemplary structure including the sidewalls of the second through-substrate cavity 67 .
- the doped material layer 52includes dopants of the second conductivity type.
- the doped material layer 52can be, for example, an arsenosilicate glass (ASG) layer.
- the thickness of the doped material layer 52is less than half of the smallest lateral dimension of the second through-substrate cavity 67 to prevent plugging of the second through-substrate cavity 67 .
- a dielectric capping layer(not shown) may be deposited over the doped material layer 52 to prevent loss of dopants during a subsequent drive-in anneal.
- a drive-in annealis performed to induce outdiffusion of dopants of the second conductivity type into a region of the semiconductor substrate 10 that surrounds the second through-substrate cavity 67 .
- An outer electrodeis formed by doping a portion of the semiconductor substrate 10 around the second through-substrate cavity 67 .
- the outer electrode 60is formed by converting a tubular region, i.e., a region in the shape of a tube, into a doped semiconductor region having a doping of the second conductivity type.
- a dopant-containing material layersuch as an arsenosilicate glass layer can be deposited on sidewalls of the second through-substrate cavity 67 and the dopants can be driven into the semiconductor substrate 10 by a drive-in anneal.
- the outer electrode 60is a doped tubular portion including a doped semiconductor material, i.e., has a shape of a tube.
- the lateral distance between the outer periphery of the outer electrode 60 and the inner periphery of the outer electrode, i.e., the boundary with the doped material layer 52can be from 150 nm to 1,000 nm, although a lesser and greater lateral distances can also be employed.
- the dopant concentration of the outer electrode 60can be from 1.0 ⁇ 10 18 /cm 3 to 1.0 ⁇ 10 20 /cm 3 , although a lesser and greater dopant concentration can also be employed.
- the doped material layer 52is subsequently removed.
- the outer electrode 60can be formed by plasma doping without employing a doped material layer 52 .
- a node dielectric 70is formed on all exposed surfaces of the first exemplary structure including the inner sidewalls of the outer electrode 60 , which are the surfaces of the second through-substrate cavity 67 , and exposed surfaces of the dielectric liner 30 .
- the node dielectric 70is formed directly on sidewalls of the doped tubular portion while the disposable material is present in the semiconductor substrate.
- the thickness of the node dielectric 70can be from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed.
- the second through-substrate cavity 67is filled with a second disposable material to form a second disposable material layer 77 L.
- the second disposable material layer 77 Lextends through the semiconductor substrate 10 and covers both sides of the semiconductor substrate 10 , thereby encapsulating the semiconductor substrate 10 .
- the second disposable materialcan be, for example, a polycrystalline silicon-containing material such as polysilicon or an amorphous silicon-containing material such as amorphous silicon.
- the second disposable material layer 77 Lis removed from the front side and the backside of the semiconductor substrate 10 , for example, by an etch-back process or chemical mechanical planarization (CMP).
- CMPchemical mechanical planarization
- the remaining portion of the second disposable material layer 77 Lconstitutes a second disposable material portion 77 .
- the top surface of the second disposable material portion 77can be coplanar with a top surface of the node dielectric 70 on the front side of the semiconductor substrate 20 .
- a hard mask layer 72is formed on one side of the semiconductor substrate 20 , which is preferably the front side of the semiconductor substrate on which the dielectric cap portion 50 is located.
- the hard mask layer 72includes a dielectric material such as silicon oxide, silicon nitride, a doped silicate glass, or a combination thereof.
- the thickness of the hard mask layer 72can be from 500 nm to 5,000 nm, and typically from 1,000 nm to 3,000 nm, although lesser and greater thicknesses can also be employed.
- the hard mask layer 72is lithographically patterned to form openings over the second disposable material portion 77 and the first disposable material portion 49 .
- the dielectric cap portion 50is removed to expose an upper surface of the first disposable material portion 49 .
- An upper portion of the second disposable material portion 77can be removed during the removal of the dielectric cap portion 50 .
- the first dielectric material of the first disposable material portion 49 and the second dielectric material of the second dielectric material portion 77are removed by an etch that employs the hard mask layer 72 as an etch mask. Removal of the first disposable material portion 49 forms a cavity in a volume corresponding to the first through-substrate cavity 47 in prior processing steps. This cavity is herein referred to as a re-formed first through-substrate cavity 79 , i.e., a first through-substrate cavity that is formed a second time Likewise, removal of the second disposable material portion 77 forms a cavity in a volume corresponding to the second through-substrate cavity 67 in prior processing steps.
- This cavityis herein referred to as a re-formed second through-substrate cavity 78 , i.e., a second through-substrate cavity that is formed a second time.
- the re-formed first through-substrate cavity 79is formed within the dielectric tubular structure 20 .
- Surfaces of the node dielectric 70is exposed around the re-formed second through-substrate cavity 78 , and surfaces of the dielectric liner 30 can be exposed around the re-formed first through-substrate cavity 79 . If the dielectric liner 30 is not present, inner surfaces of the dielectric tubular structure 20 can be exposed in the re-formed first through-substrate cavity 79 .
- the re-formed first through-substrate cavity 79 and the re-formed second through-substrate cavity 78are filled with a conductive material to form a first conductive through-substrate via (TSV) structure 80 and a second conductive TSV structure 82 , respectively.
- the conductive material of the first conductive TSV structure 80 and the second conductive TSV structure 82can include a doped semiconductor material, a metallic material, or a combination thereof.
- the conductive material of the first conductive TSV structure 80 and the second conductive TSV structure 82can include, but is not limited to, doped polysilicon, a doped silicon-containing alloy, Cu, W, Ta, Ti, WN, TaN, TiN, or a combination thereof.
- the conductive materialcan be deposited, for example, by electroplating, electroless plating, physical vapor deposition (PVD), chemical vapor deposition (CVD), or a combination thereof.
- top surfaces of the first conductive TSV structure 80 and the second conductive TSV structure 82are coplanar with a top surface of the hard mask layer 72 .
- Bottom surfaces of the conductive TSV structure 80 and the second conductive TSV structure 82are coplanar with a bottom surface of remaining portions of the first exemplary structure.
- the bottom surface of the remaining portions of the first exemplary structurecan be, for example, an exposed surface of the node dielectric 70 if a bottom portion of the node dielectric 70 remains after planarization or any other exposed surfaces at the bottom of the first exemplary structure.
- the first conductive TSV structure 80 and the second conductive TSV structure 82are formed concurrently by employing the same deposition process and the same planarization process.
- a contact structure 90is formed by forming a trench through the hard mask layer 72 , the node dielectric 70 , and the dielectric liner 30 and by filling the trench with a conductive material such as a doped semiconductor material or a metallic material.
- the contact structure 90is conductively connected to the outer electrode 60 through the doped well region 12 .
- the first conductive TSV structure 80 , the node dielectric 70 , and the outer electrode 60collective constitute a capacitor 180 , in which the first conductive TSV structure 80 is an inner electrode.
- the second conductive TSV structure 82 , the portion of the dielectric liner contacting the second conductive TSV structure 82 , and the dielectric tubular structure 20collectively constitute an laterally-insulated conductive through-substrate connection structure 182 .
- An end surface of the first conductive TSV structure 80 , an end surface of the second conductive TSV structure 82 , and an end surface of the contact structure 90can be coplanar with an exposed surface of the hard mask layer 72 .
- the first exemplary structurecan be incorporated in a semiconductor chip.
- a plurality of instances of the capacitor 180 and a plurality of instances of the laterally-insulated conductive through-substrate connection structure 182can be embedded in the same semiconductor substrate 10 of the semiconductor chip.
- the semiconductor chipmay, or may not, include other semiconductor devices such as field effect transistors, bipolar transistors, thyristors, and diodes.
- Each capacitor 180can include an inner electrode, which includes a first conductive through-substrate via (TSV) structure 80 , a node dielectric 70 , and an outer electrode 60 .
- the inner electrodecontiguously extends at least from an upper surface of the semiconductor substrate 10 to a lower surface of the semiconductor substrate 10 .
- the node dielectric 70laterally contacts and laterally encloses the inner electrode.
- the node dielectric 70contiguously extends from the upper surface to the lower surface.
- the outer electrode 60laterally contacts and laterally encloses a portion of the node dielectric 70 .
- the outer electrode 60includes a doped semiconductor material.
- the laterally-insulated conductive through-substrate connection structure 182includes a second conductive TSV structure 82 located in the semiconductor substrate 10 and a dielectric tubular structure 20 laterally surrounding the second conductive TSV structure 82 and embedded in the semiconductor substrate 10 .
- the laterally-insulated conductive through-substrate connection structure 182can include a portion of the dielectric liner 30 .
- a second exemplary structureincludes a packaging substrate 200 , a plurality of first semiconductor chips 100 , a plurality of second semiconductor chips 300 , an array of first solder balls 199 electrically connecting each of the first semiconductor chips 100 to the packaging substrate 200 , and an array of second solder balls 299 electrically connecting each of the second semiconductor chips 300 to a first semiconductor chip 100 .
- Each of the first semiconductor chips 100includes at least one capacitor 180 and at least one laterally-insulated conductive through-substrate connection structure 182 .
- the first semiconductor chips 100may, or may not, include additional semiconductor devices such as field effect transistors, bipolar transistors, thyristors, and diodes.
- the second semiconductor chips 300can include any type of semiconductor devices.
- the capacitors 180can function as decoupling capacitors that reduce noise in a power supply system that supplies power to the devices in the second semiconductor chips 300 and, if present, to the devices in the first semiconductor chips 100 .
- Each capacitor 180can provide a capacitance on the order of 1 pF to 10 nF, which is equivalent to the capacitance of 40-400,000 typical trench capacitors. Further, the capacitor 180 provides a lower inductance than a trench capacitor array that provides a comparable total capacitance. Thus, the capacitors 180 reduce noise in the power supply system especially during high frequency operations.
- a third exemplary structureincludes a packaging substrate 200 , a interposer structure 400 , a plurality of first semiconductor chips 100 , and a plurality of second semiconductor chips 300 .
- An array of first solder balls 199electrically connects each of the first semiconductor chips 100 to the interposer structure 400 .
- An array of second solder balls 299electrically connects each of the second semiconductor chips 300 to a first semiconductor chip 100 .
- An array of third solder balls 399connects the interposer structure 400 to the packaging substrate 200 .
- the interposer structure 400can include an interposer structure substrate layer 410 , a lower dielectric material layer 420 , and an upper dielectric material layer 430 .
- the interposer structure substrate layer 410includes a plurality of through-substrate via structures that are schematically illustrated as vertical lines.
- the plurality of through-substrate via structuresincludes a plurality of capacitors 180 (See FIG. 18 ) and laterally-insulated conductive through-substrate connection structure 182 (See FIG. 18 ).
- the lower dielectric material layer 420 and the upper dielectric material layer 430can include metal lines that provide electrical wiring within the lower dielectric material layer 420 or the upper dielectric material layer 430 .
- a semiconductor chip including at least one capacitor 180 and at least one laterally-insulated conductive through-substrate connection structure 182can be mounted a mounting structure, which can be any structure on which the semiconductor chip can be mounted with electrical connections thereto.
- the mounting structurecan be, but is not limited to, a packaging substrate 200 , an interposer structure 400 , an assembly of an interposer structure 400 and a packaging substrate 200 , or another semiconductor chip such as a second semiconductor chip 300 .
- a graphshows results of a simulation that shows a noise reduction at high frequency provided by an exemplary structure according to an embodiment of the present invention.
- the horizontal axisrepresents frequency of a noise component in a power supply system
- the vertical axisrepresents an equivalent impedance of a decoupling system including either a capacitor 180 (See FIG. 18 ) according to an embodiment of the present invention or an array of trench capacitors according to prior art.
- the electrical noise in a power supply systemis proportional to the equivalent impedance.
- the curve labeled “TSV w/582 pF”represents the equivalent impedance of a capacitor 180 having a capacitance of 582 pF and constructed according to an embodiment of the present invention, e.g., as shown in FIG.
- the curves labeled “DTC w/582 pF,” “2 nF,” and “4 nF”represent the equivalent impedance of trench capacitor arrays having a total capacitance of 582 pF, 2 nF, and 4 nF, respectively.
- the voltage noise in the system power supplyis limited by the total capacitance of a decoupling capacitor system.
- the voltage noise in decoupling capacitor systems employing any of the trench capacitor arraysincreases to with frequency on a converging curve irrespective of the total capacitance of the decoupling capacitor system because inductance of the decoupling capacitor system dominates.
- the decoupling capacitor system employing a capacitor 180 of an embodiment of the present inventionprovides a lower voltage noise at frequencies above 1.2 GHz except for a small frequency range between 4 GHz and 4.5 GHz because the capacitor 180 has a low inductance.
- the decoupling capacitor system employing a capacitor 180 of an embodiment of the present inventionprovides a superior performance in noise reduction while consuming less device area.
- the capacitors 180can be formed without requiring any area in the third semiconductor chips 300 .
- the capacitors 180can be formed in a smaller area than an array of trench capacitors having a comparable total capacitance, thereby providing more area for other semiconductor devices that can be included in the first semiconductor chips 100 .
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
This application is a divisional of U.S. patent application Ser. No. 12/614,883, filed Nov. 9, 2009 the entire content and disclosure of which is incorporated herein by reference.
The present invention relates to the field of semiconductor structures, and particularly to a decoupling capacitor that employs a conductive through-substrate via and methods of manufacturing the same.
In resent years, “three dimensional silicon” (3DSi) structures have been proposed to enable joining of multiple silicon chips and/or wafers that are mounted on a package or a system board. The 3DSi structures increase the density of active circuits that are integrated in a given space.
As the circuit density increases unit area, the amount of switching activity per unit area also increases. This results in an increase in the noise generated on the reference supplies. As this noise increases, the performance of the internal devices as well as the performance of off-chip drivers is adversely impacted due to the reduction of noise margins available for the system design.
At present, this noise is controlled by embedding deep trench capacitors (DTC) within active silicon devices. To obtain sufficient degree of decoupling, a large array of DTC's are required. As the circuit density, switching activity, and power distribution structures are enhanced in a 3DSi structure, more DTC's will be required to control the noise generation. Further, as a number of DTC arrays are formed, there is an increase in the inductance between the active circuits and the arrays of DTC's, thereby requiring formation of additional DTC's to store the energy to be used to counter-balance a back electromagnetic force noise.
The voltage of the noise Vn is given by the following equation:
Vn=L×(dI/dt),
in which L is inductance, I is current, and t is time. As the amount of inductance (L) increases, or as the speed at which the current changes (dI/dt), which is proportional to the switching speed of circuits, the noise Vn increases proportionally.
Vn=L×(dI/dt),
in which L is inductance, I is current, and t is time. As the amount of inductance (L) increases, or as the speed at which the current changes (dI/dt), which is proportional to the switching speed of circuits, the noise Vn increases proportionally.
The above considerations show that capacitive structures having low inductive is needed to control inductively noise generated within and transmitted into a 3DSi structure.
According to an embodiment of the present invention, a capacitor in a semiconductor substrate employs a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSV's can be provided in the semiconductor substrate to provide electrical connection for power supplies and signal transmission therethrough. The capacitor has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips.
According to an aspect of the present invention, a semiconductor structure includes a semiconductor chip, which includes a semiconductor substrate; at least one capacitor embedded in the semiconductor substrate; and at least one laterally-insulated conductive through-substrate connection structure. Each of the at least one capacitor includes an inner electrode including a conductive through-substrate via (TSV) structure; a node dielectric laterally contacting and laterally enclosing the inner electrode; and an outer electrode laterally contacting and laterally enclosing a portion of the node dielectric.
According to another aspect of the present invention, a semiconductor structure includes a capacitor located in a semiconductor substrate and a contact structure located on the semiconductor substrate. The capacitor includes an inner electrode, a node dielectric, and an outer electrode. The inner electrode includes a conductive through-substrate via (TSV) structure that contiguously extends at least from an upper surface of the semiconductor substrate to a lower surface of the semiconductor substrate. The node dielectric laterally contacts and laterally encloses the inner electrode and contiguously extends from the upper surface to the lower surface. The outer electrode laterally contacts and laterally encloses a portion of the node dielectric. The contact structure is conductively connected to the outer electrode.
According to yet another aspect of the present invention, a method of forming a semiconductor structure is provided. The method includes forming a capacitor and a laterally-insulated conductive through-substrate connection structure in a semiconductor substrate. The laterally-insulated conductive through-substrate connection structure is formed by forming a dielectric tubular structure around a first through-substrate cavity formed in the semiconductor substrate; and filling a cavity within the dielectric tubular structure with a conductive material. The capacitor is formed by forming an outer electrode by doping a portion of the semiconductor substrate around a second through-substrate cavity; forming a node dielectric on a surface of the second through-substrate cavity; and forming an inner electrode by filling the second through-substrate cavity with the conductive material.
According to still another aspect of the present invention, a method of forming a semiconductor structure is provided. The method includes providing a semiconductor chip and electrically connecting the semiconductor chip to a mounting structure employing an array of solder balls. The semiconductor chip includes a semiconductor substrate; at least one capacitor embedded in the semiconductor substrate; and at least one laterally-insulated conductive through-substrate connection structure. The at least one capacitor has an inner electrode that includes a conductive through-substrate via (TSV) structure.
As stated above, the present invention relates to semiconductor structures, and particularly to a decoupling capacitor that employs a conductive through-substrate via and methods of manufacturing the same, which are now described in detail with accompanying figures. Throughout the drawings, the same reference numerals or letters are used to designate like or equivalent elements. The drawings are not necessarily drawn to scale.
As used herein, a “conductive through-substrate via (TSV) structure” is a conductive structure that extends through a substrate, i.e., at least from a top surface of the substrate to a bottom surface of the substrate.
As used herein, a “laterally-insulated conductive through-substrate connection structure” is an assembly of a conductive TSV structure and another structure that laterally surrounds the conductive TSV structure and electrically isolates the conductive TSV structure from the substrate.
As used herein, a “mounting structure” is any structure to which a semiconductor chip can be mounded by making electrical connections thereto. A mounting structure can be a packaging substrate, an interposer structure, or another semiconductor chip.
As used herein, a first element “laterally contacts” a second element if there is a direct physical contact between the first element and the second element in a “lateral direction,” which is any direction perpendicular to a top surface or a bottom surface of a substrate.
As used herein, a first element “laterally encloses” a second element if an inner periphery of the first element is located on or outside an outer periphery of the second element.
As used herein, a first element “encapsulates” a second element if all outer surfaces of the second element are located within inner surfaces of the first element.
As used herein, two elements are “conductively connected” to each other if there exists a conductive path between the two elements to allow conduction of electricity.
Referring toFIG. 1 , a first exemplary structure according to a first embodiment of the present invention includes asemiconductor substrate 10 that has a semiconductor material. The semiconductor material of thesemiconductor substrate 10 can be selected from, but is not limited to, silicon, germanium, silicon-germanium alloy, silicon carbon alloy, silicon-germanium-carbon alloy, gallium arsenide, indium arsenide, indium phosphide, III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, and other compound semiconductor materials. Preferably, the semiconductor material of thesemiconductor substrate 10 is a single crystalline material. For example, thesemiconductor substrate 10 can be a single crystalline silicon layer. Thesemiconductor substrate 10 can be doped with dopants of a first conductivity type, which can be p-type or n-type. The dopant concentration of thesemiconductor substrate 10 can be from 1.0×1014/cm3to 1.0×1017/cm3.
A dopedwell region 12 is formed in thesemiconductor substrate 12 by implanting dopants of a second conductivity through a portion of the top surface of thesemiconductor substrate 12. The second conductivity type is the opposite of the first conductivity type. The second conductivity type is n-type if the first conductivity type is p-type, and vice versa. The dopant concentration of the dopedwell region 12 can be from 1.0×1018/cm3to 1.0×1021/cm3to increase the conductivity of the dopedwell region 12.
Referring toFIG. 2 , apad dielectric layer 16 and afirst mask layer 18 are formed on the top surface of thesemiconductor substrate 10. Thepad dielectric layer 16 may, or may not, be formed on the backside of thesemiconductor substrate 10. Thepad dielectric layer 16 includes a dielectric material such as silicon nitride. Thefirst mask layer 18 can be composed of a photoresist or a dielectric material such as silicon oxide or silicon nitride.
Referring forFIG. 3 , thefirst mask layer 18 is lithographically patterned, and the pattern in thefirst mask layer 18 is transferred through thesemiconductor substrate 10 by an anisotropic etch that employs thefirst mask layer 18 as an etch mask. A first through-substrate cavity 47 is formed in thesemiconductor substrate 10. The lateral dimensions, e.g., diameter, a major axis, a minor axis, a length of a side, of the first through-substrate cavity 47 can be from 1 micron to 100 microns, and typically from 3 microns to 30 microns, although lesser and greater lateral dimensions can also be employed.
Referring toFIG. 4 , thefirst mask layer 18 can be removed selective to thesemiconductor substrate 10. A dielectrictubular structure 20 is formed around the first through-substrate cavity 47, for example, by converting exposed portions of thesemiconductor substrate 10 on the sidewalls of the first through-substrate cavity 47 into a dielectric material. For example, the exposed portion of the semiconductor substrate can be converted into a dielectric oxide by thermal oxidation. The dielectrictubular structure 20 can include an oxide of the semiconductor material of thesemiconductor substrate 10. For example, if thesemiconductor substrate 10 includes silicon, the dielectrictubular structure 20 can include silicon oxide. Thepad dielectric layer 16 prevents conversion of other portions of thesemiconductor substrate 10 into a dielectric material. The dielectrictubular structure 20 extends from the top surface of thesemiconductor substrate 10 to the bottom surface of thesemiconductor substrate 10. A horizontal cross-sectional area of the dielectrictubular structure 20 includes a hole corresponding to the first through-substrate cavity 47. The thickness of the dielectrictubular structure 20, as measured laterally between an inner periphery of the dielectrictubular structure 20 and an outer periphery of the dielectrictubular structure 20 can be from 100 nm to 1 micron, although lesser and greater thicknesses can also be employed.
Referring toFIG. 5 , thepad dielectric layer 16 can be removed. Optionally, adielectric liner 30 is deposed on the inner sidewalls of the dielectrictubular structure 20. Thedielectric liner 30 can include, for example, a stack of a silicon oxide layer and a silicon nitride layer.
Referring toFIG. 6 , the first through-substrate cavity 47 is filled with a first disposable material to form a firstdisposable material layer 49L. The firstdisposable material layer 49L extends through thesemiconductor substrate 10 and covers both sides of thesemiconductor substrate 10, thereby encapsulating thesemiconductor substrate 10. The first disposable material can be, for example, a polycrystalline silicon-containing material such as polysilicon or an amorphous silicon-containing material such as amorphous silicon.
Referring toFIG. 7 , the firstdisposable material layer 49L is removed from the front side and the backside of thesemiconductor substrate 10, for example, by an etch-back process or chemical mechanical planarization (CMP). Further, a portion of the firstdisposable material layer 49L is recessed below the top surface of thesemiconductor substrate 10 by a recess depth rd, which can be from 200 nm to 2,000 nm, although lesser and greater recess depths rd can also be employed. The remaining portion of the firstdisposable material layer 49L constitutes a firstdisposable material portion 49.
Referring toFIG. 8 , adielectric cap portion 50 is formed by filling a cavity above the firstdisposable material portion 49 with a dielectric material and removing excess dielectric material above a top surface of thedielectric liner 30. Optionally, a silicon nitride cap layer (not shown) can be deposited on the top surface of thedielectric cap portion 50 and the portion of thedielectric liner 30 located on the front side of thesemiconductor substrate 10.
Referring toFIG. 9 , asecond mask layer 51 is formed above the top surface of thesemiconductor substrate 10. Thesecond mask layer 51 can be composed of a photoresist or a dielectric material such as silicon oxide or silicon nitride. Thesecond mask layer 51 is lithographically patterned to form an opening in an area that does not overlie thedisposable material portion 49 or the dielectrictubular structure 20. The opening in thesecond mask layer 51 is formed over or in proximity to the dopedwell region 12. The pattern in thesecond mask layer 51 is transferred through thesemiconductor substrate 10 by an anisotropic etch that employs thesecond mask layer 51 as an etch mask. A second through-substrate cavity 67 is formed in thesemiconductor substrate 10. The lateral dimensions, e.g., diameter, a major axis, a minor axis, a length of a side, of the second through-substrate cavity 67 can be from 1 micron to 100 microns, and typically from 3 microns to 30 microns, although lesser and greater lateral dimensions can also be employed.
Referring toFIG. 10 , a dopedmaterial layer 52 is deposited on the exposed surfaces of the first exemplary structure including the sidewalls of the second through-substrate cavity 67. The dopedmaterial layer 52 includes dopants of the second conductivity type. The dopedmaterial layer 52 can be, for example, an arsenosilicate glass (ASG) layer. The thickness of the dopedmaterial layer 52 is less than half of the smallest lateral dimension of the second through-substrate cavity 67 to prevent plugging of the second through-substrate cavity 67. Optionally, a dielectric capping layer (not shown) may be deposited over the dopedmaterial layer 52 to prevent loss of dopants during a subsequent drive-in anneal.
Referring toFIG. 11 , a drive-in anneal is performed to induce outdiffusion of dopants of the second conductivity type into a region of thesemiconductor substrate 10 that surrounds the second through-substrate cavity 67. An outer electrode is formed by doping a portion of thesemiconductor substrate 10 around the second through-substrate cavity 67. Specifically, theouter electrode 60 is formed by converting a tubular region, i.e., a region in the shape of a tube, into a doped semiconductor region having a doping of the second conductivity type. For example, a dopant-containing material layer such as an arsenosilicate glass layer can be deposited on sidewalls of the second through-substrate cavity 67 and the dopants can be driven into thesemiconductor substrate 10 by a drive-in anneal. Theouter electrode 60 is a doped tubular portion including a doped semiconductor material, i.e., has a shape of a tube. The lateral distance between the outer periphery of theouter electrode 60 and the inner periphery of the outer electrode, i.e., the boundary with the dopedmaterial layer 52, can be from 150 nm to 1,000 nm, although a lesser and greater lateral distances can also be employed. The dopant concentration of theouter electrode 60 can be from 1.0×1018/cm3to 1.0×1020/cm3, although a lesser and greater dopant concentration can also be employed. The dopedmaterial layer 52 is subsequently removed. In an alternate embodiment, theouter electrode 60 can be formed by plasma doping without employing a dopedmaterial layer 52.
Referring toFIG. 12 , anode dielectric 70 is formed on all exposed surfaces of the first exemplary structure including the inner sidewalls of theouter electrode 60, which are the surfaces of the second through-substrate cavity 67, and exposed surfaces of thedielectric liner 30. Thenode dielectric 70 is formed directly on sidewalls of the doped tubular portion while the disposable material is present in the semiconductor substrate. The thickness of thenode dielectric 70 can be from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed.
Referring toFIG. 13 , the second through-substrate cavity 67 is filled with a second disposable material to form a seconddisposable material layer 77L. The seconddisposable material layer 77L extends through thesemiconductor substrate 10 and covers both sides of thesemiconductor substrate 10, thereby encapsulating thesemiconductor substrate 10. The second disposable material can be, for example, a polycrystalline silicon-containing material such as polysilicon or an amorphous silicon-containing material such as amorphous silicon.
Referring toFIG. 14 , the seconddisposable material layer 77L is removed from the front side and the backside of thesemiconductor substrate 10, for example, by an etch-back process or chemical mechanical planarization (CMP). The remaining portion of the seconddisposable material layer 77L constitutes a seconddisposable material portion 77. The top surface of the seconddisposable material portion 77 can be coplanar with a top surface of thenode dielectric 70 on the front side of thesemiconductor substrate 20.
Ahard mask layer 72 is formed on one side of thesemiconductor substrate 20, which is preferably the front side of the semiconductor substrate on which thedielectric cap portion 50 is located. Thehard mask layer 72 includes a dielectric material such as silicon oxide, silicon nitride, a doped silicate glass, or a combination thereof. The thickness of thehard mask layer 72 can be from 500 nm to 5,000 nm, and typically from 1,000 nm to 3,000 nm, although lesser and greater thicknesses can also be employed.
Referring toFIG. 15 , thehard mask layer 72 is lithographically patterned to form openings over the seconddisposable material portion 77 and the firstdisposable material portion 49. Thedielectric cap portion 50 is removed to expose an upper surface of the firstdisposable material portion 49. An upper portion of the seconddisposable material portion 77 can be removed during the removal of thedielectric cap portion 50.
Referring toFIG. 16 , the first dielectric material of the firstdisposable material portion 49 and the second dielectric material of the seconddielectric material portion 77 are removed by an etch that employs thehard mask layer 72 as an etch mask. Removal of the firstdisposable material portion 49 forms a cavity in a volume corresponding to the first through-substrate cavity 47 in prior processing steps. This cavity is herein referred to as a re-formed first through-substrate cavity 79, i.e., a first through-substrate cavity that is formed a second time Likewise, removal of the seconddisposable material portion 77 forms a cavity in a volume corresponding to the second through-substrate cavity 67 in prior processing steps. This cavity is herein referred to as a re-formed second through-substrate cavity 78, i.e., a second through-substrate cavity that is formed a second time. The re-formed first through-substrate cavity 79 is formed within the dielectrictubular structure 20. Surfaces of thenode dielectric 70 is exposed around the re-formed second through-substrate cavity 78, and surfaces of thedielectric liner 30 can be exposed around the re-formed first through-substrate cavity 79. If thedielectric liner 30 is not present, inner surfaces of the dielectrictubular structure 20 can be exposed in the re-formed first through-substrate cavity 79.
Referring toFIG. 17 , the re-formed first through-substrate cavity 79 and the re-formed second through-substrate cavity 78 are filled with a conductive material to form a first conductive through-substrate via (TSV)structure 80 and a secondconductive TSV structure 82, respectively. The conductive material of the firstconductive TSV structure 80 and the secondconductive TSV structure 82 can include a doped semiconductor material, a metallic material, or a combination thereof. The conductive material of the firstconductive TSV structure 80 and the secondconductive TSV structure 82 can include, but is not limited to, doped polysilicon, a doped silicon-containing alloy, Cu, W, Ta, Ti, WN, TaN, TiN, or a combination thereof. The conductive material can be deposited, for example, by electroplating, electroless plating, physical vapor deposition (PVD), chemical vapor deposition (CVD), or a combination thereof.
After deposition of the conductive material, excess conductive material is removed from the top side and the bottom side of thesemiconductor substrate 10 by planarization employing an etch-back process, chemical mechanical planarization, or a combination thereof. Top surfaces of the firstconductive TSV structure 80 and the secondconductive TSV structure 82 are coplanar with a top surface of thehard mask layer 72. Bottom surfaces of theconductive TSV structure 80 and the secondconductive TSV structure 82 are coplanar with a bottom surface of remaining portions of the first exemplary structure. The bottom surface of the remaining portions of the first exemplary structure can be, for example, an exposed surface of thenode dielectric 70 if a bottom portion of thenode dielectric 70 remains after planarization or any other exposed surfaces at the bottom of the first exemplary structure. The firstconductive TSV structure 80 and the secondconductive TSV structure 82 are formed concurrently by employing the same deposition process and the same planarization process.
Referring toFIG. 18 , acontact structure 90 is formed by forming a trench through thehard mask layer 72, thenode dielectric 70, and thedielectric liner 30 and by filling the trench with a conductive material such as a doped semiconductor material or a metallic material. Thecontact structure 90 is conductively connected to theouter electrode 60 through the dopedwell region 12. The firstconductive TSV structure 80, thenode dielectric 70, and theouter electrode 60 collective constitute acapacitor 180, in which the firstconductive TSV structure 80 is an inner electrode. The secondconductive TSV structure 82, the portion of the dielectric liner contacting the secondconductive TSV structure 82, and the dielectrictubular structure 20 collectively constitute an laterally-insulated conductive through-substrate connection structure 182. An end surface of the firstconductive TSV structure 80, an end surface of the secondconductive TSV structure 82, and an end surface of thecontact structure 90 can be coplanar with an exposed surface of thehard mask layer 72.
The first exemplary structure can be incorporated in a semiconductor chip. For example, a plurality of instances of thecapacitor 180 and a plurality of instances of the laterally-insulated conductive through-substrate connection structure 182 can be embedded in thesame semiconductor substrate 10 of the semiconductor chip. The semiconductor chip may, or may not, include other semiconductor devices such as field effect transistors, bipolar transistors, thyristors, and diodes.
Eachcapacitor 180 can include an inner electrode, which includes a first conductive through-substrate via (TSV)structure 80, anode dielectric 70, and anouter electrode 60. The inner electrode contiguously extends at least from an upper surface of thesemiconductor substrate 10 to a lower surface of thesemiconductor substrate 10. Thenode dielectric 70 laterally contacts and laterally encloses the inner electrode. Thenode dielectric 70 contiguously extends from the upper surface to the lower surface. Theouter electrode 60 laterally contacts and laterally encloses a portion of thenode dielectric 70. Theouter electrode 60 includes a doped semiconductor material.
The laterally-insulated conductive through-substrate connection structure 182 includes a secondconductive TSV structure 82 located in thesemiconductor substrate 10 and a dielectrictubular structure 20 laterally surrounding the secondconductive TSV structure 82 and embedded in thesemiconductor substrate 10. The laterally-insulated conductive through-substrate connection structure 182 can include a portion of thedielectric liner 30.
Referring toFIG. 19 , a second exemplary structure according to a second embodiment of the present invention includes apackaging substrate 200, a plurality offirst semiconductor chips 100, a plurality ofsecond semiconductor chips 300, an array offirst solder balls 199 electrically connecting each of thefirst semiconductor chips 100 to thepackaging substrate 200, and an array ofsecond solder balls 299 electrically connecting each of thesecond semiconductor chips 300 to afirst semiconductor chip 100. Each of thefirst semiconductor chips 100 includes at least onecapacitor 180 and at least one laterally-insulated conductive through-substrate connection structure 182. Thefirst semiconductor chips 100 may, or may not, include additional semiconductor devices such as field effect transistors, bipolar transistors, thyristors, and diodes. Thesecond semiconductor chips 300 can include any type of semiconductor devices.
Thecapacitors 180 can function as decoupling capacitors that reduce noise in a power supply system that supplies power to the devices in thesecond semiconductor chips 300 and, if present, to the devices in thefirst semiconductor chips 100. Eachcapacitor 180 can provide a capacitance on the order of 1 pF to 10 nF, which is equivalent to the capacitance of 40-400,000 typical trench capacitors. Further, thecapacitor 180 provides a lower inductance than a trench capacitor array that provides a comparable total capacitance. Thus, thecapacitors 180 reduce noise in the power supply system especially during high frequency operations.
Referring toFIG. 20 , a third exemplary structure according to a third embodiment of the present invention includes apackaging substrate 200, ainterposer structure 400, a plurality offirst semiconductor chips 100, and a plurality of second semiconductor chips300. An array offirst solder balls 199 electrically connects each of thefirst semiconductor chips 100 to theinterposer structure 400. An array ofsecond solder balls 299 electrically connects each of thesecond semiconductor chips 300 to afirst semiconductor chip 100. An array ofthird solder balls 399 connects theinterposer structure 400 to thepackaging substrate 200.
Theinterposer structure 400 can include an interposerstructure substrate layer 410, a lowerdielectric material layer 420, and an upperdielectric material layer 430. The interposerstructure substrate layer 410 includes a plurality of through-substrate via structures that are schematically illustrated as vertical lines. The plurality of through-substrate via structures includes a plurality of capacitors180 (SeeFIG. 18 ) and laterally-insulated conductive through-substrate connection structure182 (SeeFIG. 18 ). The lowerdielectric material layer 420 and the upperdielectric material layer 430 can include metal lines that provide electrical wiring within the lowerdielectric material layer 420 or the upperdielectric material layer 430.
In general, a semiconductor chip including at least onecapacitor 180 and at least one laterally-insulated conductive through-substrate connection structure 182 can be mounted a mounting structure, which can be any structure on which the semiconductor chip can be mounted with electrical connections thereto. The mounting structure can be, but is not limited to, apackaging substrate 200, aninterposer structure 400, an assembly of aninterposer structure 400 and apackaging substrate 200, or another semiconductor chip such as asecond semiconductor chip 300.
Referring toFIG. 21 , a graph shows results of a simulation that shows a noise reduction at high frequency provided by an exemplary structure according to an embodiment of the present invention. The horizontal axis represents frequency of a noise component in a power supply system, and the vertical axis represents an equivalent impedance of a decoupling system including either a capacitor180 (SeeFIG. 18 ) according to an embodiment of the present invention or an array of trench capacitors according to prior art. The electrical noise in a power supply system is proportional to the equivalent impedance. The curve labeled “TSV w/582 pF” represents the equivalent impedance of acapacitor 180 having a capacitance of 582 pF and constructed according to an embodiment of the present invention, e.g., as shown inFIG. 18 . The curves labeled “DTC w/582 pF,” “2 nF,” and “4 nF” represent the equivalent impedance of trench capacitor arrays having a total capacitance of 582 pF, 2 nF, and 4 nF, respectively.
At a frequency range below 0.1 GHz, the voltage noise in the system power supply is limited by the total capacitance of a decoupling capacitor system. Above 1 GHz, however, the voltage noise in decoupling capacitor systems employing any of the trench capacitor arrays increases to with frequency on a converging curve irrespective of the total capacitance of the decoupling capacitor system because inductance of the decoupling capacitor system dominates. The decoupling capacitor system employing acapacitor 180 of an embodiment of the present invention provides a lower voltage noise at frequencies above 1.2 GHz except for a small frequency range between 4 GHz and 4.5 GHz because thecapacitor 180 has a low inductance. Thus, the decoupling capacitor system employing acapacitor 180 of an embodiment of the present invention provides a superior performance in noise reduction while consuming less device area. In the second or third exemplary structure, if thefirst semiconductor chips 100 do not include a semiconductor device, thecapacitors 180 can be formed without requiring any area in the third semiconductor chips300. In the third exemplary structure, thecapacitors 180 can be formed in a smaller area than an array of trench capacitors having a comparable total capacitance, thereby providing more area for other semiconductor devices that can be included in thefirst semiconductor chips 100.
While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details can be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
Claims (18)
1. A method of forming a semiconductor structure comprising:
forming a capacitor and an laterally-insulated conductive through-substrate connection structure in a semiconductor substrate,
wherein said forming said laterally-insulated conductive through-substrate connection structure and said capacitor comprises:
forming a dielectric tubular structure around a first through-substrate cavity formed in said semiconductor substrate;
filling said first through-substrate cavity with a disposable material;
forming an outer electrode by doping a portion of said semiconductor substrate around a second through-substrate cavity;
forming a node dielectric on a surface of said second through-substrate cavity; removing said disposable material from said first through-substrate cavity within said dielectric tubular structure; filling said first through-substrate cavity with said dielectric tubular structure with a conductive material; and
forming an inner electrode by filling said second through-substrate cavity with said conductive material.
2. The method ofclaim 1 , wherein said inner electrode constitutes a first conductive through-substrate via (TSV) structure, a second conductive TSV structure is formed in said cavity filled by said conductive material, and said first conductive TSV structure and said second conductive TSV structure are formed concurrently.
3. The method ofclaim 2 , wherein at least one of the first TSV, and the second TSV is composed of a material selected from the group consisting of doped polysilicon, doped silicon-containing alloy, Cu, W, Ta, Ti, WN, TaN, TiN, or a combination thereof.
4. The method ofclaim 2 , wherein at least one of the first TSV and the second TSV by electroplating, electroless plating, physical vapor deposition (PVD), chemical vapor deposition (CVD), or a combination thereof.
5. The method ofclaim 1 , wherein the disposable material is polysilicon or amorphous silicon.
6. The method ofclaim 1 , further comprising forming said node dielectric directly on sidewalls of said doped tubular portion while said disposable material is present in said semiconductor substrate.
7. The method ofclaim 6 , wherein the node dielectric has a thickness ranging from 3 nm to 30 nm.
8. The method ofclaim 1 , further comprising:
filling said second through-substrate cavity with a second disposable material after forming said outer electrode;
forming a hard mask layer on one side of said semiconductor substrate; and
removing said disposable material and said second disposable material employing said hard mask layer as an etch mask.
9. A method of forming a semiconductor structure comprising:
providing a semiconductor chip including:
providing a semiconductor substrate;
forming at least one capacitor embedded in said semiconductor substrate, said at least one capacitor including an inner electrode comprising a conductive through-substrate via (TSV) structure; and
forming at least one laterally-insulated conductive through-substrate connection structure, wherein said forming at least one laterally-insulated conductive through-substrate connection structure comprises:
forming a dielectric tubular structure around a first through-substrate cavity formed in said semiconductor substrate,
filling said first through-substrate cavity with a disposable material,
removing said disposable material from said first through-substrate cavity within said dielectric tubular structure before forming said inner electrode of said at least one capacitor, and
filling said cavity within said dielectric tubular structure with a conductive material; and
electrically connecting said semiconductor chip to a mounting structure employing an array of solder balls.
10. The method ofclaim 9 , wherein the conductive TSV is composed of a material selected from the group consisting of doped polysilicon, doped silicon-containing alloy, Cu, W, Ta, Ti, WN, TaN, TiN, or a combination thereof.
11. The method ofclaim 9 , wherein the mounting structure includes an interposer structure.
12. The method ofclaim 9 , wherein the semiconductor chip further comprises field effect transistors, thyristors, bipolar transistors, diodes and combinations thereof.
13. The method ofclaim 9 , wherein the capacitors are decoupling capacitors.
14. The method ofclaim 13 , wherein the decoupling capacitors have a capacitance ranging from 1 pF to 10 nF.
15. The method ofclaim 11 , wherein the interposer includes a dielectric layer and a plurality of metal lines.
16. The method ofclaim 9 , wherein first solder balls among said array are electrically connected to said inner electrodes and first conductive structures on said mounting structure, and second solder balls among said array are electrically connected to conductive TSV structures within said at least one laterally-insulated conductive through-substrate connection structure and second conductive structures on said mounting structure.
17. The method ofclaim 9 , wherein said mounting structure is selected from a packaging substrate, an interposer structure, and another semiconductor chip.
18. The method ofclaim 9 , wherein each of said at least one capacitor includes a node dielectric laterally contacting and laterally enclosing said inner electrode and an outer electrode laterally contacting and laterally enclosing a portion of said node dielectric, and each of said at least one laterally-insulated conductive through-substrate connection structure includes a conductive TSV structure and a dielectric tubular structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/975,519US8785289B2 (en) | 2009-11-09 | 2013-08-26 | Integrated decoupling capacitor employing conductive through-substrate vias |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/614,883US8558345B2 (en) | 2009-11-09 | 2009-11-09 | Integrated decoupling capacitor employing conductive through-substrate vias |
| US13/975,519US8785289B2 (en) | 2009-11-09 | 2013-08-26 | Integrated decoupling capacitor employing conductive through-substrate vias |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US12/614,883DivisionUS8558345B2 (en) | 2009-11-09 | 2009-11-09 | Integrated decoupling capacitor employing conductive through-substrate vias |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| US20130344675A1 US20130344675A1 (en) | 2013-12-26 |
| US8785289B2true US8785289B2 (en) | 2014-07-22 |
Family
ID=43970828
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US12/614,883Active2031-10-10US8558345B2 (en) | 2009-11-09 | 2009-11-09 | Integrated decoupling capacitor employing conductive through-substrate vias |
| US13/975,519ActiveUS8785289B2 (en) | 2009-11-09 | 2013-08-26 | Integrated decoupling capacitor employing conductive through-substrate vias |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US12/614,883Active2031-10-10US8558345B2 (en) | 2009-11-09 | 2009-11-09 | Integrated decoupling capacitor employing conductive through-substrate vias |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US8558345B2 (en) |
| CN (1) | CN102598263B (en) |
| DE (1) | DE112010004326B4 (en) |
| GB (1) | GB2488078B (en) |
| WO (1) | WO2011057238A2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9397038B1 (en) | 2015-02-27 | 2016-07-19 | Invensas Corporation | Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates |
| US9412806B2 (en) | 2014-06-13 | 2016-08-09 | Invensas Corporation | Making multilayer 3D capacitors using arrays of upstanding rods or ridges |
| US10424565B2 (en) | 2014-04-11 | 2019-09-24 | Osram Opto Semiconductor Gmbh | Semiconductor chip for protecting against electrostatic discharges |
| US10950689B2 (en) | 2015-09-23 | 2021-03-16 | Nanyang Technological University | Semiconductor device with a through-substrate via hole having therein a capacitor and a through-substrate via conductor |
| US11961882B2 (en) | 2021-02-26 | 2024-04-16 | Samsung Electronics Co., Ltd. | Semiconductor device |
Families Citing this family (38)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8786066B2 (en) | 2010-09-24 | 2014-07-22 | Intel Corporation | Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same |
| US8216936B1 (en)* | 2010-10-21 | 2012-07-10 | Xilinx, Inc. | Low capacitance electrical connection via |
| US8766409B2 (en)* | 2011-06-24 | 2014-07-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and structure for through-silicon via (TSV) with diffused isolation well |
| CN102856303B (en)* | 2011-06-27 | 2015-07-22 | 成都锐华光电技术有限责任公司 | Semiconductor chip |
| US8546953B2 (en)* | 2011-12-13 | 2013-10-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit |
| US8779849B2 (en) | 2012-01-27 | 2014-07-15 | Micron Technology, Inc. | Apparatuses and methods for providing capacitance in a multi-chip module |
| US8767408B2 (en) | 2012-02-08 | 2014-07-01 | Apple Inc. | Three dimensional passive multi-component structures |
| US8697567B2 (en) | 2012-05-22 | 2014-04-15 | International Business Machines Corporation | Implementing decoupling devices inside a TSV DRAM stack |
| US8519543B1 (en)* | 2012-07-17 | 2013-08-27 | Futurewei Technologies, Inc. | Large sized silicon interposers overcoming the reticle area limitations |
| EP2688092A1 (en)* | 2012-07-19 | 2014-01-22 | Ipdia | Semiconductor die with a through silicon via and corresponding manufacturing process |
| TWI497661B (en) | 2012-08-15 | 2015-08-21 | Ind Tech Res Inst | Semiconductor substrate assembly |
| US9343393B2 (en) | 2012-08-15 | 2016-05-17 | Industrial Technology Research Institute | Semiconductor substrate assembly with embedded resistance element |
| US9213386B2 (en) | 2012-10-22 | 2015-12-15 | Micron Technology, Inc. | Apparatuses and methods and for providing power responsive to a power loss |
| US9698852B2 (en) | 2012-10-30 | 2017-07-04 | Maja Systems, Inc. | Compact and low-power millimeter-wave integrated VCO-up/down-converter with gain-boosting |
| US9196671B2 (en) | 2012-11-02 | 2015-11-24 | International Business Machines Corporation | Integrated decoupling capacitor utilizing through-silicon via |
| US9379202B2 (en)* | 2012-11-12 | 2016-06-28 | Nvidia Corporation | Decoupling capacitors for interposers |
| WO2014089520A1 (en)* | 2012-12-07 | 2014-06-12 | Anayas360. Com, Llc | On-chip calibration and built-in-self-test for soc millimeter-wave integrated digital radio and modem |
| TWI518864B (en)* | 2012-12-26 | 2016-01-21 | 財團法人工業技術研究院 | Variable container |
| US9653615B2 (en) | 2013-03-13 | 2017-05-16 | International Business Machines Corporation | Hybrid ETSOI structure to minimize noise coupling from TSV |
| US9595526B2 (en)* | 2013-08-09 | 2017-03-14 | Apple Inc. | Multi-die fine grain integrated voltage regulation |
| US9202785B2 (en)* | 2013-11-08 | 2015-12-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three dimensional integrated circuit capacitor having vias |
| US9202866B2 (en)* | 2014-01-08 | 2015-12-01 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and formation thereof |
| US10468381B2 (en) | 2014-09-29 | 2019-11-05 | Apple Inc. | Wafer level integration of passive devices |
| US9548288B1 (en)* | 2014-12-22 | 2017-01-17 | Apple Inc. | Integrated circuit die decoupling system with reduced inductance |
| US9287348B1 (en)* | 2015-04-14 | 2016-03-15 | Honeywell International Inc. | Devices, systems, and methods for ion trapping |
| EP3050843B1 (en)* | 2015-01-30 | 2017-10-25 | Honeywell International Inc. | Device for ion trapping |
| US9455189B1 (en) | 2015-06-14 | 2016-09-27 | Darryl G. Walker | Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and method of manufacture |
| EP3174094B1 (en) | 2015-11-25 | 2018-09-26 | IMEC vzw | Integrated circuit comprising a metal-insulator-metal capacitor and fabrication method thereof |
| US9807867B2 (en) | 2016-02-04 | 2017-10-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure and method of manufacturing the same |
| US9872392B2 (en) | 2016-06-08 | 2018-01-16 | International Business Machines Corporation | Power decoupling attachment |
| CN108987374B (en)* | 2018-06-22 | 2020-06-26 | 西安理工大学 | A three-dimensional capacitor based on TSV and RDL |
| CN110010588B (en)* | 2019-02-18 | 2020-09-22 | 西安电子科技大学 | Complementary three-dimensional broadband capacitor based on coaxial through-silicon-via array |
| US11398516B2 (en)* | 2019-08-29 | 2022-07-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive contact for ion through-substrate via |
| DE102020101246B4 (en) | 2019-08-29 | 2025-03-27 | Taiwan Semiconductor Manufacturing Co. Ltd. | Substrate via with doped channel region and corresponding manufacturing process |
| US11264388B2 (en)* | 2020-05-18 | 2022-03-01 | Micron Technology, Inc. | Microelectronic devices including decoupling capacitors, and related apparatuses, electronic systems, and methods |
| CN114188311A (en)* | 2020-09-15 | 2022-03-15 | 联华电子股份有限公司 | Semiconductor structure |
| CN112466845B (en)* | 2020-11-24 | 2023-08-22 | 复旦大学 | Through silicon via structure and preparation method thereof |
| US20240412982A1 (en)* | 2023-06-08 | 2024-12-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and manufacturing method thereof |
Citations (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01216591A (en) | 1988-02-25 | 1989-08-30 | Canon Inc | Printed board |
| JPH03252193A (en) | 1990-03-01 | 1991-11-11 | Matsushita Electric Ind Co Ltd | wiring board |
| US5614743A (en)* | 1994-07-26 | 1997-03-25 | Kabushiki Kaisha Toshiba | Microwave integrated circuit (MIC) having a reactance element formed on a groove |
| JPH10163632A (en) | 1996-11-26 | 1998-06-19 | Sony Corp | Printed wiring board and its manufacture |
| US5915167A (en) | 1997-04-04 | 1999-06-22 | Elm Technology Corporation | Three dimensional structure memory |
| JP2000304744A (en) | 1999-04-20 | 2000-11-02 | Shimizu Corp | Method for measuring chloride content in fresh concrete |
| US6221769B1 (en)* | 1999-03-05 | 2001-04-24 | International Business Machines Corporation | Method for integrated circuit power and electrical connections via through-wafer interconnects |
| JP3252193B2 (en) | 1990-07-13 | 2002-01-28 | ヤマハ発動機株式会社 | Motorcycle |
| US20020085336A1 (en) | 2000-12-29 | 2002-07-04 | Paul Winer | High performance via capacitor and method for manufacturing same |
| US20020132465A1 (en) | 1997-04-04 | 2002-09-19 | Elm Technology Corporation | Reconfigurable integrated circuit memory |
| US20040089948A1 (en)* | 2002-11-07 | 2004-05-13 | Yu-Ting Cheng | Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer |
| US20040108587A1 (en)* | 2002-12-09 | 2004-06-10 | Chudzik Michael Patrick | High density chip carrier with integrated passive devices |
| US20050106845A1 (en) | 2001-02-22 | 2005-05-19 | Halahan Patrick B. | Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same |
| US20050116275A1 (en) | 2003-12-02 | 2005-06-02 | Shian-Jyh Lin | Trench capacitor structure |
| US6963483B2 (en) | 1999-12-29 | 2005-11-08 | Intel Corporation | Self-aligned coaxial via capacitors |
| US20060001174A1 (en) | 2004-06-30 | 2006-01-05 | Nec Electronics Corporation | Semiconductor device and method for manufacturing the same |
| US7033934B2 (en)* | 2001-11-07 | 2006-04-25 | Shinko Electric Industries Co., Ltd. | Method of production of semiconductor package |
| US20080113505A1 (en) | 2006-11-13 | 2008-05-15 | Sparks Terry G | Method of forming a through-substrate via |
| US20080128856A1 (en) | 2006-12-05 | 2008-06-05 | Sung-Ho Kwak | Semiconductor device having metal-insulator-metal capacitor and method of fabricating the same |
| US20080173993A1 (en)* | 2007-01-18 | 2008-07-24 | International Business Machines Corporation | Chip carrier substrate capacitor and method for fabrication thereof |
| US20080202799A1 (en) | 2007-02-26 | 2008-08-28 | Bhret Graydon | Embedding an electronic component between surfaces of a printed circuit board |
| US20080296731A1 (en) | 2002-06-27 | 2008-12-04 | Block Bruce A | Enhanced on-chip decoupling capacitors and method of making same |
| US20090075478A1 (en)* | 2004-12-02 | 2009-03-19 | Nec Electronics Corporation | Semiconductor device,having a through electrode, semiconductor module employing thereof and method for manufacturing semiconductor device having a through electrode |
| US20090212438A1 (en) | 2008-02-26 | 2009-08-27 | Franz Kreupl | Integrated circuit device comprising conductive vias and method of making the same |
| US7705691B2 (en)* | 2005-10-18 | 2010-04-27 | Agency For Science, Technology & Research | Capacitor interconnection |
| US20100308435A1 (en)* | 2009-06-08 | 2010-12-09 | Qualcomm Incorporated | Through Silicon Via With Embedded Decoupling Capacitor |
| US20110037144A1 (en)* | 2009-08-13 | 2011-02-17 | Broadcom Corporation | Method for fabricating a decoupling composite capacitor in a wafer and related structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4418430C1 (en)* | 1994-05-26 | 1995-05-11 | Siemens Ag | Method for producing a silicon capacitor |
| US8227847B2 (en)* | 2008-02-20 | 2012-07-24 | Nxp B.V. | Ultra high density capacity comprising pillar-shaped capacitors formed on both sides of a substrate |
- 2009
- 2009-11-09USUS12/614,883patent/US8558345B2/enactiveActive
- 2010
- 2010-11-09WOPCT/US2010/055949patent/WO2011057238A2/enactiveApplication Filing
- 2010-11-09DEDE112010004326.4Tpatent/DE112010004326B4/enactiveActive
- 2010-11-09CNCN201080050627.8Apatent/CN102598263B/enactiveActive
- 2010-11-09GBGB1209593.1Apatent/GB2488078B/enactiveActive
- 2013
- 2013-08-26USUS13/975,519patent/US8785289B2/enactiveActive
Patent Citations (63)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01216591A (en) | 1988-02-25 | 1989-08-30 | Canon Inc | Printed board |
| JPH03252193A (en) | 1990-03-01 | 1991-11-11 | Matsushita Electric Ind Co Ltd | wiring board |
| JP3252193B2 (en) | 1990-07-13 | 2002-01-28 | ヤマハ発動機株式会社 | Motorcycle |
| US5614743A (en)* | 1994-07-26 | 1997-03-25 | Kabushiki Kaisha Toshiba | Microwave integrated circuit (MIC) having a reactance element formed on a groove |
| JPH10163632A (en) | 1996-11-26 | 1998-06-19 | Sony Corp | Printed wiring board and its manufacture |
| KR100785821B1 (en) | 1997-04-04 | 2007-12-13 | 글렌 제이. 리디 | Three dimensional structure memory |
| US20090219742A1 (en) | 1997-04-04 | 2009-09-03 | Leedy Glenn J | Three dimensional structure memory |
| US20100173453A1 (en) | 1997-04-04 | 2010-07-08 | Leedy Glenn J | Three dimensional structure memory |
| TW412854B (en) | 1997-04-04 | 2000-11-21 | Glenn J Leedy | Method of forming a random access memory, information processing and bonding together multiple substrates, stacked integrated circuit memory, and integrated circuit memory structure |
| US6208545B1 (en) | 1997-04-04 | 2001-03-27 | Glenn J. Leedy | Three dimensional structure memory |
| US20100171225A1 (en) | 1997-04-04 | 2010-07-08 | Leedy Glenn J | Three dimensional structure memory |
| EP0975472A1 (en) | 1997-04-04 | 2000-02-02 | Glenn J. Leedy | Three dimensional structure memory |
| US20100172197A1 (en) | 1997-04-04 | 2010-07-08 | Leedy Glenn J | Three dimensional structure memory |
| US20020132465A1 (en) | 1997-04-04 | 2002-09-19 | Elm Technology Corporation | Reconfigurable integrated circuit memory |
| US6551857B2 (en) | 1997-04-04 | 2003-04-22 | Elm Technology Corporation | Three dimensional structure integrated circuits |
| US6563224B2 (en) | 1997-04-04 | 2003-05-13 | Elm Technology Corporation | Three dimensional structure integrated circuit |
| US20030173608A1 (en) | 1997-04-04 | 2003-09-18 | Elm Technology Corporation | Three dimensional structure integrated circuit |
| US6632706B1 (en) | 1997-04-04 | 2003-10-14 | Elm Technology Corporation | Three dimensional structure integrated circuit fabrication process |
| US20100171224A1 (en) | 1997-04-04 | 2010-07-08 | Leedy Glenn J | Three dimensional structure memory |
| US7705466B2 (en) | 1997-04-04 | 2010-04-27 | Elm Technology Corporation | Three dimensional multi layer memory and control logic integrated circuit structure |
| CN1525485A (en) | 1997-04-04 | 2004-09-01 | ���ס�J������ | Three-dimensional structure memory |
| US20090230501A1 (en) | 1997-04-04 | 2009-09-17 | Leedy Glenn J | Three dimensional structure memory |
| US20090219744A1 (en) | 1997-04-04 | 2009-09-03 | Leedy Glenn J | Three dimensional structure memory |
| JP2008166832A (en) | 1997-04-04 | 2008-07-17 | Glenn J Leedy | Information processing method |
| US20090219743A1 (en) | 1997-04-04 | 2009-09-03 | Leedy Glenn J | Three dimensional structure memory |
| US20090218700A1 (en) | 1997-04-04 | 2009-09-03 | Leedy Glenn J | Three dimensional structure memory |
| US20090219772A1 (en) | 1997-04-04 | 2009-09-03 | Leedy Glenn J | Three dimensional structure memory |
| KR100639752B1 (en) | 1997-04-04 | 2006-10-27 | 글렌 제이. 리디 | 3D memory |
| US7138295B2 (en) | 1997-04-04 | 2006-11-21 | Elm Technology Corporation | Method of information processing using three dimensional integrated circuits |
| US7193239B2 (en) | 1997-04-04 | 2007-03-20 | Elm Technology Corporation | Three dimensional structure integrated circuit |
| US5915167A (en) | 1997-04-04 | 1999-06-22 | Elm Technology Corporation | Three dimensional structure memory |
| JP2008028407A (en) | 1997-04-04 | 2008-02-07 | Glenn J Leedy | Information processing method |
| CN101188235A (en) | 1997-04-04 | 2008-05-28 | 格伦·J·利迪 | stacked integrated circuit memory |
| US6133640A (en) | 1997-04-04 | 2000-10-17 | Elm Technology Corporation | Three-dimensional structure memory |
| US20090067210A1 (en) | 1997-04-04 | 2009-03-12 | Leedy Glenn J | Three dimensional structure memory |
| US20090175104A1 (en) | 1997-04-04 | 2009-07-09 | Leedy Glenn J | Three dimensional structure memory |
| JP2008166831A (en) | 1997-04-04 | 2008-07-17 | Glenn J Leedy | Information processing method |
| US20090174082A1 (en) | 1997-04-04 | 2009-07-09 | Glenn J Leedy | Three dimensional structure memory |
| JP2008172254A (en) | 1997-04-04 | 2008-07-24 | Glenn J Leedy | Information processing method |
| US7504732B2 (en) | 1997-04-04 | 2009-03-17 | Elm Technology Corporation | Three dimensional structure memory |
| EP1986233A2 (en) | 1997-04-04 | 2008-10-29 | Glenn J. Leedy | On-chip reconfigurable memory |
| US7474004B2 (en) | 1997-04-04 | 2009-01-06 | Elm Technology Corporation | Three dimensional structure memory |
| US6221769B1 (en)* | 1999-03-05 | 2001-04-24 | International Business Machines Corporation | Method for integrated circuit power and electrical connections via through-wafer interconnects |
| JP2000304744A (en) | 1999-04-20 | 2000-11-02 | Shimizu Corp | Method for measuring chloride content in fresh concrete |
| US6963483B2 (en) | 1999-12-29 | 2005-11-08 | Intel Corporation | Self-aligned coaxial via capacitors |
| US20020085336A1 (en) | 2000-12-29 | 2002-07-04 | Paul Winer | High performance via capacitor and method for manufacturing same |
| US20050106845A1 (en) | 2001-02-22 | 2005-05-19 | Halahan Patrick B. | Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same |
| US7033934B2 (en)* | 2001-11-07 | 2006-04-25 | Shinko Electric Industries Co., Ltd. | Method of production of semiconductor package |
| US20080296731A1 (en) | 2002-06-27 | 2008-12-04 | Block Bruce A | Enhanced on-chip decoupling capacitors and method of making same |
| US20040089948A1 (en)* | 2002-11-07 | 2004-05-13 | Yu-Ting Cheng | Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer |
| US20050023664A1 (en)* | 2002-12-09 | 2005-02-03 | Chudzik Michael Patrick | High density chip carrier with integrated passive devices |
| US20040108587A1 (en)* | 2002-12-09 | 2004-06-10 | Chudzik Michael Patrick | High density chip carrier with integrated passive devices |
| US20050116275A1 (en) | 2003-12-02 | 2005-06-02 | Shian-Jyh Lin | Trench capacitor structure |
| US20060001174A1 (en) | 2004-06-30 | 2006-01-05 | Nec Electronics Corporation | Semiconductor device and method for manufacturing the same |
| US20090075478A1 (en)* | 2004-12-02 | 2009-03-19 | Nec Electronics Corporation | Semiconductor device,having a through electrode, semiconductor module employing thereof and method for manufacturing semiconductor device having a through electrode |
| US7705691B2 (en)* | 2005-10-18 | 2010-04-27 | Agency For Science, Technology & Research | Capacitor interconnection |
| US20080113505A1 (en) | 2006-11-13 | 2008-05-15 | Sparks Terry G | Method of forming a through-substrate via |
| US20080128856A1 (en) | 2006-12-05 | 2008-06-05 | Sung-Ho Kwak | Semiconductor device having metal-insulator-metal capacitor and method of fabricating the same |
| US20080173993A1 (en)* | 2007-01-18 | 2008-07-24 | International Business Machines Corporation | Chip carrier substrate capacitor and method for fabrication thereof |
| US20080202799A1 (en) | 2007-02-26 | 2008-08-28 | Bhret Graydon | Embedding an electronic component between surfaces of a printed circuit board |
| US20090212438A1 (en) | 2008-02-26 | 2009-08-27 | Franz Kreupl | Integrated circuit device comprising conductive vias and method of making the same |
| US20100308435A1 (en)* | 2009-06-08 | 2010-12-09 | Qualcomm Incorporated | Through Silicon Via With Embedded Decoupling Capacitor |
| US20110037144A1 (en)* | 2009-08-13 | 2011-02-17 | Broadcom Corporation | Method for fabricating a decoupling composite capacitor in a wafer and related structure |
Non-Patent Citations (1)
| Title |
|---|
| International Search Report and Written Opinion dated Nov. 9, 2010 issued in PCT/US2010/055949. |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10424565B2 (en) | 2014-04-11 | 2019-09-24 | Osram Opto Semiconductor Gmbh | Semiconductor chip for protecting against electrostatic discharges |
| US9412806B2 (en) | 2014-06-13 | 2016-08-09 | Invensas Corporation | Making multilayer 3D capacitors using arrays of upstanding rods or ridges |
| US9865675B2 (en) | 2014-06-13 | 2018-01-09 | Invensas Corporation | Making multilayer 3D capacitors using arrays of upstanding rods or ridges |
| US9397038B1 (en) | 2015-02-27 | 2016-07-19 | Invensas Corporation | Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates |
| US9691702B2 (en) | 2015-02-27 | 2017-06-27 | Invensas Corporation | Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates |
| US9947618B2 (en) | 2015-02-27 | 2018-04-17 | Invensas Corporation | Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates |
| US10177086B2 (en) | 2015-02-27 | 2019-01-08 | Invensas Corporation | Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates |
| US10522457B2 (en) | 2015-02-27 | 2019-12-31 | Invensas Corporation | Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates |
| US10950689B2 (en) | 2015-09-23 | 2021-03-16 | Nanyang Technological University | Semiconductor device with a through-substrate via hole having therein a capacitor and a through-substrate via conductor |
| US11961882B2 (en) | 2021-02-26 | 2024-04-16 | Samsung Electronics Co., Ltd. | Semiconductor device |
| US12328882B2 (en) | 2021-02-26 | 2025-06-10 | Samsung Electronics Co., Ltd. | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102598263A (en) | 2012-07-18 |
| CN102598263B (en) | 2015-03-11 |
| GB2488078B (en) | 2014-02-26 |
| DE112010004326T5 (en) | 2012-08-23 |
| US20110108948A1 (en) | 2011-05-12 |
| GB201209593D0 (en) | 2012-07-11 |
| US20130344675A1 (en) | 2013-12-26 |
| WO2011057238A2 (en) | 2011-05-12 |
| US8558345B2 (en) | 2013-10-15 |
| DE112010004326B4 (en) | 2017-09-21 |
| WO2011057238A3 (en) | 2011-08-18 |
| GB2488078A (en) | 2012-08-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8785289B2 (en) | Integrated decoupling capacitor employing conductive through-substrate vias | |
| JP4222929B2 (en) | Chip carrier | |
| TWI473247B (en) | Semiconductor integrated circuit device with high Q wafer back surface capacitance | |
| US8299583B2 (en) | Two-sided semiconductor structure | |
| US8729711B2 (en) | Semiconductor device | |
| US8841754B2 (en) | Semiconductor devices with stress relief layers | |
| CN101044618A (en) | Device and method for fabricating double-sided soi wafer scale package with through via connections | |
| CN103367334A (en) | Semiconductor package with through-silicon via interconnection and packaging method thereof | |
| TWI771902B (en) | Contact pads of three-dimensional memory device and fabrication method thereof | |
| CN104867905B (en) | A kind of semiconductor structure comprising silicon hole and its manufacture method | |
| US9153638B2 (en) | Integrated decoupling capacitor utilizing through-silicon via | |
| JP6180428B2 (en) | Interposer device | |
| JPWO2005086216A1 (en) | Semiconductor element and method of manufacturing semiconductor element | |
| CN116613124A (en) | Wafer Structure and Semiconductor Devices | |
| US20240113078A1 (en) | Three dimensional heterogeneous integration with double-sided semiconductor dies and methods of forming the same | |
| US20240145344A1 (en) | Via structure and method for forming the same | |
| CN102751172A (en) | Integrated passive device and manufacture method thereof | |
| KR101223541B1 (en) | Semiconductor Chip and Multi Chip Package having the same | |
| US20250006625A1 (en) | Semiconductor package | |
| US20250070062A1 (en) | Semiconductor interconnection structure and method for forming same, and semiconductor package structure | |
| CN108091623B (en) | System-in-package antistatic adapter plate based on BJT (bipolar junction transistor) | |
| CN108321155B (en) | Integrated circuit antistatic adapter plate based on BJT | |
| CN119694893A (en) | Semiconductor packaging structure and method for forming the same | |
| CN119626913A (en) | Semiconductor packaging structure and method for forming the same | |
| CN120376508A (en) | Semiconductor packaging structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AS | Assignment | Owner name:INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text:ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, TAE HONG;MCALLISTER, MICHAEL F.;SHAPIRO, MICHAEL J.;AND OTHERS;SIGNING DATES FROM 20130809 TO 20130823;REEL/FRAME:031081/0559 | |
| STCF | Information on status: patent grant | Free format text:PATENTED CASE | |
| MAFP | Maintenance fee payment | Free format text:PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551) Year of fee payment:4 | |
| AS | Assignment | Owner name:TESSERA, INC., CALIFORNIA Free format text:ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:051489/0557 Effective date:20191227 | |
| AS | Assignment | Owner name:BANK OF AMERICA, N.A., NORTH CAROLINA Free format text:SECURITY INTEREST;ASSIGNORS:ROVI SOLUTIONS CORPORATION;ROVI TECHNOLOGIES CORPORATION;ROVI GUIDES, INC.;AND OTHERS;REEL/FRAME:053468/0001 Effective date:20200601 | |
| MAFP | Maintenance fee payment | Free format text:PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment:8 |