US8532796B2 - Contact processing using multi-input/multi-output (MIMO) models - Google Patents

Abstract

The invention provides a systems and methods for creating Double Pattern (DP) structures on a patterned wafer in real-time using Dual Pattern Contact-Etch (DPCE) processing sequences and associated Contact-Etch-Multi-Input/Multi-Output (CE-MIMO) models. The DPCE processing sequences can include one or more contact-etch procedures, one or more measurement procedures, one or more contact-etch modeling procedures, and one or more contact-etch verification procedures. The CE-MIMO model uses dynamically interacting behavioral modeling between multiple layers and/or multiple contact-etch procedures. The multiple layers and/or the multiple contact-etch procedures can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created during Double Patterning (DP) procedures.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to co-pending U.S. patent application Ser. No. 12/186,668, entitled “Creating Multi-Layer/Multi-Input/Multi-Output (MLMIMO) Models for Metal-Gate Structures”, published as 2010/0036514 on Feb. 11, 2010; and co-pending U.S. patent application Ser. No. 12/059,624, entitled “Multi-Layer/Multi-Input/Multi-Output (MLMIMO) Models and Method for Using”, published as 2009/0242513 on Oct. 1, 2009. The contents of each of these applications are herein incorporated by reference in their entireties. This application is also related to U.S. Pat. No. 7,777,179, entitled “Two-Grid Ion Energy Analyzer and Methods of Manufacturing and Operating”, by Chen, et al., issued on Aug. 17, 2010, and this patent is incorporated in its entirety herein by reference. In addition, this application is also related to U.S. Pat. No. 7,875,859, entitled “Ion Energy Analyzer and Methods of Manufacturing and Operating”, by Chen, et al., issued on Jan. 25, 2011, and this patent is incorporated in its entirety herein by reference. In addition, this application is also related to U.S. Pat. No. 7,894,927, entitled “Using Multi-Layer/Multi-Input/Multi-Output (MLMIMO) Models For Metal-Gate Structures”, by Funk, et al., issued on Jan. 25, 2011, and this patent is incorporated in its entirety herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to wafer processing, and more particularly to apparatus and methods for creating Double Pattern (DP) structures on a patterned wafer in real-time using Dual Pattern Contact-etch (DPCE) processing sequences and associated Contact-Etch-Multi-Input/Multi-Output (CE-MIMO) models.

2. Description of the Related Art

Etch process behavior is inherently non-linear and interacting step-to-step (layers), or as process stacks are compiled (etch/cvd/implant). With the knowledge of the process interactions based on physical modeling of Tokyo Electron Limited (TEL) chambers and base processes and imperial data and measurements from process refinement and tuning the control of Critical Dimension (CD), Sidewall Angle (SWA), depths, film thicknesses, over etching, undercuts, surface cleaning and damage control can be recursively calculated and optimized using multi-input multi-output non-linear models. Current low cost products use a bulk silicon technology. As the transistor continues to shrink, the impact of the channel depth is becoming critical (ultra-shallow source/drain extensions). As the Silicon-on-Insulator (SOI) film shrinks, smaller variations in the gate and/or spacer thickness and thickness of the SOI film can affect the transistor's performance. When etch procedures are not controlled, the removal of the material near the gate affects the electrical performance.

Current high performance microprocessors use PD SOI (partially depleted Silicon-on-Insulator film—giving a threshold voltage 0.2 volts. PD SOI films are around 50 nm thick while the gate and/or spacer reduction amount can be a large percentage (10%) of the total gate and/or spacer thickness. Future generations of SOI films are called FD SOI (fully depleted SOI), giving a threshold voltage 0.08 volts and a thickness of ˜25 nm). Currently these films are not in production due to limitations in thickness control uniformity and defects. Channel mobility degrades with decreasing SOI thickness. With thinner films, the control of the metal-gate structures becomes more critical

SUMMARY OF THE INVENTION

The invention can provide apparatus and methods of creating Double Pattern (DP) structures on a pattern wafer in real-time using Dual Pattern Contact-etch (DPCE processing sequences and associated Contact-Etch-Multi-Input/Multi-Output (CE-MIMO) models. Other aspects of the invention will be made apparent from the description that follows and from the drawings appended hereto.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts, and in which:

FIG. 1 shows an exemplary block diagram of a processing system in accordance with embodiments of the invention;

FIGS. 2A-2G show exemplary block diagrams of contact-etch subsystems in accordance with embodiments of the invention;

FIGS. 3A-3G show exemplary block diagrams of additional contact-etch subsystems in accordance with embodiments of the invention;

FIG. 4 shows a simplified block diagram of an exemplary contact-etch Multi-Input/Multi-Output (MIMO) model optimization and control methodology in accordance with embodiments of the invention;

FIGS.5 and5′ illustrate exemplary views of a first Double-Pattern-Contact-Etch (DPCE) processing sequence for creating first double pattern (DP) features in accordance with embodiments of the invention;

FIGS.6 and6′ illustrate exemplary views of a second Double-Pattern-Contact-Etch (DPCE) processing sequence for creating second double pattern (DP) features in accordance with embodiments of the invention;

FIG. 7 illustrates exemplary views of a third Double-Pattern-Contact-Etch (DPCE) processing sequence for creating third double pattern (DP) features in accordance with embodiments of the invention;

FIG. 8 illustrates an exemplary flow diagram for a procedure for developing a contact-etch Multi-Input/Multi-Output (MIMO) model in accordance with embodiments of the invention;

FIG. 9 illustrates a simplified flow diagram of a method for processing wafers using an IE-related process sequence in accordance with embodiments of the invention;

FIG. 10 illustrates an exemplary block diagram for an Ion Energy (IE) sensor wafer in accordance with embodiments of the invention; and

FIG. 11 illustrates a method for using an IE-sensor wafer in accordance with embodiments of the invention.

FIG. 12 illustrates a method for contact etch in accordance with embodiments of the invention.

DETAILED DESCRIPTION

The contact-etch CE-MIMO models can be subdivided into layers of a finite granularity based on the application need. Each layer can be a physical material, with layer separation denoted by material changes or dimensional layer boundaries. Layers can be combination of layers of layers, such as metal gate stack layers and subsequent spacer deposition and etching of the spacer layer covering the metal gate layers. Layers can be mapped to DPCE processing sequences or contact-etch procedures with time or End Point Detection (EPD) being used to separate the steps. Additionally a continuous real-time controller can run with real-time updates from a combination of metrology data, sensors, and etch models.

Design of Experiments (DOEs) can be run to model the process gain of each potential control knob and the interactions of the inputs and outputs associated with each layer, and the interactions and gains of process control loops layer to layer. A method of determining interaction between each control knob and output can be used to evaluate and optimize the model stability such as Relative Gain Array (RGA). This information can also drive setup of individual feedback loops that are non-interacting.

The CE-MIMO models can be used to calculate the optimum inputs for a set of goals (or targeted outputs). Constraints can be ranges of process parameters such as time, gas flows, and temperature by layer. During CE-MIMO model development, a set of weightings can be applied to guide the optimizer to prioritize the outputs with most value to the current process calculations at a given time. Target weightings can be used where an equation is applied to the weighting calculation given a target and gain constants that effectively penalizes as the optimizer moves away from target in a linear or non-linear way. Targets can be a center target or and limit target (above a given value—for example with SWA).

Feedback can take the form of multiple loops, one for each targeted output with a calculation of the feedback error based on the actual less predicted error. When using an CE-MIMO model, each predicted output error could be calculated and matched with the feedback measurements to determine the real error. Feedback filtering methods such as Exponentially Weighted Moving Averages (EWMA) filters or Kalman filters can be used to filter noise. Outputs from a controller associated with a contact-etch procedure or an Ion Energy Optimized (IEO) etch procedure can include a goodness of fit value, and the GOF value can then be used as the input to a cascaded controller.

MIMO controllers can calculate updates at different times as the processing steps are performed allowing the controller to make new updates based on past calculations, errors in calculations, changes in tool state or material state then incorporated into the most recent update.

In some contact-etch procedures, when the resist parameters are measured, they can be used for feed forward, and can be weighted based on previous wafers feedback and chamber state information. At the beginning of a Lot, the CE-MIMO model can be configured to use the best known values for the patterned etch mask layer, and these can be weighted to the center of the previous lot's distribution, During the lot processing, the parameters for the inter-dielectric layer (IDL) or the hard mask layers can be measured and filtered using a weighting method such as EWMA to smooth wafer-to-wafer (W2W) variations and can be fed back to update the current feed forward SWA value. The SWA pattern analysis function can group bimodal patterns so two threads can be managed to feedback and/or feed forward data. In one example, the SWA W2W variation is more commonly driven by scanner stage so two feed forward/feedback threads can be maintained to optimize performance. In a second example, the W2W CD variation from the lithography tool can be dominated by the hot plates, so a two, three, or four variation pattern can be observed. When IM measurements are made after the lithography processes, the pattern across the wafer can be established before wafer processing and the wafer CD and SWA patterns can be established before the wafers are sent to the etcher. When more than one processing threads are used, the thread number can be added as a context item for the wafer. In addition, when the scanner and/or track cell number, scanner module number, and hot plate number are available, they can also be used to group wafers and establish feed forward threads from the Lithography tool to the Etch Tool. Alternatively, other combinations of coater/developers may also be used.

When the wafers are sorted based on context groups, the wafers can be processed based on their group or contact-etch procedure. When processing order in the etch tool is the same as the processing order in the lithography tool, the current feedback (FB) controller can be programmed to adjust for W2W for incoming drift inside the lithography tool and for drift inside the etch tool

The invention provides apparatus and methods for processing wafers having a large number of semiconductor devices thereon and an even larger number of transistor gate and/or spacer structures. In various embodiments, apparatus and methods are provided for creating and/or using a CE-MIMO evaluation library, for performing DPCE processing sequences that can include one or more contact-etch metal gate sequences, one or more contact-etch via-etch sequences, one or more CE measurement procedures, one or more cleaning procedures, and/or one or more verification procedures.

One or more periodic structures can be provided at various locations on a wafer and can be used to evaluate and/or verify contact-etch (CE) MIMO models and associated DPCE processing sequences. Wafers can have wafer data associated with them, and the wafer data can include real-time and historical contact-etch (CE) data. In addition, the wafer can have other data associated with them, and the other data can include gate structure data, the number of required sites, the number of visited sites, confidence data and/or risk data for one or more of the sites, site ranking data, transferring sequence data, or process-related data, or evaluation/verification-related data, or any combination thereof. The data associated with DPCE processing sequences can include transfer sequence data that can be used to establish when and where to transfer the wafers, and contact-etch procedures can be change using operational state data.

The contact-etch (CE) MIMO model can be subdivided into layers of a finite granularity based on the application need. Each layer can be a physical material, with layer separation denoted by material changes or dimensional layer boundaries. Layers can be combination of layers of layers, such as a metal gate stack of layers and a subsequent spacer deposition and etching of the layer covering the metal gate layers.

Layers can be mapped to etch steps with time or End Point Data (EPD) being used to separate the steps. Additionally a continuous real-time controller can run with real-time updates from a combination of metrology data, sensors, and etch models.

An analytical device used in process control multivariable applications, based on the comparison of single-loop control to multivariable control; expressed as an array (for all possible input-output pairs) of the ratios of a measure of the single-loop behavior between an input-output variable pair, to a related measure of the behavior of the same input-output pair under some idealization of multivariable control.

CE-MIMO modeling is used to calculate the optimum inputs for a set of goals (or targeted outputs). Constraints can be ranges of process parameters such as time, gas flows, and temperature by layer. With a CE-MIMO model, a set of weightings can be applied to guide the optimizer to prioritize the outputs with most value to the current process calculations at a given time. Target weightings can be used where an equation is applied to the weighting calculation given a target and gain constants that effectively penalizes as the optimizer moves away from target in a linear or non-linear way. Targets can be a center target or and limit target (above a given value—for example with SWA).

Feedback can take the form of multiple loops, one for each targeted output with a calculation of the feedback error based on the actual less predicted error. With a CE-MIMO model, each prediction output error needs to be calculated and matched with the feedback measurements to determine the real error. Feedback filtering methods such as EWMA or Kalman filters can be used to filter noise. Outputs of a layer controller can include a goodness of fit (GOF), and this GOF value can then be used as the input of a cascading layer controller.

The wafer can be partitioned into one or more upper edge regions, one or more center regions, and one or more lower edge regions.

Layer controllers can contain updates at different times as the processing steps are performed, thereby allowing the controller to make new updates based on past calculations, errors in the calculations, changes in tool state or material state then incorporated into the updates.

As feature sizes decrease below the 65 nm node, accurate processing, and/or measurement data becomes more important and more difficult to obtain. CE-MIMO models and associated DPCE processing sequences can be used to more accurately process and/or measure these ultra-small devices and features. The data from a contact-etch (CE) procedure can be compared with the warning and/or control limits, when a run-rule is violated, an alarm can be generated indicating a processing problem, and correction procedures can be performed in real time.

FIG. 1 shows an exemplary block diagram of a processing system in accordance with embodiments of the invention. In the illustrated embodiment,processing system100 comprises alithography subsystem110, ascanner subsystem120, anetch subsystem130, adeposition subsystem140, aninspection subsystem150, ametrology subsystem160, atransfer subsystem170, a manufacturing execution system (MES)180, asystem controller190, and a memory/database195. Single subsystems (110,120,130,140,150,160, and170) are shown in the illustrated embodiment, but this is not required for the invention. In some embodiments, multiple subsystems (110,120,130,140,150,160, and170) can be used in aprocessing system100. In some embodiments, one or more of the subsystems (110,120,130,140,150,160, and170) can comprise one or more processing elements that can be used in CE-MIMO models and associated DPCE processing sequences. In other embodiments, one or more of the subsystems (110,120,130,140,150,160, and170) can comprise one or more processing elements that can be used in Ion Energy Controlled (IEC) MIMO models, IEC etch sequences, and associated Ion Energy Optimized (IEO) etch procedures.

Thesystem controller190 can be coupled to thelithography subsystem110, thescanner subsystem120, theetch subsystem130, thedeposition subsystem140, theinspection subsystem150, themetrology subsystem160, and thetransfer subsystem170 using adata transfer subsystem191. Thesystem controller190 can be coupled to theMES180 using thedata transfer subsystem181. Alternatively, other configurations may be used. For example, theetch subsystem130, thedeposition subsystem140, themetrology subsystem160, and a portion of thetransfer subsystem170 can be part of a Tactras™ System available from Tokyo Electron Limited.

Thelithography subsystem110 can comprise one or more transfer/storage elements112, one ormore processing elements113, one ormore controllers114, and one ormore evaluation elements115. One or more of the transfer/storage elements112 can be coupled to one or more of theprocessing elements113 and/or to one or more of theevaluation elements115 and can be coupled bylink111 to thetransfer subsystem170. Thetransfer subsystem170 can be coupled by thelink111 to thelithography subsystem110, and one ormore wafers105 can be transferred by thelink111 between thetransfer subsystem170 and thelithography subsystem110 in real time. For example, thetransfer subsystem170 can be coupled to one or more of the transfer/storage elements112, to one or more of theprocessing elements113, and/or to one or more of theevaluation elements115. One or more of thecontrollers114 can be coupled to one or more of the transfer/storage elements112, to the one or more of theprocessing elements113, and/or to one or more of theevaluation elements115.

In some embodiments, thelithography subsystem110 can perform coating procedures, thermal procedures, measurement procedures, inspection procedures, alignment procedures, and/or storage procedures on one or more wafers using procedures and/or procedures. For example, one or more lithography-related processes can be used to deposit one or more masking layers that can include photoresist material, and/or anti-reflective coating (ARC) material, and can be used to thermally process (bake) one or more of the masking layers. In addition,lithography subsystem110 can be used to develop, measure, and/or inspect one or more of the patterned masking layers on one or more of the wafers.

Thescanner subsystem120 can comprise one or more transfer/storage elements122, one ormore processing elements123, one ormore controllers124, and one ormore evaluation elements125. One or more of the transfer/storage elements122 can be coupled to one or more of theprocessing elements123 and/or to one or more of theevaluation elements125 and can be coupled bylink121 to thetransfer subsystem170. Thetransfer subsystem170 can be coupled by thelink121 to thescanner subsystem120, and one ormore wafers105 can be transferred by thelink121 between thetransfer subsystem170 and thescanner subsystem120 in real time. For example, thetransfer subsystem170 can be coupled to one or more of the transfer/storage elements122, to one or more of theprocessing elements123, and/or to one or more of theevaluation elements125. One or more of thecontrollers124 can be coupled to one or more of the transfer/storage elements122, to the one or more of theprocessing elements123, and/or to one or more of theevaluation elements125.

In some embodiments, thescanner subsystem120 can be used to perform wet and/or dry exposure procedures, and in other cases, thescanner subsystem120 can be used to perform extreme ultraviolet (EUV) exposure procedures.

Theetch subsystem130 can comprise one or more transfer/storage elements132, one ormore processing elements133, one ormore controllers134, and one ormore evaluation elements135. One or more of the transfer/storage elements132 can be coupled to one or more of theprocessing elements133 and/or to one or more of theevaluation elements135 and can be coupled bylink131 to thetransfer subsystem170. Thetransfer subsystem170 can be coupled by thelink131 to theetch subsystem130, and one ormore wafers105 can be transferred by thelink131 between thetransfer subsystem170 and theetch subsystem130 in real time. For example, thetransfer subsystem170 can be coupled to one or more of the transfer/storage elements132, to one or more of theprocessing elements133, and/or to one or more of theevaluation elements135. One or more of thecontrollers134 can be coupled to one or more of the transfer/storage elements132, to the one or more of theprocessing elements133, and/or to one or more of theevaluation elements135. For example, one or more of theprocessing elements133 can be used to perform plasma or non-plasma etching, ashing, trimming, and cleaning procedures. Evaluation procedures and/or inspection procedures can be used to measure and/or inspect one or more surfaces and/or layers of the wafers. Theetch subsystem130 can be configured as described herein inFIGS. 2A-2G andFIGS. 3A-3G.

Thedeposition subsystem140 can comprise one or more transfer/storage elements142, one ormore processing elements143, one ormore controllers144, and one ormore evaluation elements145. One or more of the transfer/storage elements142 can be coupled to one or more of theprocessing elements143 and/or to one or more of theevaluation elements145 and can be coupled bylink141 to thetransfer subsystem170. Thetransfer subsystem170 can be coupled by thelink141 to thedeposition subsystem140, and one ormore wafers105 can be transferred by thelink141 between thetransfer subsystem170 and thedeposition subsystem140 in real time. For example, thetransfer subsystem170 can be coupled to one or more of the transfer/storage elements142, to one or more of theprocessing elements143, and/or to one or more of theevaluation elements145. One or more of thecontrollers144 can be coupled to one or more of the transfer/storage elements142, to the one or more of theprocessing elements143, and/or to one or more of theevaluation elements145. For example, one or more of theprocessing elements143 can be used to perform physical vapor deposition (PVD) procedures, chemical vapor deposition (CVD) procedures, ionized physical vapor deposition (iPVD) procedures, atomic layer deposition (ALD) procedures, plasma enhanced atomic layer deposition (PEALD) procedures, and/or plasma enhanced chemical vapor deposition (PECVD) procedures. Evaluation procedures and/or inspection procedures can be used to measure and/or inspect one or more surfaces of the wafers.

Theinspection subsystem150 can comprise one or more transfer/storage elements152, one ormore processing elements153, one ormore controllers154, and one ormore evaluation elements155. One or more of the transfer/storage elements152 can be coupled to one or more of theprocessing elements153 and/or to one or more of theevaluation elements155 and can be coupled bylink151 to thetransfer subsystem170. Thetransfer subsystem170 can be coupled by thelink151 to theinspection subsystem150, and one ormore wafers105 can be transferred by thelink151 between thetransfer subsystem170 and theinspection subsystem150 in real time. For example, thetransfer subsystem170 can be coupled to one or more of the transfer/storage elements152, to one or more of theprocessing elements153, and/or to one or more of theevaluation elements155. One or more of thecontrollers154 can be coupled to one or more of the transfer/storage elements152, to the one or more of theprocessing elements153, and/or to one or more of theevaluation elements155.

Themetrology subsystem160 can comprise one or more transfer/storage elements162, one ormore processing elements163, one ormore controllers164, and one ormore evaluation elements165. One or more of the transfer/storage elements162 can be coupled to one or more of theprocessing elements163 and/or to one or more of theevaluation elements165 and can be coupled bylink161 to thetransfer subsystem170. Thetransfer subsystem170 can be coupled by thelink161 to themetrology subsystem160, and one ormore wafers105 can be transferred by thelink161 between thetransfer subsystem170 and themetrology subsystem160 in real time. For example, thetransfer subsystem170 can be coupled to one or more of the transfer/storage elements162, to one or more of theprocessing elements163, and/or to one or more of theevaluation elements165. One or more of thecontrollers164 can be coupled to one or more of the transfer/storage elements162, to the one or more of theprocessing elements163, and/or to one or more of theevaluation elements165. Themetrology subsystem160 can comprise one ormore processing elements163 that can be used to perform real-time optical metrology procedures that can be used to measure target structures at one or more sites on a wafer using library-based or regression-based techniques. For example, the sites on wafer can include MIMO sites, target sites, overlay sites, alignment sites, measurement sites, verification sites, inspection sites, or damage-assessment sites, or any combination thereof. For example, one or more “golden wafers” or reference chips can be stored and used periodically to verify the performance of one or more of theprocessing elements163, and/or one or more of theevaluation elements165.

In some embodiments, themetrology subsystem160 can include integrated Optical Digital Profilometry (iODP) elements (not shown), and iODP elements/systems are available from Timbre Technologies Inc. (a TEL company). Alternatively, other metrology systems may be used. For example, iODP techniques can be used to obtain real-time data that can include critical dimension (CD) data, gate structure data, and thickness data, and the wavelength ranges for the iODP data can range from less than about 200 nm to greater than about 900 nm. Exemplary iODP elements can include ODP Profiler Library elements, Profiler Application Server (PAS) elements, and ODP Profiler Software elements. The ODP Profiler Library elements can comprise application specific database elements of optical spectra and its corresponding semiconductor profiles, CDs, and film thicknesses. The PAS elements can comprise at least one computer that connects with optical hardware and computer network. The PAS elements can be configured to provide the data communication, ODP library operation, measurement process, results generation, results analysis, and results output. The ODP Profiler Software elements can include the software installed on PAS elements to manage measurement recipe, ODP Profiler library elements, ODP Profiler data, ODP Profiler search/match results, ODP Profiler calculation/analysis results, data communication, and PAS interface to various metrology elements and computer network.

Themetrology subsystem160 can use polarizing reflectometry, spectroscopic ellipsometry, reflectometry, or other optical measurement techniques to measure accurate device profiles, accurate CDs, and multiple layer film thickness of a wafer. The integrated metrology process (iODP) can be executed as an integrated process in an integrated group of subsystems. In addition, the integrated process eliminates the need to break the wafer for performing the analyses or waiting for long periods for data from external systems. iODP techniques can be used with the existing thin film metrology systems for inline profile and CD measurement, and can be integrated with TEL processing systems and/or lithography systems to provide real-time process monitoring and control. Simulated metrology data can be generated by applying Maxwell's equations and using a numerical analysis technique to solve Maxwell's equations.

Thetransfer subsystem170 can comprisetransfer elements174 coupled to transfer tracks (175,176, and177) that can be used to receive wafers, transfer wafers, align wafers, store wafers, and/or delay wafers. For example, thetransfer elements174 can support two or more wafers. Alternatively, other transferring means may be used. Thetransfer subsystem170 can load, transfer, store, and/or unload wafers based on a CE-MIMO model, a DPCE processing sequence, a transfer sequence, operational states, the wafer and/or processing states, the processing time, the current time, the wafer data, the number of sites on the wafer, the type of sites on the wafers, the number of required sites, the number of completed sites, the number of remaining sites, or confidence data, or any combination thereof.

In some examples,transfer subsystem170 can use loading data to determine where and when to transfer a wafer. In other examples, a transfer system can use MIMO modeling data to determine where and when to transfer a wafer. Alternatively, other procedures may be used. For example, when the first number of wafers is less than or equal to the first number of available processing elements, the first number of wafers can be transferred to the first number of available processing elements in the one or more of the subsystems using thetransfer subsystem170. When the first number of wafers is greater than the first number of available processing elements, some of the wafers can be stored and/or delayed using one or more of the transfer/storage elements (112,122,132,142,152, and162) and/or thetransfer subsystem170.

In addition, the one or more subsystems (110,120,130,140,150,160, and170) can be used when performing lithography-related procedures, scanner-related procedures, inspection-related procedures, measurement-related procedures, evaluation-related procedures, etch-related procedures, deposition-related procedures, thermal processing procedures, coating-related procedures, alignment-related procedures, polishing-related procedures, storage-related procedures, transfer procedures, cleaning-related procedures, rework-related procedures, oxidation-related procedures, nitridation-related procedures, or external processing elements, or any combination thereof.

Operational state data can be established for the subsystems (110,120,130,140,150,160, and170) and can be used and/or updated by contact-etch procedures. In addition, operational state data can be established for the transfer/storage elements (112,122,132,142,152, and162), processing elements (113,123,133,143,153, and163), and evaluation elements (115,125,135,145,155, and165), and can be updated by contact-etch procedures. For example, the operational state data for the processing elements can include availability data, matching data for the processing elements, expected processing times for some process steps and/or sites, yield data, confidence data and/or risk data for the processing elements, or confidence data and/or risk data for one or more DPCE processing sequences. Updated operational states can be obtained by querying in real-time one or more processing elements, and/or one or more subsystems. Updated loading data can be obtained by querying in real-time one or more transfer elements, and/or one or more transfer subsystems.

One or more of the controllers (114,124,134,144,154, and164) can be coupled to thesystem controller190 and/or to each other using adata transfer subsystem191. Alternatively, other coupling configurations may be used. The controllers can be coupled in series and/or in parallel and can have one or more input ports and/or one or more output ports. For example, the controllers may include microprocessors having one or more core processing elements.

In addition, subsystems (110,120,130,140,150,160, and170) can be coupled to each other and to other devices using intranet, internet, wired, and/or wireless connections. The controllers (114,124,134,144,154,164, and190) can be coupled to external devices as required.

One or more of the controllers (114,124,134,144,154,164, and190) can be used when performing real-time DPCE processing sequences. A controller can receive real-time data from an Ion Energy (IE)-MIMO model to update subsystem, processing element, process, recipe, profile, image, pattern, simulation, sequence data, and/or model data. One or more of the controllers (114,124,134,144,154,164, and190) can be used to exchange one or more Semiconductor Equipment Communications Standard (SECS) messages with the Manufacturing Execution Systems (MES)180 or other systems (not shown), read and/or remove information, feed forward, and/or feedback the information, and/or send information as a SECS message. One or more of the formatted messages can be exchanged between controllers, and the controllers can process messages and extract new data in real-time. When new data is available, the new data can be used in real-time to update a model and/or procedure currently being used for the wafer and/or lot. For example, the current layout can be examined using the updated model and/or procedure when the model and/or procedure can be updated before the current layout is examined. The current layout can be examined using a non-updated model and/or procedure when an update cannot be performed before the current layout is processed. In addition, formatted messages can be used when contact-etch procedures are changed, when contact-etch-related models are changed, when DPCE processing sequences are changed, when design rules are changed, or when layouts are changed.

In some examples, theMES180 may be configured to monitor some subsystem and/or system processes in real-time, and factory level intervention and/or judgment rules can be used to determine which processes are monitored and which data can be used. For example, factory level intervention and/or judgment rules can be used to determine how to manage the data when a MIMO-related error condition occurs. TheMES180 can also provide modeling data, sequence data, process data, and/or wafer data.

In addition, controllers (114,124,134,144,154,164, and190) can include memory (not shown) as required. For example, the memory (not shown) can be used for storing information and instructions to be executed by the controllers, and may be used for storing temporary variables or other intermediate information during the execution of instructions by the various computers/processors in theprocessing system100. One or more of the controllers (114,124,134,144,154,164, and190), or other system components can comprise the means for reading data and/or instructions from a computer readable medium and can comprise the means for writing data and/or instructions to a computer readable medium.

Theprocessing system100 can perform a portion of or all of the processing steps of the invention in response to the computers/processors in theprocessing system100 executing one or more sequences of one or more instructions contained in a memory and/or received in a message. Such instructions may be received from another computer, a computer readable medium, or a network connection.

In some embodiments, an integrated system can be configured using system components from Tokyo Electron Limited (TEL), and external subsystems and/or tools may be included. For example, measurement elements can be provided that can include a CD-Scanning Electron Microscopy (CDSEM) system, a Transmission Electron Microscopy (TEM) system, a focused ion beam (FIB) system, an Optical Digital Profilometry (ODP) system, an Atomic Force Microscope (AFM) system, or another optical metrology system. The subsystems and/or processing elements can have different interface requirements, and the controllers can be configured to satisfy these different interface requirements.

One or more of the subsystems (110,120,130,140,150,160, and170) can perform control applications, Graphical User Interface (GUI) applications, and/or database applications. In addition, one or more of the subsystems (110,120,130,140,150,160, and170) and/or controllers (114,124,134,144,154,164, and190) can include Design of Experiment (DOE) applications, Advanced Process Control (APC) applications, Fault Detection and Classification (FDC) applications, and/or Run-to-Run (R2R) applications.

Output data and/or messages from DPCE processing sequences or contact-etch modeling procedures can be used in subsequent sequences and/or procedures to optimize the process accuracy and precision. Data can be passed to DPCE processing sequences or contact-etch procedures in real-time as real-time variable parameters, overriding current model values, and reducing DOE tables. Real-time data can be used with a library-based system, or regression-based system, or any combination thereof to optimize the DPCE processing sequences or the contact-etch procedures.

When a regression-based library creation procedure is used, measured CE-MIMO model data can be compared to simulated CE-MIMO model data. The simulated CE-MIMO model data can be iteratively generated, based on sets of contact-etch process parameters, to obtain a convergence value for the set of contact-etch process parameters that generates the closest match simulated CE-MIMO model data compared to the measured CE-MIMO model data. When a library-based process is used, a CE-MIMO model library can be generated and/or enhanced using CE-MIMO model procedures, recipes, profiles, and/or models. For example, an CE-MIMO model library can comprise simulated and/or measured CE-MIMO data and corresponding sets of contact-etch procedure data. The regression-based and/or the library-based processes can be performed in real-time. An alternative procedure for generating data for an CE-MIMO library can include using a machine learning system (MLS). For example, prior to generating the CE-MIMO library data, the MLS can be trained using known input and output data, and the MLS may be trained with a subset of the CE-MIMO library data.

The CE-MIMO models can include intervention and/or judgment rules that can be executed whenever a matching context is encountered. Intervention and/or judgment rules and/or limits can be established based on historical procedures, on the customer's experience, or process knowledge, or obtained from a host computer. Rules can be used in Fault Detection and Classification (FDC) procedures to determine how to respond to alarm conditions, error conditions, fault conditions, and/or warning conditions. The rule-based FDC procedures can prioritize and/or classify faults, predict system performance, predict preventative maintenance schedules, decrease maintenance downtime, and extend the service life of consumable parts in the system. Various actions can take place in response to an alarm/fault, and the actions taken on the alarm/fault can be context-based, and the context data can be specified by a rule, a system/process recipe, a chamber type, identification number, load port number, cassette number, lot number, control job ID, process job ID, slot number and/or the type of data.

Unsuccessful contact-etch procedures or DPCE processing sequences can report a failure when a limit is exceeded, and successful contact-etch procedures or DPCE processing sequences can create warning messages when limits are being approached. Pre-specified failure actions for known errors can be stored in a database, and can be retrieved from the database when an error occurs. For example, contact-etch procedures or DPCE processing sequences can reject some of the contact-etch data at one or more of the process times when a data collection or validation procedure fails. In addition, contact-etch procedures or DPCE processing sequences can reject the data at one or more of the sites for a wafer when a measurement procedure fails.

Contact-etch procedures, DPCE processing sequences, and/or CE-MIMO models can be used to create, modify, and/or evaluate isolated and/or nested structures at different times and/or sites. For example, gate stack dimensions and wafer thickness data can be different near isolated and/or nested structures, and gate stack dimensions and wafer thickness data can be different near open areas and/or trench array areas. A CE-MIMO model can create optimized data for isolated and/or nested structures to update and/or optimize a process recipe and/or process time.

Contact-etch procedures, DPCE processing sequences, and/or CE-MIMO models can use end-point detection (EPD) data and process time data to improve the accuracy. When EPD data is used to stop an etch procedure, the EPD time data and the process rate data can be used to estimate the amount of etch and/or to estimate a thickness.

In various examples, CE-related data limits can be obtained by performing one or more contact-etch procedure in a test processing chamber using an CE-sensor wafer, can be historical data that is stored in a library, can be obtained by performing a verified contact-etch procedure, can be obtained from theMES180, can be simulation data, and can be predicted data. In addition, IE-related procedure limits can be obtained by performing the IE-related etch procedure in a “reference/golden” processing chamber.

FIGS. 2A-2G show exemplary block diagrams of contact-etch subsystems in accordance with embodiments of the invention.

A first exemplary contact-etch subsystem200A is shown inFIG. 2A, and the illustrated contact-etch subsystem200A includes aprocess chamber210,wafer holder220, upon which awafer205 to be processed is affixed,gas supply system240, andvacuum pumping system257. For example,wafer holder220 can be coupled to and insulated from theprocess chamber210 usingbase225.Wafer205 can be, for example, a semiconductor wafer, a work piece, or a liquid crystal display (LCD). For example,process chamber210 can be configured to facilitate the generation of contact-etch (CE) plasma inprocessing region249 adjacent a surface ofwafer205, and the CE-plasma is formed via collisions between heated electrons and an ionizable gas. An ionizable gas or mixture of gases can be introduced from thegas supply system240, and process pressure is adjusted usingvacuum pumping system257. Desirably, the CE-plasma can be used to create materials specific to a predetermined material process, and to aid either the deposition of material towafer205 or the removal of material from the exposed surfaces ofwafer205. For example,controller295 can be used to controlvacuum pumping system257 andgas supply system240.

Wafer205 can be, for example, transferred into and out of theprocess chamber210 through a slot valve (not shown) and chamber feed-through (not shown) via robotic transfer system where it is received by wafer lift pins (not shown) housed withinwafer holder220 and mechanically translated by devices housed therein. After thewafer205 is received from transfer system, it is lowered to an upper surface ofwafer holder220.

For example,wafer205 can be affixed to thewafer holder220 via an electrostatic clamping system (not shown). Thewafer holder220 can includetemperature control elements229 that can be coupled to atemperature control system228. For example, thetemperature control elements229 can include resistive heating elements, or thermo-electric heaters/coolers. Backside gas can be delivered to the backside of the wafer via a dual (center/edge) backside gas delivery system (226, and227) to improve the gas-gap thermal conductance betweenwafer205 andwafer holder220. A dual (center/edge) backside gas delivery system (226 and227) can be utilized when additional temperature control of the wafer is required at elevated or reduced temperatures. For example, temperature control of thewafer205 can be useful at temperatures in excess of the steady-state temperature achieved due to a balance of the heat flux delivered to thewafer205 from the plasma and the heat flux removed fromwafer205 by conduction to thewafer holder220.

As shown inFIG. 2A,wafer holder220 includes alower electrode232 through which Radio Frequency (RF) power can be coupled to plasma inprocessing region249. For example,lower electrode232 can be electrically biased at an RF voltage via the transmission of RF power fromfirst RF generator230 throughimpedance match network231 tolower electrode232. The RF bias can serve to heat electrons to form and maintain the CE-plasma. A typical frequency for the RF bias can range from 1 MHz to 100 MHz and is preferably 13.56 MHz.

Alternatively, RF power may be applied to thelower electrode232 at multiple frequencies. Furthermore,impedance match network231 serves to maximize the transfer of RF power to CE-plasma inprocess chamber210 by minimizing the reflected power. Various match network topologies and automatic control methods can be utilized.

With continuing reference toFIG. 2A,gas supply system240 can be coupled togas plenum242 usinginterface elements241, and thegas plenum242 can be coupled to gas distribution elements (245aand245b). The gas distribution elements (245aand245b) can provide different flow rates (247aand247b) of process gases to one or more areas of theprocessing region249. Process gas can, for example, include a mixture of gases such as Argon (Ar), Tetrafluoromethane (CF₄) and Oxygen (O₂), or Ar, C₄F₈and O₂for oxide etch applications, or other chemistries such as, for example, O₂/CO/Ar/C₄F₈, O₂/CO/Ar/C₅F₈, O₂/CO/Ar/C₄F₆, O₂/Ar/C₄F₆, N₂/H₂, and hydrogen bromide (HBr). Gas distribution elements (245aand245b) can be configured to reduce or minimize the introduction of contaminants towafer205 and can include a multi-orifice gas injection showerhead. For example, process gas can be supplied from thegas supply system240. In addition, gas distribution elements (245aand245b) can provide different process gases to different regions of theprocessing region249.

Thevacuum pumping system257 can include a turbo-molecular vacuum pump (TMP)258 capable of a pumping speed up to 5000 liters per second (and greater) and agate valve259 for controlling the chamber pressure. In conventional plasma processing devices utilized for dry plasma etch processes, a 1000 to 3000 liter per second TMP is generally employed. TMPs are useful for low pressure processing, typically less than 50 mTorr. At higher pressures, the TMP pumping speed falls off dramatically. For high pressure processing (i.e., greater than 100 mTorr), a mechanical booster pump and dry roughing pump can be used. Furthermore, a device for monitoring chamber pressure (not shown) may be coupled to theprocess chamber210. The pressure-measuring device can be, for example, a Type 628B Baratron absolute capacitance manometer commercially available from MKS Instruments, Inc. (Andover, Mass.).

As depicted inFIG. 2A, the contact-etch subsystem200A can include one ormore process sensors236 coupled to theprocess chamber210 to obtain process data, andcontroller295 can be coupled to theprocess sensors236 to receive process data. Theprocess sensors236 can include both sensors that are intrinsic to theprocess chamber210 and sensors extrinsic to theprocess chamber210. Intrinsic sensors can include those sensors pertaining to the functionality ofprocess chamber210 such as the measurement of the Helium backside gas pressure, Helium backside flow, electrostatic clamping (ESC) voltage, ESC current, wafer holder temperature (or lower electrode (LEL) temperature), coolant temperature, upper electrode (UEL) temperature, forward RF power, reflected RF power, RF self-induced DC bias, RF peak-to-peak voltage, chamber wall temperature, process gas flow rates, process gas partial pressures, chamber pressure, matching network settings, a focus ring thickness, RF hours, focus ring RF hours, and any statistic thereof. In addition, extrinsic sensors can include one or more optical devices for monitoring the light emitted from the plasma inprocessing region249 as shown inFIG. 2A. The optical devices can include an optical sensor that can be used as an End Point Detector (EPD) and can provide EPD data. For example, an Optical Emissions Spectroscopy (OES) sensor may be used. Theprocess sensors236 can include a current and/or voltage probe, a power meter, or spectrum analyzer. For example,process sensors236 can include a RF Impedance analyzer.

In some embodiments, the contact-etch subsystem200A can include one or more first contact-etch (CE)sensors234 coupled to processchamber210 to obtain first contact-etch performance data, andcontroller295 coupled to the first CE-sensors234 to receive the first IE-related performance data. In addition, the contact-etch subsystem200A can include one or more second contact-etch (CE)sensors223 coupled to thewafer holder220 to obtain second IE-related performance data, and anIE control unit222 can be coupled to the CE-sensors223 to process the IE-related performance data. For example, the measurement of an IE signal, such as a time trace of voltage or current, permits the transformation of the IE signal into frequency domain using discrete Fourier series representation (assuming a periodic signal). Thereafter, the Fourier spectrum (or for a time varying signal, the frequency spectrum) can be monitored and analyzed to characterize the state of the CE-plasma.

Controller295 includes a microprocessor, memory, and a digital I/O port (potentially including D/A and/or A/D converters) capable of generating control voltages sufficient to communicate and activate inputs to contact-etch subsystem200 as well as monitor outputs from contact-etch subsystem200. As shown inFIG. 2A,controller295 can be coupled to and exchange information withprocess chamber210,IE control unit222, backside gas delivery system (226 and227),temperature control system228,first RF generator230,impedance match network231, CE-sensors234,process sensors236,gas supply system240,gas plenum242, andvacuum pumping system257 using one ormore interfaces296. Programs stored in the memory can be utilized to interact with the aforementioned components of the contact-etch subsystem200A according to a stored IE-related process recipe.

In the exemplary embodiment shown inFIG. 2B, the contact-etch subsystem200B can be similar to the embodiment ofFIG. 2A and further comprise either a stationary, or mechanically or electrically rotatingmagnetic field system255, in order to potentially increase plasma density and/or improve plasma processing uniformity, in addition to those components described with reference toFIG. 2A. Moreover,controller295 can be coupled tomagnetic field system255 in order to regulate the speed of rotation and field strength. The design and implementation of a rotating magnetic field is known to those skilled in the art.

In the embodiment shown inFIG. 2C, the contact-etch subsystem200C can be similar to the embodiment ofFIG. 2A orFIG. 2B, and can further comprise anupper electrode274 to which RF power can be coupled fromRF generator270 through optionalimpedance match network272. A frequency for the application of RF power to theupper electrode274 can range from about 0.1 MHz to about 200 MHz. Additionally, a frequency for the application of power to thelower electrode232 can range from about 0.1 MHz to about 100 MHz. Moreover,controller295 can be coupled toRF generator270 andimpedance match network272 in order to control the application of RF power toupper electrode274. The design and implementation of an upper electrode is well known to those skilled in the art. Theupper electrode274 and thegas plenum242 can be coupled to each other as shown.

In the embodiment shown inFIG. 2D, the contact-etch subsystem200D can be similar to the embodiments ofFIGS. 2A and 2B, and can further comprise aninductive coil283 to which RF power can be coupled viaRF generator280 through optionalimpedance match network282. RF power can be inductively coupled frominductive coil283 through a dielectric window (not shown) toprocessing region249. A frequency for the application of RF power to theinductive coil283 can range from about 10 MHz to about 100 MHz. Similarly, a frequency for the application of power to thelower electrode232 can range from about 0.1 MHz to about 100 MHz. In addition, a slotted Faraday shield (not shown) can be employed to reduce capacitive coupling between theinductive coil283 and the contact-etch plasma. Moreover,controller295 can be coupled toRF generator280 andimpedance match network282 in order to control the application of power toinductive coil283.

In an alternate embodiment (not shown), is a “spiral” coil or “pancake” coil configuration may be used for the inductive coil. The design and implementation of an inductively coupled plasma (ICP) source, or transformer coupled plasma (TCP) source, is well known to those skilled in the art.

In the embodiment shown inFIG. 2E, the contact-etch subsystem200E can, for example, be similar to the embodiments ofFIGS. 2A,2B,2C, and2D, and can further comprise asecond RF generator250 configured to couple RF power towafer holder220 through another optionalimpedance match network251. A typical frequency for the application of RF power towafer holder220 can range from about 0.1 MHz to about 200 MHz for either thefirst RF generator230 or thesecond RF generator250 or both. The RF frequency for thesecond RF generator250 can be relatively greater than the RF frequency for thefirst RF generator230. Furthermore, the RF power to thewafer holder220 from thefirst RF generator230 can be amplitude modulated, the RF power to thewafer holder220 from thesecond RF generator250 can be amplitude modulated, or both RF powers can be amplitude modulated. Desirably, the RF power at the higher RF frequency is amplitude modulated. Moreover,controller295 can be coupled to thesecond RF generator250 andimpedance match network251 in order to control the application of RF power towafer holder220. The design and implementation of an RF system for a wafer holder is well known to those skilled in the art.

In the embodiment shown inFIG. 2F, the contact-etch subsystem200F can be similar to the embodiments ofFIGS. 2A and 2E, and can further comprise a surface wave plasma (SWP) source. The SWP source can comprise aslot antenna287, such as a radial line slot antenna (RLSA), to which microwave power is coupled viamicrowave generator285 through optionalimpedance match network286.

In the embodiment shown inFIG. 2G, the contact-etch subsystem200G can be similar to the embodiment ofFIG. 2C, and can further comprise a split upper electrode (277a,277b) to which RF power can be coupled fromRF generator275 through an impedance match network/power splitter276. A frequency for the application of RF power to the split upper electrode (277a,277b) can range from about 0.1 MHz to about 200 MHz. Additionally, a frequency for the application of power to thelower electrode232 can range from about 0.1 MHz to about 100 MHz. Moreover,controller295 can be coupled toRF generator275 and impedance match network/power splitter276 in order to control the application of RF power to split upper electrode (277a,277b). The power splitter and the split upper electrode can be designed and configured to provide different RF power levels to the center and the edge of theprocessing region249 to facilitate the generation and control of a contact-etch plasma inprocessing region249 adjacent a surface ofwafer205. The split upper electrode (270a,270b) and thegas plenum242 can be coupled to each other as shown, or other configurations may be used.

FIGS. 3A-3G show additional embodiments for contact-etch (CE) subsystems in accordance with embodiments of the invention.FIGS. 3A-3G illustrate exemplary contact-etch subsystems300A-300G that are similar to the exemplary contact-etch subsystems200A-200G shown inFIGS. 2A-2G, but contact-etch subsystems300A-300G include at least oneDC electrode392 and at least oneDC source390.

During patterned etching, a dry plasma etch process is often utilized, and the plasma is formed from a process gas by coupling electro-magnetic (EM) energy, such as radio frequency (RF) power, to the process gas in order to heat electrons and cause subsequent ionization and dissociation of the atomic and/or molecular composition of the process gas. In addition, negative, high voltage direct current (DC) electrical power can be coupled to the plasma processing system in order to create an energetic (ballistic) electron beam that strikes the wafer surface during a fraction of the RF cycle, i.e., the positive half-cycle of the coupled RF power. It has been observed that the ballistic electron beam can enhance the properties of the dry plasma etch process by, for example, improving the etch selectivity between the underlying thin film (to be etched) and the mask layer, reducing charging damage such as electron shading damage, etc. Additional details regarding the generation of a ballistic electron beam are disclosed in pending U.S. patent application Ser. No. 11/156,559, entitled “Plasma processing apparatus and method” and published as US patent application no. 2006/0037701 A1; the entire contents of which are herein incorporated by reference in their entirety. In general, the ballistic electron beam can be implemented within various types of plasma processing system, as shown inFIGS. 3A-3G.

A first exemplary contact-etch subsystem300A is shown inFIG. 3A, and the illustrated contact-etch subsystem300A includesprocess chamber310,wafer holder320, upon which awafer305 to be processed is affixed,gas supply system340, andvacuum pumping system357. For example,wafer holder320 can be coupled to and insulated fromprocess chamber310 usingbase325.Wafer305 can be, for example, a semiconductor wafer, a work piece, or a liquid crystal display (LCD). For example,process chamber310 can be configured to facilitate the generation of CE-plasma inprocessing region349 adjacent a surface ofwafer305, and the CE-plasma is formed via collisions between heated electrons and an ionizable gas. An ionizable gas or mixture of gases can be introduced from thegas supply system340, and process pressure is adjusted usingvacuum pumping system357. Desirably, the CE-plasma can be used to create materials specific to a predetermined material process, and to aid either the deposition of material towafer305 or the removal of material from the exposed surfaces ofwafer305. For example,controller395 can be used to controlvacuum pumping system357 andgas supply system340.

Wafer305 can be, for example, transferred into and out ofprocess chamber310 through a slot valve (not shown) and chamber feed-through (not shown) via robotic transfer system where it is received by wafer lift pins (not shown) housed withinwafer holder320 and mechanically translated by devices housed therein. After thewafer305 is received from transfer system, it is lowered to an upper surface ofwafer holder320.

For example,wafer305 can be affixed to thewafer holder320 via an electrostatic clamping system (not shown). Thewafer holder320 can includetemperature control elements329 that can be coupled to atemperature control system328. For example, thetemperature control elements329 can include resistive heating elements, or thermo-electric heaters/coolers. Backside gas can be delivered to the backside of the wafer via a dual (center/edge) backside gas delivery system (326 and327) to improve the gas-gap thermal conductance betweenwafer305 andwafer holder320. A dual (center/edge) backside gas delivery system (326 and327) can be utilized when additional temperature control of the wafer is required at elevated or reduced temperatures. For example, temperature control of thewafer305 can be useful at temperatures in excess of the steady-state temperature achieved due to a balance of the heat flux delivered to thewafer305 from the plasma and the heat flux removed fromwafer305 by conduction to thewafer holder320.

As shown inFIG. 3A,wafer holder320 includes alower electrode332 through which Radio Frequency (RF) power can be coupled to plasma inprocessing region349. For example,lower electrode332 can be electrically biased at an RF voltage via the transmission of RF power fromRF generator330 throughimpedance match network331 tolower electrode332. The RF bias can serve to heat electrons to form and maintain the CE-plasma. A typical frequency for the RF bias can range from 1 MHz to 100 MHz and is preferably 13.56 MHz.

Alternatively, RF power may be applied to thelower electrode332 at multiple frequencies. Furthermore,impedance match network331 serves to maximize the transfer of RF power to CE-plasma inprocess chamber310 by minimizing the reflected power. Various match network topologies and automatic control methods can be utilized.

With continuing reference toFIG. 3A,gas supply system340 can be coupled togas plenum342 usinginterface elements341, and thegas plenum342 can be coupled to gas distribution elements (345aand345b). The gas distribution elements (345aand345b) can provide different flow rates (347aand347b) of process gases to one or more areas of theprocessing region349. Process gas can, for example, include a mixture of gases such as Argon (Ar), Tetrafluoromethane (CE) and Oxygen (O₂), or Ar, C₄F₈and O₂for oxide etch applications, or other chemistries such as, for example, O₂/CO/Ar/C₄F₈, O₂/CO/Ar/C₅F₈, O₂/CO/Ar/C₄F₆, O₂/Ar/C₄F₆, N₂/H₂, and hydrogen bromide (HBr). Gas distribution elements (345aand345b) can be configured to reduce or minimize the introduction of contaminants towafer305 and can include a multi-orifice gas injection showerhead. For example, process gas can be supplied from thegas supply system340.

Thevacuum pumping system357 can include a turbo-molecular vacuum pump (TMP)358 capable of a pumping speed up to 5000 liters per second (and greater) and agate valve359 for controlling the chamber pressure. In conventional plasma processing devices utilized for dry plasma etch processes, a 1000 to 3000 liter per second TMP is generally employed. TMPs are useful for low pressure processing, typically less than 50 mTorr. At higher pressures, the TMP pumping speed falls off dramatically. For high pressure processing (i.e., greater than 100 mTorr), a mechanical booster pump and dry roughing pump can be used. Furthermore, a device for monitoring chamber pressure (not shown) may be coupled to theprocess chamber310. The pressure-measuring device can be, for example, a Type 628B Baratron absolute capacitance manometer commercially available from MKS Instruments, Inc. (Andover, Mass.).

As depicted inFIG. 3A, the contact-etch subsystem300A can include one ormore process sensors336 coupled to processchamber310 to obtain performance data, andcontroller395 coupled to theprocess sensors336 to receive performance data. Theprocess sensors336 can include both sensors that are intrinsic to theprocess chamber310 and sensors extrinsic to theprocess chamber310. Intrinsic sensors can include those sensors pertaining to the functionality ofprocess chamber310 such as the measurement of the Helium backside gas pressure, Helium backside flow, electrostatic clamping (ESC) voltage, ESC current, wafer holder temperature (or lower electrode (LEL) temperature), coolant temperature, upper electrode (UEL) temperature, forward RF power, reflected RF power, RF self-induced DC bias, RF peak-to-peak voltage, chamber wall temperature, process gas flow rates, process gas partial pressures, chamber pressure, matching network settings, a focus ring thickness, RF hours, focus ring RF hours, and any statistic thereof. In addition, extrinsic sensors can include one or more optical devices for monitoring the light emitted from the plasma inprocessing region349 as shown inFIG. 3A. The optical devices can include an optical sensor that can be used as an End Point Detector (EPD) and can provide EPD data. For example, an Optical Emissions Spectroscopy (OES) sensor may be used. Theprocess sensors336 can include a current and/or voltage probe, a power meter, or spectrum analyzer. For example,process sensors336 can include a RF Impedance analyzer.

In some embodiments, the contact-etch subsystem300A can include one or more ion energy (IE)sensors334 coupled to processchamber310 to obtain IE-related performance data, andcontroller395 coupled to the CE-sensors334 to receive IE-related performance data. In addition, theCE subsystem300A can include one or more ion energy (IE)sensors323 coupled to thewafer holder320 to obtain IE-related performance data, and anIE control unit322 can be coupled to the CE-sensors323 to process the IE-related performance data. For example, the measurement of an IE signal, such as a time trace of voltage or current, permits the transformation of the IE signal into frequency domain using discrete Fourier series representation (assuming a periodic signal). Thereafter, the Fourier spectrum (or for a time varying signal, the frequency spectrum) can be monitored and analyzed to characterize the state of the CE-plasma.

Controller395 includes a microprocessor, memory, and a digital I/O port (potentially including D/A and/or A/D converters) capable of generating control voltages sufficient to communicate and activate inputs to the CE subsystems (300A-300G) as well as monitor outputs from the CE subsystems (300A-300G). As shown inFIG. 3A,controller395 can be coupled to and exchange information withprocess chamber310,IE control unit322, backsidegas delivery system326,temperature control system328,first RF generator330,impedance match network331, CE-sensors334,process sensors336,gas supply system340,gas plenum342, andvacuum pumping system357 using one ormore interfaces396. Programs stored in the memory can be utilized to interact with the aforementioned components of theCE subsystem300A according to a stored IE-related process recipe.

In the exemplary embodiment shown inFIG. 3B, theCE subsystem300B can be similar to the embodiment ofFIG. 3A and further comprise either a stationary, or mechanically or electrically rotatingmagnetic field system355, in order to potentially increase plasma density and/or improve plasma processing uniformity, in addition to those components described with reference toFIG. 3A. Moreover,controller395 can be coupled tomagnetic field system355 in order to regulate the speed of rotation and field strength. The design and implementation of a rotating magnetic field is known to those skilled in the art. In the embodiment shown inFIG. 3C, theCE subsystem300C can be similar to the embodiment ofFIG. 3A orFIG. 3B, and can further comprise anupper electrode374 to which RF power can be coupled fromRF generator370 through optionalimpedance match network372. A frequency for the application of RF power to theupper electrode374 can range from about 0.1 MHz to about 200 MHz. Additionally, a frequency for the application of power to thelower electrode332 can range from about 0.1 MHz to about 100 MHz. Moreover,controller395 can be coupled toRF generator370 andimpedance match network372 in order to control the application of RF power toupper electrode374. The design and implementation of an upper electrode is well known to those skilled in the art. Theupper electrode374 and thegas plenum342 can be coupled to each other as shown.

In the embodiment shown inFIG. 3D, theCE subsystem300D can be similar to the embodiments ofFIGS. 3A and 3B, and can further comprise aninductive coil383 to which RF power can be coupled viaRF generator380 through optionalimpedance match network382. RF power can be inductively coupled frominductive coil383 through a dielectric window (not shown) toprocessing region349. A frequency for the application of RF power to theinductive coil383 can range from about 10 MHz to about 100 MHz. Similarly, a frequency for the application of power to thelower electrode332 can range from about 0.1 MHz to about 100 MHz. In addition, a slotted Faraday shield (not shown) can be employed to reduce capacitive coupling between theinductive coil383 and the CE-plasma. Moreover,controller395 can be coupled toRF generator380 andimpedance match network382 in order to control the application of power toinductive coil383.

In an alternate embodiment (not shown), is a “spiral” coil or “pancake” coil configuration may be used for the inductive coil. The design and implementation of an inductively coupled plasma (ICP) source, or transformer coupled plasma (TCP) source, is well known to those skilled in the art.

In the embodiment shown inFIG. 3E, theCE subsystem300E can, for example, be similar to the embodiments ofFIGS. 3A,3B,3C, and3D, and can further comprise asecond RF generator350 configured to couple RF power towafer holder320 through another optionalimpedance match network351. A typical frequency for the application of RF power towafer holder320 can range from about 0.1 MHz to about 200 MHz for either thefirst RF generator330 or thesecond RF generator350 or both. The RF frequency for thesecond RF generator350 can be relatively greater than the RF frequency for thefirst RF generator330. Furthermore, the RF power to thewafer holder320 from thefirst RF generator330 can be amplitude modulated, the RF power to thewafer holder320 from thesecond RF generator350 can be amplitude modulated, or both RF powers can be amplitude modulated. Desirably, the RF power at the higher RF frequency is amplitude modulated. Moreover,controller395 can be coupled to thesecond RF generator350 andimpedance match network351 in order to control the application of RF power towafer holder320. The design and implementation of an RF system for a wafer holder is well known to those skilled in the art.

In the embodiment shown inFIG. 3F, theCE subsystem300F can be similar to the embodiments ofFIGS. 3A and 3E, and can further comprise a surface wave plasma (SWP) source. The SWP source can comprise aslot antenna387, such as a radial line slot antenna (RLSA), to which microwave power is coupled viamicrowave generator385 through optionalimpedance match network386.

In the embodiment shown inFIG. 3G, theCE subsystem300G can be similar to the embodiment ofFIG. 3C, and can further comprise a split upper electrode (377a,377b) to which RF power can be coupled fromRF generator375 through an impedance match network/power splitter376. A frequency for the application of RF power to the split upper electrode (377a,377b) can range from about 0.1 MHz to about 200 MHz. Additionally, a frequency for the application of power to thelower electrode332 can range from about 0.1 MHz to about 100 MHz. Moreover,controller395 can be coupled toRF generator375 and impedance match network/power splitter376 in order to control the application of RF power to split upper electrode (377a,377b). The power splitter and the split upper electrode can be designed and configured to provide different RF power levels to the center and the edge of theprocessing region349 to facilitate the generation and control of a CE-plasma inprocessing region349 adjacent a surface ofwafer305. The split upper electrode (370a,370b) and thegas plenum342 can be coupled to each other as shown, or other configurations may be used.

TheDC electrode392 shown in the CE subsystems (300A-300G) may comprise a silicon-containing material and/or a doped silicon-containing material. TheDC source390 can include a variable DC power supply. Additionally, theDC source390 can include a bipolar DC power supply. TheDC source390 can further include a system configured to perform at least one of monitoring, adjusting, or controlling the polarity, current, voltage, and/or on/off state of theDC source390. Once plasma is formed, theDC source390 facilitates the formation of a ballistic electron beam. An electrical filter may be utilized to de-couple RF power from theDC source390.

For example, the DC voltage applied toDC electrode392 byDC source390 may range from about −2000 volts (V) to about 1000 V. Desirably, the absolute value of the DC voltage has a value equal to or greater than about 100 V, and more desirably, the absolute value of the DC voltage has a value equal to or greater than about 500 V. Additionally, it is desirable that the DC voltage has a negative polarity. Furthermore, it is desirable that the DC voltage is a negative voltage having an absolute value greater than the self-bias voltage.

In alternate embodiments, a Chemical Oxide Removal (COR) subsystem (not shown) can be used to remove or trim oxidized poly-Si material. In addition, the COR subsystem may be used to remove or trim an oxide masking layer. For example, a COR subsystem can comprise a chemical treatment module (not shown) for chemically treating exposed surface layers, such as oxide surface layers, on a wafer, whereby adsorption of the process chemistry on the exposed surfaces affects chemical alteration of the surface layers. Additionally, the COR subsystem can comprise a thermal treatment module (not shown) for thermally treating the wafer, whereby the wafer temperature is elevated in order to desorb (or evaporate) the chemically altered exposed surface layers on the wafer.

FIG. 4 shows a simplified block diagram of an exemplary contact-etch (CE) Multi-Input/Multi-Output (CE-MIMO) model optimization and control methodology in accordance with embodiments of the invention. In the illustrated MIMO model methodology, exemplary images of a portion of a first patternedgate stack401 and apost-processed gate stack405 is shown. The firstpatterned gate stack401 can include one or more first contact layer features402 and one or more second contact layer features403. The firstpatterned gate stack401 can be characterized using a first set of CE-relatedparameters404 that can include center/edge (C/E) CE data, stack data C/E, CD data C/E, SWA data C/E, IEA data C/E, and EEDf data C/E. Alternatively, a different set of CE-related parameters may be used. Thepost-processed gate stack405 can include one or more previously-filled contacts/vias406, one or more first post-processed contact layer features402′ and one or more second post-processed contact layer features403′. Thepost-processed gate stack405 can be characterized using CE-related output data408 that can include center/edge (C/E) CE data, stack data C/E, CD data C/E, SWA data C/E, IEA data C/E, and EEDf data C/E. Alternatively, a different set of IC-related post-processing data may be used.

In the illustrated methodology, a pre-processing integrated metrology (IM) and/or inspect process/tool (Pre-IM/Inspect)model410 can be coupled to one or more contact-etch (CE)sequence models415. One or more of the (DPCE)sequence models415 can be coupled to one or more contact-etch (CE)procedure models420. One or more of theCE procedure models420 can be coupled to one or more CE data updatemodels425. One or more of the CE data updatemodels425 can be coupled to one or more post-processing integrated metrology (IM) and/or inspect process/tool (Post-IM/Inspect)model430.

The (Pre-IM/Inspect)model410 can receiveinput data409, can providefirst output data411 to theCE sequence model415, and can provide first feed forwarddata412 to the CE-related feedforward model435. TheDPCE sequence models415 can receivefirst output data411, can providesecond output data416 to theCE procedure model420, and can provide second feed forwarddata417 to the CE-related feedforward model435. TheCE procedure model420 can receive thesecond output data416, can receive third feed forwarddata436, can receivefeedback data438, and can send CE-procedure data421 to the CE data updatemodels425. The CEdata update model425 can receive CE-procedure data421, can provideupdate data426 to the (Post-IM/Inspect)model430, and can providefirst feedback data427 to the CE-relatedfeedback model437. The (Post-IM/Inspect)model430 can receive theupdate data426, can providethird output data431, and can providesecond feedback data432 to the CE-relatedfeedback model437. The CE-related feedforward model435 can receive first feed forwarddata412, can receive second feed forwarddata417, and can provide the third feed forwarddata436, and the CE-relatedfeedback model437 can receivefirst feedback data427, can receivesecond feedback data432, and can provide thethird feedback data438.

In some examples, theinput data409 can include CD data, SWA data, thickness data, CE data, EEDf data, DPCE data, contact data or transistor stack data, or any combination thereof, and thefirst output data411 and the first feed forwarddata412 can include CD data, SWA data, ODP data, inspection data, thickness data, CE data, EEDf data, DPCE data, or etched contact data, or any combination thereof. Thesecond output data416 and the second feed forwarddata417 can include recipe data, CD data, SWA data, ODP data, inspection data, thickness data, CE data, EEDf data, or gate data, or any combination thereof, and the CE-procedure data421 can include result data, CD data, SWA data, ODP data, inspection data, thickness data, CE data, EEDf data, or gate data, or any combination thereof. Theupdate data426 and thefirst feedback data427 can include recipe data, CE data, EEDf data, ODP data, inspection data, thickness data, DPCE data, EEDf data, or contact data, or any combination thereof, and thethird output data431 and thesecond feedback data432 can include result data, CD data, SWA data, ODP data, inspection data, thickness data, CE data, EEDf data, or contact data, or any combination thereof. The third feed forwarddata436 can include wafer-to-wafer feed-forward data (W2W FF) and within-wafer feed-forward data (WiW FF), and thethird feedback data438 can include wafer-to-wafer feedback data (W2W FB) and within-wafer feedback data (WiW FB). In addition, one or more of the models (410,415,420,425, and430) can be used to control thepost-processed gate stack405 and/or the etchedcontacts406 on a wafer-to-wafer (W2W) basis and/or to control thepost-processed gate stack405 and/or the etchedcontacts406 on a Within-Wafer (WiW) basis.

Data items413 can be sent to afirst calculation element440 that can be used to calculate some of the CE data, the EEDf data, the DPCE data, the CD data, the SWA data, and/or other gate stack data at the center of the wafer and at the edge of the wafer. For example, thefirst calculation element440 can be used to calculate the CE-related bias at the center of the wafer and at the edge of the wafer. A first set oftarget parameters441 can be provided to thefirst calculation element440, and a first set offilter outputs471 can be provided to thefirst calculation element440.Output data items442 from thefirst calculation element440 can be provided to one or moreMIMO model Optimizers450.

One or more of theMIMO model Optimizers450 can be provided with one or more CE-relatedconstraint parameters451 that can include tool limits, recipe limits, and/or time limits that are CE-related. For example, the CE-relatedconstraint parameters451 can include step-based wafer temperature limits or process gas limits during a contact-etch procedure. One or more of theMIMO model Optimizers450 can determine one or more sets of recipe/chamber parameters456 that can be sent to one or more of the tool controller/models (410,415,420,425, and430).

One or more of the tool controller/models (410,415,420,425, and430) can be used to calculate predictedCE values457 that can include one or more predicted etch biases, one or more predicted SWA biases, one or more predicted step times for one or more CE recipes, and one or more predicted process gas flows for one or more CE-recipes.

One or more of the (Post-IM/Inspect)model430 can provide one or moreactual outputs433 to one ormore comparison elements460, and one or more of theactual outputs433 can be compared to one of more of the predicted CE values457. One or more of the error values465 from one or more of thecomparison elements460 can be provided to one or more of the EWMA filters470.

One or more of the EWMA filters470 can provide one or more firstfiltered outputs471 to thefirst calculation element440, and one or more of the EWMA filters470 can provide one or more secondfiltered outputs472 to one or more of the weighting controller/models480. Each of the EWMA filters470 can filter and provide feedback data for a single parameter or error value. Alternatively, each of the EWMA filters470 can filter and provide feedback data for multiple parameters or error values. One or more of the weighting controller/models480 can receive one or moretarget data items445 and one or morefeedback data items455 from one or more of theMIMO model Optimizers450. In addition, one or more of the weighting controller/models480 can provide one or more dynamically varying weighting inputs481 to one or more of theMIMO model Optimizers450. The concept of using dynamic weightings based on the feedback error is to force the optimizer to prioritize the weightings (rebalance) with a goal of better control of the most important CVs—automation of a manual tuning of a control system in runtime.

In some embodiments, the manipulated variables and/or the disturbance variables used for control can include a calculated value that can be dynamically modeled and updated during the runtime processing by the following method: 1) the modeling procedure can start with a basic model relationship that “pairs” CE-sensor data to a controlled variable (CV). For example, the amount of atomic O or F can be calculated by using process gas data from the CE-sensor or a process sensor, and the amount of atomic O or F that is consumed can be used to predict a CD or a SWA. This could be a feedback update loop, or a real-time adjustment during an etch step. 2) After a wet clean is performed, the first patterned gate stacks processed during conditioning or production would be used to calculate and update this trace gas model. 3) The Relative Gain Array (RGA) method can be used at run-time with production patterned wafers to evaluate when to use the CE-sensor data vs. CV feedback in place of just calculating a value. The RGA matrix for the given CV value would be re-evaluated to determine if the value of the sensor based MV is stronger than the litho incoming CV for use as a real-time CV value. 4) In addition, center to edge sensor detection using OES signal—The rate of change can also be used as an example commonly understood to adjust the over etch recipe settings to improve the uniformity (correct for the non-uniformity of the previous steps etch, by adjusting the over-etch steps center to edge knobs, such as O₂flow, temp, top power, pressure. IM CV would be the film thickness of incoming wafers to separate incoming—say BARC thickness from etch rate of the current chamber center to edge.

In some embodiments, the control variables associated with various patterned wafers created by the contact-etch procedures can be center CD and SWA values, middle CD and SWA values, edge CD and SWA values, and extreme edge CD and SWA values, and this can require a total of eight IM measurements at four or more sites on the wafer. The pre- and post-IM measurements can be performed using dynamic sampling.

In other embodiments, the manipulated variables can include back-side gas flows to one or more zones in the wafer holder, and the back-side gas flows can be dynamically controlled during processing to provide dynamic backside gas temperature control for improved within-wafer process uniformity by adjusting wafer areas that are non-radial in nature based on incoming CV requirements.

In still other embodiments, the manipulated variables can include flow rates for edge gas injection flow rates. This approach could also be used to reduce the starvation problem at the wafer edge, and make the edge starvation a controllable variable based on the incoming signature and chamber state.

In some CE-MIMO models, the interaction terms can be updated between lots during an offline triggered calculation update procedure. For example, the cross term calculation update can be triggered by checking the sensitivity of the current system to changes in the cross terms, and by running a set of pre-defined delta offsets to see if adjusting the cross terms would have improved the average control. RGA can be used in this calculation, and the trigger events can be used to perform adaptive feedback updates for the CE-MIMO model. For example, adaptive feedback can be used when copying the CE-MIMO model from chamber to chamber and allowing the CE-MIMO model to adapt to the new chamber behavior. Another use arises when a new product is released and the old product equation can be used to start the model, then after so many wafers the model update is triggered and a new model is adjusted, and the resulting model can them be used and monitored for performance.

FIGS.5 and5′ illustrate exemplary views of a first Double-Pattern-Contact-Etch (DPCE) processing sequence for creating first double pattern (DP) features in accordance with embodiments of the invention. For example, one or more first Litho-Etch-Litho-Etch (LELE) processing sequences can be performed. InFIG. 5, two exemplary patterned wafers (500aand500b) are shown having exemplary transistor stacks (501a,502a,501b, and502b) thereon that can be created using a first DPCE processing sequence, but this is not required for the invention. In FIG.5′, two other exemplary patterned wafers (500cand500d) are shown having exemplary transistor stacks (501c,502c,501d, and502d) thereon that can be created using a second DPCE processing sequence, but this is not required for the invention. Alternatively, a different number of patterned wafers with different transistor configurations may be used.

FIG. 5 illustrates a firstpatterned wafer500acomprising afirst transistor stack501aand asecond transistor stack502a, where thefirst transistor stack501acan include a nFET device, and thesecond transistor stack502acan include a pFET device. Alternatively, other devices may be illustrated.

The firstpatterned wafer500acan include afirst substrate layer510a, afirst isolation layer520a, a first under-layer530a, and a second under-layer535a. For example, thefirst substrate layer510acan include a semiconductor material; thefirst isolation layer520acan include dielectric or metallic material; and the under-layers (530aand535a) can include TiN. Thefirst substrate layer510acan include a first shallow trench isolation (STI)region515a, and thefirst STI region515acan include silicon oxide (SiO₂), silicon nitride (SiN), or silicon oxynitride (SiON).

Thefirst transistor stack501acan be covered/protected by a firsthard mask layer540a, andsecond transistor stack502acan be covered by a secondhard mask layer545a. For example, firsthard mask layer540aand the secondhard mask layer545acan include SiO₂and/or SiN. An inter-layer dielectric (ILD)layer565ais shown covering the firsthard mask layer540aand the secondhard mask layer545a, and theILD layer565acan include a low-k dielectric material. A firstetch mask layer570acan be configured on top of theILD layer565a, and the firstetch mask layer570acan include a plurality of first etch mask features571a, and the first etch mask features571acan havewidths572athat can vary from about 10 nm to about 100 nm. For example, one or more first litho-related sequences can be performed to create the first etch mask features571ain the firstetch mask layer570a. In addition, the firstetch mask layer570acan include at least one radiation-sensitive material, at least one ARC material, and/or at least one resist material.

Thefirst transistor stack501acan include a firstgate dielectric layer550a, a firstcontact metal layer551a, a secondcontact metal layer552a,first capping layer553a, a firstmetal gate layer554a, a firstdummy gate layer556a, and a first gatehard mask layer558a. The firstgate dielectric layer550acan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer551aand/or the secondcontact metal layer552acan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. Thefirst capping layer553acan include a work function tuning material. The firstmetal gate layer554acan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi₂, TiN, TaN, WN, or ZrSi₂. The firstdummy gate layer556acan include Poly-Si material.

Thesecond transistor stack502acan include a secondgate dielectric layer560a, a firstcontact metal layer561a, a secondcontact metal layer562a, a secondmetal gate layer564a, a seconddummy gate layer566a, a second gatehard mask layer568a, andsecond spacers569a. The secondgate dielectric layer560acan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer561aand/or the secondcontact metal layer562acan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. The secondmetal gate layer564acan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi₂, TiN, TaN, WN, or ZrSi₂. The seconddummy gate layer566acan include Poly-Si material.

InFIG. 5, a firstinput data model580 is illustrated, and a first set of input data can be obtained when the firstinput data model580 is executed. The first input data can include real-time and/or historical CE-related data for the firstpatterned wafer500a. In some examples, the first input data can include CD data, SWA data, thickness data, IE data, EEDf data, ODP data, inspection data, thickness data, IE data, EEDf data, or gate data, or any combination thereof.

A first select contact-etch CE-MIMO model581 is illustrated, and a first contact-etch procedure can be selected using the first select CE-MIMO model581, and the first select CE-MIMO model581 can exchange Measured Variable (MV) data using transfer means590, can exchange Disturbance Variable (DV) data using transfer means591, and can exchange Controlled Variable (CV) data using transfer means592. For example, the first select CE-MIMO model581 can create and/or use first contact-etch related data associated with the firstpatterned wafer500a, and the first contact-etch related data can be fed forward and/or fed back using transfer means (590,591, and/or592).

When the first select CE-MIMO model581 is executed, a first contact-etch procedure can be selected using controller (295 shown inFIGS. 2A-2G) and/or controller (395 shown inFIGS. 3A-3G). In some examples, the controllers (295 and/or395) can use first contact-etch related library data for the firstpatterned wafer500aand/or the secondpatterned wafer500b. The first contact-etch related library data for the firstpatterned wafer500acan include historical contact-etch procedure data collected using one or more CE-sensors (223 and/or234 shown inFIGS. 2A-2G) and/or CE-sensors (323 and/or334 shown inFIGS. 3A-3G), when the first transistor stacks501awere being created on the firstpatterned wafer500a. The first CE-related library data for the secondpatterned wafer500bcan include second historical contact-etch procedure data collected using one or more CE-sensors (223 and/or234 shown inFIGS. 2A-2G) and/or CE-sensors (323 and/or334 shown inFIGS. 3A-3G), when the secondpatterned wafers500bwere previously created.

InFIG. 5, a first CE-MIMO model582 is illustrated, and when the first CE-MIMO model582 is executed, the selected first contact-etch procedure can be performed using one or more of the etch subsystems described herein inFIGS. 2A-2G andFIGS. 3A-3G. When contact-etch procedures are performed, one or more sets of process parameters can be determined, updated, and/or verified. For example, the first CE-MIMO model582 can create and exchange first contact-etch MV data using transfer means590, can create and exchange first contact-etch DV data using transfer means591, and can create and exchange first contact-etch CV data using transfer means592 with the other MIMO models (580,581, and583). In addition, the first CE-MIMO model582 can include first MV process data, first DV process data, and first CV process data associated with the first contact-etch procedure, with the firstpatterned wafer500a, and/or with the secondpatterned wafer500b.

In some examples, the firstpatterned wafer500acan be etched using the first contact-etch procedure to create a secondpatterned wafer500b. Alternatively, other patterned wafers may be created.

With continuing reference toFIG. 5, a secondpatterned wafer500bcomprising afirst transistor stack501band asecond transistor stack502bis shown, thefirst transistor stack501bcan include a nFET device, and thesecond transistor stack502bcan include a pFET device. Alternatively, other devices may be illustrated.

The secondpatterned wafer500bcan include afirst substrate layer510b, afirst isolation layer520b, a first under-layer530b, and a second under-layer535b. For example, thefirst substrate layer510bcan include a semiconductor material; thefirst isolation layer520bcan include dielectric or metallic material; and the under-layers (530band535b) can include TiN. Thefirst substrate layer510bcan include afirst STI region515b, and thefirst STI region515bcan include SiO₂, SiN, and/or SiON.

Thefirst transistor stack501bcan be covered/protected by a firsthard mask layer540b, andsecond transistor stack502bcan be covered by a secondhard mask layer545b. For example, firsthard mask layer540band the secondhard mask layer545bcan include SiO₂and/or SiN. An inter-layer dielectric (ILD)layer565bis shown covering the firsthard mask layer540band the secondhard mask layer545b, and theILD layer565bcan include a low-k dielectric material.

A first contact-etch masking layer570bcan be configured on top of theILD layer565b, and the first contact-etch masking layer570bcan include a plurality of previously-created first etch mask features571a, and one or more first litho procedures in a DPCE processing sequence can have been performed to create first etch mask features571ain the first contact-etch masking layer570b. For example, a first contact-etch procedure in the DPCE processing sequence can use the first etch mask features571ato create the first contact-etch vias575b, and the first etch mask features575bcan havewidths576bthat can vary from about 10 nm to about 100 nm. In addition, the first contact-etch masking layer570bcan include at least one radiation-sensitive material, at least one ARC material, and/or at least one resist material.

Thefirst transistor stack501bcan include a firstgate dielectric layer550b, a firstcontact metal layer551b, a secondcontact metal layer552b,first capping layer553b, a firstmetal gate layer554b, a firstdummy gate layer556b, a first gatehard mask layer558b, andfirst spacers559b. The firstgate dielectric layer550bcan include high-k dielectric material, such as hafnium oxide (Hf_O2). The firstcontact metal layer551band/or the secondcontact metal layer552bcan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. Thefirst capping layer553bcan include a work function tuning material. The firstmetal gate layer554bcan be a very thin layer (10 angstrom to 400 angstrom) and can include MoS_i2, NiS_i2, TaS_i2, TiN, TaN, WN, or ZrS_i2. The firstdummy gate layer556bcan include Poly-Si material.

Thesecond transistor stack502bcan include a secondgate dielectric layer560b, a firstcontact metal layer561b, a secondcontact metal layer562b, a secondmetal gate layer564b, a seconddummy gate layer566b, a second gatehard mask layer568bandsecond spacers569b. The secondgate dielectric layer560bcan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer561band/or the secondcontact metal layer562bcan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. The secondmetal gate layer564bcan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi2, TiN, TaN, WN, or ZrSi₂. The seconddummy gate layer566bcan include Poly-Si material.

In some embodiments, when the first contact-etch procedure is performed a firstpatterned wafer500acan be positioned on a wafer holder (220 shown inFIGS. 2A-2G) and/or wafer holder (320 shown inFIGS. 3A-3G) and a first contact-etch plasma can be created in the process chamber (210 shown inFIGS. 2A-2G) and/or process chamber (310 shown inFIGS. 3A-3G) and a first IEO-etch procedure can be performed.

During the first contact-etch procedure, first CE-sensor data can be collected using one or more CE-sensors (223 and/or234 shown inFIGS. 2A-2G) and/or CE-sensors (323 and/or334 shown inFIGS. 3A-3G), and controller (295 shown inFIGS. 2A-2G) and/or controller (395 shown inFIGS. 3A-3G) can compare the first CE-sensor data to historical CE-sensor data; and can store the first CE-sensor data. For example, the first process data can be collected using the process sensors (236 shown inFIGS. 2A-2G) and/or process sensors (336 shown inFIGS. 3A-3G) during the first contact-etch procedure.

When a first DPCE processing sequence includes additional CE-related procedures, the additional CE-related procedures can be performed using one or more of the subsystems (110,120,130,140,150,160, and170) shown inFIG. 1.

In some embodiments, the first DPCE processing sequence can include a first contact-etch procedure for a first hard mask (Si-ARC) layer, second contact-etch procedure for an IDL layer, and third contact-etch procedure for a second hard mask TEOS layer. In some examples, the first DPCE processing sequence can also include ashing procedures, cleaning procedures, and/or CMP procedures. In other examples, the first DPCE processing sequence can include (Ion Energy) IE-optimized etch procedures, IE-related metrology procedures, IE-sensor wafer measurement procedures, and/or IE-related inspection procedures.

Still referring toFIG. 5, a firstoutput data model583 is illustrated, and a first set of output data can be analyzed when the firstoutput data model583 is executed. The first output data can include real-time and/or historical CE-related data. For example, the firstoutput data model583 can create and exchange output MV data using transfer means590, can create and exchange output DV data using transfer means591, and can create and exchange output CV data using transfer means592 with the other MIMO models (580,581, and582). In addition, the firstoutput data model583 can analyze process data and/or CE-sensor data associated with the contact-etch procedures, and the analyzed process data and/or the analyzed CE-sensor data can be fed forward and/or fed back using transfer means (590,591, and/or592).

When the firstoutput data model583 is executed, update and/or verification procedures can be performed for the first contact-etch procedure and first DPCE processing sequence. For example, update procedures can be performed to update and/or verify the first process parameters, CE-sensor data, process data, and/or CE-related library data. The firstoutput data model583 can exchange updated and/or verified CE-MV data using transfer means590, can exchange updated and/or verified CE-DV data using transfer means591, and can exchange updated and/or verified CE-CV data using transfer means592 with the other CE-MIMO models (580,581, and582). During process development, DOE techniques can be used to examine the preliminary set of models (580-583) and to develop a reduced set of CE-MIMO models.

FIG.5′ illustrates a thirdpatterned wafer500ccomprising afirst transistor stack501cand asecond transistor stack502c, where thefirst transistor stack501ccan include a nFET device, and thesecond transistor stack502ccan include a pFET device. Alternatively, other devices may be illustrated. In addition, a previously-filled contact/via575b′ is shown that can include one or more metallic and/or filler materials.

The firstpatterned wafer500ccan include afirst substrate layer510c, afirst isolation layer520c, a first under-layer530c, and a second under-layer535c. For example, thefirst substrate layer510ccan include a semiconductor material; thefirst isolation layer520ccan include dielectric or metallic material; and the under-layers (530cand535c) can include TiN. Thefirst substrate layer510ccan include a first shallow trench isolation (STI)region515c, and thefirst STI region515ccan include SiO₂, SiN, and/or SiON.

Thefirst transistor stack501ccan be covered/protected by a firsthard mask layer540c, andsecond transistor stack502ccan be covered by a secondhard mask layer545c. For example, firsthard mask layer540cand the secondhard mask layer545ccan include SiO₂and/or SiN. An inter-layer dielectric (ILD)layer565cis shown covering the firsthard mask layer540cand the secondhard mask layer545c, and theILD layer565ccan include a low-k dielectric material.

A secondetch mask layer570ccan be configured on top of theILD layer565c, and a plurality of second etch mask features571ccan be configured in the secondetch mask layer570c, and the second etch mask features571ccan havewidths572cthat can vary from about 10 nm to about 100 nm. For example, one or more second litho-related sequences in the first DPCE processing sequence can be performed to create the second etch mask features571cin the secondetch mask layer570c. In addition, the secondetch mask layer570ccan include at least one radiation-sensitive material, at least one ARC material, and/or at least one resist material.

Thefirst transistor stack501ccan include a firstgate dielectric layer550c, a firstcontact metal layer551c, a secondcontact metal layer552c,first capping layer553c, a firstmetal gate layer554c, a firstdummy gate layer556c, a first gatehard mask layer558c, andfirst spacers559c. The firstgate dielectric layer550ccan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer551cand/or the secondcontact metal layer552ccan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. Thefirst capping layer553ccan include a work function tuning material. The firstmetal gate layer554ccan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi2, TiN, TaN, WN, or ZrSi₂. The firstdummy gate layer556ccan include Poly-Si material.

Thesecond transistor stack502ccan include a secondgate dielectric layer560c, a firstcontact metal layer561c, a secondcontact metal layer562c, a secondmetal gate layer564c, a seconddummy gate layer566c, a second gatehard mask layer568c, andsecond spacers569c. The secondgate dielectric layer560ccan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer561cand/or the secondcontact metal layer562ccan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. The secondmetal gate layer564ccan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi2, TiN, TaN, WN, or ZrSi₂. The seconddummy gate layer566ccan include Poly-Si material.

In FIG.5′, a secondinput data model580′ is illustrated, and a second set of input data can be obtained when the secondinput data model580′ is executed. The second input data can include real-time and/or historical contact-etch related data for one or more of the patterned wafers (500a,500b, and500c). A second select CE-MIMO model581′ is illustrated, and a second contact-etch (CE) procedure can be selected using the second select CE-MIMO model581′, and the second select CE-MIMO model581′ can exchange second MV′ data using transfer means590, can exchange second DV′ data using transfer means591, and can exchange second CV′ data using transfer means592. For example, the second select CE-MIMO model581′ can create, update, and/or use the contact-etch related data associated with one or more of the patterned wafers (500a,500b, and500c), and the CE-related data can be fed forward and/or fed back using transfer means (590,591, and/or592).

When the second select CE-MIMO model581′ is executed, a second contact-etch procedure can be selected using controller (295 shown inFIGS. 2A-2G) and/or controller (395 shown inFIGS. 3A-3G). In some examples, the controllers (295 and/or395) can use CE-related library data for one or more of the patterned wafers (500a,500b,500c, and500d). The CE-related library data can include historical contact-etch procedure data and/or DPCE data collected using one or more CE-sensors (223 and/or234 shown inFIGS. 2A-2G) and/or CE-sensors (323 and/or334 shown inFIGS. 3A-3G), when one or more of the patterned wafers (500a,500b,500c, and500d) were being previously created.

In FIG.5′, a second CE-MIMO model582′ is illustrated, and when the second CE-MIMO model582′ is executed, the selected second contact-etch procedure can be performed using one or more of the etch subsystems described herein inFIGS. 2A-2G andFIGS. 3A-3G. When second contact-etch procedures are performed, one or more sets of process parameters can be determined, updated, and/or verified. For example, the second CE-MIMO model582′ can create and exchange second contact-etch MV′ data using transfer means590, can create and exchange second contact-etch DV′ data using transfer means591, and can create and exchange second contact-etch CV′ data using transfer means592 with the other MIMO models (580′,581′, and583′). In addition, the second CE-MIMO model582′ can include second MV′ process data, second DV′ process data, and second CV′ process data associated with the second contact-etch procedure.

In some examples, the thirdpatterned wafer500ccan be etched using the second contact-etch procedure to create a fourthpatterned wafer500d. Alternatively, other patterned wafers may be created.

With continuing reference to FIG.5′, a fourthpatterned wafer500dcomprising afirst transistor stack501dand asecond transistor stack502dis shown. Thefirst transistor stack501dcan include a nFET device, and thesecond transistor stack502dcan include a pFET device. Alternatively, other devices may be illustrated. In addition, a previously-filled contact/via575b′ is shown that can include one or more metallic or filler materials. The previously-filled contact/via575b′ can have been created using the selected first contact-etch procedure, one or more deposition procedures and one or more CMP procedures.

The fourthpatterned wafer500dcan include afirst substrate layer510d, afirst isolation layer520d, a first under-layer530d, and a second under-layer535d. For example, thefirst substrate layer510dcan include a semiconductor material; the isolation layers (530dand535d) can include dielectric or metallic material; and the first under-layer530dcan include TiN. Thefirst substrate layer510dcan include afirst STI region515d, and thefirst STI region515dcan include SiO₂, SiN, and/or SiON.

Thefirst transistor stack501dcan be covered/protected by a firsthard mask layer540d, andsecond transistor stack502dcan be covered by a secondhard mask layer545d. For example, firsthard mask layer540dand the secondhard mask layer545dcan include SiO₂and/or SiN. An inter-layer dielectric (ILD)layer565dis shown covering the firsthard mask layer540dand the secondhard mask layer545d, and theILD layer565dcan include a low-k dielectric material.

A second contact-etch masking layer570dcan be configured on top of theILD layer565d, and the second contact-etch masking layer570dcan include a plurality of second etch mask features571c. For example, one or more second litho-related procedures in a first DPCE processing sequence can have been performed to create second etch mask features571cin the second contact-etch masking layer570d. A second contact-etch procedure in the DPCE processing sequence can use the second etch mask features571cto create the second contact-etch vias575d, and the second contact-etch vias575dcan havewidths576dthat can vary from about 10 nm to about 100 nm. In addition, the second contact-etch masking layer570dcan include at least one radiation-sensitive material, at least one ARC material, and/or at least one resist material.

Thefirst transistor stack501dcan include a firstgate dielectric layer550d, a firstcontact metal layer551d, a secondcontact metal layer552d,first capping layer553d, a firstmetal gate layer554d, a firstdummy gate layer556d, and a first gatehard mask layer558d. The firstgate dielectric layer550dcan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer551dand/or the secondcontact metal layer552dcan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. Thefirst capping layer553dcan include a work function tuning material. The firstmetal gate layer554dcan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi₂, TiN, TaN, WN, or ZrSi₂. The firstdummy gate layer556dcan include Poly-Si material.

Thesecond transistor stack502dcan include a secondgate dielectric layer560d, a firstcontact metal layer561d, a secondcontact metal layer562d, a secondmetal gate layer564d, a seconddummy gate layer566d, and a second gatehard mask layer568d. The secondgate dielectric layer560dcan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer561dand/or the secondcontact metal layer562dcan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. The secondmetal gate layer564dcan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi2, TiN, TaN, WN, or ZrSi₂. The seconddummy gate layer566dcan include Poly-Si material.

The thirdpatterned wafer500cand the fourthpatterned wafer500dcan include a previously createdcontact feature575b′ that can be created using the selected first contact-etch procedure, one or more deposition procedures and one or more CMP procedures.

In some embodiments, when the second contact-etch procedure is performed a thirdpatterned wafer500ccan be positioned on a wafer holder (220 shown inFIGS. 2A-2G) and/or wafer holder (320 shown inFIGS. 3A-3G) and a second contact-etch plasma can be created in the process chamber (210 shown inFIGS. 2A-2G) and/or process chamber (310 shown inFIGS. 3A-3G) and a second contact-etch procedure can be performed.

During the second contact-etch procedure, second CE-sensor data can be collected using one or more CE-sensors (223 and/or234 shown inFIGS. 2A-2G) and/or CE-sensors (323 and/or334 shown inFIGS. 3A-3G), and controller (295 shown inFIGS. 2A-2G) and/or controller (395 shown inFIGS. 3A-3G) can compare the second CE-sensor data to historical CE-sensor data; and can store the second CE-sensor data. For example, the second process data can be collected using the process sensors (236 shown inFIGS. 2A-2G) and/or process sensors (336 shown inFIGS. 3A-3G) during the second contact-etch procedure.

When the selected second contact-etch procedure includes additional CE-related procedures, the additional CE-related procedures can be performed using one or more of the subsystems (110,120,130,140,150,160, and170) shown inFIG. 1.

In some embodiments, the DPCE processing sequence can include an IDL layer etch procedure for theIDL layer565d, and contact-etch procedure for the first hard mask (TEOS)layer540dor the second hard mask (TEOS)layer545d. In some examples, the DPCE processing sequence can also include ashing procedures, cleaning procedures, and/or CMP procedures. In other examples, the DPCE processing sequence can include metrology procedures, IE-sensor wafer measurement procedures, and/or IE-related inspection procedures.

Still referring to FIG.5′, a secondoutput data model583′ is illustrated, and a second set of output data can be analyzed when the secondoutput data model583′ is executed. The second output data can include real-time and/or historical CE-related data. For example, the secondoutput data model583′ can create and exchange second output MV′ data using transfer means590, can create and exchange second output DV′ data using transfer means591, and can create and exchange second output CV′ data using transfer means592 with the other MIMO models (580′,581′, and582′). In addition, the secondoutput data model583′ can analyze process data and/or CE-sensor data associated with the contact-etch procedures, and the analyzed process data and/or the analyzed CE-sensor data can be fed forward and/or fed back using transfer means (590,591, and/or592).

When the secondoutput data model583′ is executed, update procedures can be performed for the second contact-etch sequence. For example, update procedures can be performed to update the second process parameters, CE-sensor data, process data, and/or CE-related library data. The secondoutput data model583′ can exchange updated contact-etch MV′ data using transfer means590, can exchange updated contact-etch DV′ data using transfer means591, and can exchange updated contact-etch CV′ data using transfer means592 with the other MIMO models (580′,581′, and582′). During process development, DOE techniques can be used to examine the preliminary set of models (580′-583′) and to develop a reduced set of MIMO models.

FIGS.6 and6′ illustrate exemplary views of a second Double Pattern Contact-Etch (DPCE) processing sequence for creating second double pattern (DP) features in accordance with embodiments of the invention. For example, one or more second Litho-Etch-Litho-Etch (LELE) processing sequences can be performed. InFIG. 6, two exemplary patterned wafers (600aand600b) are shown having exemplary transistor stacks (601a,602a,601b, and602b) thereon that can be created using the second DPCE processing sequence, but this is not required for the invention. In FIG.6′, two other exemplary patterned wafers (600cand600d) are shown having exemplary transistor stacks (601c,602c,601d, and602d) thereon that can be created using the second DPCE processing sequence, but this is not required for the invention. Alternatively, a different number of patterned wafers with different transistor configurations may be used.

FIG. 6 illustrates a firstpatterned wafer600acomprising afirst transistor stack601aand asecond transistor stack602a, where thefirst transistor stack601acan include a nFET device, and thesecond transistor stack602acan include a pFET device. Alternatively, other devices may be illustrated. In addition, two previously-filled contact/vias (575b′ and575d′) are shown that can include one or more metallic or filler materials.

The firstpatterned wafer600acan include afirst substrate layer610a, afirst isolation layer620a, a first under-layer630a, and a second under-layer635a. For example, thefirst substrate layer610acan include a semiconductor material; theisolation layer620acan include dielectric or metallic material; and the first under-layers (630aand635a) can include TiN. Thefirst substrate layer610acan include a first shallow trench isolation (STI)region615a, and thefirst STI region615acan include silicon oxide (SiO₂), silicon nitride (SiN), or silicon oxynitride (SiON)

Thefirst transistor stack601acan be covered/protected by a firsthard mask layer640a, andsecond transistor stack602acan be covered by a secondhard mask layer645a. For example, firsthard mask layer640aand the secondhard mask layer645acan include SiO₂and/or SiN. An inter-layer dielectric (ILD)layer665ais shown covering the firsthard mask layer640aand the secondhard mask layer645a, and theILD layer665acan include a low-k dielectric material. In addition, theILD layer665acan cover and protect the two previously-filled contact/vias (575b′ and575d′).

A firstetch mask layer670acan be configured on top of theILD layer665a, and a plurality of first etch mask features671acan be configured in the firstetch mask layer670a, and the first etch mask features671acan havewidths672athat can vary from about 10 nm to about 100 nm. For example, one or more first litho-related sequences in the DPCE processing sequences can have been performed to create the first etch mask features671ain the firstetch mask layer670a. In addition, the firstetch mask layer670acan include at least one radiation-sensitive material, at least one ARC material, and/or at least one resist material.

Thefirst transistor stack601acan include a firstgate dielectric layer650a, a firstcontact metal layer651a, a secondcontact metal layer652a,first capping layer653a, a firstmetal gate layer654a, a firstdummy gate layer656a, a first gatehard mask layer658a, andfirst spacers659a. The firstgate dielectric layer650acan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer651aand/or the secondcontact metal layer652acan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. Thefirst capping layer653acan include a work function tuning material. The firstmetal gate layer654acan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi₂, TiN, TaN, WN, or ZrSi₂. The firstdummy gate layer656acan include Poly-Si material.

Thesecond transistor stack602acan include a secondgate dielectric layer660a, a firstcontact metal layer661a, a secondcontact metal layer662a, a secondmetal gate layer664a, a seconddummy gate layer666a, a second gatehard mask layer668a, andsecond spacers669a. The secondgate dielectric layer660acan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer661aand/or the secondcontact metal layer662acan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. The secondmetal gate layer664acan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi2, TiN, TaN, WN, or ZrSi₂. The seconddummy gate layer666acan include Poly-Si material.

InFIG. 6, a firstinput data model680 is illustrated, and a first set of input data can be obtained when the firstinput data model680 is executed. The first input data can include real-time and/or historical CE-related data for the firstpatterned wafer600a. A first select CE-MIMO model681 is illustrated, and a first contact-etch procedure can be selected using the first select CE-MIMO model681, and the first select CE-MIMO model681 can exchange Measured Variable (MV) data using transfer means690, can exchange Disturbance Variable (DV) data using transfer means691, and can exchange Controlled Variable (CV) data using transfer means692. For example, the first select CE-MIMO model681 can create and/or use first CE-related data associated with the firstpatterned wafer600a, and the first CE-related data can be fed forward and/or fed back using transfer means (690,691, and/or692).

When the first select CE-MIMO model681 is executed, a first contact-etch procedure can be selected using controller (295 shown inFIGS. 2A-2G) and/or controller (395 shown inFIGS. 3A-3G). In some examples, the controllers (295 and/or395) can use first CE-related library data for the firstpatterned wafer600aand/or the secondpatterned wafer600b. The first contact-etch related library data for the firstpatterned wafer600acan include historical contact-etch procedure data collected using one or more CE-sensors (223 and/or234 shown inFIGS. 2A-2G) and/or CE-sensors (323 and/or334 shown inFIGS. 3A-3G), when thefirst transistor stack601aand/or thesecond transistor stack602awere being created on the firstpatterned wafer600a. The first CE-related library data for the secondpatterned wafer600bcan include second historical contact-etch procedure data collected using one or more CE-sensors (223 and/or234 shown inFIGS. 2A-2G) and/or CE-sensors (323 and/or334 shown inFIGS. 3A-3G), whenfirst transistor stack601band/or thesecond transistor stack602bwere previously created on the secondpatterned wafers600b.

InFIG. 6, a first CE-MIMO model682 is illustrated, and when the first CE-MIMO model682 is executed, the selected first contact-etch procedure can be performed using one or more of the etch subsystems described herein inFIGS. 2A-2G andFIGS. 3A-3G. When contact-etch procedures are performed, one or more sets of process parameters can be determined, updated, and/or validated. For example, the first CE-MIMO model682 can create and exchange first contact-etch MV data using transfer means690, can create and exchange first contact-etch DV data using transfer means691, and can create and exchange first contact-etch CV data using transfer means692 with the other MIMO models (680,681, and683). In addition, the first CE-MIMO model682 can include first MV process data, first DV process data, and first CV process data associated with the first contact-etch procedure, with the firstpatterned wafer600a, and/or with the secondpatterned wafer600b.

In some examples, the firstpatterned wafer600acan be etched using the first contact-etch procedure to create a secondpatterned wafer600b. Alternatively, other patterned wafers may be created.

With continuing reference toFIG. 6, a secondpatterned wafer600bcomprising afirst transistor stack601band asecond transistor stack602b, thefirst transistor stack601bcan include a nFET device, and thesecond transistor stack602bcan include a pFET device. Alternatively, other devices may be illustrated. The firstpatterned wafer600aand the secondpatterned wafer600bcan include previously-filled contact features (575b′ and575d′) that can have been created using the first DPCE processing sequence.

The secondpatterned wafer600bcan include afirst substrate layer610b, afirst isolation layer620b, a first under-layer630b, and a second under-layer635b. For example, thefirst substrate layer610bcan include a semiconductor material; thefirst isolation layer620bcan include dielectric or metallic material; and the first under-layers (630band635b) can include TiN. Thefirst substrate layer610bcan include afirst STI region615b, and thefirst STI region615bcan include SiO₂, SiN, and/or SiON.

Thefirst transistor stack601bcan be covered/protected by a firsthard mask layer640b, andsecond transistor stack602bcan be covered by a secondhard mask layer645b. For example, firsthard mask layer640band the secondhard mask layer645bcan include SiO₂and/or SiN. An inter-layer dielectric (ILD)layer665bis shown covering the firsthard mask layer640band the secondhard mask layer645b, and theILD layer665bcan include a low-k dielectric material. In addition, theILD layer665bcan cover and protect the previously-filled contact features (575b′ and575d′).

A first contact-etch masking layer670bcan be configured on top of theILD layer665b, and the first contact-etch masking layer670bcan include a plurality of first etch mask features671a. For example, one or more first litho-related procedures in the second DPCE processing sequence can have been performed to create first etch mask features671ain the first contact-etch masking layer670b, and a first contact-etch procedure in the second DPCE processing sequence can use the first etch mask features671ato create the first contact-etch vias675b, and the contact-etch vias675bcan havewidths676bthat can vary from about 10 nm to about 100 nm. In addition, the first contact-etch masking layer670bcan include at least one radiation-sensitive material, at least one ARC material, and/or at least one resist material.

Thefirst transistor stack601bcan include a firstgate dielectric layer650b, a firstcontact metal layer651b, a secondcontact metal layer652b,first capping layer653b, a firstmetal gate layer654b, a firstdummy gate layer656b, a first gatehard mask layer658b, andfirst spacers659b. The firstgate dielectric layer650bcan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer651band/or the secondcontact metal layer652bcan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. Thefirst capping layer653bcan include a work function tuning material. The firstmetal gate layer654bcan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi₂, TiN, TaN, WN, or ZrSi₂. The firstdummy gate layer656bcan include Poly-Si material.

Thesecond transistor stack602bcan include a secondgate dielectric layer660b, a firstcontact metal layer661b, a secondcontact metal layer662b, a secondmetal gate layer664b, a seconddummy gate layer666b, a second gatehard mask layer668b, andsecond spacers669b. The secondgate dielectric layer660bcan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer661band/or the secondcontact metal layer662bcan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. The secondmetal gate layer664bcan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi₂, TiN, TaN, WN, or ZrSi₂. The seconddummy gate layer666bcan include Poly-Si material.

In some embodiments, when the first contact-etch procedure is performed, a firstpatterned wafer600acan be positioned on a wafer holder (220 shown inFIGS. 2A-2G) and/or wafer holder (320 shown inFIGS. 3A-3G) and a first contact-etch plasma can be created in the process chamber (210 shown inFIGS. 2A-2G) and/or process chamber (310 shown inFIGS. 3A-3G) and a first contact-etch procedure can be performed. In other embodiments, first Ion Energy Optimized (IEO) plasma can be created in the process chamber (210 shown inFIGS. 2A-2G) and/or process chamber (310 shown inFIGS. 3A-3G) and a first IEO-etch procedure can be performed.

During the first contact-etch procedure, first CE-sensor data can be collected using one or more CE-sensors (223 and/or234 shown inFIGS. 2A-2G) and/or CE-sensors (323 and/or334 shown inFIGS. 3A-3G), and controller (295 shown inFIGS. 2A-2G) and/or controller (395 shown inFIGS. 3A-3G) can compare the first CE-sensor data to historical CE-sensor data; and can store the first CE-sensor data. For example, the first process data can be collected using the process sensors (236 shown inFIGS. 2A-2G) and/or process sensors (336 shown inFIGS. 3A-3G) during the first contact-etch procedure.

When the selected first contact-etch procedure includes additional CE-related procedures, the additional CE-related procedures can be performed using one or more of the subsystems (110,120,130,140,150,160, and170) shown inFIG. 1.

In some embodiments, the first contact-etch procedure can include a Si-ARC layer etch procedure, an IDL layer etch procedure, and/ora TEOS layer etch procedure. In some examples, the second DPCE processing sequence can also include ashing procedures, cleaning procedures, and/or CMP procedures. In other examples, the second DPCE processing sequence can include IE-related etch procedures, IE-sensor wafer measurement procedures, and/or IE-related measurement procedures.

Still referring toFIG. 6, a firstoutput data model683 is illustrated, and a first set of output data can be analyzed when the firstoutput data model683 is executed. The first output data can include real-time and/or historical CE-related data. For example, the firstoutput data model683 can create and exchange output MV data using transfer means690, can create and exchange output DV data using transfer means691, and can create and exchange output CV data using transfer means692 with the other MIMO models (680,681, and682). In addition, the firstoutput data model683 can analyze process data and/or CE-sensor data associated with the contact-etch procedures, and the analyzed process data and/or the analyzed CE-sensor data can be fed forward and/or fed back using transfer means (690,691, and/or692).

When the firstoutput data model683 is executed, update procedures can be performed for the DPCE processing sequences. For example, update procedures can be performed to update and/or verify the first contact-etch parameters, the contact-etch metrology data, the contact-etch process data, and/or CE-related library data. The firstoutput data model683 can exchange updated and/or verified contact-etch MV data using transfer means690, can exchange updated contact-etch DV data using transfer means691, and can exchange updated and/or verified contact-etch CV data using transfer means692 with the other MIMO models (680,681, and682). During process development, DOE techniques can be used to examine the preliminary set of models (680-684) and to develop a reduced set of CE-MIMO models.

FIG.6′ illustrates a thirdpatterned wafer600ccomprising afirst transistor stack601cand asecond transistor stack602c, where thefirst transistor stack601ccan include a nFET device, and thesecond transistor stack602ccan include a pFET device. Alternatively, other devices may be illustrated.

The firstpatterned wafer600ccan include afirst substrate layer610c, afirst isolation layer620c, a first under-layer630c, and a second under-layer635c. For example, thefirst substrate layer610ccan include a semiconductor material; thefirst isolation layer620ccan include dielectric or metallic material; and the first under-layers (630cand635c) can include TiN. Thefirst substrate layer610ccan include a first shallow trench isolation (STI)region615c, and thefirst STI region615ccan include SiO₂, SiN, and/or SiON.

Thefirst transistor stack601ccan be covered/protected by a firsthard mask layer640c, andsecond transistor stack602ccan be covered by a secondhard mask layer645c. For example, firsthard mask layer640cand the secondhard mask layer645ccan include SiO₂and/or SiN. An inter-layer dielectric (ILD)layer665cis shown covering the firsthard mask layer640cand the secondhard mask layer645c, and theILD layer665ccan include a low-k dielectric material. A secondetch mask layer670ccan be configured on top of thefirst ILD layer665c, and a plurality of second etch mask features671ccan be configured in the secondetch mask layer670c, and the second etch mask features671ccan havewidths672cthat can vary from about 10 nm to about 100 nm. For example, one or more second litho processing sequences can be performed to create the second etch mask features671cin the secondetch mask layer670c. In addition, the secondetch mask layer670ccan include at least one radiation-sensitive material, at least one ARC material, and/or at least one resist material.

Thefirst transistor stack601ccan include a firstgate dielectric layer650c, a firstcontact metal layer651c, a secondcontact metal layer652c,first capping layer653c, a firstmetal gate layer654c, a firstdummy gate layer656c, a first gatehard mask layer658c, andfirst spacers659c. The firstgate dielectric layer650acan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer651cand/or the secondcontact metal layer652ccan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. Thefirst capping layer653ccan include a work function tuning material. The firstmetal gate layer654ccan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi₂, TiN, TaN, WN, or ZrSi₂. The firstdummy gate layer656ccan include Poly-Si material.

Thesecond transistor stack602ccan include a secondgate dielectric layer660c, a firstcontact metal layer661c, a secondcontact metal layer662c, a secondmetal gate layer664c, a seconddummy gate layer666c, a second gatehard mask layer668c, andsecond spacers669c. The secondgate dielectric layer660ccan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer661cand/or the secondcontact metal layer662ccan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. The secondmetal gate layer664ccan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi2, TiN, TaN, WN, or ZrSi₂. The seconddummy gate layer666ccan include Poly-Si material.

In FIG.6′, a secondinput data model680′ is illustrated, and a second set of input data can be obtained when the secondinput data model680′ is executed. The second input data can include real-time and/or historical CE-related data for one or more of the patterned wafers (600a,600b, and600c). A second select CE-MIMO model681′ is illustrated, and a second contact-etch procedure can be selected using the second select CE-MIMO model681′, and the second select CE-MIMO model681′ can exchange second MV′ selection data using transfer means690, can exchange second DV′ selection data using transfer means691, and can exchange second CV′ selection data using transfer means692. For example, the second select CE-MIMO model681′ can create, update, and/or use the contact-etch selection data associated with one or more of the patterned wafers (600a,600b, and600c), and the contact-etch selection data can be fed forward and/or fed back using transfer means (690,691, and/or692).

When the second select CE-MIMO model681′ is executed, a second contact-etch procedure can be selected using controller (295 shown inFIGS. 2A-2G) and/or controller (395 shown inFIGS. 3A-3G). In some examples, the controllers (295 and/or395) can use CE-related library data for one or more of the patterned wafers (600a,600b,600c, and600d). The CE-related library data can include historical contact-etch procedure data collected using one or more CE-sensors (223 and/or234 shown inFIGS. 2A-2G) and/or CE-sensors (323 and/or334 shown inFIGS. 3A-3G), when one or more of the patterned wafers (600a,600b,600c, and600d) were being previously created.

In FIG.6′, a second CE-MIMO model682′ is illustrated, and when the second CE-MIMO model682′ is executed, the selected second contact-etch procedure can be performed using one or more of the etch subsystems described herein inFIGS. 2A-2G andFIGS. 3A-3G. When contact-etch procedures are performed, one or more sets of process parameters can be determined using the second contact-etch sequence. For example, the second CE-MIMO model682′ can create and exchange second contact-etch MV′ data using transfer means690, can create and exchange second contact-etch DV′ data using transfer means691, and can create and exchange second contact-etch CV′ data using transfer means692 with the other MIMO models (680′,681′, and683′). In addition, the second CE-MIMO model682′ can include second MV′ process data, second DV′ process data, and second CV′ process data associated with the second contact-etch sequence.

In some examples, the thirdpatterned wafer600ccan be etched using the second contact-etch procedure to create a fourthpatterned wafer600d. Alternatively, other patterned wafers may be created.

With continuing reference to FIG.6′, a fourthpatterned wafer600dcomprising afirst transistor stack601dand asecond transistor stack602dis shown. Thefirst transistor stack601dcan include a nFET device, and thesecond transistor stack602dcan include a pFET device. Alternatively, other devices may be illustrated. In addition, a plurality of previously-filled contact/vias (575b′,575d′, and675b′) are shown that can include one or more metallic fill materials. The previously-filled contact/vias (575b′,575d′, and675b′) can have been created using one or more contact-etch sequences, one or more deposition procedures, and one or more CMP procedures.

The fourthpatterned wafer600dcan include afirst substrate layer610d, afirst isolation layer620d, a first under-layer630d, and a second under-layer635d. For example, thefirst substrate layer610dcan include a semiconductor material; thefirst isolation layer620dcan include dielectric or metallic material; and the first under-layers (630dand635d) can include TiN. Thefirst substrate layer610dcan include afirst STI region615d, and thefirst STI region615dcan include SiO₂, SiN, and/or SiON.

Thefirst transistor stack601dcan be covered/protected by a firsthard mask layer640d, andsecond transistor stack602dcan be covered by a secondhard mask layer645d. For example, firsthard mask layer640dand the secondhard mask layer645dcan include SiO₂and/or SiN. An inter-layer dielectric (ILD)layer665dis shown covering the firsthard mask layer640dand the secondhard mask layer645d, and theILD layer665dcan include a low-k dielectric material. In addition, theILD layer665dcan cover and protect the previously-filled contact/vias (575b′,575d′, and675b′).

A second contact-etch masking layer670dcan be configured on top of theILD layer665d, and the second contact-etch masking layer670dcan include a plurality of second etch mask features671c. For example, one or more second litho-related procedures in the second DPCE processing sequence can be performed to create second etch mask features671cin the second contact-etch masking layer670d, and a second contact-etch procedure in the second DPCE processing sequence can use the second etch mask features671cto create the second contact-etch vias675d, and the second contact-etch vias675dcan havewidths676dthat can vary from about 10 nm to about 100 nm. In addition, the second contact-etch masking layer670dcan include at least one radiation-sensitive material, at least one ARC material, and/or at least one resist material.

Thefirst transistor stack601dcan include a firstgate dielectric layer650d, a firstcontact metal layer651d, a secondcontact metal layer652d,first capping layer653d, a firstmetal gate layer654d, a firstdummy gate layer656d, a first gatehard mask layer658d, andfirst spacers659d. The firstgate dielectric layer650dcan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer651dand/or the secondcontact metal layer652dcan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. Thefirst capping layer653dcan include a work function tuning material. The firstmetal gate layer654dcan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi₂, TiN, TaN, WN, or ZrSi₂. The firstdummy gate layer656dcan include Poly-Si material.

Thesecond transistor stack602dcan include a secondgate dielectric layer660d, a firstcontact metal layer661d, a secondcontact metal layer662d, a secondmetal gate layer664d, a seconddummy gate layer666d, a second gatehard mask layer668d, andsecond spacers669d. The secondgate dielectric layer660dcan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer661dand/or the secondcontact metal layer662dcan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. The secondmetal gate layer664dcan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi₂, TiN, TaN, WN, or ZrSi₂. The seconddummy gate layer666dcan include Poly-Si material.

In some embodiments, when the second contact-etch procedure is performed a thirdpatterned wafer600ccan be positioned on a wafer holder (220 shown inFIGS. 2A-2G) and/or wafer holder (320 shown inFIGS. 3A-3G) and a second contact-etch plasma can be created in the process chamber (210 shown inFIGS. 2A-2G) and/or process chamber (310 shown inFIGS. 3A-3G) and the second contact-etch procedure can be performed.

During the second contact-etch procedure, second CE-sensor data can be collected using one or more CE-sensors (223 and/or234 shown inFIGS. 2A-2G) and/or CE-sensors (323 and/or334 shown inFIGS. 3A-3G), and controller (295 shown inFIGS. 2A-2G) and/or controller (395 shown inFIGS. 3A-3G) can compare the second CE-sensor data to historical CE-sensor data; and can store the second CE-sensor data. For example, the second process data can be collected using the process sensors (236 shown inFIGS. 2A-2G) and/or process sensors (336 shown inFIGS. 3A-3G) during the second contact-etch procedure.

When the selected second contact-etch procedure includes additional CE-related procedures, the additional CE-related procedures can be performed using one or more of the subsystems (110,120,130,140,150,160, and170) shown inFIG. 1.

In some embodiments, the second contact-etch procedure can include a Si-ARC layer etch procedure, an IDL layer etch procedure, and a TEOS layer etch procedure. In some examples, the second DPCE processing sequence can also include ashing procedures, cleaning procedures, and/or CMP procedures. In other examples, the second DPCE processing sequence can include IE-related etch procedures, IE-sensor wafer measurement procedures, and/or IE-related measurement procedures.

Still referring to FIG.6′, a secondoutput data model683′ is illustrated, and a second set of output data can be analyzed when the secondoutput data model683′ is executed. The second output data can include real-time and/or historical CE-related data. For example, the secondoutput data model683′ can create and exchange second output MV′ data using transfer means690, can create and exchange second output DV′ data using transfer means691, and can create and exchange second output CV′ data using transfer means692 with the other MIMO models (680′,681′, and682′). In addition, the secondoutput data model683′ can analyze process data and/or CE-sensor data associated with the contact-etch procedures, and the analyzed process data and/or the analyzed CE-sensor data can be fed forward and/or fed back using transfer means (690,691, and/or692).

When the secondoutput data model683′ is executed, update and/or verify procedures can be performed for the second contact-etch sequence. For example, update and/or verify procedures can be performed to update and/or verify the second process parameters, CE-sensor data, process data, and/or CE-related library data. The secondoutput data model683′ can exchange updated and/or verified contact-etch MV′ data using transfer means690, can exchange updated and/or verified contact-etch DV′ data using transfer means691, and can exchange updated and/or verified contact-etch CV′ data using transfer means692 with the other MIMO models (680′,681′, and682′). During process development, DOE techniques can be used to examine the preliminary set of models (680′-683′) and to develop a reduced set of MIMO models.

FIG. 7 illustrates exemplary views of a third Double-Pattern-Contact-Etch (DPCE) processing sequence for creating third double pattern (DP) features in accordance with embodiments of the invention. For example, a first Litho-Litho-Etch (LLE) processing sequence can be used to create the third DP features. InFIG. 7, two exemplary patterned wafers (700aand700b) are shown having exemplary transistor stacks (701a,702a,701b, and702b) thereon that can be created using the third DPCE processing sequence, but this is not required for the invention.

FIG. 7 illustrates a firstpatterned wafer700acomprising afirst transistor stack701aand asecond transistor stack702a, where thefirst transistor stack701acan include a nFET device, and thesecond transistor stack702acan include a pFET device. Alternatively, other devices may be illustrated. In addition, a number of previously-filled contact/vias (575b′,575d′,675b′, and675d′) are shown that can include one or more metallic or fill materials.

The firstpatterned wafer700acan include afirst substrate layer710a, afirst isolation layer720a, a first under-layer730a, and a second under-layer735a. For example, thefirst substrate layer710acan include a semiconductor material; thefirst isolation layer720acan include dielectric or metallic material; and the under-layers (730aand735a) can include TiN. Thefirst substrate layer710acan include a first shallow trench isolation (STI)region715a, and thefirst STI region715acan include silicon oxide (SiO₂), silicon nitride (SiN), silicon oxynitride (SiON)

Thefirst transistor stack701acan be covered/protected by a firsthard mask layer740a, andsecond transistor stack702acan be covered by a secondhard mask layer745a. For example, firsthard mask layer740aand the secondhard mask layer745acan include SiO₂and/or SiN. An inter-layer dielectric (ILD)layer765ais shown covering the firsthard mask layer740aand the secondhard mask layer745a, and theILD layer765acan include a low-k dielectric material. A firstetch mask layer770acan be configured on top of thefirst ILD layer765a, and the firstetch mask layer770acan include a plurality of first etch mask features771aand a plurality of second etch mask features773a. The first etch mask features771acan havewidths772athat can vary from about 10 nm to about 100 nm, and the second etch mask features773acan havewidths774athat can vary from about 10 nm to about 100 nm. For example, at least two litho-related sequences can be performed to create the first etch mask features771aand the second etch mask features773ain the firstetch mask layer770a. In addition, the firstetch mask layer770acan include at least one radiation-sensitive material, at least one ARC material, and/or at least one resist material.

Thefirst transistor stack701acan include a firstgate dielectric layer750a, a firstcontact metal layer751a, a secondcontact metal layer752a,first capping layer753a, a firstmetal gate layer754a, a firstdummy gate layer756a, a first gatehard mask layer758a, andfirst spacers759a. The firstgate dielectric layer750acan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer751aand/or the secondcontact metal layer752acan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. Thefirst capping layer753acan include a work function tuning material. The firstmetal gate layer754acan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi₂, TiN, TaN, WN, or ZrSi₂. The firstdummy gate layer756acan include Poly-Si material.

Thesecond transistor stack702acan include a secondgate dielectric layer760a, a firstcontact metal layer761a, a secondcontact metal layer762a, a secondmetal gate layer764a, a second dummy gate layer766a, a second gatehard mask layer768a, and second spacers769a. The secondgate dielectric layer760acan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer761aand/or the secondcontact metal layer762acan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. The secondmetal gate layer764acan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi₂, TiN, TaN, WN, or ZrSi₂. The second dummy gate layer766acan include Poly-Si material.

InFIG. 7, a firstinput data model780 is illustrated, and a first set of input data can be obtained when the firstinput data model780 is executed. The first input data can include real-time and/or historical IE-related data for the firstpatterned wafer700a.

A select CE-MIMO model781 is illustrated, and a first contact-etch procedure can be selected using the select CE-MIMO model781, and the select CE-MIMO model781 can exchange Measured Variable (MV) data using transfer means790, can exchange Disturbance Variable (DV) data using transfer means791, and can exchange Controlled Variable (CV) data using transfer means792. For example, the select CE-MIMO model781 can create and/or use first CE-related data associated with the firstpatterned wafer700a, and the first CE-related data can be fed forward and/or fed back using transfer means (790,791, and/or792).

When the select CE-MIMO model781 is executed, a first contact-etch procedure can be selected using controller (295 shown inFIGS. 2A-2G) and/or controller (395 shown inFIGS. 3A-3G). In some examples, the controllers (295 and/or395) can use first contact-etch related library data for the firstpatterned wafer700aand/or the secondpatterned wafer700b. The first CE-related library data for the firstpatterned wafer700acan include historical contact-etch procedure data collected using one or more CE-sensors (223 and/or234 shown inFIGS. 2A-2G) and/or CE-sensors (323 and/or334 shown inFIGS. 3A-3G), when thefirst transistor stack701aand/or thesecond transistor stack702awere being created on the firstpatterned wafer700a. The first CE-related library data for the secondpatterned wafer700bcan include second historical contact-etch procedure data collected using one or more CE-sensors (223 and/or234 shown inFIGS. 2A-2G) and/or CE-sensors (323 and/or334 shown inFIGS. 3A-3G), when first transistor stacks701band/or the second transistor stacks702bwere previously created on the secondpatterned wafers700b.

InFIG. 7, a CE-MIMO model782 is illustrated, and when the CE-MIMO model782 is executed, the selected first contact-etch procedure can be performed using one or more of the etch subsystems described herein inFIGS. 2A-2G andFIGS. 3A-3G. When contact-etch procedures are performed, one or more sets of process parameters can be determined, updated, and/or verified. For example, the CE-MIMO model782 can create and exchange first contact-etch MV data using transfer means790, can create and exchange first contact-etch DV data using transfer means791, and can create and exchange first contact-etch CV data using transfer means792 with the other MIMO models (780,781, and783). In addition, the CE-MIMO model782 can include first MV process data, first DV process data, and first CV process data associated with the first contact-etch procedure, with the firstpatterned wafer700a, and/or with the secondpatterned wafer700b.

In some examples, the firstpatterned wafer700acan be etched using the first contact-etch procedure to create a secondpatterned wafer700b. Alternatively, other patterned wafers may be created.

With continuing reference toFIG. 7, a secondpatterned wafer700bcomprising afirst transistor stack701band asecond transistor stack702b, thefirst transistor stack701bcan include a nFET device, and thesecond transistor stack702bcan include a pFET device. Alternatively, other devices may be illustrated.

The secondpatterned wafer700bcan include afirst substrate layer710b, afirst isolation layer720b, a first under-layer730b, and a second under-layer735b. For example, thefirst substrate layer710bcan include a semiconductor material; thefirst isolation layer720bcan include dielectric or metallic material; and the under-layers (730band735b) can include TiN. Thefirst substrate layer710bcan include afirst STI region715b, and thefirst STI region715bcan include SiO₂, SiN, and/or SiON.

Thefirst transistor stack701bcan be covered/protected by a firsthard mask layer740b, andsecond transistor stack702bcan be covered by a secondhard mask layer745b. For example, firsthard mask layer740band the secondhard mask layer745bcan include SiO₂and/or SiN. An inter-layer dielectric (ILD)layer765bis shown covering the firsthard mask layer740band the secondhard mask layer745b, and theILD layer765bcan include a low-k dielectric material. For example, the firstetch mask layer770bcan include first radiation-sensitive material, first ARC material, and/or first resist material.

Thefirst transistor stack701bcan include a firstgate dielectric layer750b, a firstcontact metal layer751b, a secondcontact metal layer752b,first capping layer753b, a firstmetal gate layer754b, and a first etchedgate feature775b, andfirst spacers759b. The firstgate dielectric layer750bcan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer751band/or the secondcontact metal layer752bcan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. Thefirst capping layer753bcan include a work function tuning material. The firstmetal gate layer754bcan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi2, TiN, TaN, WN, or ZrSi₂. The first etchedgate feature777bcan be filled with first replacement gate material during subsequent gate depositon procedures.

Thesecond transistor stack702bcan include a secondgate dielectric layer760b, a firstcontact metal layer761b, a secondcontact metal layer762b, a secondmetal gate layer764b, a second etchedgate feature777b, andsecond spacers769b. The secondgate dielectric layer760bcan include high-k dielectric material, such as hafnium oxide (HfO₂). The firstcontact metal layer761band/or the secondcontact metal layer762bcan include cobalt silicide, nickel silicide, tantalum silicide, titanium silicide, or tungsten silicide, or any combination thereof. The secondmetal gate layer764bcan be a very thin layer (10 angstrom to 400 angstrom) and can include MoSi₂, NiSi₂, TaSi₂, TiN, TaN, WN, or ZrSi₂. The second etchedgate feature777bcan be filled with second replacement gate material during subsequent gate depositon procedures.

One or more litho-related procedures in the third DPCE processing sequence can have been previously performed to create first etch mask features771aand the second etch mask features773ain the contact-etch masking layer770b. For example, one or more contact-etch procedures in the DPCE processing sequence can use the first etch mask features771ato create the first contact-etch vias775band can use the second etch mask features773ato create the second contact-etch vias777b. In addition, the first contact-etch vias775bcan havefirst widths776bthat can vary from about 10 nm to about 100 nm, and the second contact-etch vias777bcan havewidths778bthat can vary from about 10 nm to about 100 nm.

In some embodiments, when the first contact-etch procedure is performed a firstpatterned wafer700acan be positioned on a wafer holder (220 shown inFIGS. 2A-2G) and/or wafer holder (320 shown inFIGS. 3A-3G) and a first contact-etch plasma can be created in the process chamber (210 shown inFIGS. 2A-2G) and/or process chamber (310 shown inFIGS. 3A-3G), and the first contact-etch procedure can be performed. In other embodiments, Ion Energy Optimized (IEO) plasma can be created in the process chamber (210 shown inFIGS. 2A-2G) and/or process chamber (310 shown inFIGS. 3A-3G) and a first IEO-etch procedure can be performed.

During the first contact-etch procedure, first CE-sensor data can be collected using one or more CE-sensors (223 and/or234 shown inFIGS. 2A-2G) and/or CE-sensors (323 and/or334 shown inFIGS. 3A-3G), and controller (295 shown inFIGS. 2A-2G) and/or controller (395 shown inFIGS. 3A-3G) can compare the first CE-sensor data to historical CE-sensor data; and can store the first CE-sensor data. For example, the first process data can be collected using the process sensors (236 shown inFIGS. 2A-2G) and/or process sensors (336 shown inFIGS. 3A-3G) during the first contact-etch procedure.

When the selected first contact-etch procedure includes additional CE-related procedures, the additional CE-related procedures can be performed using one or more of the subsystems (110,120,130,140,150,160, and170) shown inFIG. 1.

In some embodiments, the first contact-etch procedure can include a Si-ARC layer etch procedure, an ILD layer etch procedure, and a TEOS layer etch procedure. In some examples, the third DPCE processing sequence can also include ashing procedures, cleaning procedures, and/or CMP procedures. In other examples, the third DPCE processing sequence can include IE-related etch procedures, IE-sensor wafer measurement procedures, and/or IE-related measurement procedures.

Still referring toFIG. 7, anoutput data model783 is illustrated, and a first set of output data can be analyzed when theoutput data model783 is executed. The first output data can include real-time and/or historical CE-related data. For example, theoutput data model783 can create and exchange output MV data using transfer means790, can create and exchange output DV data using transfer means791, and can create and exchange output CV data using transfer means792 with the other CE-MIMO models (780,781, and782). In addition, the firstoutput data model783 can analyze process data and/or CE-sensor data associated with the contact-etch procedures, and the analyzed process data and/or the analyzed CE-sensor data can be fed forward and/or fed back using transfer means (790,791, and/or792).

When the firstoutput data model783 is executed, update and/or verify procedures can be performed for the first contact-etch procedure. For example, update procedures can be performed to update and/or verify the first CE process parameters, the CE sensor data, CE process data, and/or the CE-related library data. The firstoutput data model783 can exchange updated and/or verified contact-etch MV data using transfer means790, can exchange updated and/or verified contact-etch DV data using transfer means791, and can exchange updated and/or verified contact-etch CV data using transfer means792 with the other CE-MIMO models (780,781, and782). During process development, DOE techniques can be used to examine the preliminary set of models (780-784) and to develop a reduced set of CE-MIMO models.

In some embodiments, the DPCE processing sequence can include one or more “break through (BT) etch procedures, one or more Main-Etch (ME) etch procedures, one or more Over-Etch (OE) etch procedures, and one or more Titanium Nitride (TiN) etch procedures. Alternatively, other etching, ashing, or cleaning procedures may be used. In other embodiments, the DPCE processing sequence can include one or more Si-ARC layer etch procedures, one or more TiN etch procedures, one or more TEOS etch procedures, and one or more TEOS layer etch procedures.

In other embodiments, the DPCE processing sequence may include a first Ion-Energy Optimized (IEO) etch procedure for a first hard mask layer, second IEO etch procedure for an IDL layer, and third IEO etch procedure for a second hard mask layer. For example, the first IEO etch procedure can include a Si-ARC layer etch procedure, the second IEO etch procedure can include a width layer etch procedure, and the third IEO etch procedure can include a TEOS layer etch procedure. In some examples, the DPCE processing sequence can also include ashing procedures, cleaning procedures, and/or CMP procedures. In other examples, DPCE processing sequence can include IE-related metrology procedures, IE-sensor wafer measurement procedures, and/or IE-related inspection procedures.

During hardmask (SiARC) contact-etch procedures, the chamber pressure can range from about 12 mT to about 18 mT; the top power can vary from about 450 watts to about 550 watts; the lower power can vary from about 90 watts to about 110 watts; the ESC voltage can be set at about 2500 V; the Tetrafluoromethane (CF₄) flow rate can vary between about 60 sccm and about 100 sccm; the trifluoromethane (CHF₃) flow rate can vary between about 40 sccm and about 60 sccm; the top chamber temperature can vary from about 70 degrees Celsius to about 90 degrees Celsius; the chamber wall temperature can vary from about 50 degrees Celsius to about 70 degrees Celsius; the bottom chamber temperature can vary from about 10 degrees Celsius to about 30 degrees Celsius; the temperature at the center of the wafer holder can vary from about 12 degrees Celsius to about 20 degrees Celsius; the temperature at the edge of the wafer holder can vary from about 8 degrees Celsius to about 12 degrees Celsius; the center backside pressure for the wafer holder can vary from about 15 Torr to about 25 Torr; the edge backside pressure for the wafer holder can vary from about 27 Torr to about 33 Torr; and the processing time can vary from about 60 seconds to about 90 seconds.

During IDL contact-etch procedures, the chamber pressure can range from about 15 mT to about 25 mT; the top power can vary from about 450 watts to about 550 watts; the lower power can vary from about 90 watts to about 110 watts; the ESC voltage can be set at about 2500 V; the O₂flow rate can vary between about 30 sccm and about 50 sccm; the CO₂flow rate can vary between about 70 sccm and about 90 sccm; the HBr flow rate can vary between about 25 sccm and about 35 sccm; the top chamber temperature can vary from about 70 degrees Celsius to about 90 degrees Celsius; the chamber wall temperature can vary from about 50 degrees Celsius to about 70 degrees Celsius; the bottom chamber temperature can vary from about 10 degrees Celsius to about 30 degrees Celsius; the temperature at the center of the wafer holder can vary from about 12 degrees Celsius to about 20 degrees Celsius; the temperature at the edge of the wafer holder can vary from about 8 degrees Celsius to about 12 degrees Celsius; the center backside pressure for the wafer holder can vary from about 15 Torr to about 25 Torr; the edge backside pressure for the wafer holder can vary from about 27 Torr to about 33 Torr; and the processing time can vary from about 90 seconds to about 130 seconds.

During TEOS layer contact-etch procedures, the chamber pressure can range from about 35 mT to about 45 mT; the top power can vary from about 550 watts to about 650 watts; the lower power can vary from about 90 watts to about 110 watts; the ESC voltage can be set at about 2500 V; the CF₄flow rate can vary between about 40 sccm and about 60 sccm; the CHF₃flow rate can vary between about 40 sccm and about 60 sccm; the O₂flow rate can vary between about 3 sccm and about 7 sccm; the top chamber temperature can vary from about 30 degrees Celsius to about 90 degrees Celsius; the chamber wall temperature can vary from about 50 degrees Celsius to about 70 degrees Celsius; the bottom chamber temperature can vary from about 30 degrees Celsius to about 50 degrees Celsius; the temperature at the center of the wafer holder can vary from about 25 degrees Celsius to about 35 degrees Celsius; the temperature at the edge of the wafer holder can vary from about 8 degrees Celsius to about 12 degrees Celsius; the center backside pressure for the wafer holder can vary from about 15 Torr to about 25 Torr; the edge backside pressure for the wafer holder can vary from about 27 Torr to about 33 Torr; and the processing time can vary from about 50 seconds to about 90 seconds.

During TEOS OE contact-etch procedures, the chamber pressure can range from about 35 mT to about 45 mT; the top power can vary from about 550 watts to about 650 watts; the lower power can vary from about 90 watts to about 110 watts; the ESC voltage can be set at about 2500 V; the CF₄flow rate can vary between about 40 sccm and about 60 sccm; the CHF₃flow rate can vary between about 40 sccm and about 60 sccm; the O₂flow rate can vary between about 3 sccm and about 7 sccm; the top chamber temperature can vary from about 30 degrees Celsius to about 90 degrees Celsius; the chamber wall temperature can vary from about 50 degrees Celsius to about 70 degrees Celsius; the bottom chamber temperature can vary from about 30 degrees Celsius to about 50 degrees Celsius; the temperature at the center of the wafer holder can vary from about 25 degrees Celsius to about 35 degrees Celsius; the temperature at the edge of the wafer holder can vary from about 8 degrees Celsius to about 12 degrees Celsius; the center backside pressure for the wafer holder can vary from about 15 Torr to about 25 Torr; the edge backside pressure for the wafer holder can vary from about 27 Torr to about 33 Torr; and the processing time can vary from about 5 seconds to about 10 seconds.

During BT contact-etch procedures, the chamber pressure can range from about 8 mT to about 12 mT; the top power can vary from about 600 watts to about 700 watts; the lower power can vary from about 175 watts to about 200 watts; the ESC voltage can be set at about 2500 V; the CF₄flow rate can vary between about 120 sccm and about 150 sccm; the top chamber temperature can vary from about 70 degrees Celsius to about 90 degrees Celsius; the chamber wall temperature can vary from about 50 degrees Celsius to about 70 degrees Celsius; the bottom chamber temperature can vary from about 10 degrees Celsius to about 30 degrees Celsius; the wafer holder temperature can vary from about 60 degrees Celsius to about 70 degrees Celsius; the center backside pressure for the wafer holder can vary from about 8 Torr to about 12 Torr; the edge backside pressure for the wafer holder can vary from about 8 Torr to about 12 Torr; and the processing time can vary from about 5 seconds to about 15 seconds.

During ME contact-etch procedures, the chamber pressure can range from about 8 mT to about 12 mT; the top power can vary from about 120 watts to about 150 watts; the ESC voltage can be set at about 2500 V; the O₂flow rate can vary between about 2 sccm and about 6 sccm; the HBr flow rate can vary between about 220 sccm and about 280 sccm; the top chamber temperature can vary from about 70 degrees Celsius to about 90 degrees Celsius; the chamber wall temperature can vary from about 50 degrees Celsius to about 70 degrees Celsius; the bottom chamber temperature can vary from about 10 degrees Celsius to about 30 degrees Celsius; the wafer holder temperature can vary from about 60 degrees Celsius to about 70 degrees Celsius; the center backside pressure for the wafer holder can vary from about 8 Torr to about 12 Torr; the edge backside pressure for the wafer holder can vary from about 8 Torr to about 12 Torr; and the processing time can vary from about 50 seconds to about 70 seconds.

During OE contact-etch procedures, the chamber pressure can range from about 8 mT to about 12 mT; the top power can vary from about 120 watts to about 150 watts; the lower power can vary from about 20 watts to about 40 watts; the ESC voltage can be set at about 2500 V; the O₂flow rate can vary between about 2 sccm and about 6 sccm; the HBr flow rate can vary between about 220 sccm and about 280 sccm; the top chamber temperature can vary from about 70 degrees Celsius to about 90 degrees Celsius; the chamber wall temperature can vary from about 50 degrees Celsius to about 70 degrees Celsius; the bottom chamber temperature can vary from about 60 degrees Celsius to about 80 degrees Celsius; the wafer holder temperature can vary from about 60 degrees Celsius to about 70 degrees Celsius; the center backside pressure for the wafer holder can vary from about 8 Torr to about 12 Torr; the edge backside pressure for the wafer holder can vary from about 8 Torr to about 12 Torr; and the processing time can vary from about 20 seconds to about 30 seconds.

During TiN contact-etch procedures, the chamber pressure can range from about 8 mT to about 12 mT; the top power can vary from about 180 watts to about 220 watts; the lower power can vary from about 40 watts to about 60 watts; the ESC voltage can be set at about 2500 V; the chlorine (Cl₂) flow rate can vary between about 12 sccm and about 18 sccm; the Ar flow rate can vary between about 180 sccm and about 220 sccm; the top chamber temperature can vary from about 70 degrees Celsius to about 90 degrees Celsius; the chamber wall temperature can vary from about 50 degrees Celsius to about 70 degrees Celsius; the bottom chamber temperature can vary from about 60 degrees Celsius to about 80 degrees Celsius; the wafer holder temperature can vary from about 60 degrees Celsius to about 70 degrees Celsius; the center backside pressure for the wafer holder can vary from about 8 Torr to about 12 Torr; the edge backside pressure for the wafer holder can vary from about 8 Torr to about 12 Torr; and the processing time can vary from about 50 seconds to about 80 seconds.

During HK contact-etch procedures, the HK chamber pressure can range from about 8 mT to about 12 mT; the top power can vary from about 550 watts to about 650 watts; the ESC voltage can be set at about 500 V; the Boron Trichloride (BCl₃) flow rate can vary between about 120 sccm and about 180 sccm; the top chamber temperature can vary from about 70 degrees Celsius to about 90 degrees Celsius; the chamber wall temperature can vary from about 40 degrees Celsius to about 60 degrees Celsius; the bottom chamber temperature can vary from about 60 degrees Celsius to about 80 degrees Celsius; and the processing time can vary from about 30 seconds to about 40 seconds.

During Ashing procedures, the chamber pressure can range from about 125 mT to about 175 mT; the top power can vary from about 350 watts to about 450 watts; the lower power can vary from about 20 watts to about 30 watts; the ESC voltage can be set at about 2500 V; the O₂flow rate can vary between about 430 sccm and about 470 sccm; the top chamber temperature can vary from about 30 degrees Celsius to about 90 degrees Celsius; the chamber wall temperature can vary from about 50 degrees Celsius to about 70 degrees Celsius; the bottom chamber temperature can vary from about 70 degrees Celsius to about 80 degrees Celsius; the temperature at the center of the wafer holder can vary from about 70 degrees Celsius to about 80 degrees Celsius; the temperature at the edge of the wafer holder can vary from about 8 degrees Celsius to about 12 degrees Celsius; the center backside pressure for the wafer holder can vary from about 15 Torr to about 25 Torr; the edge backside pressure for the wafer holder can vary from about 27 Torr to about 33 Torr; and the processing time can vary from about 150 seconds to about 210 seconds.

During CE-MIMO model development, the number of feed forward and feedback paths actually used in the CE-MIMO can be optimized. DOE techniques can be used to create and/or examine the CE-MIMO models and to develop a reduced set of feed forward and feedback paths/variables.

FIG. 8 illustrates exemplary block diagram for a two-part Contact-Etch Multi-Input/Multi-Output (CE-MIMO) model in accordance with embodiments of the invention.

A first generalized CE-MIMO model810 is shown that can be associated with a first contact-etch procedure and that includes a first set of manipulated variables MVs(1a-na), a first set of disturbance variables DVs(1a-na), and a first set of controlled variables CVs(1a-na). A first set ofexemplary MVs811 is shown that includes eight manipulated variables {(MV_1a)-(MV_8a)} that can be associated with the first CE-MIMO model810. Alternatively, a different number of different manipulated variables may be associated with the first CE-MIMO model810. A first set ofexemplary DVs812 is shown that includes six disturbance variables {(DV_1a)-(DV_6a)} that can be associated with the first CE-MIMO model810. Alternatively, a different number of different disturbance variables may be associated with the first CE-MIMO model810. A first set ofexemplary CVs813 is shown that includes six controlled variables {(CV_1a)-(CV_6a)} that can be associated with the first CE-MIMO model810. Alternatively, a different number of different controlled variables may be associated with the first CE-MIMO model810. In addition, a first set ofexemplary equations815 is shown that can be associated with the first CE-MIMO model810. Alternatively, other equations may be associated with the first CE-MIMO model810.

A second generalized CE-MIMO model820 is shown that can be associated with a second contact-etch procedure and that includes a second set of manipulated variables MVs(1b-nb), a second set of disturbance variables DVs(1b-nb), and a second set of controlled variables CVs(1b-nb). A second set ofexemplary MVs821 is shown that includes eight manipulated variables {(MV_1b)-(MV_8b)} that can be associated with the second CE-MIMO model820. Alternatively, a different number of different manipulated variables may be associated with the second CE-MIMO model820. A second set of exemplary DVs822 is shown that includes six disturbance variables {(DV_1b)-(DV_6b)} that can be associated with the second CE-MIMO model820. Alternatively, a different number of different disturbance variables may be associated with the second CE-MIMO model820. A second set ofexemplary CVs823 is shown that includes six controlled variables {(CV_1b)-(CV_6b)} that can be associated with the second CE-MIMO model820. Alternatively, a different number of different controlled variables may be associated with the second CE-MIMO model820. In addition, a second set ofexemplary equations825 is shown that can be associated with the second CE-MIMO model820. Alternatively, other equations may be associated with the second CE-MIMO model820.

One or more of the variables (811,812, or813) associated with the first CE-MIMO model810 can be fed forward830 to the second CE-MIMO model820, and one or more of the second variables (821,822, or823) associated with the second CE-MIMO model820 can be fed back835 to the first CE-MIMO model810.

FIG. 9 illustrates an exemplary flow diagram for a procedure for developing Contact-Etch-Multi-Input/Multi-Output (CE-MIMO) models for contact-etch procedures in accordance with embodiments of the invention. In the illustrated embodiment, aprocedure900 is shown having a number of steps. Alternatively, a different number of alternate steps may be used.

In910, one or more contact-etch procedures can be identified as candidates for a CE-MIMO modeling analysis procedure. In some examples, one or more contact-etch procedures and associated MIMO models can be established to create one or more patterned wafers (500aand500b,FIGS. 5), or (500cand500d, FIG.5′), or (600aand600b,FIGS. 6), or (600cand600d, FIG.6′), or (700a, and700b,FIG. 7).

In915, a first set of controlled outputs variables (CVs) and the ranges associated with the CVs can be determined. One or more of the CVs can be specified by an end user or a customer. The CVs can include one or more critical dimensions (CDs) and/or one or more side wall angles associated with one or more of the transistor stacks (501a,502a,501b, and502b) shown inFIG. 5 or transistor stacks (501c,502c,501d, and502d) shown in FIG.5′ or with one or more of the transistor stacks (601a,602a,601b, and602b) shown inFIG. 6 or with one or more of the transistor stacks (601c,602c,601d, and602d) shown in FIG.6′, or with one or more of the transistor stacks (701a,702a,701b, and702b) shown inFIG. 7. In some examples, the first and second contact-etch procedures can be performed to create contacts in pFET devices, nFET devices, Tri-gate devices, and/or FinFET devices.

In920, a first set of candidates can be determined for the manipulated variables (MVs) associated with the CE-MIMO using one or more candidate contact-etch procedures/recipes. The MVs can include WiW manipulated variables (WiW-MVs), and the WiW-MVs can include “fast” MVs that can be controlled while a wafer is being processed. The MVs can include W2W manipulated variables (W2W-MVs), and the W2W-MVs can include “slow” MVs that can be controlled when a wafer lot is being processed. The ranges for the MVs can be examined for each step in a candidate recipe.

When a two-zone wafer holder with a fast response time is used, the center temperature and the edge temperature for the wafer holder can be used as (WiW-MVs) and can be changed on a systematic basis. When a RF source with a fast response time is used with a split upper electrode and power splitter, the center RF power and the edge RF power for the plasma can be used as (WiW-MVs) and can be changed on a systematic basis. When a low temperature chiller (−10° C.) is used, there can be a larger temperature delta center to edge. In addition, pressure, time, and gas flows can be used as MVs.

The disturbance variables (DVs) can include CD and SWA values for a first input contact (IC₁) at the center and edge, the control layer CD and SWA at the center and edge, the feature thicknesses at the center and edge, the chemical and etch rate properties of the different layers, the maintenance events on chamber, the chamber-to-chamber data, the input IE values, and other stack data.

In925, Design of Experiment (DOE) procedures can be performed to analyze the contact-etch procedure and/or the CE-MIMO model. Using CE-sensor data and/or process sensor data from DOE wafers, contact-etch-related experiments can be performed to establish statistical models that can connect MVs with each CV. When the number of experiments increases, a more accurate model can be obtained, but at the expense of additional materials and time. Therefore, cost and availability can limit the number of procedures performed using IE-sensor wafers and/or the number of DOE wafers processed in processing chambers. A critical factor for DOE procedures is the format of the predicted model. One or more model types can be selected, ranges can be provided for the CVs and/or MVs, and statistical software, such as JMP® statistical software from the SAS Institute) can be used to establish one or more of the DOE tables). The DOE data can be used to establish candidate MVs, CVs, and DVs that can be associated with a first, second, and/or third contact-etch procedures. In other analysis procedures, other MVs, DVs, and CVs can be used. In some embodiments, the chamber state data for the etching chambers and the IM chambers can be used as manipulated variables. Alternatively, the process modeling may assume that the chamber state is stable between wafers and/or lots.

In some examples, the contact-etch procedure can include a Si-ARC layer etch procedure, an IDL layer etch procedure, a TEOS layer etch procedure, a TEOS Over-Etch (OE) etch procedure, and an ashing procedure. In other examples, the DPCE processing sequence can include a “Break-Though” (BT) etch procedure, a Main-Etch (ME) etch procedure, an Over-Etch (OE) etch procedure, a Titanium Nitride (TiN) etch procedure, and a HK etch procedure. The DOE data obtained for the contact-etch procedures and/or DPCE processing sequences can include CE-sensor data, process sensor data, and IE-sensor wafer data.

In930, after performing the first contact-etch procedures and/or the second contact-etch procedures required to populate one or more DOE tables, nonlinear models with quadratic and interaction terms can be created by using a least squares technique and statistical software. In some models, terms can be deleted that have extremely small coefficients associated with them.

In935, one or more linear gain matrices (G) can be created using the DOE data. For example, a Relative Gain Array (RGA) matrix can created using:

$\lambda \mathrm{ij}=\frac{{\left[\frac{\partial {\mathrm{CV}}_i}{\partial {\mathrm{MV}}_j}\right]}_{{\mathrm{MV}}_{k,k\ne j}}}{{\left[\frac{\partial {\mathrm{CV}}_i}{\partial {\mathrm{MV}}_j}\right]}_{{\mathrm{CV}}_{k,k\ne j}}}=\frac{\mathrm{Gain}\left(\mathrm{open}-\mathrm{loop}\right)}{\mathrm{Gain}\left(\mathrm{closed}-\mathrm{loop}\right)}$

for i=1, 2, . . . , n and j=1, 2, . . . , n.

The symbol (∂CV_i/∂MV_j)_MVdenotes a partial derivative that is evaluated with all of the manipulated variables except MV_jheld constant, and this term is the open-loop gain between CV_iand MV_j. In addition, the symbol (∂CV_i/∂MV_j)_CVcan be interpreted as a closed loop gain that indicates the effect of MV_jand CV_iwhen all of the control loops are closed.

When a non-square matrix is obtained, some of the MVs or CVs may be eliminated to create a square matrix. In addition, when there are more MV's than CVs, the non-square matrix can be analyzed using a non-square RGA (NRGA). For example,
NRGA=G

(G⁺)^T

and the pseudo-inverse, G⁺, is used instead of the normal inverse, G⁻¹. NRGA provides several criteria for the selection of a square system, but their criteria are not always valid in some non-square systems, so all combinations of square pairing of subsystems might need considered. To compare one subsystem with others RGA pairing rules can be used as a metric. This creates sub combinations that can then be compared for best square matrix.

In940, one or more RGAs can be calculated using one or more of the linear gain matrices (G). For example, when square matrices are used,
RGA=G

(G⁻¹)^T

where G is the gain matrix and G⁻¹is the inverse gain matrix.

In945, pairing rules in the RGA can be used to investigate the best combinations of MVs and CVs. RGA analysis can be used for measured model parameter selection, and CV-MV pairs can be selected such that their sum is closest to one. In addition, paring on negative elements can be avoided. In addition, the RGA analysis can be used to determine a number of candidate models and to identify the best-case solution. When there are more CVs than MVs, RGA analysis can be used for selecting the most controllable CV (sensitivity analysis of CVs to MVs).

In950, the system stability and conditioning can be determined. For example, the Niederlinski Stability Theorem states that a closed loop system resulting from diagonal pairing is unstable if:

$\mathrm{NST}=\frac{\det \left(G\right)}{\prod _{i=1}^n{g}_{\mathrm{ii}}}<0$

where NST is the Niederlinski index, G is the gain matrix, det(G) is the determinant of the gain matrix (G), and g_iiis the diagonal elements of the gain matrix. The condition of the gain matrix (G) can be determined using the following:
G=USV^T

where G, U, S, and V are matrices determined using singular value decomposition (SVD). In addition, a condition number (CN) can be determined using the ratio of the larger value to the smaller value in the S matrix. Additional information concerning the Niederlinski Theorem may be found in a book (ISBN 978047001168-3) entitled “Multivariable Feedback Control: Analysis and Design” by Sigurd Skogestad and Ian Postlethwaite from which pages (75-86) and pages (431-449) are incorporated herein in their entirety. For example, when CN is greater than fifty, the system is nearly singular and will have poor control performance.

In955, the CE-MIMO model can be optimized using actual equipment and/or performance constraints. In some examples, the measurement locations can be examined and selected to optimize performance, the number of pre- and/or post measurement procedure can be established to optimize performance, and the multi-chamber sequences can be examined to optimize throughput. The feedback can be optimized by tuning the EWMA filters. The time constants for the MVs can be determined, and their update frequency can be based on Lot-to-Lot (L2L), W2W, WiW, and process step values. In addition, process center points, CV center points, and MV center points can be examined to optimize performance. Historical data can be used to perform simulations.

The wafers can include one or more layers that can include semiconductor material, carbon material, dielectric material, glass material, ceramic material, metallic material, oxidized material, mask material, or planarization material, or a combination thereof.

In other embodiments, one or more IE-sensor wafers can be processed to verify a CE-MIMO model and/or to verify a contact-etch procedure. When an contact-etch sequence or MIMO model is verified, one or more contacts (575b,575d,675b, and675d) can be created on a test wafer, and when the test wafer is examined. During the examination, measurement data can be obtained from the contacts (575b,575d,675b, and675d). A best estimate contact and associated best estimate data can be selected from the CE-MIMO library that includes verified transistor structures, verified contacts, and associated data. One or more differences can be calculated between the contacts (575b,575d,675b, and675d) and the best estimate contact from the library, the differences can be compared to matching criteria, creation criteria, or product requirements, or any combination thereof. When matching criteria are used, the contacts (575b,575d,675b, and675d) can be identified as members of the CE-MIMO library, and the test wafer can be identified as a reference “golden” wafer if the matching criteria are met or exceeded. When creation criteria are used, the contacts (575b,575d,675b, and675d) can be identified as a new member of the CE-MIMO library, and the test wafer can be identified as a verified reference wafer if the creation criteria are met. When product requirements data are used, the contacts (575b,575d,675b, and675d) can be identified as verified contacts, and the test wafer can be identified as verified production wafer if one or more product requirements are met. Corrective actions can be applied if one or more of the criteria or product requirements are not met. CE-MIMO confidence data and/or risk data can be established for the contacts (575b,575d,675b, and675d) using the measurement data and the best estimate contact data. For example, the CE-MIMO evaluation library data can include goodness of fit (GOF) data, creation rules data, measurement data, inspection data, verification data, map data, confidence data, accuracy data, process data, or uniformity data, or any combination thereof.

When the contacts (575b,575d,675b, and675d) are produced and/or examined, accuracy and/or tolerance limits can be used. When these limits are not correct, refinement procedures can be performed. Alternatively, other procedures can be performed, other sites can be used, or other wafers can be used. When a refinement procedure is used, the refinement procedure can utilize bilinear refinement, Lagrange refinement, Cubic Spline refinement, Aitken refinement, weighted average refinement, multi-quadratic refinement, bi-cubic refinement, Turran refinement, wavelet refinement, Bessel's refinement, Everett refinement, finite-difference refinement, Gauss refinement, Hermite refinement, Newton's divided difference refinement, osculating refinement, or Thiele's refinement algorithm, or a combination thereof.

When CE-related data is collected, a number of verification wafers and/or IE-sensor wafers can be used and candidate disturbance variables can be identified. During data collection, the variations associated with one or more CVs can be minimized, and the collected data can be used for a simulation. The simulation can execute the same process steps as the contact-etch procedures used in production. For example, one or more of the processed wafers can be measured in an integrated metrology chamber and the IM data can include CD and SWA data from multiple sites in a patterned masking layer on each incoming wafer. In addition, IE-sensor data, process sensor data, and/or other sensor data can be received and analyzed. Grating density and transistor type should be selected to correlate to the most critical chip level performance metric (such as P or N channel transistor type) because each of the transistor structures can have some variations that can be related to the etch profile control needs.

FIG. 10 illustrates an exemplary block diagram for an Ion Energy (IE) sensor wafer in accordance with embodiments of the invention. In the illustrated embodiment, a top view of IE-sensor wafer1000 is shown. The IE-sensor wafer1000 can have a first diameter1001 of about 300 millimeters (mm). Alternatively, the diameter1001 can be smaller or larger.

The IE-sensor wafer1000 can include one or moreion energy analyzers1010 configured at one or more first locations within the IE-sensor wafer1000. For example, the IE-sensor wafer1000 and methods for using it can be as described in U.S. Pat. No. 7,777,179, entitled “Two-Grid Ion Energy Analyzer and Methods of Manufacturing and Operating”, by Chen, et al., issued on Aug. 17, 2010, and this patent is incorporated in its entirety herein by reference. Additional the IE-sensor wafers and methods for using can be as described in U.S. Pat. No. 7,875,859, entitled “Ion Energy Analyzer and Methods of Manufacturing and Operating”, by Chen, et al., issued on Jan. 25, 2011, and this patent is incorporated in its entirety herein by reference. A top view of theion energy analyzers1010 are shown, and theion energy analyzers1010 can include a circular opening having asecond diameter1011. Thesecond diameter1011 can vary from about 10 mm to about 50 mm.

Acontroller1050 is shown inFIG. 10 and asignal bus1055 can be used to electrically couple thecontroller1050 to the IE-sensor wafer1000. For example, thecontroller1050 can exchange IE-related data with one or more of theion energy analyzers1010 using thesignal bus1055.

In some embodiments, theion energy analyzer1010 can be used for determining the ion energy distribution (IED) of ions incident on a radio frequency (RF) biased wafer/substrate immersed in plasma. Theion energy analyzer1010 can include an entrance grid (not shown) exposed to the plasma, an electron rejection grid (not shown) disposed proximate to the entrance grid, and an ion current collector (not shown) disposed proximate to the electron rejection grid. The ion current collector can be coupled to an ion selection voltage source, configured in thecontroller1050, and configured to positively bias the ion current collector by an ion selection voltage, and the electron rejection grid can be coupled to an electron rejection voltage source, configured in thecontroller1050, and configured to negatively bias the electron rejection grid by an electron rejection voltage. In addition, an ion current meter, configured in thecontroller1050, can be coupled to the ion current collector to measure the ion current.

A plurality oftest chips1020 can be removably coupled at one or more second locations on the top surface of the IE-sensor wafer1000, and the second locations can be proximate to the first locations. For example, thetest chips1020 can include one or more of the exemplary patterned wafers (500a, and500b) having exemplary transistor stacks (501a,502a,501b, and502b) thereon, or one or more of the exemplary patterned wafers (500c, and500d) having exemplary transistor stacks (501c,502c,501d, and502d) thereon that can be created using a first DPCE processing sequence. In addition, thetest chips1020 can include one or more of the second exemplary patterned wafers (600a, and600b) having exemplary transistor stacks (601a,602a,601b, and602b) thereon, or one or more of the exemplary patterned wafers (600c, and600d) having exemplary transistor stacks (601c,602c,601d, and602d) thereon that can be created using a second DPCE processing sequence. Furthermore, thetest chips1020 can include one or more of the third exemplary patterned wafers (700a, and700b) having exemplary transistor stacks (701a,702a,701b, and702b) thereon that can be created using a third DPCE processing sequence.

FIG. 11 illustrates a method for using an IE-sensor wafer to obtain data for contact-etch procedures in accordance with embodiments of the invention.

In1110, an IE-sensor wafer1000 can be positioned on a wafer holder (220,FIG. 2 or320,FIG. 3) in a process chamber (210,FIG. 2 or310,FIG. 3) configured in a contact-etch subsystem shown inFIGS. 2A-2G orFIGS. 3A-3G.

In1115, one ormore test chips1020 can be removably coupled at one or more second locations on the top surface of the IE-sensor wafer1000, and the second locations can be proximate to the first locations. For example, thetest chips1020 can include one or more of the exemplary patterned wafers (500a, and500b) having exemplary transistor stacks (501a,502a,501b, and502b) thereon, or one or more of the exemplary patterned wafers (500c, and500d) having exemplary transistor stacks (501c,502c,501d, and502d) thereon that can be created using a first DPCE processing sequence. In addition, thetest chips1020 can include one or more of the second exemplary patterned wafers (600a, and600b) having exemplary transistor stacks (601a,602a,601b, and602b) thereon, or one or more of the exemplary patterned wafers (600c, and600d) having exemplary transistor stacks (601c,602c,601d, and602d) thereon that can be created using a second DPCE processing sequence. Furthermore, thetest chips1020 can include one or more of the third exemplary patterned wafers (700a, and700b) having exemplary transistor stacks (701a,702a,701b, and702b) thereon that can be created using a third DPCE processing sequence.

In1120, an (Ion Energy Optimized) IEO-etch procedure can be performed in which an (Ion Energy Optimized) IEO-plasma is created in at least one of the process chambers (210,FIG. 2 or310,FIG. 3).

In1125, when theion energy analyzers1010 configured in the IE-sensor wafer1000 comprise ion current collectors the ion current received by the ion current collector can be measured by thecontroller1050, and the ion current can stored as a function of the ion selection voltage on the ion selection grid. For example, the ion current collector can provide a dual function of receiving ion current for measurement and selecting the ions that contribute to the received ion current.

When theion energy analyzer1010 includes an entrance grid, the entrance grid can be exposed to plasma at a floating DC potential. When theion energy analyzer1010 includes an electron rejection grid proximate to the entrance grid, the electron rejection grid can be biased with a negative DC voltage to reject electrons from the plasma. When theion energy analyzer1010 includes an ion current collector proximate to the electron rejection grid, the ion current collector can be biased with a positive DC voltage, from thecontroller1050, to discriminate between ions reaching the ion current collector. When the IEO-plasma is created, one or more selected ion currents at the ion current collector can be measured by thecontroller1050. For example, the selected ion current can be stored, by thecontroller1050, as a function of the positive DC voltage on the ion current collector, and the positive DC voltage on the ion current collector can be varied. Then, the stored ion current data as a function of the ion selection voltage may be integrated, by thecontroller1050, to determine an IED to associate with the test circuit.

In1130, process data can be measured and stored during the IEO-etch procedure. For example, one or more process sensors (236,FIG. 2) or (336,FIG. 3) can be coupled to process chamber (210,FIG. 2) or (310,FIG. 3) to obtain performance data, andcontroller1050 can be coupled to the process sensors (236,FIG. 2) or (336,FIG. 3) to receive and analyze the performance data.

In1135, one or more of thetest chips1020 can be removed from the IE-sensor wafer after the IEO-etch procedure has been performed.

In1140, measurement data can be obtained for one or more of thetest chips1020 after the test chip102 has been removed from the IE-sensor wafer and the IEO-etch procedure has been performed. For example, Critical Dimension—Scanning Electron Microscopy (CD-SEM) data can be obtained, ODP data can be obtained, and Transmission Electron Microscopy (TEM) data can be obtained.

In1145, IE-related difference data can be determined using the measurement data and IE-related reference data. For example, the IE-related reference can be obtained from an IE-related data library.

In1150, the process recipe associated with the IEO-etch procedure can be identified as a verified IEO-process recipe when the difference data is less than or equal to an IEO-related threshold.

In1155, the process recipe associated with the IEO-etch procedure can be identified as a non-verified IEO-process recipe when the difference data is greater than the IEO-related threshold.

The CD DV can be a critical DV and can have associated DVs that modify the measurement due to the mechanisms at work during the DPCE processing sequences. SWA can be a primary modifier that increases in sensitivity as the angle become less than ninety degrees. In addition, the middle CD can be used if it gives the most accurate correlation to the final CD. Middle CD performs the best in simple terms because it averages the variation of the top and bottom CD measurements.

A second modifier of CD can be the BARC thickness variation across the wafer and water-to-wafer. BARC thickness can affect CD if the thickness is non-uniform because during the BARC etch the resist is continuing to be etched. A thinner BARC can give a shorter etch time, and thicker BARC can give a longer etch time, and a longer etch time will result in a smaller CD. Therefore, BARC non-uniformity can directly result in increased center to edge CD variation that will need to be modeled for control during the partial and final etch.

The IM data can be fed forward to one or more optimization controllers to calculate the value of manipulated variables (MV). The nonlinear model formulas associated with each controlled variable (CV) can be used with each CV target value. A quadratic objective function can utilize weighting factors to prioritize each CV term in the objective function, and an optimizer in the MIMO can be used to determine etch recipe by minimizing or maximizing the objective function with the constraints of MVs using nonlinear programming.

In some examples, one or more of the wafers can be processed using the adjusted recipes. For example, the adjusted recipes can include optimized MVs from the optimizer for the DPCE processing sequence. Then, measurement data can be obtained for one or more of the processed wafers. For example, measurements can be made at one or more sites on the wafer. The output CVs can be measured using the IM tool after the first DPCE processing sequence is performed and/or after the second DPCE processing sequence is performed. The data obtained from the DPCE processing sequences can be filtered and/or qualified. In addition, process errors can be calculated for the DPCE processing sequence. For example, errors (actual outputs minus model outputs) can be calculated for each CV. Next, feedback data items can be calculated for the DPCE processing sequence, and errors can be used to update the MIMO model CVs offsets using an exponentially weighted moving average (EWMA) filter. Then, new model offsets can be updated for the DPCE processing sequence and these offset values can be provided to the optimization controller to be used for compensating the disturbance for next run. For example, this offset can be used until a new update is calculated, and this procedure can be performed until the final patterned wafer is processed.

When send-ahead wafer are used, IM data can be obtained at intermediate points in the DPCE processing sequence. When new and/or additional measurement data, inspection data, and/or evaluation data is required, additional IM data can be obtained from one or more sites on the wafer. For example, measurement structures, such as periodic gratings, periodic arrays, and/or other periodic structures, on a wafer can be measured at one or more sites.

In some embodiments, the historical and/or real-time data can include IE maps, wafer-related maps, process-related maps, damage-assessment maps, reference maps, measurement maps, prediction maps, risk maps, inspection maps, verification maps, evaluation maps, particle maps, and/or confidence map(s) for one or more wafers. In addition, some IEO-etch procedures may use wafer maps that can include one or more Goodness Of Fit (GOF) maps, one or more thickness maps, one or more gate-related maps, one or more Critical Dimension (CD) maps, one or more CD profile maps, one or more material related maps, one or more structure-related maps, one or more sidewall angle maps, one or more differential width maps, or a combination thereof.

When wafer maps are created and/or modified, values may not be calculated and/or required for the entire wafer, and a wafer map may include data for one or more sites, one or more chip/dies, one or more different areas, and/or one or more differently shaped areas. For example, a processing chamber may have unique characteristics that may affect the quality of the processing results in certain areas of the wafer. In addition, a manufacturer may allow less accurate process and/or evaluation data for chips/dies in one or more regions of the wafer to maximize yield. When a value in a map is close to a limit, the confidence value may be lower than when the value in a map is not close to a limit. In addition, the accuracy values can be weighted for different chips/dies and/or different areas of the wafer. For example, a higher confidence weight can be assigned to the accuracy calculations and/or accuracy data associated with one or more of the previously used evaluation sites.

In addition, process result, measurement, inspection, verification, evaluation, and/or prediction maps associated with one or more processes may be used to calculate a confidence map for a wafer. For example, values from another map may be used as weighting factors.

Although only certain embodiments of this invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention.

Thus, the description is not intended to limit the invention and the configuration, operation, and behavior of the present invention has been described with the understanding that modifications and variations of the embodiments are possible, given the level of detail present herein. Accordingly, the preceding detailed description is not mean or intended to, in any way, limit the invention—rather the scope of the invention is defined by the appended claims.

Claims (19)

What is claimed:

1. A method for processing a wafer comprising:

receiving, by a processing system, a first set of patterned wafers and associated contact-etch (CE) data, each patterned wafer having a plurality transistor stacks and a plurality of additional layers thereon;

selecting a first patterned wafer from the first set of patterned wafers;

establishing a first double-pattern-contact-etch (DPCE) processing sequence for the selected first patterned wafer using the CE data;

determining if the first DPCE processing sequence includes a first contact-etch procedure;

performing the first contact-etch procedure when the first DPCE processing sequence includes the first contact-etch procedure, wherein a second set of patterned wafers is created when the first contact-etch procedure is performed using the first set of patterned wafers;

performing a first corrective action when the first DPCE processing sequence does not include the first contact-etch procedure;

determining if the first DPCE processing sequence includes an Ion Energy Optimized (IEO)-etch procedure;

performing the IEO-etch procedure when the first DPCE processing sequence includes the IEO-etch procedure, wherein the IEO-etch procedure uses a new etch subsystem having a new process chamber configured therein; and

performing a new corrective action when the first DPCE processing sequence does not include the IEO-etch procedure.

2. The method ofclaim 1, further comprising:

positioning the selected patterned wafer on a first wafer holder in a first process chamber;

creating a first contact-etch plasma in the first process chamber;

processing the selected patterned wafer using the first contact-etch plasma; and

obtaining first process sensor data while the selected patterned wafer is processed, wherein a first process sensor is coupled to the first process chamber and is configured to obtain the first process sensor data.

3. The method ofclaim 2, wherein performing the IEO-etch procedure comprises:

positioning the selected patterned wafer on a wafer holder in a process chamber;

creating an IEO-etch plasma in the process chamber;

processing the selected second patterned wafer using the IEO-etch plasma; and

obtaining process sensor data while the selected patterned wafer is processed, wherein a second process sensor is coupled to the process chamber and is configured to obtain the process sensor data.

4. The method ofclaim 2, wherein creating the first contact-etch plasma comprises:

establishing a first chamber pressure in the first process chamber, wherein the first chamber pressure ranges from about 12 mT to about 18 mT;

establishing a first edge temperature and a first center temperature for the first wafer holder, the first center temperature being between about 12 degrees Celsius and about 20 degrees Celsius, the first edge temperature being between about 8 degrees Celsius and about 12 degrees Celsius;

establishing a first edge backside pressure and a first center backside pressure using a dual backside gas system in the first wafer holder, the first center backside pressure being between about 15 Torr and about 25 Torr, the first edge backside pressure being between about 27 Torr and about 33 Torr;

providing a first process gas into the first process chamber during the first time, wherein the first process gas includes CF₄and CHF₃, a CF₄flow rate varying between about 60 sccm and about 100 sccm and a first CHF₃flow rate varying between about 40 sccm and about 60 sccm, wherein a gas plenum in the first process chamber is configured to provide the first process gas to one or more areas of a processing region;

providing a first radio frequency (RF) power to a center region in the first process chamber and providing a second RF power to an edge region in the first process chamber using a first power splitter coupled to two upper electrodes in the first process chamber, wherein a first RF source is coupled to the first power splitter, the first RF source operating in a frequency range from about 0.1 MHz. to about 200 MHz, the first RF power ranging from about 450 watts to about 550 watts and the second RF power ranging from about 10 watts to about 100 watts during the first time; and

providing a lower radio frequency (RF) power to a lower electrode in the first wafer holder using an RF generator and an impedance match network, the RF generator operating in a first frequency range from about 0.1 MHz. to about 200 MHz, the lower RF power ranging from about 90 watts to about 110 watts during the first time.

5. The method ofclaim 1, wherein performing the first corrective action comprises:

selecting a new patterned wafer from the first set of patterned wafers;

positioning the new patterned wafer on a new wafer holder in a new process chamber;

creating a new contact-etch plasma in the new process chamber;

processing the new patterned wafer using the new contact-etch plasma; and

obtaining new process sensor data while the new patterned wafer is processed, wherein a new process sensor is coupled to the new process chamber and is configured to obtain the new process sensor data.

6. The method ofclaim 1, further comprising:

determining if the first DPCE processing sequence includes a second contact-etch procedure;

performing the second contact-etch procedure when the first DPCE processing sequence includes the second contact-etch procedure, wherein the second contact-etch procedure uses a second etch subsystem having a second process chamber configured therein; and

performing a second corrective action when the first DPCE processing sequence does not include the second contact-etch procedure.

7. The method ofclaim 6, wherein performing the second contact-etch procedure comprises:

selecting an etched patterned wafer from a first set of etched patterned wafers; positioning the selected etched patterned wafer on a second wafer holder in the second process chamber;

creating a second contact-etch plasma in the second process chamber; processing the selected etched patterned wafer using the second contact-etch plasma; and

obtaining second process sensor data while the selected etched patterned wafer is processed, wherein a second process sensor is coupled to the second process chamber and is configured to obtain the second process sensor data.

8. The method ofclaim 6, wherein performing the second corrective action comprises:

selecting a new patterned wafer from the first set of patterned wafers;

positioning the new patterned wafer on a new wafer holder in a new process chamber;

creating a new contact-etch plasma in the new process chamber;

processing the new patterned wafer using the new contact-etch plasma; and

obtaining new process sensor data while the new patterned wafer is processed, wherein a new process sensor is coupled to the new process chamber and is configured to obtain the new process sensor data.

9. The method ofclaim 8, further comprising:

determining if the second (DPCE) sequence includes a new first contact-etch (CE) procedure;

performing the new first CE procedure when the second (DPCE) sequence includes the new first CE procedure, wherein the new first CE procedure uses a new first etch subsystem having a new first process chamber configured therein and a new first MIMO controller coupled thereto; and

performing a new first validation procedure when the second (DPCE) sequence does not include the new first CE procedure.

10. The method ofclaim 6, further comprising:

creating second simulation data for the second contact-etch procedure using a second Contact-Etch Multi-Input/Multi-Output (CE-MIMO) model, wherein the second CE-MIMO model includes a new first number (N_b) of new first Controlled Variables (CV_1b, CV_2b, . . . CV_Nb), a new second number (M_a) of new first Manipulated Variables (MV_1b, MV_2b, . . . MV_Mb), and a new third number (L_b) of new first Disturbance Variables (DV_1b, DV_2b, . . . DV_Lb), wherein (L_b, M_b, and N_b) are integers greater than one;

obtaining second sensor data during the second contact-etch procedure, wherein a second sensor is coupled to the second process chamber;

establishing second difference data by comparing the second simulation data to the second sensor data;

verifying the second contact-etch procedure when the second difference data is less than or equal to second threshold data; and

storing the second simulation data and/or the second sensor data when the second difference data is greater than the second threshold data.

11. The method ofclaim 10, further comprising;

determining second risk data for the second contact-etch procedure using the second difference data;

identifying the second contact-etch procedure as a verified contact-etch procedure when the second risk data is less than a second risk limit; and

identifying the second contact-etch procedure as a non-verified contact-etch procedure when the second risk data is not less than the second risk limit.

12. The method ofclaim 1, further comprising:

creating first simulation data for the first contact-etch procedure using a first Contact-Etch Multi-Input/Multi-Output (CE-MIMO) model, wherein the first CE-MIMO model includes a first number (N_a) of first Controlled Variables (CV_1a, CV_2a, . . . CV_Na), a second number (M_a) of first Manipulated Variables (MV_1a, MV_2a, . . . MV_Ma), and a third number (L_a) of first Disturbance Variables (DV_1a, DV_2a, . . . DV_La), wherein (L_a, M_a, and N_a) are integers greater than one;

obtaining first sensor data during the first contact-etch procedure, wherein a first sensor is coupled to a first process chamber;

establishing first difference data by comparing the first simulation data to the first sensor data;

verifying the first contact-etch procedure when the first difference data is less than or equal to first threshold data; and

storing the first simulation data and/or the first sensor data when the first difference data is greater than the first threshold data.

13. The method ofclaim 12, further comprising;

determining risk data for the first contact-etch procedure using the first difference data;

identifying the first contact-etch procedure as a verified contact-etch procedure when the risk data is less than a first risk limit; and

identifying the first contact-etch procedure as a non-verified contact-etch procedure when the risk data is not less than the first risk limit.

14. A method for processing a wafer using an Ion Energy (IE) controlled processing chamber, the method comprising:

receiving, by a processing system, a first set of patterned wafers and associated Ion Energy (IE) data, each patterned wafer having a first patterned etch-mask layer and a plurality of additional layers thereon;

determining an IE-related process sequence for the first set of patterned wafers using the IE data;

determining a first set of subsystems configured to perform the IE-related process sequence, wherein the first set of subsystems includes an etch subsystem having a first Ion Energy Controlled (IEC) process chamber configured therein and a Multi-Input/Multi-Output (MIMO) controller coupled thereto;

positioning a first patterned wafer on a first wafer holder in a first process chamber;

creating a first Ion Energy Optimized (IEO) plasma in the first process chamber; and

creating a new patterned wafer using a first contact-etch plasma, wherein first IE-sensor data is obtained while the new patterned wafer is created, wherein a first Ion Energy (IE) sensor is coupled to the first process chamber and is configured to obtain the first IE-sensor data.

15. The method as claimed inclaim 14, wherein

establishing first difference data by comparing the first IE-sensor data to historical IE-sensor data;

continuing to process the first patterned wafer when the first difference data is less than or equal to first threshold data; and

stopping the IE-related process sequence when the first difference data is greater than the first threshold data.

16. A method for establishing a Contact-Etch Multi-Input/Multi-Output (CE-MIMO) model for creating a plurality of Double Pattern (DP) structures on a patterned wafer, the method comprising:

selecting a first Double Pattern Contact-Etch (DPCE) processing sequence and a first CE-MIMO model, a first contact-etch procedure in the first DPCE processing sequence being configured to create a plurality of contact structures on a second set of wafers using a patterned etch-mask layer on a first set of wafers, wherein the first CE-MIMO model is configured to simulate the first contact-etch procedure in the first DPCE processing sequence and includes a plurality of first Controlled Variables (CVs), a plurality of first Manipulated Variables (MVs), and a plurality of first Disturbance Variables (DVs);

determining a first number (N_a) of first Disturbance Variables (DV_1a, DV_2a, . . . DV_Na) associated with the first CE-MIMO model, wherein N_ais an integer greater than one and at least one first contact-etch procedure is configured to provide one or more of the first (DV_1a, DV_2a, . . . DV_Na);

determining a first number (L_a) of first (CV_1a, CV_2a, . . . CV_La), associated with the first CE-MIMO model and ranges associated with the first (CV_1a, CV_2a, . . . CV_La), wherein La is an integer greater than one and the first (CV_1a, CV_2a, . . . CV_La), include a first etch-mask width;

establishing a first number (M_a) of first (MV_1a, MV_2a, . . . MV_Ma) associated with the first CE-MIMO model using one or more candidate process chambers, wherein M_ais an integer greater than one and the first (MV_1a, MV_2a, . . . MV_Ma), include one or more Within-Wafer Manipulated Variables (WiW-MVs) configured to change while a wafer is being processed, and one or more Wafer-to-Wafer- Manipulated Variables (W2W-MVs) configured to change after the wafer has been processed;

analyzing the first CE-MIMO model, wherein one or more statistical models are selected, one or more ranges are provided for the first (CV_1a, CV_2a, . . . CV_La) and the first (MV_1a, MV_2a, . . . MV_Ma), and one or more statistical analysis procedures are performed to establish Design of Experiments (DOE) data, wherein the statistical models are configured to associate one or more of the first (MV_1a, MV_2a, . . . MV_Ma), with one or more of the first (CV_1a, CV_2a, . . . CV_La);

determining one or more stability conditions for the first CE-MIMO model; and

optimizing the first CE-MIMO model using performance parameters associated with a first set of processing tools configured to perform the first DPCE processing sequence.

17. The method ofclaim 16, further comprising:

creating one or more steady-state linear gain matrices (G) using the DOE data associated with the first DPCE processing sequence, wherein each gain matrix includes two or more of the first (MV_1a, MV_2a, . . . MV_Ma), and two or more of the first (CV_1a, CV_2a, . . . CV_La);

calculating one or more Relative Gain Arrays (RGA) using one or more steady-state linear gain matrices (G), wherein RGA=G

(G⁻¹)^Tand

denotes element-by-element multiplication; and

optimizing one or more sets of first (MV_1a, MV_2a, . . . MV_Ma), using one or more pairing rules.

18. The method ofclaim 16, wherein the calculating one or more Relative Gain Arrays (RGA) comprises:

$\lambda \mathrm{ij}=\frac{{\left[\frac{\partial {\mathrm{CV}}_i}{\partial {\mathrm{MV}}_j}\right]}_{{\mathrm{MV}}_{k,k\ne j}}}{{\left[\frac{\partial {\mathrm{CV}}_i}{\partial {\mathrm{MV}}_j}\right]}_{{\mathrm{CV}}_{k,k\ne j}}}=\frac{\mathrm{Gain}\left(\mathrm{open}-\mathrm{loop}\right)}{\mathrm{Gain}\left(\mathrm{closed}-\mathrm{loop}\right)}$

wherein i=1,2, . . . , n and j=1,2, . . . , n, and wherein (∂CV_i/∂MV_j)_mvis an open-loop gain between CV_iand MV_J, and (∂CV_i/∂MV_j)_cvis a closed loop gain.

19. The method ofclaim 16, wherein the one or more stability conditions are determined using a Niederlinski Stability Theorem wherein:

$\mathrm{NST}=\frac{\det \left(G\right)}{\prod _{i=1}^n{g}_{\mathrm{ii}}}<0$

wherein NST is a Niederlinski Stability Index, G is a gain matrix, det(G) is a determinant of the gain matrix, and g_iiis diagonal elements of the gain matrix.

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