US8330195B2 - Multilayer image sensor pixel structure for reducing crosstalk - Google Patents

Abstract

An image sensor pixel includes a substrate, a first epitaxial layer, a collector layer, a second epitaxial layer and a light collection region. The substrate is doped to have a first conductivity type. The first epitaxial layer is disposed over the substrate and doped to have the first conductivity type as well. The collector layer is selectively disposed over at least a portion of the first epitaxial layer and doped to have a second conductivity type. The second epitaxial layer is disposed over the collector layer and doped to have the first conductivity type. The light collection region collects photo-generated charge carriers and is disposed within the second epitaxial layer. The light collection region is also doped to have the second conductivity type.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a Divisional of U.S. patent application Ser. No. 12/430,006, filed on Apr. 24, 2009.

This patent application is related to commonly-owned U.S. patent application Ser. No. 12/109,134, filed Apr. 24, 2008, entitled MULTILAYER IMAGE SENSOR PIXEL STRUCTURE FOR REDUCING CROSSTALK.

BACKGROUND

Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, as well as in, medical, automobile, and other applications. The technology used to manufacture image sensors, and in particular, complementary metal-oxide-semiconductor (“CMOS”) image sensors (“CIS”), has continued to advance at great pace. For example, the demands of higher resolution and lower power consumption have encouraged the further miniaturization and integration of these image sensors.

FIG. 1 illustrates a conventional front side illuminatedCIS pixel100. The front side ofCIS pixel100 is the side of aP+ substrate105 upon whichpixel circuitry130 is disposed and over a whichmetal stack110 for redistributing signals is formed. The metal layers (e.g., metal layer M1 and M2) are patterned in such a manner as to create an optical passage through which light (indicated by dashed arrows) incident on the front side ofCIS pixel100 can reach a photosensitive or photodiode (“PD”)region115. To implement a color CIS, the front side ofCIS pixel100 further includes acolor filter layer120 disposed under amicrolens125. Microlens125 aids in focusing the light ontoPD region115.

CIS pixel100 includes pixel circuitry130 (indicated by a dashed rectangle) disposed adjacent toPD region115 within a P doped well.Pixel circuitry130 provides a variety of functionality for regular operation ofCIS pixel100. For example,pixel circuitry130 may include circuitry to commence acquisition of an image charge withinPD region115, to reset the image charge accumulated withinPD region115 toready CIS pixel100 for the next image, or to transfer out the image data acquired byCIS pixel100.

FIG. 2 illustrates details of a portion of two neighboringCIS pixels100 formed within a P− epitaxial (“epi”)layer140 disposed overP+ substrate105 and separated by shallow trench isolation regions (STI). When a photo-generated charge carrier is formed shallow within the CIS pixel (e.g., a first charge carrier150), it experiences a strong upward attractive force (shown by arrows200) towardsPD region115, due to a depletion region or P-N junction found between the PD and the surrounding epitaxial layer. When a photo-generated charge carrier is formed deeper within the CIS pixel (e.g., a second charge carrier155), it initially experiences a weaker upward repulsive force due to the presence of a dopant gradient at the junction between P−epi layer140 andP+ substrate105.

Crosstalk is a serious problem in image sensors. There are generally three components to crosstalk: a) electrical crosstalk, b) optical crosstalk, and c) spectral crosstalk. Electrical crosstalk results when charge carriers generated in one pixel of an image sensor are collected by a neighboring pixel of the image sensor. Optical crosstalk can be caused by the diffraction and/or scattering of light off of metal lines and at interfaces between the dielectric layers withinmetal stack110. Spectral crosstalk results from the finite (nonzero) transmittance ofcolor filter120 to wavelengths outside its target pass band, such as the finite transmittance of green and blue wavelengths through a red filter.

One form of electrical crosstalk is lateral drift of photo-generated charge carriers created deep in the semiconductor epitaxial layers (e.g., second charge carrier155). As these photo-generated charge carriers rise, they can drift laterally and end up collected in the PD region of a neighboring pixel. Blooming is another form of electrical crosstalk characterized by the lateral diffusion of charge carriers when a PD region becomes full or saturated with charge carriers. Blooming is most commonly experienced in high luminous environments. Photo carriers that are generated near asaturated PD region115 will not be collected and therefore remain free to diffuse laterally into a neighboring pixel. Blooming results in the blurring of edges in still images and streaking in moving images. Both forms of electrical crosstalk are due to charge carriers generated in one pixel being collected by a neighboring pixel.

SUMMARY

In one embodiment, electrical crosstalk between image sensor pixels is reduced relative to traditional image sensor pixels by disposing a collector layer below the photodiode regions which acts to prevent carriers formed deep within the photodiode regions from being collected in neighboring photodiode regions. Under proper bias conditions a field is established by which photo-generated carriers are swept away from locations deep within the photodiode regions and collected by the collector layer below the photodiode regions in order to prevent their collection by adjacent photodiodes.

In another embodiment electrical crosstalk between image sensor pixels is reduced relative to traditional image sensor pixels by disposing a barrier layer at least partially covering a collector layer, the barrier layer acting to prevent carriers formed deep within the photodiode regions from being collected in neighboring photodiode regions. Under certain bias conditions a field is established by which photo-generated carriers are swept away from locations deep within the photodiode regions and collected by the collector layer below the photodiode regions in order to prevent their collection by adjacent photodiodes. Additionally there is created a field between the barrier layer and the photodiode region that provides for increased collection within the photodiode regions of carriers generated moderately deep within photodiode regions.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

FIG. 1 is a cross sectional view of a conventional front side illuminated CMOS image sensor pixel.

FIG. 2 is a cross sectional view of two neighboring CMOS image sensor pixels illustrating a mechanism for electrical crosstalk.

FIG. 3 is a cross sectional view of two neighboring CMOS image sensor pixels having a structure that reduces electrical crosstalk, in accordance with an embodiment.

FIG. 4 is a cross sectional view of two neighboring CMOS image sensor pixels having a structure that reduces electrical crosstalk, in accordance with an embodiment.

FIG. 5 is a cross sectional view of two neighboring image sensor pixels having a structure that reduces electrical crosstalk, in accordance with an embodiment.

FIG. 6 is a cross sectional view of two neighboring image sensor pixels having a structure that reduces electrical crosstalk, in accordance with an embodiment.

FIG. 7 is a cross sectional view of two neighboring image sensor pixels having a structure that reduces electrical crosstalk, in accordance with an embodiment.

FIG. 8 is a functional block diagram illustrating a sensor, in accordance with an embodiment.

FIG. 9 is a circuit diagram illustrating sample pixel circuitry of two image sensor pixels within an image sensor array, in accordance with an embodiment.

FIG. 10 is a block diagram illustrating an imaging system with reduced electrical crosstalk, in accordance with an embodiment.

DETAILED DESCRIPTION

Embodiments of a pixel, an image sensor, an imaging system, and methods of fabrication of a pixel, image sensor, and imaging system having improved electrical crosstalk characteristics are described herein. In the following description numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects. For example, although not illustrated, it should be appreciated that image sensor pixels (reference numbers300,400,500,600, and700 in the figures) may include a number of material layers disposed on the front side, such as those illustrated inFIG. 1 (e.g.,pixel circuitry130, a dielectric layer,metal stack110,color filter120,microlens125, etc.), as well as other conventional layers (e.g., antireflective films, etc.) used for fabricating CIS pixels. Furthermore, the illustrated cross sections of image sensor pixels illustrated herein do not illustrate the pixel circuitry associated with each pixel. However, it should be appreciated that each pixel may include pixel circuitry (e.g., as shown inFIG. 9) coupled to its collection region for performing a variety of functions, such as commencing image acquisition, resetting accumulated image charge, transferring out acquired image data, or otherwise.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Referring again to the figures,FIG. 3 is a cross sectional view of two neighboringCIS pixels300A and300B (collectively pixels300) having a multilayer structure that reduces electrical crosstalk, in accordance with an embodiment. The illustrated embodiment of pixels300 include asubstrate305, agradient junction307, an epitaxial (“epi”)layer315,collection regions320, and abiasing circuit325.Collection regions320 ofpixels300A and300B are isolated from each other by shallow trench isolations (“STI”)360 anddopant wells330. In the illustrated embodiment, a pinning layer335 (e.g., P type pinning) overlayscollection regions320 to passivate their surfaces.

In the embodiment illustrated inFIG. 3,substrate305 is a silicon substrate highly doped with N type dopants (e.g., Arsenic; Phosphorous) whileepi layer315 is a silicon layer lightly doped with P type dopants (e.g., Boron).Collection regions320 represent photosensitive regions (e.g., photodiode), which are doped with the same conductivity type assubstrate305.Dopant wells330 are P wells for isolatingadjacent collection regions320 and preventing a direct interface betweenSTI360 andcollection regions320. However, it should be appreciated that the conductivity types of all the elements can be swapped such thatsubstrate305 is P+ doped,epi layer315 is N− doped,collection regions320 are P+ doped, anddopant wells330 are N doped.

In one embodiment, electrical crosstalk between image sensor pixels is reduced relative to traditional CIS pixels by disposing a P− epi layer over an N type substrate. N type substrates may include silicon wafers doped with high concentrations of Arsenic or Phosphorous (also referred to as N+ substrates). Traditional CIS pixels typically use P type epitaxial layers (e.g., P− epi layer315) disposed on P+ substrates When using N+ substrates, Ptype epi layer315 may be fabricated by growing the P type epi layer on the N+ substrate. Electric field340 (indicated by arrows) formed at the interface between P−epi layer315 andN+ substrate305 acts as a barrier to photo generated charge carriers (e.g., photo electrons) that are formed inN+ substrate305. This barrier lowers the probability that a charge carrier formed deep in the CIS pixel structure can diffuse to anadjacent collection region320. Similarly, this structure reduces blooming. Ifcollection region320 is full, uncollected electrons are drawn intoN+ substrate305 byelectric field340, rather than diffusing down arounddopant wells330 and into a neighboringcollection region320.

The junction between P−epi layer315 andN+ substrate305 is not infinitely abrupt. The N+ substrate is typically heavily doped with As or P. During the epitaxial growth, which is typically done at high temperatures (>800 C), N type dopants may diffuse into P−epi layer315. In addition, thermal processing associated with CIS fabrication increases the N type dopant diffusion intoepi layer315. As such, the junction betweensubstrate305 andepi layer315 is graded (illustrated as gradient junction307).Electric field340, and therefore the field barrier generated to reduce crosstalk and blooming, is dependent on the diffusion gradient profile. The final thickness ofepi layer315 after diffusion is thus dependent on the diffusion gradient profile. Becausecollection regions320 are disposed withinepi layer315, the light collection efficiency and the degree of lateral charge carrier diffusion and blooming will vary with the CIS process thermal budget and the epitaxial layer growth process.

During operation, photo-generated charge carriers that are created shallow withinepi layer315 are collected by the electric field generated by the depletion region at the P-N junction betweencollection region320 andepi layer315. In contrast, photo-generated charge carriers that are created deep withinepi layer315 have a statistically increased chance of being drawn intosubstrate305 byelectric field340 where they recombine without contributing to crosstalk. Similarly, photo-generated charge carriers that are created even deeper withinsubstrate305 are inhibited from diffusing up into a neighboringcollection region320 by the potential barrier created byfield340. Finally, in one embodiment,substrate305 can be positively biased relative toepi layer315 andcollection regions320 by biasingcircuit325. The presence of the biasing operates to further impede photo-electrons from crossing the potential barrier offield340. It should be appreciated that in an embodiment wheresubstrate305 is a P+ substrate andepi layer315 is an N− epi layer, biasingcircuit325 would be used to negatively biassubstrate305 relative toepi layer315.

FIG. 4 is a cross sectional view of two neighboringCIS pixels400A and400B (collectively pixels400) having a multilayer structure that reduces electrical crosstalk, in accordance with an embodiment. Pixels400 are similar to pixels300 with the following exceptions. Pixels400 include anadditional buffer layer410 having the same conductivity type doping as asubstrate405, but in a lesser concentration. Since the N type dopant concentration interface is not infinitely abrupt, agradient junction407 represents a graded dopant profile fromN+ substrate405 to a N−buffer layer410. In one embodiment, pixels400 may also include biasingcircuit425 tobias substrate405 relative tocollection regions420 and an epi layer415 (e.g., positive for N type substrate and collection regions or negatively for a P type substrate and collection regions).

The depletion region formed at the interface of N−buffer layer410 and P− epilayer415 generates anelectric field414, which draws deep photo-electrons intobuffer layer410 where they can recombine. In addition, adopant gradient field416 is generated atgradient junction407, which also pulls photo-electrons generated inbuffer layer410 intosubstrate405 or impedes the diffusion of photo-electrons generated insubstrate405 from migrating intobuffer layer410 and from there intoepi layer415.

Similar toepi layer415,buffer layer410 is an epitaxial layer grown oversubstrate405 and serves a dual purpose. First,buffer layer410 traps deep or excess photo-electrons resulting in a reduction in crosstalk and blooming. Second,buffer layer410 serves as an N type diffusion buffer, preventing the high concentration N type dopants ofsubstrate405 from diffusing into the Ptype epi layer415 during epitaxial growth cycles and the other high temperature CIS processes. The dopant concentration inbuffer layer410 is significantly lower thansubstrate405, resulting in significantly less N type dopant diffusion into the Ptype epi layer415. As such,buffer layer410 can increase the thermal budget of pixels400 during fabrication.Buffer layer410 adds process margin to device fabricated on N+ substrates, which eases process development and process transfers. In addition, this multilayer structure is less dependent on a particular wafer vendor's growth conditions, allowing wider sources of starting material.

The lower thickness limit tobuffer layer410 is determined by the amount of dopant diffusion expected fromsubstrate405. However, the upper limit to the thickness ofbuffer layer410 is not limited by the fabrication process. Photo-electrons present inbuffer layer410 will more easily diffuse tosubstrate405 than cross the P-N junction barrier offield414. Therefore a wide margin can be used in choosing the thickness ofbuffer layer410. For example,buffer layer410 may range from approximately 0.3 μm to 10 μm. The use of additional layers, in conjuction with optional applied bias from biasingcircuit425, to create additional barriers to diffusion of photo-generated carriers, may be further advantageous in reducing electrical crosstalk between image sensor pixels. The use of such additional layers is described herein in the following embodiments.

FIG. 5 is a cross sectional view of two neighboringimage sensor pixels500A and500B (collectively pixels500) having a multilayer structure that reduces electrical crosstalk, in accordance with an embodiment. Pixels500 are similar to pixels400 with the following exceptions. Pixels500 include abarrier layer512 disposed between anepi layer515 andbuffer layer510.Barrier layer512 has the same conductivity type as epi layer515 (e.g., P type), but with a greater dopant concentration thanepi layer515. In an alternative embodiment, pixels500 includebarrier layer512, but lackbuffer layer510. Fabrication of such an embodiment may have less complexity but may also have reduced performance.

Barrier layer512 serves at least two purposes. On the photodiode side,barrier layer512 creates anelectric field513 that drives photo-electrons present inepi layer515 up towardscollection regions520. On the substrate side, the depletion region formed at the interface ofbarrier layer512 andbuffer layer510 creates anelectric field514 which draws deep photo-generated carriers into the buffer layer where they recombine.Electric field514 is also a potential barrier that photo-generated carriers inbuffer layer510 must overcome to diffuse intoepi layer515. Accordingly,barrier layer512 impedes deep photo-electrons from migrating into neighboringcollection region520 while promoting the collection of shallow photo-electrons by driving them upwards towardcollection region520 and mitigating lateral drift. The size of the potential barrier formed byelectric field514 is dependent upon the dopant concentrations ofbuffer layer510 andbarrier layer512.Barrier layer512 may be doped via ion implantation ofbuffer layer510, or grown epitaxially using controlled growth conditions. In one embodiment, pixels500 may also include abiasing circuit525 tobias substrate505 relative tocollection regions520 and epi layer515 (e.g., positive for N type substrate and N type collection regions or negatively for a P type substrate and P type collection regions).

FIG. 6 is a cross sectional view of two neighboringimage sensor pixels600A and600B (collectively pixels600) having a multilayer structure that reduces electrical crosstalk, in accordance with an embodiment. The illustrated embodiment of pixels600 includes asubstrate605, an epitaxial (“epi”)layer607, acollector layer610, abarrier layer612, anepi layer615,collection regions620, and abiasing circuit625. Thecollection regions620 of each pixel600 are isolated from each other withSTI660 anddopant wells630. In the illustrated embodiment, a pinning layer635 (e.g., P type pinning) overlayscollection regions620 to passivate their surfaces.

Referring still to the embodiment illustrated inFIG. 6,substrate605 is a silicon substrate highly doped with P type dopants (e.g., Boron) while epilayers607 and615 are silicon layers lightly doped with P type dopants (e.g., Boron).Collector layer610 is doped with N type dopants.Barrier layer612 is doped with P type dopants, but with a greater dopant concentration thanepi layer615.Collection regions620 represent photosensitive regions (e.g., photodiodes), which are doped with the N-type dopants.Dopant wells630 are P wells for isolatingadjacent collection regions620 and preventing a direct interface betweenSTI660 andcollection regions620. In oneembodiment dopant wells630 optionally extend down to reach barrier layer612 (illustrated inFIG. 6). By electricallycoupling dopant wells630 tobarrier layer612, excess charges that are formed or migrate intodopant wells630 are electrostatically carried away fromcollection regions620 and drawn down intocollector layer610.

It should be appreciated that the conductivity types of all the elements can be swapped such thatsubstrate605 is N+ doped,epi layer615 is N− doped,collection regions620 are P doped,dopant wells630 are N doped,collector layer610 is P doped, andbarrier layer612 is N doped. In such a case any applied bias voltage at biasingcircuit625 would have a polarity opposite that illustrated inFIG. 6.

Barrier layer612 serves at least two purposes. On the photodiode side,barrier layer612 creates anelectric field613 that drives photo-electrons present inepi layer615 up towardscollection regions620. On the substrate side, the depletion region formed at the interface ofbarrier layer612 and buriedcollector layer610 creates anelectric field614 that draws deep photo-generated carriers into the buried collector layer where they recombine.Electric field614 is also a potential barrier that photo-generated carriers incollector layer610 must overcome to diffuse intoepi layer615. Accordingly,barrier layer612 impedes deep photo-electrons from migrating into a neighboringcollection region620 while promoting the collection of shallow photo-electrons by driving them towardscollection region620 and mitigating their lateral migration. The size of the potential barrier is dependent upon the thickness and dopant concentrations ofbarrier layer612.Barrier layer612 may have a thickness of approximately 0.3 μm to 10 μm and a doping concentration of approximately 2×10¹⁶atoms/cm³to 2×10¹⁸atoms/cm³.

Collector layer610 may have a thickness of approximately 0.3 μm to 10 μm and a dopant concentration of approximately 1×10¹⁶atoms/cm³to 1×10¹⁸atoms/cm³. In one embodiment, the doping concentration ofcollector layer610 is less than the doping concentration ofbarrier layer612. Of course, pixels600 may also include abiasing circuit625 tobias collector layer610 relative to epi layer615 (e.g., positive for N type collection regions or negatively for P type collection regions).

During operation of image sensor pixel600, photo-generated charge carriers that are created shallow withinepi layer615 are collected byelectric field618 generated by the depletion region at a P-N junction formed betweencollection region620 andepi layer615. In contrast, photo-generated charge carriers that are created deep withinepi layer615 may either be driven up towardscollection regions620 byelectric field613 or be drawn intocollector layer610 byelectric field614 where they recombine without contributing to crosstalk. Also, whencollection regions620 have reached their maximum capacity, any additional carriers may overcomeelectric field613 and be drawn byelectric field614 intocollector layer610 without contributing to blooming. Similarly, photo-generated charge carriers that are created even deeper withincollector layer610,epi layer607, andsubstrate605 are inhibited from diffusing up into a neighboringcollection region620 by the potential barrier created byelectric field614. Finally, in one embodiment,collector layer610 can be positively biased relative toepi layer615 andcollection regions620 by biasingcircuit625. The presence of the biasing operates to further impede photo-electrons from crossing the potential barrier offield614. Epi layers607 and615, andsubstrate605 may typically be electrically grounded but depending on the application other structures may be grounded as well. It should be appreciated that in an embodiment wherecollector layer610 is P+ doped andepi layer615 is an N− epi layer, the biasingcircuit625 would negatively biassubstrate610 relative toepi layer615.

FIG. 7 is a cross sectional view of two neighboringimage sensor pixels700A and700B (collectively pixels700) having a multilayer structure that further reduces electrical crosstalk, in accordance with an embodiment. Pixels700 are similar to pixels600 with the following exceptions.Collector layer710 is formed by ion implantation of selected regions ofepi layer707, resulting in the creation of electrical pass-through702 betweenbarrier layer712 andepi layer707 at selected locations. Electrical pass-through702 is an area ofepi layer707 that is not selected to becomecollector710 by ion implantation. Electrical pass-through702 allows for more efficient draining of electrical carriers fromepi layer707 intobarrier layer712. In an embodiment wherebarrier layer712 is doped P type, photon generated holes may be improperly drained frombarrier layer712 without the presence of electrical pass-through702. Electrical pass-through702 may be maintained alongbarrier layer712 in a specific pattern (e.g. under pixels having one or more specific color filters) or they could be placed less frequently and/or randomly within the array. Other design parameters for electrical pass-through702 such as density and size depend, for example, on the barrier layer resistance, the number of neighboring pixels within a pixel array, and the size of eachcollection region720.

FIG. 8 is a functional block diagram illustrating aCIS800, in accordance with an embodiment. The illustrated embodiment ofCIS800 includespixel array805 having improved electrical crosstalk characteristics,readout circuitry810,function logic815, andcontrol circuitry820.

Pixel array805 is a two-dimensional (“2D”) array of image sensor pixels (e.g., pixels P1, P2 . . . , Pn). In one embodiment, each pixel represents any of pixels300,400,500,600 or700, illustrated inFIGS. 3-7. In one embodiment, each pixel is a CIS pixel. In one embodiment,pixel array805 includes a color filter array including a color pattern (e.g., Bayer pattern or mosaic) of red, green, and blue filters. As illustrated, each pixel is arranged into a row (e.g., rows R1 to Ry) and a column (e.g., column C1 to Cx) to acquire image data of a person, place, or object, which can then be used to render a 2D image of the person, place, or object.

After each pixel has acquired its image data or image charge, the image data is readout byreadout circuitry810 and transferred to functionlogic815.Readout circuitry810 may include amplification circuitry, analog-to-digital (“ADC”) conversion circuitry, or otherwise.Function logic815 may simply store the image data or even manipulate the image data by applying post image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise). In one embodiment,readout circuitry810 may readout a row of image data at a time along readout column lines (illustrated) or may readout the image data using a variety of other techniques (not illustrated), such as a column/row readout, a serial readout, or a full parallel readout of all pixels simultaneously.

Control circuitry820 is connected withpixel array805 to control operational characteristic ofpixel array805. For example,control circuitry820 may generate a shutter signal for controlling image acquisition. In one embodiment, the shutter signal is a global shutter signal for simultaneously enabling all pixels withinpixel array805 to simultaneously capture their respective image data during a single acquisition window. In an alternative embodiment, the shutter signal is a rolling shutter signal whereby each row, column, or group of pixels is sequentially enabled during consecutive acquisition windows.

FIG. 9 is a circuit diagram illustratingpixel circuitry900 of two four-transistor (“4T”) pixels within a pixel array, in accordance with an embodiment.Pixel circuitry900 is one possible pixel circuitry architecture for implementing each pixel withinpixel array805 ofFIG. 8. However, it should be appreciated that the embodiments described herein are not limited to 4T pixel architectures; rather, one of ordinary skill in the art having the benefit of the instant disclosure will understand that the present teachings are also applicable to 3T designs, 5T designs, and various other pixel architectures.

InFIG. 9, pixels Pa and Pb are arranged in two rows and one column. The illustrated embodiment of eachpixel circuitry900 includes a photodiode PD, a transfer transistor T1, a reset transistor T2, a source-follower (“SF”) transistor T3, and a select transistor T4. During operation, transfer transistor T1 receives a transfer signal TX, which transfers the charge accumulated in photodiode PD to a floating diffusion node FD. In one embodiment, floating diffusion node FD may be coupled to a storage capacitor for temporarily storing image charges.

Reset transistor T2 is coupled between a power rail VDD and the floating diffusion node FD to reset the pixel (e.g., discharge or charge the FD and the PD to a preset voltage) under control of a reset signal RST. The floating diffusion node FD is coupled to control the gate of SF transistor T3. SF transistor T3 is coupled between the power rail VDD and select transistor T4. SF transistor T3 operates as a source-follower providing a high impedance connection to the floating diffusion FD. Finally, select transistor T4 selectively couples the output ofpixel circuitry900 to the readout column line under control of a select signal SEL.

In one embodiment, the TX signal, the RST signal, and the SEL signal are generated bycontrol circuitry820. In an embodiment wherepixel array805 operates with a global shutter, the global shutter signal is coupled to the gate of each transfer transistor T1 in theentire pixel array805 to simultaneously commence charge transfer from each pixel's photodiode PD. Alternatively, rolling shutter signals may be applied to groups of transfer transistors T1.

FIG. 10 illustrates animaging system1000 that utilizes aCMOS image sensor1100 having image sensor pixel structures providing reduced electrical crosstalk, according to any of the embodiments disclosed herein.Image system1000 further includesimaging optics1200 for directing light from an object to be imaged ontoCMOS image sensor1100, and may also include asignal processor1300 for producing processed image data for display onoptional display1400.

The above description of illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. While specific embodiments are described herein for illustrative purposes, various modifications are possible within the scope, as those skilled in the relevant art will recognize. These modifications can be made in light of the above detailed description. Examples of some such modifications include dopant concentration, layer thicknesses, and the like. Further, although the embodiments illustrated herein refer to CMOS sensors using frontside illumination, it will be appreciated that they may also be applicable to CMOS sensors using backside illumination.

The terms used in the following claims should not be construed to limit the disclosure to the specific embodiments disclosed in the specification. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (11)

1. A method of operating an image sensor, comprising:

collecting charge carriers within collection regions disposed within a first P type epitaxial layer in response to light incident on the image sensor;

generating a first field at a junction between an N type collector layer and a P type barrier layer to draw excess charge carriers generated within the P type barrier layer away from the collection regions into the N type collector layer, wherein the N type collector layer and the P type barrier layer are disposed between a substrate layer and the first P type epitaxial layer, wherein a second P type epitaxial layer is disposed between the substrate layer and the N type collector layer;

generating a second field at a junction between the P type barrier layer and the first P type epitaxial layer to push photo-electrons generated within the first P type epitaxial layer towards the collection regions; and

electrically coupling the second P type epitaxial layer to the P type barrier layer via electrical pass-throughs selectively disposed through the N type collector layer.

2. The method ofclaim 1, wherein the image sensor comprises a complementary metal-oxide-semiconductor (“CMOS”) image sensor.

3. The method ofclaim 1, wherein the P type barrier layer is electrically coupled to P wells separating adjacent collection regions, the method further comprising:

electrostatically drawing excess charge carriers within the P wells down through the barrier layer towards the collector layer.

4. The method ofclaim 1, wherein the P type barrier layer has a higher concentration of P type dopants than the first P type epitaxial layer, wherein the second field comprises a P type dopant concentration gradient, and wherein the first field comprises an electrostatic field due to a depletion region.

5. The method ofclaim 1, further comprising positively biasing the N type collector layer relative to the P type barrier layer.

6. The method ofclaim 1, wherein the substrate layer comprise a P type substrate.

7. The method ofclaim 1, wherein the N type collector layer has a dopant concentration of approximately 10¹⁶atoms/cm³to 10¹⁷atoms/cm³.

8. The method ofclaim 1, wherein the N type collector layer is about 0.3 μm to 10 μm thick.

9. The method ofclaim 1, wherein the P type barrier layer has a dopant concentration of approximately 10¹⁷atoms/cm³to 10¹⁸atom/cm³.

10. The method ofclaim 1, wherein the P type barrier layer has a thickness of approximately 0.3 um to 1.0 um.

11. A method of operating an image sensor, comprising: collecting charge carriers within collection regions disposed within a first N type epitaxial layer in response to light incident on the image sensor; generating a first field at a junction between an P type collector layer and a N type barrier layer to draw excess charge carriers generated within the N type barrier layer away from the collection regions into the P type collector layer, wherein the P type collector layer and the N type barrier layer are disposed between a substrate layer and the first N type epitaxial layer, wherein a second N type epitaxial layer is disposed between the substrate layer and the P type collector layer; generating a second field at a junction between the N type barrier layer and the first N type epitaxial layer to push photo-generated charge carriers generated within the first N type epitaxial layer towards the collection regions; and electrically coupling the second N type epitaxial layer to the N type barrier layer via electrical pass-throughs selectively disposed through the P type collector layer.

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