US8325072B2 - Calibration circuit and method for calibrating capacitive compensation in digital-to-analog converters - Google Patents

Abstract

A digital-to-analog converter converts a digital input signal into an analog output signal. The digital-to-analog converter includes an input selector configured to input the digital input signal and an output terminal configured to output the analog signal. An array of current source cells is provided. Each current source cell includes a current source transistor having a gate terminal and a source terminal, a current source switch for coupling the source terminal to the output terminal based on the digital input signal, and a compensation capacitor configured to compensate a capacitive feedback between the gate terminal and the source terminal when the source terminal is coupled to the output terminal. At least one of the current source cells further includes a calibration circuit configured to detect a voltage variation at the gate terminal and provide a compensation voltage for the compensation capacitor.

Description

TECHNICAL FIELD

Embodiments described herein relate to an electronic circuit for converting digital input signals into analog output signals, and in particular relate to a single-ended digital-to-analog converter having switchable current source cells for converting a digital input signal into an analog output signal and a method for converting a digital input signal into an analog output signal.

BACKGROUND

Digital-to-analog converters (DACs) for converting a digital input signal into an analog output signal may include a plurality of current source cells which are controlled by a digital input signal. Output currents of the individual current source cells are added up so that a sum current is provided as an analog output signal. Furthermore, digital-to-analog converters may be designed in single-ended and in differential set-ups.

Single-ended digital-to-analog converters have lower power consumption as compared to differential digital-to-analog converters. Single-ended digital-to-analog converters, however, may provide a distorted output signal due to a capacitive feedback (capacitance feedback) into a gate of a current source transistor provided in a current source cell, when the current source cell is switched to an output line. Thus, when summing up individual currents from switched current source cells, compensation of capacitive feedback is an issue.

SUMMARY

Embodiments described herein refer inter alia to a digital-to-analog converter (DAC) for converting a digital input signal into an analog output signal. An input selector is provided which is configured to input the digital input signal which then may be used for controlling the DAC. Furthermore, an output terminal is provided which is configured to output the analog signal. According to an embodiment which can be combined with other embodiments described herein, the DAC is provided as a single-ended DAC.

Moreover, the DAC includes an array of current source cells, each current source cell including a current source transistor having a gate terminal and a source terminal. The current source transistor provides an output on the basis of the digital input signal. In order to provide an output, a current source switch is actuated, which is configured to couple the source terminal of the current source transistor to the output terminal on the basis of the digital input signal. Furthermore, each current cell includes a compensation capacitor configured to compensate a capacitive feedback between the gate terminal and the source terminal when the source terminal is coupled to the output terminal. At least one current source cell of the array of current source cells further includes a calibration circuit configured to detect a voltage variation at the gate terminal, which is an input bias node of the current source cell. The voltage variation at the gate terminal may be detected when the source terminal is coupled to the output terminal so that a compensation voltage may be provided for charging the compensation capacitor.

Furthermore, embodiments described herein refer inter alia to a compensation circuit for compensating a capacitive feedback between a gate terminal and a source terminal of the current source transistor. The source terminal is switchable to an output terminal for outputting a current which then is provided for external circuit units. The compensation circuit includes a compensation voltage source which may provide a compensation voltage, a compensation capacitor which is coupled between the gate terminal and the compensation voltage source, and a detection circuit coupled to the compensation voltage source and configured to detect a voltage variation at the gate terminal, when the source terminal is switched to the output terminal for outputting the current. Furthermore, the compensation voltage may be adjusted on the basis of the detected voltage variation at the gate terminal of the current source transistor so that the capacitive feedback is compensated.

In addition, embodiments described herein refer inter alia to a method for converting a digital input signal into an analog output signal. The method includes inputting the digital input signal into a circuit unit, switching at least one of an array of current source transistors included in the circuit unit, to an output terminal on the basis of the digital input signal. Then, a voltage variation may be detected at a gate terminal of at least one current source transistor of the array of current source transistors. The voltage variation at the gate terminal may be detected at a time when the current source transistor is switched to the output terminal. Furthermore, a capacitive feedback on the gate terminal based on the detected voltage variation may be compensated. The capacitive feedback may result from a capacitive coupling between the source terminal and the gate terminal of the at least one current source transistor. Then, the analog output signal is output from the output terminal.

Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be better understood with reference to the following drawings and description. The components in the figures are not necessarily to scale, instead emphasis being placed upon illustrating the principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts. In the drawings:

FIG. 1 shows a schematic view of a digital-to-analog converter including a plurality of current source cells according to an embodiment;

FIG. 2 illustrates a current source cell including a current source transistor and being fed by a bias voltage from a bias voltage source according to an embodiment;

FIG. 3 illustrates a current source cell connected to a compensation circuit according to an embodiment;

FIG. 4 is a circuit diagram of a calibration circuit connected to a current source cell according to an embodiment;

FIG. 5 is a calibration circuit for two current source cells operated in a differential mode according to an embodiment;

FIG. 6 shows a graph illustrating an adjustment of a compensation voltage on the basis of a bias current and an output current of the digital-to-analog converter; and

FIG. 7 shows a flowchart illustrating a method for converting a digital input signal into an analog output signal according to an embodiment.

DETAILED DESCRIPTION

Reference will now be made in detail to the various embodiments described herein, one or more examples of which are illustrated in the figures. Within the following description of the drawings, the same reference numbers refer to same components. Generally, only the differences with respect to individual embodiments are described. Each example is provided by way of explanation and is not intended as a limitation. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations.

FIG. 1 illustrates a digital-to-analog converter (DAC)100 in a schematic circuit arrangement. As shown inFIG. 1, adigital input signal401 is provided at aninput selector104. Theinput selector104 is designed to operate a plurality ofcurrent source switches103a,103b, . . . ,103nof respectivecurrent source cells101a-101n. The current source switches103a-103nmay be provided as transistors or any other means capable of a low-impedance connection of two terminals. TheDAC100 may include an array ofcurrent source cells101a,101b, . . . ,101n. Eachcurrent source cell101a-101nmay output anindividual output current106a,106b, . . . ,106n.

Theoutput currents106a-106nmay be differ from each other, in particular, the output currents may exhibit values corresponding to a digital code. For example, 1024current source cells101a-101nmay be provided, wherein the firstcurrent source cell106amay correspond to a least significant bit (LSB), wherein the 1024^thcurrent source cell106nmay correspond to a most significant bit (MSB). Using thecurrent source switches103a-103n(1024 switches in the present example), a digital input word (input code) may be converted into ananalog output current106a-106n.

Theindividual output currents106a-106nare summed up at anoutput terminal105 and are outputted as theanalog output signal402. Thus, theanalog output signal402 may be outputted on the basis of thedigital input signal401. In order to obtain an analog output voltage on the basis of theanalog output signal402, e.g., a current-to-voltage operational amplifier may be used which may sum up the individual currents provided at theoutput terminal105 and may then convert the summed-up currents into an output voltage (not shown inFIG. 1).

FIG. 2 is a schematic view of a circuit arrangement illustrating acurrent source cell101 in more detail. As shown inFIG. 2, thecurrent source cell101 is connected to abias voltage source114. Thecurrent source cell101 includes acurrent source transistor102 having agate terminal107, adrain terminal108 and asource terminal109. Furthermore, thecurrent source cell101 includes acurrent source switch103 provided for coupling thesource terminal109 to theoutput terminal105. When thecurrent source switch103 is closed, an output current may be provided by thecurrent source cell101 so that the output current contributes to the analog output signal102 (arrow106 inFIG. 2). In order to operate thecurrent source cell101, abias voltage118 may be provided at thegate terminal107, i.e., thebias voltage118 is provided between abias node113 andground110. Thebias voltage118 is generated by thebias voltage source114 including abias transistor111.

When thecurrent source switch103 is closed, a voltage jump may occur at thesource terminal109, e.g., a voltage may rise from 0 volts to approximately 0.6 volts at a time when the current source cell is activated, i.e., whenswitch103 is closed.

The voltage jump at thesource terminal109 when the current source cell is activated may result in a capacitive feedback between thesource terminal109 and thegate terminal107 of thecurrent source transistor102. Due to the capacitive feedback transferred to thebias node113, a voltage level on thebias node113 may increase. Furthermore, if thecurrent source switch103 is switched off and on (toggled) at a high rate, a distortion occurs at theoutput terminal105. Undesirable capacitive feedback from thesource terminal109 to thegate terminal107 of thecurrent source transistor102 may be compensated by circuit arrangements described herein below with reference toFIGS. 3,4 and5.

Although abias voltage118 is provided by thebias voltage source114 including thebias transistor111, thebias voltage118 may change when thecurrent source switch103 is closed. This change results from the capacitive feedback between thesource terminal109 and thegate terminal107 of thecurrent source transistor102. Thebias transistor111 does not represent an ideal voltage source for providing thebias voltage118 so that the capacitive feedback to thebias node113, i.e., thegate107 of thecurrent source transistor102 may increase thebias voltage118 resulting in distortions with respect to theoutput current106 of thecurrent source cell101.

FIG. 3 is a schematic circuit diagram showing acurrent source cell101 connected to acompensation circuit200. As shown inFIG. 3, thecurrent source cell101 includes acurrent source transistor102 having agate terminal107, asource terminal109 and adrain terminal108. Thedrain terminal108 is connected toground110. Thesource terminal109 is connected to thecurrent source switch103 which provides an outflow of output current106 toward theoutput terminal105. Theoutput current106 of thecurrent source cell101 contributes to theanalog output signal402. Thecurrent source switch103 is controlled by theinput selector104 receiving adigital input signal401 and afirst control signal411. Thefirst control signal411 provides an activation of thecurrent source cell101 viacurrent source switch103.

Thecompensation circuit200 includes acompensation capacitor112 which compensates the capacitive feedback from thesource terminal109 to thegate terminal107 of thecurrent source transistor102 when the current source transistor is coupled to theoutput terminal105, i.e., when thesource terminal109 of thecurrent source transistor102 is connected to theoutput terminal105.

Thecurrent source transistor102 may be a field effect transistor (FET). The capacitive feedback may then result in an increased gate-drain charge. On the other hand, a charge provided for thecompensation capacitor112 depends on acompensation voltage403 applied at the compensation capacitor if aswitching unit201 couples amain switch terminal205 to afirst switch terminal301. Thecompensation voltage403 which is suited for charging thecompensation capacitor112 so that the capacitive feedback at thecurrent source transistor102 is compensated is determined by measuring avoltage variation404 by adetection circuit202 included in thecompensation circuit200. Compensation of the gate-drain charge of the102 may thus be achieved by charging thecompensation capacitor112 to a charge opposite the gate-drain charge.

To obtain a measure for the capacitive feedback to thegate terminal107 of thecurrent source transistor102, thevoltage variation404 at thebias node113 is measured, e.g., a voltage between thebias node113 andground110 is detected. Thedetection circuit202 receives thevoltage variation404 resulting from the capacitive feedback at thegate terminal107 and outputs a compensation signal to thecompensation voltage source203. Thecompensation voltage source203 provides thecompensation voltage403 applied at thecompensation capacitor112 when theswitching unit201 is switched to thefirst switch terminal301 in a charging mode on the basis of the compensation signal.

Thecontrol unit204 controls both thecurrent source switch103 and theswitching unit201 of thecompensation circuit200. When theswitching unit201 switches to the first switch terminal301 (charging position), thecurrent source switch103 is opened. Then, when closing thecurrent source switch103 again so that the output current106 may flow toward theoutput terminal105, a voltage jump at thebias node113 may be compensated by concurrently switching theswitching unit201 to asecond switch terminal302 which is connected toground110. Thus, a charge opposite the charge representing the capacitive feedback between thesource terminal109 and thegate terminal107 of thecurrent source switch102 is present at thebias node113.

A total charge which is deposited in thecompensation capacitor112 before closing thecurrent source switch103 may be determined as given by:
Q₁₁₂=U×C₁₁₂,  (1)
wherein Q₁₁₂represents the charge deposited at thecompensation capacitor112, U represents the voltage across thecompensation capacitor112 and C₁₁₂represents the capacity of thecompensation capacitor112. Thus, in order to provide an appropriate charge for compensating the capacitive feedback mentioned above, the amount of charge Q₁₁₂may be varied by thecompensation voltage403. Thecompensation voltage403 may be adjusted by thecompensation voltage source203.

Thecontrol unit204 may toggle bothswitches103 and201, e.g., thecurrent source switch103 and theswitching unit201 in an alternate manner, e.g., ifswitch103 is closed, then switch201 couples thecompensation capacitor112 to ground, and ifswitch103 is closed, thecompensation capacitor112 connectsterminals205 and301 in order to charge thecompensation capacitor112 with thecompensation voltage403. Thedetection unit202 detects avoltage variation404 at thebias node113 whenever the compensation of the capacitive feedback to thegate terminal107 of thecurrent source transistor102 is not fully achieved. A full compensation of the capacitive feedback results in avoltage variation404 of approximately 0 volts. Once thedetection circuit202 detects avoltage variation404 of approximately 0 volts, thecompensation voltage source203 holds thecompensation voltage403 at the adjusted level.

Then, a compensation of the capacitive feedback within thecurrent source cell101 is achieved. In this way, an appropriate value of thecompensation voltage403 for compensating capacitive feedback can be found, that is thecompensation circuit200 is calibrated. After calibrating thecompensation circuit200, thecurrent source cell101 may be connected to and disconnected from theoutput terminal105 without generating avoltage variation404 at thebias node113. Due to temperature changes, changes in input bias current into thecurrent source transistor102, variation in the bias voltage, a value of a supply voltage of the circuit arrangement, and any combination thereof, a re-calibration may be necessary.

As described herein above, thevoltage variation404 is detected by thedetection circuit202 and a compensation control signal is provided for thecompensation voltage source203 so that anew compensation voltage403 is found. Once thevoltage variation404 is approximately zero after connecting thesource terminal109 to theoutput terminal105 by thecurrent source switch103, a new calibration has been found and thenew compensation voltage403 may be held at the output of thecompensation voltage source203.

Operation of thecurrent source cell101 shown inFIG. 3 is based on providing abias voltage118 provided by thebias voltage source114 as described herein above with respect toFIG. 2. Bias voltage generation illustrated inFIG. 2 is not shown again inFIG. 3.

Thecompensation circuit200 provides a compensation of the capacitive feedback between thegate terminal107 and thesource terminal109 of thecurrent source transistor102, wherein thesource terminal109 is switchable to theoutput terminal105 for outputting theoutput current106 of thecurrent source cell101. Thecompensation voltage403 provided by thecompensation voltage source203 is applied at thecompensation capacitor112 which in turn is coupled between thegate terminal107 and thecompensation voltage source203, in a charging position.

Thedetection circuit202 is coupled to thecompensation voltage source203 and is configured to detect thevoltage variation404 at thegate terminal107, i.e., at thebias node113, thevoltage variation404 occurring when thesource terminal109 is switched to theoutput terminal105 for outputting theoutput current106. Thecompensation voltage203 is adjusted on the basis of the detectedvoltage variation404 so that the capacitive feedback is compensated, at least partially.

Theswitching unit201 is configured to couple thecompensation capacitor112 between thegate terminal107 of thecurrent source transistor102 and thecompensation voltage source203, or between thegate terminal107 andground110. Switching of theswitching unit201 is controlled by thecontrol unit204 so that theswitching unit201 connects themain switch terminal205 to thesecond switch terminal302 when thecurrent source switch103 is closed by control of thefirst control signal411 of thecontrol unit204.

Thus, thecompensation circuit200 provides anadjustable compensation voltage403 so that thevoltage variation404 is lowered to a value of approximately 0 volts. In other words, the capacitive feedback on thegate terminal107 is compensated by thecompensation voltage403 applied at thecompensation capacitor112 so that a resulting compensation charge Q₁₁₂deposited in thecompensation capacitor112 compensates a gate-drain charge of thecurrent source transistor102. Thus, the voltage for the compensation is determined by a calibration process so that a charge transferred to thebias node113 is cancelled by an opposite charge provided by thecompensation capacitor112.

FIG. 4 is a schematic diagram of a circuit arrangement for calibrating a compensation of capacitive feedback in acurrent source transistor102. As shown inFIG. 4, acalibration circuit300 includes acomparator circuit303, an up-down counter304 and an auxiliary digital-to-analog converter305.

Thecurrent source cell101 shown inFIG. 4 may be one of a plurality of acurrent source cells101a-101nof aDAC100 described herein above with respect toFIG. 1. Eachcurrent source cell101a-101nof theDAC100 may include thecurrent source transistor102 having agate terminal107 and asource terminal109 and providing an output current106, acurrent source switch103 configured to couple thesource terminal109 to theoutput terminal105 based on adigital input signal401, and thecompensation capacitor112 configured to compensate the capacitive feedback between thegate terminal107 and thesource terminal109 when thesource terminal109 is coupled to theoutput terminal105.

Thecurrent source cell101 shown inFIG. 4 may be provided as a replica cell, which is arranged in addition to the current source cells used for DAC operation. A replica cell denotes a cell which is identical or nearly identical to the current source cells of theDAC100, but which is only used for compensation and/or calibration purposes and not for DAC operation. Thecurrent source cell101 shown inFIG. 4 further includes thecalibration circuit300 for detecting thevoltage variation404 at thegate terminal107, i.e., at thebias node113, when thesource terminal109 is coupled to theoutput terminal105. Furthermore, thecalibration circuit300 provides thecompensation voltage403 for thecompensation capacitor112. Thus, the replica cell is designed in a similar manner as thecurrent source cells101 of theDAC100 shown inFIG. 1, e.g., for a number of 1024current source cells101, a number of 1024current source transistors102, 1024compensation capacitors112 and a number of 1024 switchingunits201 are provided.

Eachcurrent source cell101a-101nof theDAC100 receives thesame compensation voltage403 provided by thecalibration circuit300 of the replica cell shown inFIG. 4 so that theindividual voltage variations404 of thecurrent source cells101a-101nmay be reduced to zero or approximately zero. Thus the capacitive feedback at an individualcurrent source transistor102a-102nof an individualcurrent source cell101a-101n(seeFIG. 1) is compensated. Thecompensation voltage403 may be the same for allcurrent source cells101a-101nof aDAC100, because, even if a mismatch between the capacitive feedback and thecompensation capacitor112 is present, this mismatch is identical or nearly identical for allcurrent source cells101a-101n. Thus, thecalibration circuit300 is provided once in combination with the replica cell shown inFIG. 4.

Although only one replica cell is shown in the circuit arrangement of thecalibration circuit300, two or more replica cells may be provided within thecalibration circuit300. As compared to the circuit arrangement shown inFIG. 3, the compensation voltage source inFIG. 4 is provided by an analog output of the auxiliary analog-digital converter305. Thecomparator303 of thecalibration circuit300 detects thevoltage variation404 by comparing thevoltage variation404 at the bias node113 (i.e., at the gate terminal of the current source transistor102) to a predetermined voltage value and outputs a comparator signal based on the comparison.

The comparator signal is fed to the up-down counter304 connected to an output terminal of the comparator circuit. The up-down counter304 provides adigital control signal406 based on the comparator signal. Thedigital control signal406 serves as a DAC input code for the auxiliary digital-to-analog converter305. The auxiliary digital-to-analog converter305 converts the DAC input code, i.e., thedigital control signal406 into thecompensation voltage403 provided for thecompensation capacitor112. The up-down counter304 provided in thecalibration circuit300 may be designed as a digital filter unit. Thecontrol unit204 shown inFIG. 3 may toggle bothswitches103 and201, e.g., thecurrent source switch103 and theswitching unit201 in an alternate manner, e.g., ifswitch103 is closed, then switch201 couples thecompensation capacitor112 toground110, and ifswitch103 is closed, thecompensation capacitor112 connectsterminals205 and301 in order to charge the compensation capacitor12 with thecompensation voltage403.

FIG. 5 is a schematic circuit diagram illustrating a calibration circuit according to yet another embodiment which can be combined with other embodiments described herein.FIG. 5 illustrates a differential operation mode of at least two replicacurrent source cells101a,101bincluding respectivecurrent source transistors102a,102b. Eachcurrent source cell101a,101bincludes aswitching unit201a,201band acompensation capacitor112a,112b. Furthermore, the replicacurrent source cells101a,101binclude current source switches103a,103bfor connecting the respectivecurrent source cell101a,101bto anoutput terminal105 so thatrespective output currents106a,106bcan be provided as output signals.

Furthermore, abias voltage source114 including abias transistor111 and acapacitor115 connecting the output of thebias voltage source114 to ground are provided. Thebias voltage source114 provides, as its output, thebias voltage118, which may be applied atinput capacitors117a,117bof thecomparator circuit303 and which is switchable via bias switches116a,116b. Therespective bias voltages118 applied at theoperator circuit303 are held by theinput capacitors117a,117b. An additional voltage variation caused by closing the current source switches103a,103bmay then be compensated by the compensation circuit and calibrated by the calibration circuit including thecomparator circuit303, the up-down counter304 and the auxiliary digital-to-analog converter305.

Although not shown inFIG. 5, a control unit is provided for toggling theswitches103a,103b,201aand201bin an alternating manner. In other words, whencurrent source switch103bis closed, as shown inFIG. 5, current source switch103ais opened and vice versa. In addition,compensation capacitor112ais switched to the output of the auxiliary digital-to-analog converter305 whencompensation capacitor112bis switched toground110 and vice versa. Thecomparator circuit303 detects voltage variations at its inputs and thus is able to set the up-down counter304 to a value resulting in acompensation voltage404 at the output of the auxiliary digital-to-analog converter305 so that a voltage variation due to switching theswitches103aand103b, respectively, to theoutput terminal105 is compensated, i.e., a capacitive feedback occurring at thecurrent source transistors102a,102bis compensated by the charge deposited incompensation capacitors112a,112b. In this way, by compensating the capacitive feedback, interferences on the output signal are eliminated or at least reduced.

Thecurrent source cells101a,101bincluding thecurrent source transistors102a,102bare replica cells, that is cells which are identical or nearly identical to the current source cells of theDAC100, but which are used for compensation and/or calibration purposes and not for DAC operation. Although twocurrent source cells101a,101b(replica cells) are shown, the present application is not restricted to a calibration circuit including twocurrent source cells101a,101b, rather one, or more than twocurrent source cells101a-101nmay be provided for the calibration circuit. Here, at least twocurrent source transistors102a,102bprovided in the circuit arrangement shown inFIG. 5 are operated in compensation modes shifted in phase by approximately 180 degrees. Preloading during the offset compensation phase of the comparator is provided because the capacity of thecurrent source transistors102a,102bdepends on the appliedbias voltage118.

FIG. 6 is a graph illustrating an operation principle of the calibration procedure according to an embodiment which can be combined with other embodiments described herein. The curves shown inFIG. 6 represent different compensation situations as a function oftime405. Atime axis405 is the x-axis in units of 10 microseconds (μs). The y-axis corresponds to aDAC input code406 into the auxiliary digital-to-analog converter305 shown inFIGS. 4 and 5.

Afirst compensation curve407 is obtained by detecting the DAC input code into the auxiliary digital-to-analog converter305 after changing the bias current flowing into thecurrent cell101 shown inFIG. 4 to 156 μA and by obtaining an output current of theDAC100 of 20 mA. Asecond compensation curve408 is obtained at a bias current I_biasof 312 μA and a DAC output current of 40 mA, and athird compensation curve409 is obtained at a bias current of 625 μA resulting in a DAC output current of 80 mA. As a further example, afourth compensation curve410 is shown at a bias current of 781 μA and an output current of the DAC100 (FIG. 1) of 100 mA. As can be seen from the compensation curves shown inFIG. 6, theDAC input code406 may not be determined unambiguously from the output current of theDAC100, rather a calibration procedure taking into account thevoltage variation404 at thebias node113 is required.

FIG. 7 is a flowchart illustrating a method for converting adigital input signal401 into ananalog output signal402. Atstep501 the procedure is started. Thedigital input signal401 is input atstep502. Then, at least one of the array ofcurrent source transistors102a-102nis switched to anoutput terminal105 on the basis of the digital input signal401 (step503). During switching by the current source switches103, avoltage variation404 is detected at agate terminal107 of at least onecurrent source transistor102a-102n, when thecurrent source transistor102a-102nis switched to the output terminal105 (step504).

Acompensation voltage403 for compensating a capacitive feedback between thegate terminal107 and thesource terminal109 of thecurrent source transistor102a,102nis then adjusted based on the detected voltage variation404 (step505). Thevoltage variation404 results from a mismatch of a capacitance of thecompensation capacitor112 with respect to the capacitive feedback. The mismatch can be assumed to be the same or nearly the same for allcurrent source cells101a-101nof theDAC100. It is determined whether or not the capacitive feedback between thesource terminal109 and thegate terminal107 of thecurrent source transistor102 is compensated (step506). If the capacitive feedback is compensated (“yes”), theanalog signal402 is output on the basis of switchedcurrent source transistors102a-102n(step507) and the procedure ends (step508). If it is determined that the capacitive feedback is not compensated (“no”), the procedure returns to step504 where anothervoltage variation404 is detected at the gate terminal107 (i.e., at the bias node113).Steps505 and506 are then carried out again.

Thus, the calibration process for determining the compensation voltage may be provided. An accurate compensation without knowledge of other parameters except for the assumption of an identical or nearly identical mismatch in the individualcurrent source cells101a-101nmay be achieved. After the calibration procedure, thecalibration circuit300 may be deactivated to save supply power.

As shown inFIGS. 4 and 5, the auxiliary digital-to-analog converter305 serving as a current source for providing thecompensation voltage403 may hold its output voltage after stopping the calibration process. Thus, thecompensation voltage403 is held at the adjusted level before deactivating thecalibration circuit300. In some situations, the deactivatedcalibration circuit300 may be reactivated after a variation of at least one of a bias voltage, a bias current, an operation temperature, and a supply voltage has occurred.

While the foregoing is directed to embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Terms such as “first”, “second”, and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.

As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.

Claims (21)

1. A compensation circuit for compensating a capacitive feedback between a gate terminal and a source terminal of a current source transistor, the source terminal being switchable to an output terminal for outputting an output current, the compensation circuit comprising:

a compensation voltage source configured to provide a compensation voltage;

a compensation capacitor coupled between the gate terminal and the compensation voltage source; and

a detection circuit coupled to the compensation voltage source and configured to detect a voltage variation at the gate terminal when the source terminal is switched to the output terminal for outputting the output current,

wherein the compensation voltage is adjusted based on the detected voltage variation so that the capacitive feedback is compensated.

2. The compensation circuit in accordance withclaim 1, further comprising a switching unit configured to couple the compensation capacitor between the gate terminal and the compensation voltage source, or between the gate terminal and ground.

3. The compensation circuit in accordance withclaim 1, further comprising a comparator circuit configured to compare the voltage variation at the gate terminal to a predetermined voltage value and output a comparator signal based on the comparison.

4. The compensation circuit in accordance withclaim 3, further comprising an up-down counter connected to an output terminal of the comparator circuit and configured to provide a digital control signal based on the comparator signal.

5. The compensation circuit in accordance withclaim 4, further comprising an auxiliary digital-to-analog converter configured to convert the digital control signal into the compensation voltage.

6. The compensation circuit in accordance withclaim 4, wherein the up-down counter is a digital filter unit.

7. A digital-to-analog converter for converting a digital input signal into an analog output signal, comprising:

an input selector configured to input the digital input signal;

an output terminal configured to output the analog signal; and

an array of current source cells, each current source cell comprising:

a current source transistor having a gate terminal and a source terminal and configured to provide an output current;

a current source switch configured to couple the source terminal to the output terminal based on the digital input signal; and

a compensation capacitor configured to compensate a capacitive feedback between the gate terminal and the source terminal when the source terminal is coupled to the output terminal,

wherein at least one of the current source cells further comprises a calibration circuit configured to detect a voltage variation at the gate terminal when the source terminal is coupled to the output terminal and provide a compensation voltage for the compensation capacitor.

8. The digital-to-analog converter in accordance withclaim 7, wherein the calibration circuit comprises an adjustable compensation voltage source configured to provide the compensation voltage.

9. The digital-to-analog converter in accordance withclaim 7, wherein the at least one current source cells further comprises a switching unit configured to couple the compensation capacitor between the gate terminal and the compensation voltage source, or between the gate terminal and ground.

10. The digital-to-analog converter in accordance withclaim 7, wherein the calibration circuit further comprises a comparator circuit configured to compare the voltage variation at the gate terminal to a predetermined voltage value and output a comparator signal based on the comparison.

11. The digital-to-analog converter in accordance withclaim 10, wherein the calibration circuit further comprises an up-down counter connected to an output terminal of the comparator circuit and configured to provide a digital control signal based on the comparator signal.

12. The digital-to-analog converter in accordance withclaim 11, wherein the calibration circuit further comprises an auxiliary digital-to-analog converter configured to convert the digital control signal into the compensation voltage.

13. The digital-to-analog converter in accordance withclaim 7, wherein the current source transistor is a field effect transistor.

14. A method for converting a digital input signal into an analog output signal, comprising:

inputting the digital input signal;

switching at least one of an array of current source transistors to an output terminal based on the digital input signal;

detecting a voltage variation at a gate terminal of at least one current source transistor when the current source transistor is switched to the output terminal;

compensating capacitive feedback on the gate terminal based on the detected voltage variation; and

outputting the analog output signal from the output terminal.

15. The method in accordance withclaim 14, wherein the capacitive feedback on the gate terminal is compensated by a compensation voltage applied at a compensation capacitor so that a resulting compensation charge of the compensation capacitor compensates a gate-drain charge of the current source transistor.

16. The method in accordance withclaim 15, further comprising implementing a calibration procedure for providing the compensation voltage by a calibration circuit.

17. The method in accordance withclaim 16, wherein the gate terminal is preloaded with a bias voltage during the calibration procedure.

18. The method in accordance withclaim 16, wherein the calibration circuit is deactivated after the calibration procedure.

19. The method in accordance withclaim 18, wherein the compensation voltage is held at an adjusted level before deactivating the calibration circuit.

20. The method in accordance withclaim 18, wherein the calibration circuit is reactivated after a variation of at least one of a bias voltage at the gate terminal and an operation temperature.

21. The method in accordance withclaim 14, wherein at least two current source transistors are operated in compensation modes shifted in phase by approximately 180 degrees.

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