US8304794B2 - Light emitting device - Google Patents

Abstract

A light emitting device includes a substrate having a first surface and a second surface not parallel to the first surface, and a light emission layer disposed over the second surface to emit light. The light emission layer has a light emission surface which is not parallel to the first surface.

Description

This application is a divisional application of U.S. patent application Ser. No. 12/177,114, filed on Jul. 21, 2008 now abandoned, which is a continuation-in-part of U.S. patent application Ser. No. 11/761,446, filed on Jun. 12, 2007 (now U.S. Pat. No. 7,956,370 ). The entire disclosure of each of the prior applications is incorporated herein by reference.

BACKGROUND

The present patent application is related to light emitting devices.

Solid-state light sources, such as light emitting diodes (LEDs) and laser diodes, can offer significant advantages over other forms of lighting, such as incandescent or fluorescent lighting. For example, when LEDs or laser diodes are placed in arrays of red, green and blue elements, they can act as a source for white light or as a multi-colored display. In such configurations, solid-state light sources are generally more efficient and produce less heat than traditional incandescent or fluorescent lights. Although solid-state lighting offers certain advantages, conventional semiconductor structures and devices used for solid-state lighting are relatively expensive. One of the costs related to conventional solid-state light emitting devices is related to the relatively low manufacturing throughput of the conventional solid-state light emitting devices.

Referring toFIG. 1, aconventional LED structure100 includes asubstrate105, which may, for example, be formed of sapphire, silicon carbide, or spinel. Abuffer layer110 is formed on thesubstrate105. Thebuffer layer110 serves primarily as a wetting layer, to promote smooth, uniform coverage of the sapphire substrate. Thebuffer layer110 is typically formed of GaN, InGaN, AlN, or AlGaN and has a thickness of about 100-500 Angstroms. The buffer layer310 is typically deposited as a thin amorphous layer using Metal Organic Chemical Vapor Deposition (MOCVD).

A p-doped Group III-V compound layer120 is formed on thebuffer layer110. The p-doped Group III-Vcompound layer120 is typically made of GaN. An InGaN quantum-well layer130 is formed on the p-doped Group III-V compound layer120. An active Group III-Vcompound layer140 is then formed on the InGaN quantum-well layer130. An n-doped Group III-Vcompound layer150 is formed on thelayer140. The p-doped Group III-V compound layer120 is n-type doped. A p-electrode160 is formed on the n-doped Group III-V compound layer150. An n-electrode170 is formed on the first Group III-V compound layer120.

A drawback of theconventional LED structure100 is the low manufacturing throughput associated with the small substrate dimensions. For example, sapphire or silicon carbide substrates are typically supplied in diameters of 2 to 4 inches. Another drawback of theconventional LED structure100 is that its layered structure often suffers from cracking. Suitable substrates such as sapphire or silicon carbide are typically not available in single crystalline forms. The p-doped Group III-Vcompound layer120 can suffer from cracking or delamination due to differential thermal expansions and lattice mismatching between the p-doped Group III-V compound layer and the substrate even in the presence of thebuffer layer110. The differential thermal expansions and lattice mismatching can also produce a bowing deformation (i.e. curling up) in the LED structure. As a result, light emitting performance of theLED structure100 can be compromised.

Accordingly, there is therefore a need for a light emitting device that can overcome some or all of the drawbacks in the conventional light emitting systems.

SUMMARY OF THE INVENTION

In one aspect, the present invention relates to a light emitting device that includes a substrate having a first surface and a second surface not parallel to the first surface; and a light emission layer disposed over the second surface to emit light, the light emission layer having a light emission surface which is not parallel to the first surface.

In another aspect, the present invention relates to a light emitting device that includes a substrate; and a light emission layer disposed over the substrate to emit light, the light emission layer having a footprint area and having a light emission surface area which is greater than the footprint area.

In another aspect, the present invention relates to a light emitting device that includes a substrate having a first surface; a light emission layer disposed over at least a portion of the substrate, the light emission layer having a light emission surface that is not parallel to the first surface; and a reflective buffer layer disposed over at least a portion of the light emission layer, to reflect light emitted from the light emission layer, and wherein the reflective buffer layer has a reflectance coefficient higher than 30% in a spectral range of light emitted by the light emission layer.

In another aspect, the present invention relates to a light emitting device that includes a substrate having a first surface and a trench formed in the first surface; and a light emission layer disposed within the trench to emit light, the light emission layer having a light emission surface which is not parallel to the first surface, wherein the first surface outside of the trench can include at least one width dimension narrower than 1000 microns.

In another aspect, the present invention relates to a light emitting device that includes a substrate having a first surface and a protrusion formed on the first surface; and a light emission layer disposed on the protrusion to emit light, the light emission layer having a light emission surface which is not parallel to the first surface.

In another aspect, the present invention relates to a light emitting device that includes a substrate having a first surface; a trench formed in the substrate, wherein the trench is defined in part by a plurality of first trench surfaces that are not parallel to the first surface; a reflective buffer layer on at least a portion of the first surface and the plurality of first trench surfaces; and a light emitting layer over the reflective buffer layer, wherein the light emitting layer can emit light away from the reflective buffer layer, wherein the light emitted is confined in an angular range narrower than 150 degrees.

In another aspect, the present invention relates to a method for fabricating a light emitting device. The method includes forming a light emission layer over a substrate having a first surface and a second surface not parallel to the first surface, wherein the light emission layer has a light emission surface not parallel to the first surface, wherein the light emission layer can emit light.

Implementations of the system may include one or more of the following. The light emission layer can include a quantum-well layer that can emit light when an electric current is produced in the quantum-well layer. The quantum-well layer can include a layer formed by a material selected from the group consisting of InN, InGaN, GaN, AlGaN, and InGaAlN. The light emitting device can further include a buffer layer between the substrate and the light emission layer. The buffer layer can have a reflectance coefficient higher than 30% in the spectral range of the light emitted by the light emission layer. The buffer layer can have a reflectance coefficient higher than 50% in the spectral range of the light emitted by the light emission layer. The buffer layer can have a thickness in the range of 200 to 200,000 Angstroms. The buffer layer can include aluminum, aluminum nitride, an aluminum alloy, or Ag and its alloy, as reflective buffer layer. The buffer layer can include a material selected from the group consisting of GaN, ZnO, AlN, HfN, AlAs, SiCN, TaN, and SiC. The light emitting device can further include a lower Group III-V compound layer between the substrate and the light emission layer and an upper Group III-V compound layer over the light emission layer. The substrate can have a trench formed in the first surface, and wherein the light emission layer is disposed within the trench. The first surface outside of the trench can include at least one width dimension narrower than 1000 microns. The substrate can have a protrusion formed on the first surface, and wherein the light emission layer is disposed on the protrusion. The first surface outside of the protrusion can include at least one width dimension narrower than 1000 microns. The substrate can include silicon, silicon oxide, gallium nitride, silicon carbide, or sapphire. The substrate can include a silicon-on-insulator (SOI) structure, or simply a silicon bonded on glass to form a stop layer for interconnect electrodes.

An advantage associated with the disclosed light emitting device is that it significantly increases light emission intensity comparing to conventional LED light emitting devices. The disclosed light emitting devices and methods provide much larger light emitting surface than conventional LED light emitting devices having the same substrate foot print. A reflective layer under the disclosed light emitting devices can decrease absorption-related light loss and further increase emission efficiency. A transparent conductive layer formed on the upper Group III-V compound layer of the disclosed light emitting device can increase electric contact between the upper electrode and the upper III-V layer, and at the same time, maximize light emission intensity from the disclosed light emitting device.

Another advantage associated with the disclosed light emitting device is that its light emission is focused in much narrower angular range than conventional LED light emitting devices. The more concentrated angular light emission in the disclosed light emitting device reduces the light loss to unwanted directions and can thus increase brightness in the intended illumination directions and reduce energy consumption.

Another advantage associated with the disclosed light emitting device is that it is more practical to manufacture, robust, and reliable than some conventional light emitting systems. The disclosed light emitting devices and fabrication processes can overcome differential thermal expansions and lattice mismatch between the lower group compound III-V layer and the substrate and prevent associated layer cracking and delamination, problems known in conventional LED lighting systems.

The disclosed light emitting device and fabrication processes allow for high-throughput and high-volume manufacturing of the light emitting devices. A large number of solid state LEDs can be fabricated on a large substrate such as a silicon wafer or a glass substrate. Manufacturing throughput can be much improved since silicon wafer can be provided in much larger dimensions (e.g. 6 to 12 inch silicon wafers) compared to the small substrates used in the conventional light emitting devices. The disclosed light emitting device can be fabricated using commercially available semiconductor processing equipment such as ALD and MOCVD systems without using customized fabrication equipments, which makes the disclosed manufacturing process easily implemented. The disclosed light emitting device can thus be fabricated more efficiently in cost and time than some conventional light emitting devices that need.

Furthermore, the disclosed light emitting devices can be made more integrated, compact, and cost effective compared to some conventional LED devices. The disclosed light emitting devices can be fabricated on a silicon-based substrate which allows the integration of electronic control circuitry in the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The following drawings, which are incorporated in and from a part of the specification, illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a cross-sectional view of a conventional LED structure.

FIG. 2A is a perspective view of a light emitting device in accordance with one embodiment of the present application.

FIG. 2B is a detailed perspective view of the front corner portion of the light emitting device inFIG. 2A.

FIG. 3A is a cross-sectional view of the light emitting device along line A-A inFIG. 2A.

FIG. 3B is a detailed cross-sectional view of a side portion of the light emitting device inFIG. 3A.

FIG. 3C is a detailed cross-sectional view of the bottom portion of the light emitting device inFIG. 3A.

FIG. 3D is a cross-sectional view the light emitting structures along line B-B inFIG. 2A.

FIGS. 3E and 3F illustrate examples of layer structures and material compositions for the light emitting structures.

FIG. 4A is a perspective view of a 2×2 array of light emitting structures fabricated on a substrate in accordance with the present application.

FIG. 4B is a partial cross-sectional view of the light emitting structures along line B-B inFIG. 4A.

FIG. 4C is a perspective view of a 4×4 array of light emitting structures fabricated on a substrate in accordance with the present application.

FIG. 5A is a cross-sectional view of a substrate having a patterned mask for preparing for forming the light emitting device ofFIG. 4B.

FIG.5B1 is a perspective view of the light emitting device inFIG. 5A after etching through the mask shown inFIG. 5A.

FIGS.5B2 and5C-5I are cross-sectional views at different steps of forming the light emitting device ofFIG. 4B.

FIG. 6A is a schematic diagram illustrating an example of the emission angular distribution of a conventional LED light emitting device.

FIG. 6B is a schematic diagram illustrating angular distribution of light emission from the light emitting device illustrated inFIG. 2A.

FIG. 7 is a perspective view of another light emitting device in accordance with the present application.

FIG. 8 is a flowchart for a fabricating process for the silicon-based light emitting devices ofFIGS. 2-7.

FIG. 9A is a perspective view of a light emitting device in accordance with another embodiment of the present application.

FIG. 9B is a detailed perspective view of the front corner portion of the light emitting device inFIG. 9A.

FIG. 10A is a cross-sectional view of the light emitting device along line A-A inFIG. 9A.

FIG. 10B is a detailed cross-sectional view of a side portion of the light emitting device inFIG. 10A.

FIG. 10C is a detailed cross-sectional view of the top portion of the light emitting device inFIG. 10A.

FIG. 11A is a perspective view of a 2×2 array of light emitting structures fabricated on a substrate in accordance with the present application.

FIG. 11B is a partial cross-sectional view of the light emitting structures along line B-B inFIG. 11A.

FIG. 11C is a perspective view of a 4×4 array of light emitting structures fabricated on a substrate in accordance with the present application.

FIG. 12 is a schematic diagram illustrating angular distribution of light emission from the light emitting device illustrated inFIG. 9A.

DESCRIPTION OF THE INVENTION

Referring toFIGS. 2A to 3C, alight emitting device200 is formed on asubstrate205 having an upper surface207 (FIG. 3B). Thelight emitting device200 includes atrench210 in thesubstrate205 below theupper surface207. Thetrench210 has one or more trench surfaces213 (FIG. 3B) at a slope relative to theupper surface207. Thetrench210 can also have abottom surface219 that is parallel to theupper surface207. The area of thebottom surface219 can be kept smaller than 20% of one of the trench surfaces213. Thesubstrate205 can be silicon based: theupper surface207 can be parallel to the (100) crystalline plane. Thetrench surface213 can be parallel to the (111) crystalline surface. (Alternatively, theupper surface207 can be parallel to the (111) crystalline plane. Thetrench surface213 can be parallel to the (100) crystalline surface.) Thetrench210 thus can have the shape of an inverted pyramid or a truncated inverted pyramid in thesubstrate205, which forms a square opening in theupper surface207. Aninternal edge217 is formed at the intersection of two adjacent trench surfaces213. Thesubstrate205 can have a rectangular or square shape having anouter edge208. Thelight emitting device200 can be fabricated together with a batch of other light emitting devices on a semiconductor wafer, and diced to form separate dies. Thelight emitting device200 can have a rectangular or square die shape defined by a planar area in the plane parallel to theupper surface207.

Thelight emitting device200 includes areflective buffer layer215 on theupper surface207 and the trench surfaces213, a lower Group III-V compound layer220 on thereflective buffer layer215, one or more quantum-well layers230 on the lower Group III-V compound layer220, and an upper Group III-V compound layer240. The lower Group III-V compound layer220 and the upper Group III-V compound layer240 each includes a group III element and a group V element. The group III element is typically gallium. The group V element is typically nitride. Group III-V compounds suitable for the lower Group III-V compound layer220 and the upper Group III-V compound layer240 can include GaN or InGaAlN. The lower Group III-V compound layer220 and the upper Group III-V compound layer240 can be respectively n-type and p-type doped. The portion of the upper Group III-V compound layer240 over thetrench surface213 is referred to as a sloped upper Group III-V compound layer240A and is oriented at an angle relative to theupper surface207 of thesubstrate205. Thelight emitting device200 also includes alower electrode270 on the lower Group III-V compound layer220 and anupper electrode260 on the upper Group III-V compound layer240.

In some embodiments, as shown inFIG. 4A, asemiconductor wafer400 includes a 2×2 array of light emittingstructures400A-400D formed on asubstrate405. Each of thelight emitting structures400A-400D can have a similar structure as that of thelight emitting device200 as described above. Thelight emitting structures400A-400D can be formed in a 2×2 matrix on a semiconductor wafer. Thelight emitting structures400A-400D can be used as a single light device, or they can be separated by cutting and dicing to form individual light emitting devices similar to thelight emitting device200. In another example, asemiconductor wafer500 comprising a 4×4 array of light emittingstructures510 is shownFIG. 4C.

Referring toFIGS. 3D and 4B, thelight emitting structures400A,400B can be formed ontrenches410 in asubstrate405. Thesubstrate205 can be formed by silicon, silicon oxide, gallium nitride, silicon carbide, sapphire, or glass. Thesubstrate205 can also be formed by a double-layer structure such as a silicon layer on glass, or simply a silicon-on-insulator (SOI) wafer. The silicon layer can have a (100) upper surface. The thickness of the silicon layer can be used to define the depth of a trench. For a silicon based substrate, thesubstrate405 can have anupper surface405A in the (100) crystalline plane direction. Thesurfaces410A,410B of thetrench410 can be along the (111) crystalline plane direction. Thesubstrate405 can also include a complimentary metal oxide semiconductor (CMOS) material and a CMOS electric circuitry for driving and controlling thelight emitting device400.

Areflective buffer layer415 is formed on thesurface405A of thesubstrate405 and thesloped surfaces410A,410B in thetrenches410. A function of thereflective buffer layer415 is to reflect light emitted by thelight emitting device400 away from thesubstrate405 to prevent the emitted light from being absorbed by thesubstrate405. For example, thesubstrate405 can be silicon based, which absorbs light in the visible light range. Thereflective buffer layer415 can have a reflectance coefficient higher than 30%, 50%, or 70% in the spectral range for the emitted light from thelight emitting device400.

Thereflective buffer layer415 can be deposited on thesubstrate405 using atomic layer deposition (ALD) in a vacuum chamber maintained at a temperature in the range of 550° C. to 850° C., such as about 700° C. Thereflective buffer layer415 can have a thickness of about 200 to 200,000 Angstroms such as 1000 to 10,000 Angstroms. Thereflective buffer layer415 can wet and form a uniform layer on thesubstrate405. Thereflective buffer layer415 can also have crystal structures with lattices expitaxially matched to thesubstrate405 and the lower Group III-V compound layer420 (described below).

The ALD formation of thereflective buffer layer415 can involve the use of TaN or TiN and a layer thickness of 10 to 100 angstromes. Atomic layer deposition (ALD) is a “nano” technology, allowing ultra-thin films of a few nanometers to be deposited in a precisely controlled way. ALD has the beneficial characteristics of self-limiting atomic layer-by-layer growth and is highly conformal to the substrate. For the formation of buffer layer in the light emitting devices, ALD can use two or more precursors such as liquid halide or organometallic in vapor form. The ALD can involve heat to dissociate the precursors into the reaction species. One of the precursors can also be a plasma gas. By depositing one layer per cycle, ALD offers extreme precision in ultra-thin film growth since the number of cycles determines the number of atomic layers and therefore the precise thickness of deposited film. Because the ALD process deposits precisely one atomic layer in each cycle, complete control over the deposition process is obtained at the nanometer scale. Moreover, ALD has the advantage of being capable of substantially isotropic depositions. ALD is therefore beneficial for depositing buffer layers on thesloped surfaces410A and410B in the V-shape trenches, and the vertical surfaces in a U-shape trench.

A lower Group III-V compound layer420 is formed on thereflective buffer layer415. The lower Group III-V compound layer420 can be formed by silicon doped n-GaN. The lower Group III-V compound layer420 can have a thickness in the range of 1 to 50 microns, such as 10 microns.

The material for thereflective buffer layer415 is selected to satisfy the requirements of high reflectivity and lattice matching with thesubstrate405 and a lower Group III-V compound layer420. For example, thereflective buffer layer415 can be formed by Al, aluminum nitride, Al oxide, Ag, Ag oxide, Au, Au oxide, and their alloys of Al, Au and Ag. Thereflective buffer layer415 can be also formed by one or more materials such as TaN, TiN, GaN, ZnO, AlN, HfN, AlAs, or SiC. Thereflective buffer layer415 can have a thickness in the range of 200 to 200,000 Angstroms, such as 1,000 to 10,000 Angstroms.

A quantum-well layer430 is formed on the lower Group III-V compound layer420. The quantum-well layer430 can be made of InN or InGaN with a thickness in the range of 5 to 200 Angstroms, such as 50 Angstroms. An upper Group III-V compound layer440 is formed on the quantum-well layer430. The upper Group III-V compound layer440 can be formed by p-type doped GaN such as Al_0.1Ga_0.9N. The upper Group III-V compound layer can be an aluminum doped p-GaN layer440 having a thickness in the range of 0.1 to 10 microns, such as 1 micron. The quantum-well layer430 forms a quantum well between the lower Group III-V compound layer420 and the upper Group III-V compound layer440. Aconductive layer450 is optionally formed on the upper Group III-V compound layer440. Theconductive layer450 is at least partially transparent. Materials suitable for theconductive layer450 can include ITO or a thin layer p-type ohmic metal such as Ni/Au. Anupper electrode460 can be formed on the conductive layer450 (or the upper Group III-V compound layer440 in absence of the conductive layer450). The inclusion of theconductive layer450 can be based on whether thesubstrate405 is thinned to all allow more emitted light to exit thelight emitting device400. Theconductive layer450 is preferably included if thesubstrate405 is not thinned so more light can exit theLight emitting device400. Alower electrode470 can then be formed on the lower Group III-V compound layer420. Theupper electrode460 andlower electrode470 can be respectively referred as p-electrode and n-electrode. The use of transparent ITO material in theconductive layer450 can significantly increase the conductivity between theelectrode460 and the upper Group III-V compound layer440 while maximizing the transmission light out of the upper surface of theconductive layer450 emitted from the quantum-well layer430.

The quantum-well layer430 can form a quantum well for electric carriers in between the lower Group III-V compound layer420 and the upper Group III-V compound layer440. An electric voltage can be applied across thelower electrode470 and theupper electrode460 to produce an electric field in the quantum-well layer430 to excite carriers in the quantum well formed by the quantum-well layer430, forming a quantum well for electric carriers in between the lower Group III-V compound layer420 and the upper Group III-V compound layer440. The recombinations of the excited carriers can produce light emission. The emission wavelengths are determined mostly by the bandgap of the material in the quantum-well layer430.

In the present specification, the term “quantum well” refers to a potential well that confines charge carriers or charged particles such as electrons and holes to a substantially two-dimensional planar region. In a semiconductor light emitting device, the quantum well can trap excited electrons and holes and define the wavelength of light emission when the electrons and the holes recombine in the quantum well and produce photons.

In the present specification, a quantum-well layer can include a uniform layer or a plurality of quantum wells. For example, a quantum-well layer (e.g.430 inFIGS. 5E to 5I) can include a substantially uniform layer made of InN, GaN, InGaN, AlGaN, InAlN, or AlInGaN. A quantum-well layer can also include a multi-layer structure defining one or more quantum wells. A quantum well can for example be formed by an InGaN, an AlGaN, an InAlN, or an InGaAlN layer sandwiched in between two GaN layers. A quantum well can also be formed by an InGaN layer sandwiched in between GaN or AlGaN layers. The quantum-well layer can include one or a stack of such layered structure each defining a quantum well as described above.

The bandgap for InN is about 1.9 eV, lower than the bandgap for GaN that is at about 3.4 eV. The lower bandgap of the InN or the InGaN layer can define a potential well for trapping charge carriers such as electrons and holes. The trapped electrons and holes can recombine to produce photons (light emission). The bandgap in the InN or the InGaN layer can therefore determine the colors of the light emissions. In other words, the colors of light emissions can be tuned by adjusting the compositions of In and Ga in InGaN. For example, a quantum well can produce red light emission from an InN layer, green light emission from an In(0.5)Ga(0.5)N layer, and blue light emission from an In(0.3)Ga(0.7)N in the quantum-well.

In one aspect, the disclosed light emitting device can include a substrate having a first surface and a second surface not parallel to the first surface; and a light emission layer disposed over the second surface to emit light, the light emission layer having a light emission surface which is not parallel to the first surface. By stating that one layer is disposed “over” or “above” another layer, this does not necessarily mean that the two layers must be in direct contact with each other; indeed, there may be one or more additional layers in between, as will be further apparent from other portions of this description. In another aspect, the disclosed light emitting device can include a substrate; and a light emission layer disposed over the substrate to emit light, the light emission layer having a footprint area and having a light emission surface area which is greater than the footprint area. In another aspect, the disclosed light emitting device can include a substrate having a first surface and a protrusion formed on the first surface; and a light emission layer disposed on the protrusion to emit light, the light emission layer having a light emission surface which is not parallel to the first surface.

FIGS. 3E and 3F respectively illustrate other examples of layer structures and material compositions for the light emitting structures, which can include trenches, protrusions such as pyramids, and other structures including a sloped surface not parallel to the upper surface of the substrate. The layers are shown in the horizontal direction only for the purpose of illustration. The sequence, thicknesses, and compositions described the layers on the sloped surfaces in the trenches or on the protrusions as well as the upper surface of the substrate. An Al₂O₃layer below the buffer layer can provide the reflectivity needed to reflect the light emission away from the substrate. The quantum well layers can be formed by two to ten periods of GaN:Mg and In_xGa_1-xN layers. The GaN:Mg layer can for example be about 5 nm thick. The In_xGa_1-xN layer can for example be about 2 nm thick. The lower Group III-V compound layer can be made of GaN doped with Mg or Si, and approximately 2 μm in thickness. The upper Group III-V compound layers can be made of GaN doped with Mg or Si, AlGaN doped with Mg or Si, and can be approximately 100 nm in thickness. The upper electrode can be formed by an ITO layer approximately 200 nm in thickness or a bi-layer of respectively made of Ni and Au.

In some embodiments, more than one reflective buffer layer can be formed on thesubstrate405. A first buffer layer and a second buffer layer are sequentially formed on thesubstrate405. At least the second buffer layer is reflective. The combined reflectance coefficient for the first buffer layer and the second buffer layer are higher than 30%, 50%, or 70% in the spectral range for the emitted light from the light emitting device. A lower Group III-V compound layer is then formed on the second reflective buffer layer. The quantum-well layer, the upper Group III-V compound layer, the conductive layer, the upper electrode, and the lower electrode can then be formed successively to form the light emitting device.

It should be noted that the light emitting structures in thewafers400,500 can be separated by dicing and cutting to form individual light emitting devices, each of which can be powered to emit light in separate applications. The light emitting structures in thewafers400,500 each can also be used as an integrated light emitting device. The lower electrodes of the light emitting structures in thewafers400 or500 can be electrically connected to allow them to be connected to a common external electrode. The upper electrodes of the light emitting structures in thewafers400 or500 can be connected to different external electrodes, which allow the light emitting structures in thewafers400 or500 to be individually addressed for turning on and off. The upper electrodes of the light emitting structures in thewafers400 or500 can also be connected to a common external electrode to allow the light emitting structures in thewafers400 or500 to be turned on and off as a group to provide a large-area light emitting device.

Another advantage of the described light emitting devices is that the disclosed Light emitting devices and fabrication processes can overcome differential thermal expansions and lattice mismatch between the lower Group III-V compound layers and the substrate and prevent associated layer cracking and delamination. It is known that the severity of the lattice mismatch and differential thermal expansions increase as a function of the lateral contact dimensions between the lower Group III-V compound layer and the substrate (or the buffer layer). Conventional LED light devices are often manufactured on 2-inch and 4-inch substrate and can thus suffer from large distress at the contact area between the lower Group III-V compound layer and the substrate (or the buffer layer). The lattice mismatch and differential thermal expansions are much larger for the (100) surface than for the (111) surface for a silicon-based substrate.

The disclosed light emitting devices breaks down the large (100) surface areas by segmented (111) trench surfaces and the (100) upper surfaces between the trenches. The openings of the trenches (210 inFIGS. 3A-3C) can be in a range between 100 microns to 100 mm, such as 1 to 20 mm. The width “D” of the (100) upper surface207 (FIG. 4B) can be kept narrow, for example, to be less than 1000 microns, which is much shorter than the width of the wafer substrate for fabricating convention LED light emitting devices. Similarly the width “W” of the bottom surface215 (FIG. 3C) can be kept narrow, for example, to be less than 200 microns. By keeping these dimensions small, stress related to differential thermal expansions and lattice mismatch can thus be drastically reduced.

The described light emitting devices can produce significantly higher emission light intensity than conventional LED devices. Referring toFIGS. 6A and 6B, a conventional LEDlight emitting device600 includes aflat emission surface610 on asubstrate600. Alight emitting device650 according to the present application includes asubstrate655 having anupper surface660 and a trench having sloped emission surfaces670. For a silicon based substrate, the upper surface can be along the (100) crystalline plane and the slopedemission surfaces670A,670B parallel to the (111) crystalline planes. The slopedemission surfaces670A,670B are at a 54.7° angle relative to theupper surface660. For the same foot print on theupper surface660, the sum of the areas of the emission surfaces670A,670B, measured along each of those surfaces, is 1/(cos(54.7° )) of (i.e., approximately 1.73 times) the area of theflat emission surface610 in theconventional LED device600. The disclosed light emitting devices are compatible with other substrate materials and relative orientations of the sloped trench surfaces. It should be understood that the disclosed light emitting devices are compatible with other substrate materials and relative orientations of the sloped trench surfaces. The sloped trench surface can be at an angle between 20 degrees and 80 degrees, or as a more specific example, between 50 degrees and 60 degrees relative to the upper surface of the substrate.

The emission surfaces in a trench in the disclosed light emitting device can be more than one time, or 1.2, or 1.4, or 1.6 times of the area of the trench openings. The large emission surface areas in the described light emitting devices allow the disclosed light emitting device can thus generate much higher light emission intensity than conventional LED devices. For a light emitting device (e.g.200 inFIG. 2A) formed on an individual die, the emission surfaces provided by the sloped trench surfaces in sum can have a larger area than the planar area of the light emitting device (e.g. the footprint area of thelight emitting device200 inFIG. 2A).

Another advantage of the described light emitting devices is that they can emit light in more concentrated angular range than conventional LED devices. Referring again toFIGS. 6A and 6B, theflat emission surface610 emits light in a 180 angular range. Theangular emission distribution620 has a 360 degree rotational symmetry relative to the substrate normal direction. Thelight emitting device650 includes slopedemission surfaces670A and670B emit light according toangular distributions680A and680B respectively, which combine to give an emissionangular distribution680. The emissionangular distribution680 has a 90 degree rotational symmetry relative to the substrate normal direction and a 70.6° angular width, less than half of the angular range in theangular emission distribution620 in the conventional LEDlight emitting device600. The emission of thelight emitting device650 is therefore much more concentrated and efficient than conventional LED light emitting devices. The disclosed light emitting devices are compatible with other substrate materials and relative orientations of the sloped trench surfaces. The light emitted from the sloped trench surfaces can be confined in an angular range narrower than 150 degrees, 120 degrees, 100 degrees, or 80 degrees, to provide different degrees of angularly concentrated light emission.

Referring toFIGS. 5A-5I, and8, the fabrication process of the light emitting device400 (200,300, or600) can include the following steps. It should be noted that the process is described using trenches as an example for the light emitting structure. The process is applicable to other light emitting structures such as protrusions (e.g. pyramids) and other different structures that include sloped surfaces not parallel to their respective upper surfaces of the substrates. Amask layer401 is formed on the substrate405 (FIG. 5A). Thesubstrate405 has anupper surface405A. Theopenings402 in themask layer401 are intended to define the locations and the openings of the trenches to be formed. One ormore trenches410 are formed in a substrate405 (step810, FIGS.5B1 and5B2). Thetrench410 can be formed by chemically etching of thesubstrate405. Wet etch is isotropic along all directions. For example, an etchant may have a slower etching rate for the (111) silicon crystal plane than in other crystalline plane directions. The etchant (e.g. KOH) can thus createtrenches410 in thesubstrate405 wherein the trench surfaces410A,410B are along the (111) silicon crystal planes. Etching can undercut the silicon underneath thehard mask layer401 to form the hangover of the (hard)mask layer401 on top of Si(100) wafer (FIG.5B1). Thehard mask layer401 is subsequently removed (a shown in FIG.5B2).

One or more buffer layers can next be next formed on thesubstrate405 using atomic layer deposition (ALD) or MOCVD (step820). For example, a first buffer layer213 (or210) is next formed on thesubstrate205 using atomic layer deposition (ALD) (step820). Thesubstrate205 can have an upper surface oriented in the (100) crystalline plane. Thebuffer layer213 or210 can be formed of GaN, ZnO, AlN, HfN, AlAs, or SiC. The atomic layer deposition of the buffer material can be implemented using commercial equipment such as IPRINT™ Centura® available from Applied Materials, Inc. The atomic layer deposition can involve the steps of degassing of a vacuum chamber, the application of a precursor material, and deposition of the buffer material monolayer by monolayer. The substrate (or the chamber) temperature can be controlled at approximately 600° C. The layer thickness to form nucleation in an ALD process can be as thin 12 angstrom, much thinner than the approximately thickness of 300 angstrom required by MOCVD for buffer layer formation in some convention LED structure (e.g. theLED structure100 depicted inFIG. 1). Thestep820 can also be referred as ALD of a low temperature buffer layer.

A reflective buffer layer is deposited on thesubstrate205 using atomic layer deposition (ALD) in a vacuum chamber maintained at a relatively lower temperature in a range of 550° C. to 850° C., such as 6700° C. A second buffer layer can be deposited on the first buffer layer using atomic layer deposition (ALD) in a vacuum chamber maintained at a relatively higher temperature in a range of 850° C. to 1250° C., such as 1,000° C. The reflective buffer layer can be formed of Al, an Al oxide, Ag, an Ag oxide, Au, an Au oxide, and an alloy comprising Al, Ag, or Au. The reflective buffer layer can also include GaN, ZnO, AlN, HfN, AlAs, or SiC. The reflective buffer layer can have a thickness of about 20-300 Angstroms. The crystal structure of the reflective buffer layer can have lattices expitaxially matched to the substrate and the lower Group III-V compound layer to reduce the strain in the lattice structural transition from the substrate to the lower Group III-V compound layer, which can reduce the chance for cracking and delamination in the multi-layer structure.

For thelight emitting device400, thereflective buffer layer415 can be formed by MOCVD, PVD, ALD, or molecular beam epitaxy (MBE) on thesurface405A of thesubstrate405 and thesloped surfaces410A,410B in thetrenches410. Thereflective buffer layer415 can be formed by ALD of TaN or TiN materials. In other examples, the formation of thereflective buffer layer415 can include one of the following procedures: depositions of AlN at1000° C. and GaN at 1000° C. using MOCVD, deposition of GaN at 700° C. using MOCVD followed by deposition of GaN at 1000° C. using MOCVD, deposition of HfN at 500° C. using PVD followed by deposition of GaN using MBE at 700° C., and deposition of SiCN at 1000° C. using MOCVD followed by deposition of GaN at 1000° C. using MOCVD.

An advantage for forming thereflective buffer layer415 on thesurfaces410A and410B in the V-shape trenches410 is that the (111) crystalline direction of thesurfaces410A and410B can allow better lattice matching between silicon substrate, thereflective buffer layer415, and the lower Group III-V compound layer420. Better lattice matching can significantly reduce the cracking problems caused by lattice mismatches in some convention light emitting devices.

A lower Group III-V compound layer420 is next formed on the reflective buffer layer415 (step830,FIG. 5D). The lower Group III-V compound layer420 can be formed by an n-type doped GdN material. GaN can be grown on thereflective buffer layer415 using MOCVD while silicon is doped. The silicon doping can enhance tensile stresses to make the compression and tensile strengths more balanced. As a result, cracks can be substantially prevented in the formation of the lower Group III-V compound layer420.

A quantum-well layer430 is next formed on the lower Group III-V compound layer430 (step840,FIG. 5E). The quantum-well layer430 can include can include a substantially uniform layer made of InN, GaN, InGaN, AlGaN, InAlN, or AlInGaN. The quantum-well layer430 can also include a multi-layer structure defining one or more quantum wells. A quantum well can for example be formed by an InGaN, an AlGaN, an InAlN, or an InGaAlN layer sandwiched in between two GaN layers or AlGaN layers. The quantum-well layer430 can include one or a stack of such layered structure each defining a quantum well.

An upper Group III-V compound layer440 is formed on the quantum-well layer430 (step850,FIG. 5F). Instead of having the lower Group III-V compound layer420 n-type doped and the upper Group III-V compound layer440 p-type doped, the lower Group III-V compound layer420 can be p-type doped and the upper Group III-V compound layer440 can be n-type doped (as shown in the flow chart ofFIG. 9).

A transparentconductive layer450 can next be optionally formed on the upper Group III-V compound layer440 (step860,FIG. 5G). The formation of the quantum-well layer can include multiple MOCVD steps. For example, each of the multiple steps can include the deposition of a layer 50 Angstroms in thickness.

The quantum-well layer430, the upper Group III-V compound layer440, and theconductive layer450 can also be formed by MOCVD. The MOCVD formations of the lower Group III-V compound layer420, the quantum-well layer430, the upper Group III-V compound layer440, and theconductive layer450 and the ALD formation of the buffer layers415 can be formed in a same ALD/CVD chamber system to minimize the number times the substrate's moving in and out of vacuum chambers. The process throughput can be further improved. Impurities during handling an also be reduced.

The quantum-well layer430, the upper Group III-V compound layer440, and theconductive layer450 can next be coated by a photo resist and patterned by photolithography. Portions of the quantum-well layer430, the upper Group III-V compound layer440, and theconductive layer450 can then be removed by wet etching to expose a portion of the upper surface of the lower Group III-V compound layer420 (step870,FIG. 5H).

Theupper electrode460 is next formed on the conductive layer450 (step880,FIG. 5H). Theupper electrode460 can include Ni/Au bi-layers that have thicknesses of 12 nm and 100 nm respectively. The fabrication of theupper electrode460 can involve the coating a photo resist layer on theconductive layer450 and the exposed upper surface of the lower Group III-V compound layer420. The photo resist layer is then patterned using photolithography and selectively removed to form a mask. Electrode materials are next successively deposited in the openings in the mask. The unwanted electrode materials and the photo resist layer are subsequently removed.

Thelower electrode470 is next formed on the lower Group III-V compound layer420 (FIG. 5H). Thelower electrode470 can include AuSb/Au bi-layers. The AuSb layer is 18 nm in thickness whereas the Au layer is 100 nm in thickness. The formation of thelower electrode470 can also be achieved by forming photo resist mask having openings on the lower Group III-V compound layer420, the depositions of the electrode materials and subsequent removal of the unwanted electrode materials and the photo resist layer. Thelight emitting device400 is finally formed.

Optionally, referring toFIG. 5I, aprotection layer480 can be introduced over thelight emitting device400 for protecting it from moisture, oxygen, and other harmful substance in the environment. Theprotection layer480 can be made of a dielectric material such as silicon oxide, silicon nitride, or epoxy. The protection layer can be patterned to expose theupper electrode460 and thelower electrode470 to allow them to receive external electric voltages. In some embodiments, the protection layer can also include thermally conductive materials such as Al and Cu to provide proper cooling thelight emitting device400.

It should be noted that the lower Group III-V compound layer and the upper Group III-V compound layer can have different doping arrangement as long as their doping content are opposite to each other. The lower Group III-V compound layer can be p-type doped and the upper Group III-V compound layer n-type doped. Alternatively, the lower Group III-V compound layer can be n-type doped and the upper Group III-V compound layer p-type doped.

FIG. 7 is a perspective view of anotherlight emitting device700 in accordance with the present application. Instead of a square opening in the mask layer (FIG. 5A and step800 below), a rectangle opening is formed in themask layer410 to produce an elongated trench after etching. A rectangular opening is sometimes preferred for the long aspect ratio of the trench opening. For example, some light devices require elongated light emission surface(s). For a silicon-based substrate, the upper surface can be parallel to the (100) crystalline plane. The sloped trench surfaces are parallel to the (111) crystalline plane similar to the previous descriptions. The long sloped trench surface can be at least 50% larger in area than the sloped first trench surfaces at the ends of the elongated trench.

The disclosed light emitting devices and fabrication processes can include one or more of the following advantages. The disclosed light emitting devices and fabrication processes can overcome associated with can overcome latter mismatch between the lower Group III-V compound layer and the substrate and prevent associated layer cracking in conventional light emitting devices. The disclosed light emitting devices and fabrication processes can also prevent cracking or delamination in the p-doped or n-doped Group III-V compound layer caused by different thermal expansions between the p-doped Group III-V compound layer and the substrate. An advantage associated with the disclosed light emitting devices is that light emitting devices can significantly increase light emission efficiency by increasing densities of the light emitting devices and by additional light emissions from the sloped or vertical surfaces in the trenches.

The light emission layers in the disclosed light emitting devices can be formed on types of structures other than trenches as described above. Referring toFIGS. 9A to 10C, for example, alight emitting device900 is formed on asubstrate905 having anupper surface907. Thelight emitting device900 includes aprotrusion910 on theupper surface907. Theprotrusion910 has one or more protrusion surfaces913 (FIGS. 10A-10C) at a slope relative to theupper surface907. Theprotrusion910 can also have atop surface919 that is substantially parallel to theupper surface907. The area of thetop surface919 can be kept smaller than 20% of one of the protrusion surfaces913. Theprotrusion910 can have the shape of a pyramid or a truncated pyramid above theupper surface907.

Thesubstrate905 can be silicon based: theupper surface907 can be parallel to the (100) crystalline plane. Theprotrusion surface913 can be parallel to the (111) crystalline surface. (Alternatively, theupper surface907 can be parallel to the (111) crystalline plane. Theprotrusion surface913 can be parallel to the (100) crystalline surface.) Thesubstrate905 can also include a multi-layer silicon-on-insulator (SOI) structure.

Anedge917 is formed at the intersection of two adjacent protrusion surfaces913. Thesubstrate905 can have a rectangular or square shape having anouter edge908. Thelight emitting device900 can be fabricated together with a batch of other light emitting devices on a semiconductor wafer, and diced to form separate dies. Thelight emitting device900 can have a rectangular or square die shape defined by a planar area in the plane parallel to theupper surface907.

Thelight emitting device900 includes areflective buffer layer915 on theupper surface907 and the protrusion surfaces913, a lower Group III-V compound layer920 on thereflective buffer layer915, one or more quantum-well layers930 on the lower Group III-V compound layer920, and an upper Group III-V compound layer940. The portion of the upper Group III-V compound layer940 over theprotrusion surface913 is oriented at an angle relative to theupper surface907 of thesubstrate905. Thelight emitting device900 also includes alower electrode970 on the lower Group III-V compound layer920 and anupper electrode960 on the upper Group III-V compound layer940.

In some embodiments, as shown inFIG. 11A,11B, asemiconductor wafer1000 includes a 2×2 array of light emittingstructures1000A-1000D formed on asubstrate905. Each of thelight emitting structures1000A-1000D can have a similar structure as that of thelight emitting device900 as described above. Thelight emitting structures1000A-1000D can be formed in a 2×2 matrix on a semiconductor wafer. Thelight emitting structures1000A-1000D can be used as a single light device, or they can be separated by cutting and dicing to form individual light emitting devices similar to thelight emitting device200. In another example, as shownFIG. 11C, asemiconductor wafer1100 can include a 4×4 array of light emittingstructures1110.

As described above, thesubstrate905 can be silicon based. Theupper surface907 can be parallel to the (100) crystalline plane. Theprotrusion surface913 can be parallel to the (111) crystalline surface. The width “D1” of the (100) upper surface207 (FIG. 11B) can be kept narrow, for example, to be less than 1000 microns, which is much shorter than the width of the wafer substrate for fabricating convention LED light emitting devices. By keeping this dimension small, stress related to differential thermal expansions and lattice mismatch can thus be drastically reduced.

The light emitting devices shown inFIGS. 9A-11C can produce different angular distribution from conventional LED devices. Referring toFIG. 12, alight emitting device900 includes aprotrusion910 formed on thesubstrate905. Light emitting layers havinglight emission surfaces1270A and1270B are formed on the sloped surfaces of theprotrusion910. For a silicon based substrate, theupper surface907 can be along the (100) crystalline plane and the sloped light emission surfaces1270A,1270B parallel to the (111) crystalline planes. The light emission surfaces1270A,1270B are at a 54.7° angle relative to theupper surface907. For the same foot print on the upper surface, the sum of the areas of the emission surfaces on the light emission surfaces1270A,1270B is approximately 1.73 times the area of theflat emission surface610 in the conventional LED device600 (FIGS. 6A). The disclosed light emitting devices are compatible with other substrate materials and relative orientations of the sloped protrusion surfaces. The sloped protrusion surface can be at an angle between 20 degrees and 80 degrees, or as a more specific example, between 50 degrees and 60 degrees relative to the upper surface of the substrate.

The emission surfaces on a protrusion in the disclosed light emitting device can be more than one time, or 1.2, or 1.4, or 1.6 times of the base area of the protrusion. The large emission surface areas in the described light emitting devices allow the disclosed light emitting device can thus generate much higher light emission intensity than conventional LED devices. The light emission from the light emission surfaces1270A,1270B can assume abroad distribution1280 as shown inFIG. 12.

Embodiments may include one or more of the following advantages. The disclosed light emitting device and related fabrication processes can provide light emitting devices at higher manufacturing throughput and thus manufacturing cost compared to the conventional light emitting devices. The disclosed light emitting device and related fabrication processes can also provide more-integrated light emitting devices that can include, for example, a light emitting element, a driver, power supply, and light modulation unit integrated on a single semiconductor substrate.

The foregoing descriptions and drawings should be considered as illustrative only of the principles of the invention. The invention may be configured in a variety of shapes and sizes and is not limited by the dimensions of the preferred embodiment. Numerous applications of the present invention will readily occur to those skilled in the art. Therefore, it is not desired to limit the invention to the specific examples disclosed or the exact construction and operation shown and described. Rather, all suitable modifications and equivalents may be resorted to, falling within the scope of the invention. For example, the n-doped and the p-doped Group III-V compound layers can be switched in position, that is, the p-doped Group III-V compound layer can be positioned underneath the quantum-well layer and n-doped Group III-V compound layer can be positioned on the quantum-well layer. The disclosed light emitting device may be suitable for emitting green, blue, and emissions of other colored lights.

It should be noted that the disclosed systems and methods are compatible with a wide range of applications such as laser diodes, blue/UV LEDs, Hall-effect sensors, switches, UV detectors, micro electrical mechanical systems (MEMS), and RF power transistors. The disclosed devices may include additional components for various applications. For example, a laser diode based on the disclosed device can include reflective surfaces or mirror surfaces for producing lasing light. For lighting applications, the disclosed system may include additional reflectors and diffusers.

It should also be understood that the presently disclosed light emitting devices are not limited to the trenches and protrusions described above. A substrate can include a first surface having a first orientation and a second surface having a second orientation. The first and the second surfaces may or may not form a trench or a protrusion. A plurality of Group III-V compound layers can be formed on the substrate. The Group III-V compound layers can emit light when an electric current is produced in the Group III-V compound layers.

Claims (11)

1. A light emitting device, comprising:

a silicon substrate having a first surface;

a trench having two surfaces formed beneath the first surface, the two surfaces of the trench are not parallel to the first surface, and wherein the first surface of the substrate is substantially parallel to the (100) crystal plane of the silicon and the surfaces of the trench are substantially parallel to the (111) crystal plane of the silicon;

a light emission layer formed over and parallel to the two surfaces of the trench to emit light.

2. The light emitting device ofclaim 1, wherein the two trench surfaces are each at an angle between 10 degrees and 90 degrees relative to the first surface.

3. The light emitting device ofclaim 1, wherein the trench comprises a third trench surface at a bottom of the trench, the third trench surface being substantially parallel to the first surface.

4. The light emitting device ofclaim 3, wherein the area ratio of the third trench surface to the total area of the two trench surfaces is smaller than 50%.

5. The light emitting device ofclaim 1, wherein the trench has two additional trench surfaces substantially parallel to the (111) crystal plane.

6. The light emitting device ofclaim 5, wherein the trench has an opening in the first surface of the substrate, and wherein the opening has a substantially rectangular shape.

7. The light emitting device ofclaim 1, wherein the trench has an opening in the first surface of the substrate, wherein the opening has a width in the range of 100 microns to 100 mm.

8. The light emitting device ofclaim 1, wherein the light emission layer comprises a quantum-well layer configured to emit light when an electric current is produced in the quantum-well layer.

9. The light emitting device ofclaim 1, further comprising a buffer layer between the substrate and the light emission layer.

10. The light emitting device ofclaim 1, further comprising additional trenches each having: (1) two surfaces formed beneath the first surface, the two surfaces are not parallel to the first surface, and (2) a light emission layer disposed along the two surfaces to emit light.

11. The light emitting device ofclaim 1 wherein the angle between the first surface and each of the two trench surfaces is 54.7 degrees.

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