US8183113B2 - Methods of forming recessed gate structures including blocking members, and methods of forming semiconductor devices having the recessed gate structures - Google Patents

Abstract

A recessed gate structure in a semiconductor device includes a gate electrode partially buried in a substrate, a blocking member formed in the buried portion of the gate electrode, and a gate insulation layer formed between the gate electrode and the substrate. The blocking member may effectively prevent a void or a seam in the buried portion of the gate electrode from contacting the gate insulation layer adjacent to a channel region in subsequent manufacturing processes. Thus, the semiconductor device may have a regular threshold voltage and a leakage current passing through the void or the seam may efficiently decrease.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. patent application Ser. No. 11/507,753 filed Aug. 22, 2006, now abandoned, which is a continuation-in-part of U.S. patent application Ser. No. 11/285,558 filed Nov. 22, 2005, now abandoned, which are incorporated herein by reference in their entireties. This application also claims priority under 35 USC §119 to Korean Patent Application No. 2005-77190 filed on Aug. 24, 2005, the contents of which are incorporated herein by reference in their entirety.

FIELD OF THE INVENTION

The present invention relates generally to gate structures and, more particularly, to recessed gate structures, methods of forming recessed gate structures, and semiconductor devices having recessed gate structures.

BACKGROUND OF THE INVENTION

As semiconductor devices have become highly integrated, patterns therein have been formed with greatly reduced widths and intervals therebetween. Accordingly, precise technologies for forming finer patterns in semiconductor devices are increasingly being demanded. A width of a gate in a semiconductor device having a high integration degree may decrease according to a decrease of a design rule in the semiconductor device. Hence, in order to ensure a minute width and an increased channel length, methods of manufacturing semiconductor devices including a recessed gate electrode have been developed.

A conventional recessed gate electrode is disclosed in Korean Patent No. 304,717, Japanese Laid-Open Patent Publication No. 2000-349289 and U.S. Pat. No. 6,762,098 issued to Hshieh et al. Particularly, Korean Patent No. 236048 describes a transistor including a recessed gate electrode having an enlarged lower portion.

FIGS. 1A to 1F are cross-sectional views illustrating a method of manufacturing a transistor having a recessed gate electrode in accordance with Korean Patent No. 236048.

Referring toFIG. 1A, a first photosensitive film is formed on asubstrate1 having an active region and a field region defined by anisolation layer3, and then the first photosensitive film is exposed and developed to form a firstphotosensitive film pattern6 partially exposing the active region of thesubstrate1.

Using the firstphotosensitive film pattern6 as an ion implantation mask, impurities are doped into an exposed portion of the active region, thereby forming afirst impurity region9 and achannel region12. Thechannel region12 is formed on thefirst impurity region9.

Referring toFIG. 1B, after removing the firstphotosensitive film pattern6, a second photosensitive film pattern14 is formed on thesubstrate1 to expose thechannel region12.

The exposedchannel region12 is partially etched using the second photosensitive film pattern14 as an etching mask so that afirst trench15 and asecond trench16 are formed on thechannel region12.

Referring toFIG. 1C, a first oxide layer is formed on the active region and on bottoms and sidewalls of the first and thesecond trenches15 and16 after removing the second photosensitive film pattern14.

Portions of the first oxide layer on the active region and the bottoms of the first and thesecond trenches15 and16 are removed to thereby form firstoxide layer patterns18 on the sidewalls of the first and thesecond trenches15 and16.

Referring toFIG. 1D, a thirdphotosensitive film pattern21 is formed on thesubstrate1 to expose the bottoms of the first and thesecond trenches15 and16 and also to expose the firstoxide layer patterns18.

Portions of thechannel region12 exposed by the first and thesecond trenches15 and16 are partially etched using the thirdphotosensitive film pattern21 and the firstoxide layer patterns18 as etching masks. Thus, lower portions of the first and thesecond trenches15 and16 are enlarged in rounded shapes. Thefirst impurity region9 is exposed by the first and thesecond trenches15 and16 having the enlarged lower portions.

Referring toFIG. 1E, the thirdphotosensitive film pattern21 and the firstoxide layer patterns18 are sequentially removed, and then secondoxide layer patterns24 are formed on sidewalls of the enlarged lower portions of the first and thesecond trenches15 and16.

A fourth photosensitive film pattern (not shown) is formed on thesubstrate1 to cover thefirst trench15. The fourth photosensitive film pattern exposes the bottom of thesecond trench16. A portion of the secondoxide layer patterns24 on the bottom of thesecond trench16 is removed using the fourth photosensitive film pattern as an etching mask. Hence, a portion of thefirst impurity region9 is exposed through thesecond trench16.

Referring toFIG. 1F, after removing the fourth photosensitive film pattern, a polysilicon layer is formed on thesubstrate1 to fill up the first and thesecond trenches15 and16.

A portion of the polysilicon layer on the active region is removed by an etch-back process to thereby fort recessedgates27 having enlarged lower portions buried in the first and thesecond trenches15 and16.

After a fifth photosensitive film pattern (not shown) is formed on thesubstrate1 to expose therecessed gates27,second impurity regions30 are formed at upper portions of therecessed gates27 by implanting impurities using the fifth photosensitive film pattern as a mask.

As for the above-mentioned method for manufacturing a transistor having the recessed gate, a void or a seam is generated in the enlarged lower portion of the recessed gate so that electrical characteristics of the transistor may deteriorate. This problem will be described in detail with reference to the accompanying drawings.

FIGS. 2A and 2B are electron microscopic pictures showing cross-sections of a conventional transistor having a recessed gate.

Referring toFIG. 2A, a polysilicon layer filling a trench having an enlarged lower portion is formed so as to form the recessed gate. An upper portion of the trench has a reduced width, for example, about 60 nm when a design rule of the transistor decreases. Thus, a void or a seam occurs in a lower portion of the polysilicon layer filling the trench, which has the enlarged lower portion. That is, the void or the seam is generated in a lower portion of the recessed gate.

As shown inFIG. 2B, the void or the seam generated in the lower portion of the recessed gate moves toward the gate insulation layer enclosing the recessed gate during subsequent processes for forming the transistor. Since a channel region of the transistor is formed around the lower portion of the recessed gate, the transistor may have poor electrical characteristics when the void or the seam makes contact with the channel region. In other words, when voids or seams are in contact with channel regions, threshold voltages of transistors in a unit cell of a semiconductor device may be considerably irregular and also leakage currents may be greatly increased through portions of the channel regions making contact with the voids or the seams. As a result, the transistor may have poor electrical characteristics when the void or the seam is in contact with the channel region thereof.

SUMMARY OF THE INVENTION

Some embodiments of the present invention provide a recessed gate structure having a blocking member for preventing the migration of a void or a seam to a gate insulating layer to allow improved electrical characteristics thereof.

Some embodiments of the present invention provide methods of forming a recessed gate structure having improved electrical characteristics by forming a blocking member therein.

Some embodiments of the present invention provide semiconductors including a recessed gate structure with a blocking member that can improve electrical characteristics thereof.

Some embodiments of the present invention provide methods of manufacturing semiconductor devices including recessed gate structures that can improve electrical characteristics thereof by forming a blocking member in the recessed gate structure.

According to some embodiments of the present invention, there is provided a recessed gate structure including a gate electrode partially buried in a substrate, a blocking member in a buried portion of the gate electrode, and a gate insulation layer formed between the substrate and the gate electrode.

According to some embodiments of the present invention, the gate electrode may include a first conductive layer pattern, a second conductive layer pattern and a third conductive layer pattern. The first conductive layer pattern may be buried in the substrate. The second conductive layer pattern may be formed on the first conductive layer pattern. The second conductive layer pattern may also be buried in the substrate. The third conductive layer pattern may be formed on the first conductive layer pattern, the second conductive layer pattern and the substrate.

According to some embodiments of the present invention, lower portions of the first and the second conductive patterns may be enlarged in circular shapes, elliptical shapes or track shapes, respectively.

According to some embodiments of the present invention, the first to the third conductive layer patterns may include doped polysilicon or metal.

According to some embodiments of the present invention, the blocking member may be formed between the first conductive layer pattern and the second conductive layer pattern.

According to some embodiments of the present invention, a void or a seam may be generated in the second conductive layer pattern. The blocking member may prevent the void or the seam from moving toward the gate insulation layer.

According to some embodiments of the present invention, the gate insulation layer may extend on the substrate. The blocking member may also extend on the extended gate insulation layer.

According to some embodiments of the present invention, the blocking member may include an oxide or a metal silicide. For example, the blocking member may include silicon oxide, tungsten silicide, titanium silicide, cobalt silicide or tantalum silicide.

According to some embodiments of the present invention, the blocking member may be formed by an oxidization and silicidation of a surface of the first conductive layer pattern.

According to some embodiments of the present invention, the blocking member may be formed by a silicidation of a surface of the first conductive layer pattern.

According to some embodiments of the present invention, a thickness ratio among the gate insulation layer, the first conductive layer pattern and the second conductive layer pattern may be in a range of about 1.0:1.0 to 4.0:0.1 to 1.0.

According to some embodiments of the present invention, the gate electrode may include a first conductive layer and a second conductive layer pattern. The first conductive layer may be buried in the substrate. The second conductive layer pattern may be formed on the first conductive layer. The second conductive layer pattern may include a lower portion buried in the substrate and an upper portion protruded from the substrate.

According to some embodiments of the present invention, the first conductive layer and the second conductive layer pattern may include doped polysilicon or metal.

According to some embodiments of the present invention, lower portions of the first conductive layer and the second conductive layer pattern may be enlarged in circular shapes, elliptical shapes or track shapes, respectively.

According to some embodiments of the present invention, the blocking member may be formed between the first conductive layer and a lower portion of the second conductive layer pattern.

According to some embodiments of the present invention, a void or a seam may occur in the lower portion of the second conductive layer pattern. The blocking member may prevent the void or the seam from moving toward the gate insulation layer.

According to some embodiments of the present invention, there is provided a recessed gate structure including a substrate with a recess structure, which has an enlarged lower portion, a gate electrode partially buried in the recess structure, a gate mask formed on the gate electrode, a blocking member formed in the gate electrode, and a gate insulation layer formed between the recess structure and the gate electrode. The gate insulation layer extends on the substrate.

According to some embodiments of the present invention, the gate electrode may include a first conductive layer pattern, a second conductive layer pattern and a third conductive layer pattern. The first conductive layer pattern may be formed on the gate insulation layer to partially fill up the recess structure. The second conductive layer pattern may be formed on the first conductive layer pattern to fully fill up the recess structure. The third conductive layer pattern may be formed on the gate insulation layer, the first conductive layer pattern and the second conductive layer pattern.

According to some embodiments of the present invention, the gate electrode may include a first conductive layer and a second conductive layer pattern. The first conductive layer may be formed on the gate insulation layer to partially fill up the recess structure. The first conductive layer may extend on the extended gate insulation layer. The second conductive layer pattern may be formed on the first conductive layer to completely fill up the recess structure. The second conductive layer pattern may include a lower portion buried in the recess structure and an upper portion protruded from the substrate.

According to some embodiments of the present invention, there is provided a semiconductor device including a substrate with an isolation layer for defining an active region on the substrate, a recess structure, which is formed in the active region and has an enlarged lower portion, a gate electrode partially buried in the recess structure, a gate insulation layer extending between the recess structure and the gate electrode onto the active region, a blocking member formed in a buried portion of the gate electrode, and source/drain regions formed at portions of the substrate adjacent to the buried portion of the gate electrode.

According to some embodiments of the present invention, a void may occur in the buried portion of the gate electrode. Here, the blocking member may prevent the void from moving toward the gate insulation layer adjacent to the buried portion of the gate electrode.

According to some embodiments of the present invention, there is provided a method of forming a recessed gate structure. In the method of forming the recessed gate structure, a recess structure having an enlarged lower portion is formed in a substrate. A gate insulation layer is formed on surfaces of the recess structure and the substrate. A gate electrode partially buried in the recess structure is formed on the gate insulation layer. A blocking member is formed in a buried portion of the gate electrode.

In the formation of the recess structure according to some embodiments of the present invention, a first mask may be formed on the substrate. A first recess may be formed from the surface of the substrate by etching the substrate using the first mask. A second mask may be formed on a sidewall of the first recess. A second recess may be formed beneath the first recess by etching the substrate using the second mask.

In the formation of the gate electrode and the blocking member according to some embodiments of the present invention, a first conductive layer pattern may be formed on the gate insulation layer to partially fill up the recess structure. The blocking member may be formed on the first conductive layer pattern. A second conductive layer pattern may be formed on the blocking member to fully fill up the recess structure. A third conductive layer pattern may be formed on the first conductive layer pattern, the second conductive layer pattern and the blocking member.

In the formation of the first conductive layer pattern and the blocking member according to some embodiments of the present invention, a first conductive layer may be formed on the gate insulation layer. A preliminary blocking member may be formed on the first conductive layer. The first conductive layer pattern and the blocking member may be formed by partially removing the first conductive layer and the preliminary blocking member.

According to some embodiments of the present invention, the preliminary blocking member may be partially removed using an etching solution including fluoride or an etching gas including fluoride. The first conductive layer may be partially removed by an etch-back process.

In the formation of the gate electrode and the blocking member according to some embodiments of the present invention, a first conductive layer may be formed on the gate insulation layer to partially fill up the recess structure. The blocking member may be formed on the first conductive layer. A second conductive layer pattern may be farmed on the blocking member to fill up the recess structure and to be protruded from the substrate.

According to some embodiments of the present invention, there is provided a method of manufacturing a semiconductor device. In the method of manufacturing the semiconductor device, an isolation layer is formed on a substrate to define an active region. A recess structure having an enlarged lower portion is formed in the active region. A gate insulation layer is formed from a surface of the recess structure onto the active region. A gate electrode partially buried in the recess structure is formed on the gate insulation layer. A blocking member is formed in a buried portion of the gate electrode. Source/drain regions are formed at portions of the substrate adjacent to the gate electrode.

According to some embodiments of the present invention, the blocking member is formed in the enlarged lower portion of the recessed gate electrode and efficiently separates a void or a seam formed in the gate electrode from the gate insulation layer adjacent to the channel region and prevents the void or the seam from moving to the channel region. Therefore, the semiconductor device having the recessed gate structure may have a uniform threshold voltage and a leakage current through the void or the seam may be suppressed. Additionally, the channel region of the semiconductor device is formed along the recessed gate electrode and the recessed gate electrode has the enlarged lower portion in a circular shape, an elliptical shape or a track shape, thereby considerably increasing a channel length of the semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:

FIGS. 1A to 1F are cross-sectional views illustrating a method of forming a conventional transistor including a recessed gate;

FIGS. 2A and 2B are electron microscopic pictures showing cross-sections of a conventional transistor including a recessed gate;

FIG. 3 is a cross-sectional view illustrating a recessed gate structure in accordance with some embodiments of the present invention;

FIGS. 4A to 4H are cross-sectional views illustrating a method of forming a recessed gate structure in accordance with some embodiments of the present invention;

FIG. 5 is a cross-sectional view illustrating a recessed gate structure in accordance with some embodiments of the present invention;

FIGS. 6A to 6E are cross-sectional views illustrating a method of forming a recessed gate structure in accordance with some embodiments of the present invention;

FIG. 7 is a cross-sectional view illustrating a semiconductor device including a recessed gate structure in accordance with some embodiments of the present invention;

FIGS. 8A to 8F are cross-sectional views illustrating a method of manufacturing a semiconductor device including a recessed gate structure in accordance with some embodiments of the present invention;

FIG. 9 is an electron microscopic picture illustrating a semiconductor device including a recessed gate structure in accordance with some embodiments of the present invention;

FIG. 10 is a graph illustrating the distribution of threshold voltages of transistors including recessed gate structures;

FIG. 11 is a cross-sectional view illustrating a semiconductor device including a recessed gate structure in accordance with some embodiments of the present invention; and

FIGS. 12A to 12D are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recessed gate structure in accordance with some embodiments of the present invention.

DESCRIPTION OF THE EMBODIMENTS

The present invention is described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the present invention are shown. The present invention may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of a device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. A device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Example embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The term “track shape” is defined herein to mean any generally circular or oval shape and that may or may not include one or more generally linear sections.

Recessed Gate Structures and Methods of Manufacturing the Same

FIG. 3 is a cross-sectional view illustrating a recessed gate structure in accordance with some embodiments of the present invention.

Referring toFIG. 3, a recessedgate structure160 formed on asubstrate100 includes agate insulation layer120, a blockingmember130, agate electrode150 and agate mask155.

Thesubstrate100 may include a semiconductor substrate such as a silicon wafer or a silicon-on-insulator (SOI) substrate. Arecess structure115 having afirst recess105 and asecond recess110 is formed in an upper portion of thesubstrate100. Thefirst recess105 may be formed from a surface of thesubstrate100 along a first direction substantially perpendicular to thesubstrate100. Thesecond recess110 is formed beneath thefirst recess105. Thesecond recess110 communicates with thefirst recess105. Thesecond recess110 may be enlarged along the first direction and a second direction substantially perpendicular to the first direction. Thus, thesecond recess110 may have a width substantially wider that that of thefirst recess105. For example, thesecond recess110 may have a cross section of a circular shape, an elliptical shape or a track shape.

Thegate insulation layer120 is formed on surfaces of thefirst recess105, thesecond recess110 and thesubstrate100. Thegate insulation layer120 may extend from therecess structure115 to thesubstrate100. Thegate insulation layer120 may include an oxide or a metal oxide having a high dielectric constant. For example, thegate insulation layer120 may include silicon oxide (SiO_X), hafnium oxide (HfO_X), tantalum oxide (TaO_X), zirconium oxide (ZrO_X), titanium oxide (TiO_X), aluminum oxide (AlO_X), etc. Thegate insulation layer120 may have a first thickness measured from the surfaces of the first and thesecond recesses105 and110. For example, thegate insulation layer120 may have a first thickness of about 50 Å to about 100 Å.

Thegate electrode150 includes a firstconductive layer pattern125, a secondconductive layer pattern140 and a thirdconductive layer pattern145.

The firstconductive layer pattern125 is formed on thegate insulation layer120 positioned on the surfaces of the first and thesecond recesses105 and110. The firstconductive layer pattern125 on thegate insulation layer120 partially fills up therecess structure115. A lower portion of the firstconductive layer pattern125 is positioned on thesecond recess110 and an upper portion of the firstconductive layer pattern125 is formed on thefirst recess105. Thus, the lower portion of the firstconductive layer pattern125 is also enlarged along the first direction and the second direction with respect to thesubstrate100. For example, the lower portion of the firstconductive layer pattern125 may have a cross section of a circular shape, an elliptical shape or a track shape.

The firstconductive layer pattern125 may be formed using a first conductive material. Examples of the first conductive material may include polysilicon doped with impurities, tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), copper (Cu), etc. The firstconductive layer pattern125 may have a second thickness of about 100 Å to about 200 Å based on an upper face of thegate insulation layer120. Therefore, a thickness ratio between thegate insulation layer120 and the firstconductive layer pattern125 may be in a range of about 1.0:1.0 to 4.0.

The blockingmember130 is formed on the firstconductive layer pattern125 in therecess structure115. The blockingmember130 is located between the firstconductive layer pattern125 and the secondconductive layer pattern140. According to some embodiments of the present invention, the blockingmember130 may be formed by an oxidization and silicidation of a surface of the firstconductive layer pattern125. According to some embodiments of the present invention, the blockingmember130 may be formed by depositing oxide on the firstconductive layer pattern125.

The blockingmember130 may have a third thickness substantially thinner than the first thickness of thegate insulation layer120. The blockingmember130 may have the third thickness of about 10 Å to about 50 Å measured from an upper face of the firstconductive layer pattern125. Hence, a thickness ratio of thegate insulation layer120 relative to the blockingmember130 may be in a range of about 1.0:0.1 to 1.0. Additionally, a thickness ratio between the firstconductive layer pattern125 and the blockingmember130 may be in a range of about, 1.0:0.05 to 0.5. As a result, a thickness ratio among thegate insulation layer120, the firstconductive layer pattern125 and the blockingmember130 may be in a range of about 1.0:1.0 to 4.0:0.1 to 1.0.

The secondconductive layer pattern140 of thegate electrode150 is formed on the blockingmember130 to completely fill up therecess structure115. The secondconductive layer pattern140 may be formed using a second conductive material. Examples of the second conductive material may include doped polysilicon, tungsten, aluminum, titanium, tantalum, copper, etc. The firstconductive layer pattern125 partially fills up the first and thesecond recesses105 and110, whereas the secondconductive layer pattern140 fully fills up the first and thesecond recesses105 and110. Particularly, an upper portion of the secondconductive layer pattern140 sufficiently fills up thefirst recess105, and a lower portion of the secondconductive layer pattern140 completely fills up thesecond recess110. Hence, the lower portion of the secondconductive layer pattern140 is enlarged in the first and the second directions relative to thesubstrate100. For example, the lower portion of the secondconductive layer pattern140 may have a cross section of a circular shape, an elliptical shape or a track shape.

In the formation of the secondconductive layer pattern140, a void148 or a seam is generated in the lower portion of the secondconductive layer pattern140. Particularly, the void148 or the seam occurs in the lower portion of the secondconductive layer pattern140 filling up thesecond recess110. The blockingmember130 enclosing the secondconductive layer pattern140 effectively prevents the migration of the void148 or the seam toward thegate insulation layer120 adjacent to a channel region of a semiconductor device such as a transistor. Therefore, the semiconductor device may have improved electrical characteristics such as a uniform threshold voltage, a reduced leakage current, etc.

The thirdconductive layer pattern145 of thegate electrode150 is formed on the firstconductive layer pattern125, the blockingmember130, the secondconductive layer pattern140 and thegate insulation layer120. The thirdconductive layer pattern145 may be formed using a third conductive material. For example, the thirdconductive layer pattern145 may be formed using doped polysilicon, tungsten, aluminum, titanium, tantalum, copper, etc.

According to some embodiments of the present invention, the thirdconductive layer pattern145 may have a polycide structure that includes a doped polysilicon film pattern and a metal silicide film pattern.

Thegate mask155 is formed on the thirdconductive layer pattern145 of thegate electrode150. Thegate mask155 may be formed using a material having an etching selectivity relative to thegate electrode150. That is, thegate mask155 may be formed using, for example, a nitride, an oxynitride or an oxide. For example, thegate mask155 may be formed using silicon nitride, silicon oxynitride, titanium oxynitride, silicon oxide, etc.

As described above, the migration of the void148 or the seam is efficiently blocked by the blockingmember130 formed in thegate electrode150 so that the recessedgate structure160 may have a uniform threshold voltage and a reduced leakage current by preventing the void148 or the seam from contacting thegate insulation layer120 adjacent to the channel region.

FIGS. 4A to 4H are cross-sectional views illustrating a method of forming a recessed gate structure in accordance with some embodiments of the present invention.

Referring toFIG. 4A, abuffer oxide layer170 and afirst mask layer175 are successively formed on asubstrate100 corresponding to a silicon wafer or an SOI substrate.

Thebuffer oxide layer170 may be formed on thesubstrate100 by, for example, a thermal oxidation process, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a high density plasma-chemical vapor deposition (HDP-CVD) process, etc.

Thefirst mask layer175 may be formed on thebuffer oxide layer170 using a material having an etching selectivity with respect to thebuffer oxide layer170 and thesubstrate100. For example, thefirst mask layer175 may be formed using a nitride such as silicon nitride or an oxynitride such as silicon oxynitride, titanium oxynitride, etc. Thefirst mask layer175 may be formed by, for example, a CVD process, a PECVD process, an atomic layer deposition (ALD) process, a sputtering process, an electron beam evaporation process, a pulsed laser deposition (PLD) process, etc.

After a first photoresist film is formed on thefirst mask layer175, the first photoresist film is exposed and developed to form afirst photoresist pattern180 that partially exposes thefirst mask layer175.

Referring toFIG. 4B, thefirst mask layer175 is partially etched using thefirst photoresist pattern180 as an etching mask, thereby forming afirst mask190 on the bufferoxide layer pattern185. Thefirst photoresist pattern180 may be removed from thefirst mask190 by, for example, an ashing process and/or a stripping process.

Thebuffer oxide layer170 and thesubstrate100 are partially etched by a first etching process using thefirst mask190 as an etching mask. Thus, afirst recess105 is formed at an upper portion of thesubstrate100 and a bufferoxide layer pattern185 is formed on thesubstrate100. Thefirst mask190 serves as the etching mask for forming thefirst recess105. The first etching process may include an anisotropic etching process. Thefirst recess105 may have a first width W1. For example, thefirst recess105 may have a first width W1 of about 500 Å to about 700 Å. Thefirst recess105 may be formed along a first direction substantially perpendicular to thesubstrate100. Namely, thefirst recess105 is formed along a vertical direction from a surface of thesubstrate100.

Asecond mask layer195 is continuously formed on a bottom and a sidewall of thefirst recess105 and on thefirst mask190. In particular, thesecond mask layer195 is formed on the sidewall of thefirst recess105, on vertical cross sections of thesubstrate100, the bufferoxide layer pattern185 and thefirst mask190, which are exposed by thefirst recess105, and on an upper face of thefirst mask190. Thesecond mask layer195 may be formed using a material that has an etching selectivity with respect to thesubstrate100. For example, thesecond mask layer195 may be formed using an oxide such as silicon oxide, a nitride such as silicon nitride or an oxynitide such as silicon oxynitride or titanium oxynitride. Thesecond mask layer195 may be formed, for example, by a CVD process, an ALD process, a PECVD process, an HDP-CVD process, a sputtering process, an electron beam evaporation process, a PLD process, etc. According to some embodiments of the present invention, thesecond mask layer195 may be formed using a material substantially the same as that of thefirst mask layer175. According to some embodiments of the present invention, thesecond mask layer195 may be formed using a material different from that of thefirst mask layer175.

Referring toFIG. 4C, asecond mask198 is formed on the sidewall of thefirst recess105 by removing portions of thesecond mask198 on thefirst mask190 and the bottom of thefirst recess105. Thesecond mask198 may be formed, for example, by an etch-back process. Since thesecond mask198 is formed on the sidewall of thefirst recess105, the portion of thesubstrate100 is exposed by thefirst recess105 after the formation of thesecond mask198.

The exposed portion of thesubstrate100 is etched by a second etching process using thesecond mask198 as an etching mask so that asecond recess110 is formed beneath thefirst recess105. Thesecond recess110 communicates with thefirst recess105. Thesecond mask198 serves as the etching mask for forming thesecond recess110. Therefore, arecess structure115 including the first and thesecond recesses105 and110 is formed at the upper portion of thesubstrate100. The second etching process may include an isotropic etching process. As a result of thesecond mask198, thesecond recess110 is formed and extended along the first direction and a second direction substantially perpendicular to the first direction. That is, thesecond recess110 is formed in a vertical direction and a horizontal direction relative to thesubstrate100. Hence, thesecond recess110 has a second width W2 substantially wider than the first width W1 of the first recess105 (seeFIG. 4C). For example, thesecond recess110 may have a cross section having a circular shape, an elliptical shape, a track shape, etc.

Referring toFIG. 4D, thefirst mask190, thesecond mask198 and the bufferoxide layer pattern185 are sequentially removed to complete therecess structure115 at the upper portion of thesubstrate100. Thefirst mask190, thesecond mask198 and the bufferoxide layer pattern185 may be simultaneously removed from thesubstrate100.

Agate insulation layer120 is formed on a surface of therecess structure115 and thesubstrate100. Thegate insulation layer120 extends on thesubstrate100 from thesecond recess110 and thefirst recess105. Thegate insulation layer120 may be formed, for example, by a thermal oxidation process, a CVD process, a PECVD process, an ALD process, an HDP-CVD process, etc. Further, the gate insulation layer may be formed using an oxide or a metal oxide having a high dielectric constant. For example, thegate insulation layer120 may be formed using silicon oxide, hafnium oxide, tantalum oxide, zirconium oxide, titanium oxide, aluminum oxide, etc. Thegate insulation layer120 may have a first thickness measured from the upper faces of the first and thesecond recesses105 and110. For example, thegate insulation layer120 may have a first thickness of about 50 Å to about 100 Å. When the first width W1 of thefirst recess105 is about 600 Å, the first thickness of thegate insulation layer120 may be about 50 Å.

A firstconductive layer122 is formed on thegate insulation layer120 with which therecess structure115 is coated. The firstconductive layer122 may be formed using a first conductive material such as doped polysilicon or metal. The firstconductive layer122 may be formed, for example, by a CVD process, a PECVD process, an ALD process, a sputtering process, a PLD process, an electron beam evaporation process, etc. The firstconductive layer122 may have a second thickness based on an upper face of thegate insulation layer120. For example, the firstconductive layer122 may have a second thickness of about 100 Å to about 200 Å. When thefirst recess105 has a first width W1 of about 600 Å, the firstconductive layer122 may have a second thickness of about 100 Å. Since thegate insulation layer120 has a first thickness of about 50 Å, thefirst recess105 has a reduced width of about 300 Å in accordance with the formations of thegate insulation layer120 and the firstconductive layer122. That is, the firstconductive layer122 may have a second thickness corresponding to one-third of the first width W1 so that thefirst recess105 may have a reduced width corresponding to a half of the first width W1.

According to some embodiments of the present invention, apreliminary blocking member123 may be formed on the firstconductive layer122, for example, by an oxidization and silicidation of a surface of the firstconductive layer122. For example, thepreliminary blocking member123 may be formed by a thermal oxidation process. In the thermal oxidation process, oxygen may react with silicon contained in the firstconductive layer122 so that thepreliminary blocking member123 may be formed on the firstconductive layer122.

According to some embodiments of the present invention, thepreliminary blocking member123 may be formed by depositing an oxide on the firstconductive layer122 through, for example, a CVD process, a PECVD process, an ALD process or an HDP-CVD process.

Thepreliminary blocking member123 may have a third thickness measured from an upper face of the firstconductive layer122. For example, thepreliminary blocking member123 may have a third thickness of about 10 Å to about 50 Å. When the first width W1 of thefirst recess105 is about 600 Å, the third thickness of thepreliminary blocking member123 may be about 10 Å. Since thepreliminary blocking member123 has a relatively thin third thickness, the reduced width of thefirst recess105 may be slightly decreased after the formation of thepreliminary blocking member123.

Referring toFIG. 4E, a secondconductive layer138 is formed on thepreliminary blocking member123 to completely fill up therecess structure115 having the first and thesecond recesses105 and110. The secondconductive layer138 may be formed, for example, using a second conductive material such as doped polysilicon or metal. Further, the secondconductive layer138 may be formed, for example, by a CVD process, a PECVD process, an ALD process, a sputtering process, a PLD process, an electron beam evaporation process, etc.

In the formation of the secondconductive layer138 filling up therecess structure115 having an enlarged lower portion (the second recess110), the secondconductive layer138 may not completely fill up thesecond recess110 because thesecond recess110 has an enlarged structure compared to thefirst recess105. Thus, a void148 or a seam may be generated in a lower portion of the secondconductive layer138 filling thesecond recess110.

Referring toFIG. 4F, the secondconductive layer138 is partially removed to form a secondconductive layer pattern140 buried in therecess structure115. Particularly, a portion of the secondconductive layer138 over thesubstrate100 is removed until thepreliminary blocking member123 is exposed to thereby form the secondconductive layer pattern140 sufficiently filling up therecess structure115. The secondconductive layer pattern140 may be formed by an etch-back process. When the secondconductive layer pattern140 is formed in therecess structure115, thepreliminary blocking member123 is exposed.

The exposedpreliminary blocking member123 and the firstconductive layer122 are partially removed until thegate insulation layer120 is exposed to form a blockingmember130 and a firstconductive layer pattern125. The blockingmember130 encloses the secondconductive layer pattern140 and the firstconductive layer pattern125 locates between thegate insulation layer120 and the blockingmember130. Namely, the firstconductive layer pattern125 and the blockingmember130 are sequentially formed between thegate insulation layer120 and the secondconductive layer pattern140 in therecess structure115. The blockingmember130 may be formed, for example, by a wet etching process using an etching solution containing fluorine (F). Alternatively, the blockingmember130 may be formed, for example, by a dry etching process using an etching gas containing fluorine. Additionally, the firstconductive layer pattern125 may be formed, for example, by an etch-back process. When the firstconductive layer pattern125, the blockingmember130 and the secondconductive layer pattern140 are formed in therecess structure115, a portion of thegate insulation layer120 on thesubstrate100 is exposed.

Referring toFIG. 4G, a thirdconductive layer143 is formed on the exposed portion of thegate insulation layer120, the firstconductive layer pattern125, the blockingmember130 and the secondconductive layer pattern140. The thirdconductive layer143 may be formed using a third conductive materials such as doped polysilicon, tungsten, titanium, aluminum, tantalum, copper, etc. The thirdconductive layer143 may be formed, for example, by a CVD process, a PECVD process, an ALD process, a sputtering process, an electron beam evaporation process, a PLD process, etc. According to some embodiments of the present invention, the thirdconductive layer143 may have a polycide structure that includes a doped polysilicon film and a metal silicide film.

Agate mask layer153 is formed on the thirdconductive layer143. Thegate mask layer153 may be formed using a material that has an etching selectivity with respect to the thirdconductive layer143. For example, thegate mask layer153 may be formed using a nitride such as silicon nitride, an oxynitride such as silicon oxynitride or titanium oxynitride, or an oxide such as silicon oxide. Further, thegate mask layer153 may be formed, for example, by a CVD process, a PECVD process, an ALD process, an HDP-CVD process, a sputtering process, an electron beam evaporation process, a PLD process, etc.

In the formation of the thirdconductive layer143 and/or thegate mask layer153, the void148 generated in the lower portion of the secondconductive layer pattern140 may move toward thegate insulation layer120 adjacent to a channel region. The blockingmember130 effectively prevents the migration of the void148 from making contact with thegate insulation layer120 adjacent to the channel region. As a result, a recessed gate structure160 (seeFIG. 4H) may have improved electrical characteristics regardless of the presence of avoid148.

Referring toFIG. 4H, after a second photoresist pattern (not shown) is formed on thegate mask layer153, thegate mask layer153 is etched using the second photoresist pattern as an etching mask. Hence, agate mask155 is formed on a portion of the thirdconductive layer143 directly over the secondconductive layer pattern140. The second photoresist pattern may be removed from thegate mask155, for example, by an ashing process and/or a stripping process.

The thirdconductive layer143 is partially removed using thegate mask155 as an etching mask to form a thirdconductive layer pattern145 on the secondconductive layer pattern140, the firstconductive layer pattern125, thegate insulation layer120 and the blockingmember130. Thus, agate electrode150 having the first to the thirdconductive layer patterns120,140 and145 is formed on thesubstrate100. Thegate mask155 is positioned on the thirdconductive layer pattern145. When thegate electrode150 is formed, the recessedgate structure160 having thegate insulation layer120, thegate electrode150 and thegate mask155 is completed on thesubstrate100.

As for the recessedgate structure160, the first and the secondconductive layer patterns125 and140 are buried in therecess structure115 whereas the thirdconductive layer pattern145 are protruded from thesubstrate100. That is, a lower portion of the recessedgate structure160 is buried in thesubstrate100 while an upper portion of the recessedgate structure160 protrudes upwardly from thesubstrate100. Since the blockingmember130 encloses the secondconductive layer pattern140 in therecess structure115, the thirdconductive layer pattern145 is positioned on the blockingmember115, the secondconductive layer pattern140 and the firstconductive layer pattern120.

According to some embodiments of the present invention, the blockingmember130 is formed in the lower portion of the recessedgate structure160 buried in thesubstrate100. The blockingmember130 efficiently blocks the movement of a void148 toward thegate insulation layer120 so that the recessedgate structure160 may have enhanced electrical characteristics.

FIG. 5 is a cross-sectional view illustrating a recessed gate structure in accordance with some embodiments of the present invention.

Referring toFIG. 5, a recessedgate structure260 includes agate insulation layer220, a blockingmember230, agate electrode245 and agate mask250.

Thegate electrode245 has a lower portion buried in asubstrate200 and an upper portion protruded from thesubstrate200. Particularly, the lower portion of thegate electrode245 is buried in arecess structure215 formed at an upper portion of thesubstrate200.

Therecess structure215 includes afirst recess205 and asecond recess210 formed in the upper portion of thesubstrate200. Thesubstrate200 may correspond to a silicon wafer or an SOI substrate. Thefirst recess205 may be formed from a surface of thesubstrate200 along a first direction substantially perpendicular relative to thesubstrate200. Thesecond recess210 may be formed beneath thefirst recess205 in the first direction and a second direction substantially perpendicular to the first direction. For example, thesecond recess210 may be enlarged along a vertical direction and a horizontal direction with respect to thesubstrate200. Thesecond recess210 may have a width substantially wider than a width of thefirst recess205 whereas a depth of thesecond recess210 may be substantially shallower than a depth of thefirst recess205.

Thegate insulation layer220 is formed on surfaces of therecess structure215 and thesubstrate200. In particular, thegate insulation layer220 is positioned on thesubstrate200, a surface of thefirst recess205 and a surface of thesecond recess210. For example, thegate insulation layer220 may have a thickness of about 50 Å to about 100 Å based on upper faces of therecess structure215 and thesubstrate200. Thegate insulation layer220 may include oxide or metal oxide having a high dielectric constant.

Thegate electrode245 includes a firstconductive layer225 and a second conductive layer pattern240.

The firstconductive layer225 is formed on thegate insulation layer220 to partially fill up therecess structure215. Therecess structure215 is sufficiently filled with the second conductive layer pattern240. The second conductive layer pattern240 is protruded from thesubstrate200. The firstconductive layer225 extends along a surface of therecess structure215 and a surface of thesubstrate200. The firstconductive layer225 and the second conductive layer pattern240 may include polysilicon doped with impurities. The first conductive layer may have a thickness of about 100 Å to about 200 Å measured from an upper face of thegate insulation layer220.

The blockingmember230 is disposed on the firstconductive layer225. Particularly, the blockingmember230 is located between the firstconductive layer225 and the second conductive layer pattern240 in therecess structure215. Additionally, the blockingmember230 extends on the firstconductive layer225, which is disposed on thegate insulation layer220 positioned on thesubstrate200. According to some embodiments of the present invention, the blockingmember230 may have an area substantially the same as that of thegate insulation layer220.

The blockingmember230 may include a metal silicide. For example, the blockingmember230 may include tungsten silicide (WSi_X), titanium silicide (TiSi_X), tantalum silicide (TaSi_X), cobalt silicide (CoSi_X), etc. The blockingmember230 may have a thickness of about 10 Å to about 50 Å based on an upper face of the firstconductive layer225. Therefore, a thickness ratio among thegate insulation layer220, the firstconductive layer225 and the blockingmember230 may be in a range of about 1.0:1.0 to 4.0:0.1 to 1.0.

Since the second conductive layer pattern240 of thegate electrode245 has a lower portion buried in therecess structure215, a void248 or a seam may occur in the lower portion of the second conductive layer pattern240. The blockingmember230 blocks the void248 or the seam from moving toward a channel region so that the void248 or the seam is separated from thegate insulation layer220 adjacent to the channel region. Additionally, because the blockingmember230 includes the metal silicide, an interface resistance between the second conductive layer pattern240 and the blockingmember230 may be reduced. Furthermore, the blockingmember230 extends along a surface of therecess structure215 and an upper face of thesubstrate200 so that the blockingmember230 may sufficiently enclose the second conductive layer pattern240.

Thegate mask250 is formed on the second conductive layer pattern240 of thegate electrode245. Thegate mask250 serves as an etching mask for forming thegate electrode245 and also electrically insulates thegate electrode245 from an upper wiring in a semiconductor device.

FIGS. 6A to 6E are cross-sectional views illustrating a method of forming a recessed gate structure in accordance with example embodiments of the present invention.

Referring toFIG. 6A, a buffer oxide layer (not shown) and a first mask layer (not shown) are successively formed on asubstrate200, and then the first mask layer is etched by a photolithography process to form afirst mask290 on the buffer oxide layer.

The buffer oxide layer may be formed, for example, by a thermal oxidation process, a CVD process, a PECVD process, an HDP-CVD process, etc. Thefirst mask290 may be formed using oxynitride by a CVD process, a PECVD process, an ALD process, a sputtering process, an electron beam evaporation process, a PLD process, etc.

The buffer oxide layer and thesubstrate200 are partially etched by a first etching process using thefirst mask290 as an etching mask so that afirst recess205 is formed at an upper portion of thesubstrate200 and a bufferoxide layer pattern285 is formed on thesubstrate200. The first etching process may include an anisotropic etching process such as a wet anisotropic etching process or a dry anisotropic etching process. Thefirst recess205 may be formed in a perpendicular direction from a surface of thesubstrate200.

Referring toFIG. 6B, a second mask layer (not shown) is formed on a bottom and a sidewall of thefirst recess205 and on thefirst mask290. The second mask layer is partially etched to form asecond mask298 on the sidewall of thefirst recess205. That is, portions of the second mask layer on the bottom of thefirst recess205 and thefirst mask290 are removed to form thesecond mask298 on the sidewall of thefirst recess205 only. Thesecond mask298 may be formed using, for example, oxide, nitride or oxynitide by a CVD process, an ALD process, a PECVD process, an HDP-CVD process, a sputtering process, an electron beam evaporation process, a PLD process, etc.

With a second etching process using thesecond mask298 as an etching mask, a portion of thesubstrate200 exposed through thefirst recess205 is etched along a vertical direction and a horizontal direction so that asecond recess210 is formed beneath thefirst recess205. Thesecond recess210 may be formed by a dry isotropic etching process or a wet isotropic etching process. Thus, arecess structure215 having the first and thesecond recesses205 and210 is formed at the upper portion of thesubstrate200. Thesecond recess210 may have a cross section that has a circular shape, an elliptical shape, a track shape, etc.

Referring toFIG. 6C, after thesecond mask298, thefirst mask290 and the bufferoxide layer pattern285 are successively removed, agate insulation layer220 is formed on surfaces of therecess structure215 and an upper face of thesubstrate200. Thegate insulation layer220 may be formed using, for example, oxide or metal oxide by a thermal oxidation process, a CVD process, a PECVD process, an ALD process, an HDP-CVD process, etc. Thegate insulation layer220 extends along the surfaces of therecess structure215 and the upper face of thesubstrate200.

A firstconductive layer225 is formed on thegate insulation layer220 to partially fill up therecess structure215. The firstconductive layer225 may be formed, for example, using doped polysilicon or metal by a CVD process, a PECVD process, an ALD process, a sputtering process, a PLD process, an electron beam evaporation process, etc. When the firstconductive layer225 is formed using polysilicon doped with impurities, the impurities may be doped, for example, by an ion implantation process, a diffusion process or an in-situ doping process. The firstconductive layer225 may have a length substantially the same as that of thegate insulation layer220. Namely, the firstconductive layer225 extends along the surfaces of therecess structure215 and the upper face of thesubstrate200.

A blockingmember230 is formed on the firstconductive layer225. According to some embodiments of the present invention, the blockingmember230 may be formed using metal silicide, for example, by a CVD process, an ALD process, a PECVD process, a PLD process, an electron beam evaporation process, a sputtering process, etc. According to some embodiments of the present invention, the blockingmember230 may be formed on the firstconductive layer225 using a silicidation process on a surface of the firstconductive layer225.

The blockingmember230 may have a length substantially the same as that of thegate insulation layer220. That is, the blockingmember230 may be formed along the surfaces of therecess structure215 and the upper face of thesubstrate200.

Referring toFIG. 6D, a secondconductive layer237 is formed on the blockingmember230 to fully fill up therecess structure215. The secondconductive layer237 may be formed using, for example, doped polysilicon, tungsten, aluminum, tantalum, titanium, copper, etc. Additionally, the secondconductive layer237 may be formed, for example, by a CVD process, a PECVD process, an ALD process, a sputtering process, an electron beam evaporation process, a PLD process, etc.

During forming of the secondconductive layer237, a void248 or a seam may occur in a lower portion of the secondconductive layer237 because the lower portion of the secondconductive layer237 is formed in the enlargedsecond recess210.

Referring toFIG. 6E, after a gate mask layer (not shown) is formed on the secondconductive layer237, the gate mask layer is partially etched to form agate mask250 on the secondconductive layer237. Thegate mask250 may be formed, for example, using nitride, oxynitride or oxide by a CVD process, a PECVD process, an ALD process, an HDP-CVD process, a sputtering process, an electron beam evaporation process, a PLD process, etc.

When thegate mask250 is formed on the secondconductive layer237, the void248 or the seam formed in the lower portion of the secondconductive layer237 may move toward thegate insulation layer220 adjacent to a channel region. Here, the blockingmember230 sufficiently prevents the void248 or the seam from moving toward thegate insulation layer220. Therefore, a recessedgate structure260 may have improved electrical characteristics although the void248 or the seam occurs in thegate electrode245.

The secondconductive layer237 is partially removed using thegate mask250 as an etching mask to form a second conductive layer pattern240. The second conductive layer pattern240 includes an upper portion that protrudes over thesubstrate200 and the lower portion buried in therecess structure215. Hence, the recessedgate structure260 having thegate insulation layer220, thegate electrode245, the blockingmember230 and thegate mask250 is completed on thesubstrate200. Thegate electrode245 includes the firstconductive layer225 and the second conductive layer pattern240.

Semiconductor Device and Method of Manufacturing the Same

FIG. 7 is a cross-sectional view illustrating a semiconductor device having a recessed gate structure in accordance with some embodiments of the present invention.

Referring toFIG. 7, the semiconductor device includes a recessedgate structure310 partially buried in asemiconductor substrate300, and source/drain regions395 formed at portions of thesemiconductor substrate300 adjacent to the recessedgate structure310.

The recessedgate structure310 has agate insulation layer330, a blockingmember340, agate electrode360 and agate mask365.

The source/drain regions395 may have depths substantially the same as a depth of a portion of thegate electrode360 having a maximum width in thesemiconductor substrate300.

Anisolation layer305 is formed on thesemiconductor substrate300 to define an active region and a field region. Theisolation layer305 may include an oxide such as silicon oxide.

Arecess structure325 having afirst recess315 and asecond recess320 is formed in the active region of thesemiconductor substrate300. Thefirst recess315 is formed vertically from a direction along which an upper face of thesubstrate300 stretches. Thesecond recess320 is vertically and horizontally enlarged beneath thefirst recess315. Thesecond recess320 has a width greater than that of thefirst recess315 so that therecess structure325 has an enlarged lower portion. Thesecond recess320 may be enlarged in a circular shape, an elliptical shape or a track shape.

Thegate insulation layer330 is formed on the active region of thesubstrate300 and a surface of therecess structure325. Thegate insulation layer330 is formed along the surface of therecess structure325 and an upper face of the active region of thesubstrate300. Thegate insulation layer330 may include oxide or metal oxide.

Thegate electrode360 includes a firstconductive layer pattern335, a secondconductive layer pattern350 and a thirdconductive layer pattern355.

The firstconductive layer pattern335 partially fills up therecess structure325 and only locates on a portion thegate insulation layer330 positioned on therecess structure325. The firstconductive layer pattern335 may include doped polysilicon or metal.

The blockingmember340 is formed on the firstconductive layer pattern335. The blockingmember340 may include oxide. In one example embodiment of the present invention, the blockingmember340 may be formed by an oxidation of a surface of the firstconductive layer pattern335. In another example embodiment of the present invention, the blockingmember340 may be formed on the firstconductive layer pattern335 by depositing oxide on the firstconductive layer pattern335.

The secondconductive layer pattern350 is formed on the blockingmember340 to sufficiently fill up therecess structure325. The blockingmember340 may enclose a lower portion of the secondconductive layer pattern350 positioned in therecess structure325. The secondconductive layer pattern350 may include metal or polysilicon doped with impurities. Since therecess structure325 has the enlargedsecond recess320, the lower portion of the secondconductive layer pattern350 also has an enlarged cross section of the circular shape, the elliptical shape or the track shape. A void368 is generated in the lower portion of the secondconductive layer pattern350. The void368 may move toward a channel region of the semiconductor device formed along a lower portion of thegate electrode360 adjacent to the source/drain regions395 during subsequent manufacturing processes. However, the blockingmember340 effectively separates the void368 from the channel region. Thus, thegate electrode360 may have a regular threshold voltage (Vth) and a leakage current through the void368 may be sufficiently prevented. Further, all transistors in a unit cell of the semiconductor device may have uniform threshold voltage to improve electrical characteristics of the semiconductor device.

The thirdconductive layer pattern355 is located on the secondconductive layer pattern350. Thegate electrode360 having the thirdconductive layer pattern355 includes a lower portion buried in therecess structure325 and an upper portion protruded and on the upper face of the active region of thesubstrate300. The thirdconductive layer pattern355 may include doped polysilicon or metal.

Thegate mask365 is formed on the thirdconductive layer pattern355. Thegate mask365 may include, for example, nitride, oxynitride or oxide. Thegate mask365 serves as an etching mask for forming thegate electrode360. Additionally, thegate mask365 electrically insulates thegate electrode360 from upper wiring (not shown).

FIGS. 8A to 8F are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recessed gate structure in accordance with some embodiments of the present invention.

Referring toFIG. 8A, anisolation layer305 is formed on asemiconductor substrate300 by an isolation process. An active region and a field region of thesemiconductor substrate300 are defined by the formation of theisolation layer305. Theisolation layer305 may be formed, for example, through a shallow trench isolation (STI) process or a local oxidation of silicon (LOCOS) process.

Abuffer oxide layer370 is formed on the active region and the field region. Thebuffer oxide layer370 may be formed by a thermal oxidation process or a CVD process. Thebuffer oxide layer370 may protect thesemiconductor substrate300 during forming of a recess structure325 (seeFIG. 8C) in thesemiconductor substrate300.

Afirst mask layer375 is formed on the buffer oxide layer370 (seeFIG. 8A). Thefirst mask layer375 may be formed using a material that has an etching selectivity with respect to thebuffer oxide layer370 and thesubstrate300. For example, thefirst mask layer375 may be formed using nitride or oxynitride such as silicon nitride, silicon oxynitride, titanium oxynitride, etc. Thefirst mask layer375 may be formed, for example, through a CVD process, an ALD process, a PECVD process, an HDP-CVD process, an electron beam evaporation process, a PLD process, a sputtering process, etc.

Referring toFIG. 8B, a first photoresist pattern (not shown) is formed on thefirst mask layer375, and then thefirst mask layer375 is patterned using the first photoresist pattern as an etching mask. Hence, afirst mask385 is formed on thebuffer oxide layer370. The first photoresist pattern may be removed from thefirst mask385, for example, by an ashing process and/or a stripping process. Thefirst mask375 defines a portion of thesemiconductor substrate300 where afirst recess315 is formed. That is, thefirst mask385 serves as an etching mask for forming thefirst recess315 at an upper portion of thesubstrate300.

By a first etching process that utilizes thefirst mask385 as the etching mask, thebuffer oxide layer370 and thesubstrate300 are partially etched to simultaneously form thefirst recess315 and a bufferoxide layer pattern380. Thefirst recess315 having a predetermined depth is formed at the upper portion of thesubstrate300. The bufferoxide layer pattern380 is located on an upper face of thesubstrate300. The first etching process may include, for example, a dry etching process that uses an etching gas or a wet etching process using an etching solution. Thefirst recess315 is formed along a vertical direction relative to thesubstrate300. When thefirst recess315 is formed, a portion of thesubstrate300 is exposed through thefirst recess315.

Referring toFIG. 8C, a second mask layer (not shown) is formed on the exposed portion of thesubstrate300, sidewall of thefirst recess315 and the first mask370 (seeFIG. 8A). The second mask layer may be formed using a material that has an etching selectivity with respect to thesubstrate300. For example, the second mask layer may be formed using silicon oxide, silicon nitride, silicon oxynitride, titanium oxynitride, etc. Further, the second mask layer may be formed, for example, by a CVD process, a PECVD process, an ALD process, an HDP-CVD process, a PLD process, an electron beam evaporation process, a sputtering process, etc.

Asecond mask390 is formed on the sidewall of thefirst recess315 by removing portions of the second mask layer on thefirst mask385 and exposing a portion of thesubstrate300. Thesecond mask390 may be formed, for example, by an anisotropic etching process. When thesecond mask390 is formed, the portion of thesubstrate300 corresponding to the bottom of thefirst recess315 is exposed again.

The exposed portion of thesubstrate300 is etched by a second etching process using thesecond mask390 as an etching mask so that asecond recess320 is formed beneath thefirst recess315. For example, thesecond recess320 may be formed by a dry isotropic etching process or a wet isotropic etching process. Since thesecond mask390 protects the sidewall of thefirst recess315, a portion of thesubstrate300 corresponding to the sidewall of thefirst recess315 is not etched in the formation of thesecond recess320. Thus, the exposed portion of thesubstrate300 is vertically and horizontally etched to form thesecond recess320 having a width greater than that of thefirst recess315. For example, thesecond recess320 has an enlarged cross section in a circular shape, an elliptical shape or a track shape. Throughout the formation of the first and thesecond recesses315 and320, therecess structure325 located in the active region of thesubstrate300 has a lower portion enlarged in a rounded shape.

Referring toFIG. 8D, thefirst mask385 and the bufferoxide layer pattern380 are removed from thesubstrate300 after thesecond mask390 is removed from the sidewall of thefirst recess315.

Agate insulation layer330 is formed on therecess structure325 and the active region. Particularly, thegate insulation layer330 is formed along surfaces of the first and thesecond recesses315 and320 as well as an upper face of the active region of thesubstrate300. Thegate insulation layer330 may be formed, for example, by a thermal oxidation process, a CVD process, an ALD process, a PECVD process, an HDP-CVD process, etc. Thegate insulation layer330 may be formed using oxide or metal oxide having a high dielectric constant. For example, thegate insulation layer330 may have a thickness of about 50 Å to about 100 Å based on an upper face of therecess structure325.

A firstconductive layer333 is formed on thegate insulation layer330 with which therecess structure325 is coated. The firstconductive layer333 may be formed using doped polysilicon or metal. The firstconductive layer333 may have a thickness of about 100 Å to about 200 Å based on an upper face of thegate insulation layer330. The firstconductive layer333 may be formed, for example, by a CVD process, a PECVD process, an ALD process, a sputtering process, an electron beam evaporation process, a PLD process, etc. Impurities may be doped, for example, by an ion implantation process, a diffusion process or an in-situ doping process when the firstconductive layer333 is formed using polysilicon doped with the impurities.

Apreliminary blocking member337 is formed on the firstconductive layer333. Thepreliminary blocking member337 may be formed using oxide. Thepreliminary blocking member337 may have a thin thickness of about 10 Å to about 50 Å measured from an upper face of the firstconductive layer333. Thepreliminary blocking member337 may be formed by oxidizing an upper portion of the firstconductive layer330. Alternatively, thepreliminary blocking member337 may be formed by depositing oxide on the firstconductive layer330. Here, thepreliminary blocking member337 may be formed, for example, by a CVD process, a PECVD process, an ALD process, an HDP-CVD process, etc.

A secondconductive layer347 is formed on thesubstrate300 and thepreliminary blocking member337 to sufficiently fill up therecess structure325. The secondconductive layer347 may be formed using doped polysilicon or metal. The secondconductive layer347 may be formed, for example, by a CVD process, a PECVD process, an ALD process, a sputtering process, an electron beam evaporation process, a PLD process, etc. Since the secondconductive layer347 fills up therecess structure215 having the enlarged lower portion, avoid368 is formed in a lower portion of the secondconductive layer347.

Referring toFIG. 8E, a portion of the secondconductive layer347 on thesubstrate300 is removed to expose thepreliminary blocking member337. On the other hand, the lower portion of the secondconductive layer347 remains in therecess structure325. The secondconductive layer347 may be partially removed by an etch-back process. As a result, a secondconductive layer pattern350 is formed to be buried in therecess structure325.

A portion of thepreliminary blocking member337 on thesubstrate300 is etched to form a blockingmember340 on the firstconductive layer333 in therecess structure325. The blockingmember340 may be formed, for example, using an etching solution containing fluorine (F) or an etching gas including fluorine.

A portion of the firstconductive layer333 on the active region is exposed after the formation of the blockingmember340. The exposed portion of the firstconductive layer333 is removed to form a firstconductive layer pattern335 between the blockingmember340 and thegate insulation layer330. The firstconductive layer pattern335 may be formed by an etch-back process. When the firstconductive layer pattern335 is formed in therecess structure325, a portion of thegate insulation layer330 on the active region is exposed. The blockingmember340 encloses the secondconductive layer pattern350, and the firstconductive layer pattern335 encloses the blockingmember340. Additionally, thegate insulation layer330 encloses the firstconductive layer pattern335.

Still referring toFIG. 8E, a thirdconductive layer353 is formed on the secondconductive layer pattern350 and the exposed portion of thegate insulation layer330. In particular, the thirdconductive layer353 is formed on the firstconductive layer pattern335, the blockingmember340, the secondconductive layer pattern350 and the exposed portion of thegate insulation layer330. The thirdconductive layer pattern353 may be formed, for example, using doped polysilicon or metal. According to some embodiments of the present invention, the thirdconductive layer pattern353 may have a polycide structure that includes a polysilicon film pattern and a metal silicide film pattern. The thirdconductive layer pattern353 may be formed, for example, by a CVD process, a PECVD process, an ALD process, a sputtering process, an electron beam process, a PLD process, etc.

After a gate mask layer (not shown) is formed on the thirdconductive layer pattern353, a second photoresist pattern (not shown) is formed on the gate mask layer. The gate mask layer may be formed using a material having an etching selectivity with respect to the thirdconductive layer pattern353. For example, the gate mask layer may be formed using nitride, oxide or oxynitride. The gate mask layer may be formed, for example, by a CVD process, a PECVD process, an ALD process, an HDP-CVD process, an electron beam evaporation process, a sputtering process, a PLD process, etc.

Using the second photoresist pattern as an etching mask, the gate mask layer is patterned to form agate mask365 included in a gate electrode360 (seeFIG. 8F) on the thirdconductive layer353.

In the processes for forming the thirdconductive layer353 and/or thegate mask365, the void368 formed in the lower portion of the secondconductive layer pattern350 moves toward thegate insulation layer330 adjacent to the secondconductive layer pattern350.

FIG. 9 is an electron microscopic picture illustrating a cross section of a semiconductor device in accordance with some embodiments of the present invention.

As shown inFIG. 9, the blockingmember340 enclosing the secondconductive layer pattern350 prevents the migration of the void368 so that thevoid368 does not make contact with thegate insulation layer330 around the secondconductive layer pattern350. Namely, thevoid368 is separated from thegate insulation layer330 by the blockingmember340.

Referring back toFIG. 8F, the thirdconductive layer353 is partially etched using thegate mask365 as an etching mask to thereby form a thirdconductive layer pattern355 on the secondconductive layer pattern350 and thegate insulation layer330. The thirdconductive layer pattern355 may have a length substantially greater than that of the secondconductive layer pattern350. In the formation of the thirdconductive layer pattern355, thegate electrode360 having the first to the thirdconductive layer patterns335,350 and355 is formed in the active region of thesubstrate300. Additionally, a recessedgate structure310 is completed on thesubstrate300. The recessedgate structure310 includes thegate insulation layer330, the blockingmember340, thegate electrode360 and thegate mask365.

In an ion implantation process that utilizes thegate mask365 and the thirdconductive layer pattern355 as masks, impurities are implanted into portions of the active region adjacent to thegate electrode360 so that source/drain regions395 are formed in the active region. As a result, the semiconductor device having the recessedgate structure310 and the source/drain regions395 is formed on thesubstrate300.

FIG. 10 is a graph illustrating the distributions of threshold voltages of transistor in a unit cell of a semiconductor device. InFIG. 10, a first line I indicates the distributions of threshold voltages in conventional transistors, and a second line II represents the distributions of threshold voltages in transistors according to some embodiments of the present invention. Additionally, a third line III denotes the distributions of threshold voltages in conventional transistors having enlarged recessed gate electrodes with voids therein.

Referring toFIG. 10, the conventional transistors have irregular threshold voltages of about 1.2V to about 1.8V. When transistors in a unit cell of a semiconductor device have irregular threshold voltages, the semiconductor device may be not properly operated with a predetermined voltage so that the electrical characteristics of the semiconductor device may be deteriorated. However, the transistors of the present invention have uniform threshold voltages of about 1.3V to about 1.5V. Thus, the semiconductor device including the transistors of the present invention may have considerably improved electrical characteristics.

FIG. 11 is a cross-sectional view illustrating a semiconductor device having a recessed gate structure in accordance with some embodiments of the present invention.

Referring toFIG. 11, the semiconductor device includes a recessedgate structure410 partially buried in asubstrate400 having a recessedstructure410, and source/drain regions495 formed at portions of thesubstrate400 adjacent to the recessedgate structure410.

The recessedgate structure410 has agate insulation layer430, a blockingmember430, agate electrode445 and agate mask455. Thegate electrode445 has a firstconductive layer435 and a secondconductive layer pattern450. The firstconductive layer435 is formed along surfaces of the recessedstructure410 and an upper face of thesubstrate400. A lower portion of the secondconductive layer pattern450 is buried in the recessedstructure410, whereas an upper portion of the secondconductive layer pattern450 protrudes over thesubstrate400.

Anisolation layer405 is formed on thesubstrate400 to define an active region and a field region. Therecess structure410 is formed in the active region of thesubstrate400. Therecess structure410 includes afirst recess415 and asecond recess420. Thefirst recess415 is vertically formed at an upper portion of the active region of thesubstrate400. Thesecond recess420 is vertically and horizontally enlarged beneath thefirst recess415. Thesecond recess420 has an enlarged cross section of a circular shape, an elliptical shape or a track shape.

Thegate insulation layer430 is formed along a surface of therecess structure410 and an upper face of the active region of thesubstrate400. Thegate insulation layer430 may include oxide or metal oxide.

The firstconductive layer435 of thegate electrode445 is formed on thegate insulation layer430 to partially fill up therecess structure410. The firstconductive layer435 is formed from therecess structure410 to thesubstrate400. The firstconductive layer435 may include metal or polysilicon doped with impurities.

The blockingmember440 is formed on the firstconductive layer435. The blockingmember440 extends from therecess structure410 over thesubstrate400. Thus, the blockingmember440, the firstconductive layer435 and thegate insulation layer430 may have substantially the same lengths. The blockingmember440 may include metal silicide. According to some embodiments of the present invention, the blockingmember440 may be formed by depositing metal silicide on the firstconductive layer435. According to some embodiments of the present invention, the blockingmember440 may be formed by a silicidation on a surface of the firstconductive layer435.

The secondconductive layer pattern450 is formed on the blockingmember440 to completely fill up therecess structure410. Therecess structure410 is filled with the lower portion of the secondconductive layer pattern450. The upper portion of the secondconductive layer pattern450 protrudes from the upper face of the active region by a predetermined height. The blockingmember440 encloses the lower portion of the secondconductive layer pattern450 buried in therecess structure410. As described above, thesecond recess420 has an enlarged cross section so that the lower portion of the secondconductive layer pattern450 also has an enlarged cross section of a circular shape, an elliptical shape or a track shape. A void468 or a seam occurs in the lower portion of the secondconductive layer pattern450, and the void468 or the seam may move toward a channel region of the semiconductor device formed along a lower portion of thegate electrode445 in successive manufacturing processes. Here, the blockingmember440 blocks the void468 from the channel region. Therefore, thegate electrode445 may have a uniform threshold voltage, and a leakage current through the void468 or the seam may be sufficiently prevented. When all transistors in a unit cell of a semiconductor device may have uniform threshold voltages, the semiconductor device may have enhanced electrical characteristics.

Thegate mask455 is formed on the secondconductive layer pattern450 of thegate electrode445. Thegate mask455 may include, for example, nitride, oxynitride or oxide. Thegate mask455 serves as an etching mask for forming thegate electrode445 and also electrically insulates thegate electrode445 from upper wiring (not shown).

FIGS. 12A to 12D are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recessed gate structure in accordance with some embodiments of the present invention.

Referring toFIG. 12A, anisolation layer405 is formed on asubstrate400 by an isolation process so that thesubstrate400 is divided into an active region and a field region. Theisolation layer405 may be formed, for example, using oxide by an STI process or an LOCOS process.

Impurities are doped into the active region of thesubstrate400 by an ion implantation process such that preliminary source/drain regions457 are formed in the active region. The preliminary source/drain regions457 will be changed into source/drain regions495 (seeFIG. 12B).

Abuffer oxide layer470 is formed on the active region and the field region of thesubstrate400. Thebuffer oxide layer470 may be formed, for example, by a thermal oxidation process or a CVD process.

Afirst mask layer475 is formed on thebuffer oxide layer470 using nitride or oxynitride. Thefirst mask layer475 may be formed, for example, by a CVD process, an ALD process, a PECVD process, an HDP-CVD process, an electron beam evaporation process, a PLD process, a sputtering process, etc.

Referring toFIG. 12B, thefirst mask layer475 is etched by a photolithography process so that afirst mask485 for afirst recess415 is formed on thebuffer oxide layer470. Thefirst mask485 serves as an etching mask for forming thefirst recess415 at an upper portion the active region of thesubstrate400.

Thebuffer oxide layer470 and thesubstrate400 are partially etched by an anisotropic etching process using thefirst mask485 as the etching mask. Hence, thefirst recess415 is formed at the upper portion of thesubstrate400 and a bufferoxide layer pattern480 is simultaneously formed on thesubstrate400. Thefirst recess415 having a predetermined depth is formed at the upper portion of thesubstrate300. Thefirst recess415 is vertically formed from a surface of thesubstrate400 to have a predetermined depth. When thefirst recess415 is formed, a portion of thesubstrate400 corresponding to a bottom of thefirst recess415 is exposed.

A second mask layer (not shown) is formed on the exposed portion of thesubstrate400, thefirst mask485 and sidewall of thefirst recess415. The second mask layer may be formed using, for example, nitride, oxynitride or oxide by, for example, a CVD process, a PECVD process, an ALD process, an HDP-CVD process, a PLD process, an electron beam evaporation process, a sputtering process, etc.

Portions of the second mask layer on thefirst mask485 and the exposed portion of thesubstrate400 are etched by an isotropic etching process. Thus, asecond mask490 is formed on the sidewall of thefirst recess415 only.

With an isotropic etching process using thesecond mask490 as an etching mask, the exposed portion of thesubstrate400 is removed to form asecond recess420 beneath thefirst recess415. A portion of thesubstrate400 corresponding to the sidewall of thefirst recess415 is not etched in the formation of thesecond recess420 because thesecond mask490 is positioned on the sidewall of thefirst recess415. The exposed portion of thesubstrate400 is vertically and horizontally etched to thereby form thesecond recess420 having an enlarged cross section beneath thefirst recess415. When the first and thesecond recesses415 and420 are formed, arecess structure425 having a lower portion enlarged in a rounded shape is formed at the upper portion of thesubstrate400. Additionally, the preliminary source/drain regions457 are changed into the source/drain regions495 in accordance with the formation of therecess structure425 in the active region.

Referring toFIG. 12C, thesecond mask490 is removed from the sidewall of thefirst recess415, and then thefirst mask485 and the bufferoxide layer pattern480 are removed from thesubstrate400.

Agate insulation layer430 is formed on therecess structure425 and the active region using, for example, oxide or metal oxide. Namely, thegate insulation layer430 is formed along an upper face of the active region and a surface of thesubstrate400 corresponding to the first and thesecond recesses415 and420. Thegate insulation layer430 may be formed, for example, by a thermal oxidation process, a CVD process, an ALD process, a PECVD process, an HDP-CVD process, etc.

A firstconductive layer435 is formed on thegate insulation layer430 to partially fill up therecess structure425. The firstconductive layer435 may be formed, for example, using doped polysilicon or metal, for example, by a CVD process, a PECVD process, an ALD process, a sputtering process, an electron beam evaporation process, a PLD process, etc. The firstconductive layer435 is formed along the surfaces of therecess structure425 and on the upper face of the active region.

A blockingmember440 is formed on the firstconductive layer435. The blockingmember440 may be formed by a silicidation of an upper portion of the firstconductive layer435. Alternatively, the blockingmember440 may be formed by depositing metal silicide on the firstconductive layer435 through, for example, a CVD process, a PECVD process, an ALD process, an HDP-CVD process, etc.

A secondconductive layer458 is formed on thesubstrate400 and the blockingmember440 to completely fill up therecess structure425. The secondconductive layer458 may be formed, for example, using doped polysilicon or metal, for example, by a CVD process, a PECVD process, an ALD process, a sputtering process, an electron beam evaporation process, a PLD process, etc. Since the secondconductive layer458 fills up therecess structure425 having the enlargedsecond recess420, a void468 or a seam is formed in the secondconductive layer458. Particularly, the void468 or the seam is generated in a lower portion of the secondconductive layer458 buried in thesecond recess420.

Referring toFIG. 12D, a gate mask layer (not shown) is formed on the secondconductive layer458, and then the gate mask layer is partially etched by a photolithography process. Thus, agate mask455 is formed on the secondconductive layer458. The gate mask layer may be formed, for example, using nitride, oxynitride or oxide by, for example, a CVD process, a PECVD process, an ALD process, an HDP-CVD process, a sputtering process, an electron beam process, a PLD process, etc.

During the process for forming thegate mask455 and/or a subsequent process for forming upper wiring, the void468 or the seam in the lower portion of the secondconductive layer458 moves toward thegate insulation layer430 adjacent to the source/drain regions495. Here, the blockingmember440 enclosing the lower portion of the secondconductive layer458 effectively prevents the void468 or the seam from contacting thegate insulation layer430.

Still referring toFIG. 12D, the secondconductive layer458 is partially etched using thegate mask455 as an etching mask to form a secondconductive layer pattern450 having the lower portion buried in therecess structure425 and an upper portion protruded from the active region. Thus, a recessedgate structure410 having thegate insulation layer430, the blockingmember440, agate electrode445 and thegate mask455 is completed on the active region of thesubstrate400. Here, thegate electrode445 includes the firstconductive layer435 and the secondconductive layer pattern450. The source/drain regions495 of the semiconductor device are positioned at portions of thesubstrate400 adjacent to the recessedgate structure410.

According to the present invention, a blocking member is formed in a recessed gate structure having an enlarged lower portion so that the blocking member effectively prevents a void or a seam in the lower portion of the recessed gate structure from contacting a gate insulation layer making contact with the channel region. Therefore, a semiconductor device including the recessed gate structure may have a uniform threshold voltage and a leakage current through the voids or the seam may considerably decrease. Additionally, since the recessed gate structure has the lower portion enlarged in a circular shape, an elliptical shape or a track shape, the channel region formed along the lower portion of the recessed gate structure may have a greatly increased length to ensure improved electrical characteristics of the semiconductor device.

The foregoing is illustrative of the present invention and is not to be construed as limiting thereof. Although a few example embodiments of the present invention have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of the present invention as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of the present invention and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The present invention is defined by the following claims, with equivalents of the claims to be included therein.

Claims (10)

1. A method of forming a recessed gate structure, comprising:

forming a recess structure having an enlarged lower portion in a substrate;

forming a gate insulation layer on surfaces of the recess structure and the substrate;

forming a gate electrode partially buried in the recess structure on the gate insulation layer, comprising forming a first conductive layer pattern on the gate insulation layer to partially fill up the recess structure;

forming a blocking member on the first conductive layer pattern;

forming a second conductive layer pattern on the blocking member to fill up the recess structure; and

forming a third conductive layer pattern on the first conductive layer pattern, the second conductive layer pattern and the blocking member.

2. The method ofclaim 1, wherein forming the recess structure comprises:

forming a first mask on the substrate;

forming a first recess from the surface of the substrate by etching the substrate using the first mask;

forming a second mask on a sidewall of the first recess; and

forming a second recess beneath the first recess by etching the substrate using the second mask.

3. The method ofclaim 1, wherein the blocking member is formed by an oxidization or a silicidation of a surface of the first conductive layer.

4. The method ofclaim 1, wherein forming the first conductive layer pattern and forming the blocking member comprise:

forming a first conductive layer on the gate insulation layer;

forming a preliminary blocking member on the first conductive layer; and

forming the first conductive layer pattern and the blocking member by partially removing the first conductive layer and the preliminary blocking member.

5. The method ofclaim 4, wherein the preliminary blocking member is partially removed using an etching solution including fluorine or an etching gas including fluorine, and the first conductive layer is partially removed by an etch-back process.

6. The method ofclaim 1, wherein

the second conductive layer pattern is formed on the blocking member so as to protrude from the substrate.

7. A method of manufacturing a semiconductor device, comprising:

forming an isolation layer on a substrate to define an active region;

forming a recess structure having an enlarged lower portion in the active region;

forming a gate insulation layer from a surface of the recess structure onto the active region;

forming a gate electrode partially buried in the recess structure on the gate insulation layer, comprising forming a first conductive layer pattern on the gate insulation layer to partially fill up the recess structure;

forming a blocking member on the first conductive layer pattern;

forming a second conductive layer pattern on the blocking member to fill up the recess structure;

forming a third conductive layer pattern on the first conductive layer pattern, the second conductive layer pattern and the blocking member; and

forming source/drain regions at portions of the substrate adjacent to the gate electrode.

8. The method ofclaim 7, wherein the blocking member is formed by an oxidization and a silicidation of a surface of the first conductive layer.

9. The method ofclaim 7, wherein forming the first conductive layer pattern and forming the blocking member comprise:

forming a first conductive layer on the gate insulation layer;

forming a preliminary blocking member on the first conductive layer; and

forming the first conductive layer pattern and the blocking member by partially removing the first conductive layer and the preliminary blocking member.

10. The method ofclaim 7, wherein

the second conductive layer pattern is formed on the blocking member so as to protrude from the substrate.

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