US8039303B2 - Method of forming stress relief layer between die and interconnect structure - Google Patents

Abstract

A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.

Description

CLAIM TO DOMESTIC PRIORITY

The present nonprovisional application claims the benefit of priority of U.S. Provisional Application Ser. No. 61/060,778, filed Jun. 11, 2008, titled “3D Fan-out WLCSP Structure and Method Thereof”, by Il Kwon Shim et al.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming a stress relief insulating layer between a semiconductor die and build-up interconnect structure.

BACKGROUND OF THE INVENTION

Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).

Semiconductor devices perform a wide range of functions such as high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.

A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.

Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size may be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.

The electrical interconnection between stacked semiconductor die can be accomplished with conductive through silicon vias (TSVs) or through hole vias (THVs) and an intermediate build-up interconnect layer. To form TSVs or THVs, a via is cut through the semiconductor material or peripheral region around the semiconductor die. The vias are then filled with an electrically conductive material, for example, copper deposition through an electroplating process. A potential mismatch between the coefficient of thermal expansion (CTE) of the semiconductor die and mounting board or intermediate build-up interconnect layer causes stress which can lead to THV or TSV joint failure and delamination of the die from the adjacent interconnect structure. These device failures reduce yield and increase manufacturing costs.

SUMMARY OF THE INVENTION

A need exists to provide a vertical interconnect structure for stacked semiconductor devices with a lower failure rate. Accordingly, in one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a temporary carrier, forming a first conductive layer over the temporary carrier, forming a conductive pillar over the first conductive layer, and mounting an active surface of a semiconductor die to the temporary carrier with an adhesive layer. The semiconductor die is vertically offset from the first conductive layer by the adhesive layer. The method further includes the steps of depositing an encapsulant over the semiconductor die and around the conductive pillar, removing the temporary carrier and adhesive layer, and forming a stress relief insulating layer over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. The method further includes the steps of forming a first interconnect structure over the stress relief insulating layer, and forming a second interconnect structure over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.

In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a first carrier, forming a conductive pillar over the first carrier, mounting a semiconductor component to the first carrier, depositing an encapsulant over the semiconductor component and around the conductive pillar, removing the first carrier, and forming a stress relief insulating layer over the semiconductor component and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor component and a second thickness less than the first thickness over the encapsulant. The method further includes the steps of forming a first interconnect structure over the stress relief insulating layer, and forming a second interconnect structure over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.

In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a first carrier, forming a conductive pillar over the first carrier, mounting a semiconductor component to the first carrier, depositing an encapsulant over the semiconductor component and around the conductive pillar, removing the first carrier, forming a stress relief insulating layer over the semiconductor component and a first surface of the encapsulant, and forming a first interconnect structure over the stress relief insulating layer. The first interconnect structure is electrically connected to the conductive pillar.

In another embodiment, the present invention is a semiconductor device comprising a semiconductor component and conductive pillar formed around the semiconductor component. An encapsulant is deposited over the semiconductor component and around the conductive pillar. A stress relief insulating layer is formed over the semiconductor component and a first surface of the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a PCB with different types of packages mounted to its surface;

FIGS. 2a-2cillustrate further detail of the representative semiconductor packages mounted to the PCB;

FIGS. 3a-3millustrate a process of forming a vertical interconnect structure using conductive pillars and stress relief layer between die and build-up interconnect structure;

FIG. 4 illustrates stacked semiconductor devices electrically interconnected with the conductive pillars;

FIG. 5 illustrates a back surface of the semiconductor die coplanar with a surface of the conductive pillars; and

FIG. 6 illustrates the semiconductor device with IPD formed in a topside interconnect structure.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.

Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, resistors, and transformers, create a relationship between voltage and current necessary to perform electrical circuit functions.

Passive and active components are formed over the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the electrical conductivity of semiconductor material in active devices, transforming the semiconductor material into an insulator, conductor, or dynamically changing the semiconductor material conductivity in response to an electric field or base current. Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of the electric field or base current.

Active and passive components are formed by layers of materials with different electrical properties. The layers can be formed by a variety of deposition techniques determined in part by the type of material being deposited. For example, thin film deposition may involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components.

The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. The portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

Depositing a thin film of material over an existing pattern can exaggerate the underlying pattern and create a non-uniformly flat surface. A uniformly flat surface is required to produce smaller and more densely packed active and passive components. Planarization can be used to remove material from the surface of the wafer and produce a uniformly flat surface. Planarization involves polishing the surface of the wafer with a polishing pad. An abrasive material and corrosive chemical are added to the surface of the wafer during polishing. The combined mechanical action of the abrasive and corrosive action of the chemical removes any irregular topography, resulting in a uniformly flat surface.

Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation. To singulate the die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with solder bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.

FIG. 1 illustrateselectronic device50 having a chip carrier substrate orPCB52 with a plurality of semiconductor packages mounted on its surface.Electronic device50 may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown inFIG. 1 for purposes of illustration.

Electronic device50 may be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively,electronic device50 may be a subcomponent of a larger system. For example,electronic device50 may be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASICs), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components.

InFIG. 1,PCB52 provides a general substrate for structural support and electrical interconnect of the semiconductor packages mounted on the PCB. Conductive signal traces54 are formed over a surface or within layers ofPCB52 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces54 provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components.Traces54 also provide power and ground connections to each of the semiconductor packages.

In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate carrier. Second level packaging involves mechanically and electrically attaching the intermediate carrier to the PCB. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to the PCB.

For the purpose of illustration, several types of first level packaging, includingwire bond package56 andflip chip58, are shown onPCB52. Additionally, several types of second level packaging, including ball grid array (BGA)60, bump chip carrier (BCC)62, dual in-line package (DIP)64, land grid array (LGA)66, multi-chip module (MCM)68, quad flat non-leaded package (QFN)70, and quadflat package72, are shown mounted onPCB52. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected toPCB52. In some embodiments,electronic device50 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using cheaper components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

FIGS. 2a-2cshow exemplary semiconductor packages.FIG. 2aillustrates further detail ofDIP64 mounted onPCB52. Semiconductor die74 includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and are electrically interconnected according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of semiconductor die74. Contactpads76 are one or more layers of conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within semiconductor die74. During assembly ofDIP64, semiconductor die74 is mounted to anintermediate carrier78 using a gold-silicon eutectic layer or adhesive material such as thermal epoxy. The package body includes an insulative packaging material such as polymer or ceramic. Conductor leads80 andwire bonds82 provide electrical interconnect between semiconductor die74 andPCB52.Encapsulant84 is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating die74 or wire bonds82.

FIG. 2billustrates further detail ofBCC62 mounted onPCB52. Semiconductor die88 is mounted overcarrier90 using an underfill or epoxy-resin adhesive material92.Wire bonds94 provide first level packing interconnect betweencontact pads96 and98. Molding compound orencapsulant100 is deposited over semiconductor die88 andwire bonds94 to provide physical support and electrical isolation for the device. Contactpads102 are formed over a surface ofPCB52 using a suitable metal deposition such electrolytic plating or electroless plating to prevent oxidation. Contactpads102 are electrically connected to one or more conductive signal traces54 inPCB52.Bumps104 are formed betweencontact pads98 ofBCC62 andcontact pads102 ofPCB52.

InFIG. 2c, semiconductor die58 is mounted face down tointermediate carrier106 with a flip chip style first level packaging.Active region108 of semiconductor die58 contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements withinactive region108. Semiconductor die58 is electrically and mechanically connected tocarrier106 throughbumps110.

BGA60 is electrically and mechanically connected toPCB52 with a BGA style second levelpackaging using bumps112. Semiconductor die58 is electrically connected to conductive signal traces54 inPCB52 throughbumps110,signal lines114, and bumps112. A molding compound orencapsulant116 is deposited over semiconductor die58 andcarrier106 to provide physical support and electrical isolation for the device. The flip chip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die58 to conduction tracks onPCB52 in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die58 can be mechanically and electrically connected directly toPCB52 using flip chip style first level packaging withoutintermediate carrier106.

FIGS. 3a-3millustrate a process of forming a vertical interconnect structure with conductive pillars and a stress relief layer between a semiconductor die and build-up interconnect structure. InFIG. 3a, a sacrificial or temporary substrate orcarrier120 contains a base material such as silicon, polymer, polymer composite, metal foil, ceramic, glass, glass epoxy, beryllium oxide, tape, or other suitable low-cost, rigid material for structural support. Anoptional interface layer122 can be formed overcarrier120 as an etch-stop. An electricallyconductive layer124 is formed overcarrier120 using patterning with PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process.Conductive layer124 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, W, poly-silicon, or other suitable electrically conductive material.Conductive layer124 includes wettable contact pads for later formation of conductive pillars. In one embodiment, the wettable contact pads ofconductive layer124 are pre-plated oncarrier120.

InFIG. 3b, a plurality of conductive pillars orposts128 are formed over the wettable contact pads ofconductive layer124. In one embodiment,conductive pillars128 are formed by depositing one or more layers of photoresist overinterface layer122 orcarrier120. The portion of photoresist overconductive layer124 is exposed and removed by an etch development process. Conductive material is deposited in the removed portion of the photoresist layer using a selective plating process. The photoresist layer is stripped away leaving behind individualconductive pillars128.Conductive pillars128 can be Cu, Al, tungsten (W), Au, solder, or other suitable electrically conductive material.Conductive pillars128 have a height ranging from 2-120 micrometers (μm). In another embodiment,conductive pillars128 can be formed as stud bumps or stacked bumps.

A plurality of semiconductor die orcomponents130 is mounted tointerface layer122 with protectiveadhesive layer132 in a flipchip arrangement. Contactpads134 andactive surface136 are oriented downward overinterface layer122 andcarrier120. Protectiveadhesive layer132 can be one or more layers of ultraviolet (UV) curable and thermal stable adhesive tape. Protectiveadhesive layer132 creates a vertical offset betweenactive surface136 andconductive layer124.

Semiconductor die130 includes anactive surface136 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed withinactive surface136 to implement baseband analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit. Semiconductor die130 may also contain IPD, such as inductors, capacitors, and resistors, for RF signal processing. In another embodiment, a discrete semiconductor component can be mounted tointerface layer122 orcarrier120.Conductive pillars128 are disposed around semiconductor die130.

FIG. 3dshows an encapsulant ormolding compound138 deposited over semiconductor die130 andconductive pillars128 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, or other suitable applicator.Encapsulant138 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.Encapsulant138 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. Protectiveadhesive layer132 prevents encapsulant138 from bleeding intoactive surface136.

InFIG. 3e,carrier120,interface layer122, and protectiveadhesive layer132 are removed by chemical wet etching, plasma dry etching, mechanical peel-off, CMP, mechanical grinding, thermal bake, laser scanning, or wet stripping.Encapsulant138 provides structural support for semiconductor die130 after removal ofcarrier120.Conductive layer124 andcontact pads134 of semiconductor die130 are exposed following removal ofcarrier120,interface layer122, and protectiveadhesive layer132.

InFIG. 3f, the structure is inverted and a stressrelief insulating layer140 is formed overencapsulant138,conductive layer124, andactive surface136 using PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. The stressrelief insulating layer140 can be one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), or other material having similar insulating and structural properties. The insulatinglayer140 is thicker overactive region136, due to vertical offset of protectiveadhesive layer132, than overencapsulant138 andconductive layer124 to provide additional stress relief for semiconductor die130. In one embodiment, the portion of insulatinglayer140 overactive region136 has a thickness ranging from 5-100 μm, and the portion of insulatinglayer140 overencapsulant138 has a thickness ranging from 2-50 μm. A portion of insulatinglayer140 is removed by a patterning and etching process to exposeconductive layer124 andcontact pads134, as shown inFIG. 3g.

InFIG. 3h, a bottom-side build-upinterconnect structure142 is formed overinsulating layer140. An electricallyconductive layer144 is formed overinsulating layer140,conductive layer124, andcontact pads134 using patterning with PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process.Conductive layer144 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Portions ofconductive layer144 are electrically connected toconductive pillars128,conductive layer124, andcontact pads134. Other portions ofconductive layer144 can be electrically common or electrically isolated depending on the design and function of the semiconductor device. For example,portion145 ofconductive layer144 operates as a redistribution layer (RDL) or runner to extend the conductivity ofconductive pillars128 andconductive layer124.

InFIG. 3i, an insulating orpassivation layer146 is formed overinsulating layer140 andconductive layer144 using PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. Thepassivation layer146 can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion ofpassivation layer146 is removed by an etching process to exposeconductive layer144.

An electricallyconductive layer148 is formed overpassivation layer146 andconductive layer144 using patterning with PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process.Conductive layer148 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.Conductive layer148 is electrically connected toconductive layer144.Conductive layer148 is an under bump metallization (UBM) in electrical contact withconductive layer144 andconductive pillars128.UBM148 can be a multi-metal stack with adhesion layer, barrier layer, and seed or wetting layer. The adhesion layer is formed overconductive layer144 and can be Ti, titanium nitride (TiN), titanium tungsten (TiW), Al, or chromium (Cr). The barrier layer is formed over the adhesion layer and can be made of Ni, nickel vanadium (NiV), platinum (Pt), palladium (Pd), TiW, or chromium copper (CrCu). The barrier layer inhibits the diffusion of Cu into the active area of the die. The seed layer can be Cu, Ni, NiV, Au, or Al. The seed layer is formed over the barrier layer and acts as an intermediate conductive layer betweenconductive layer144 and subsequent solder bumps or other interconnect structure.UBM148 provides a low resistive interconnect toconductive layer144, as well as a barrier to solder diffusion and seed layer for solder wettability.

InFIG. 3j,encapsulant138 undergoes grinding or plasma etching to planarize the surface for formation of the topside build-up interconnect structure. The grinding operation exposes a surface ofconductive pillars128. Anoptional process carrier150, such as backgrinding tape, can be mounted topassivation layer146 andconductive layer148 withadhesive layer152 for additional structural support during the grinding operation.

InFIG. 3k, the structure is inverted and a topside build-upinterconnect structure154 is formed overencapsulant138 andconductive pillars128. An insulating orpassivation layer156 is formed overencapsulant138 andconductive pillars128 using PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. Thepassivation layer156 can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion ofpassivation layer156 is removed by an etching process to exposeconductive pillars128.

An electricallyconductive layer158 is formed overpassivation layer156 andconductive pillars128 using patterning with PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process.Conductive layer158 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. A portion ofconductive layer158 is electrically connected toconductive pillars128. Other portions ofconductive layer158 can be electrically common or electrically isolated depending on the design and function of the semiconductor device. For example,portion159 ofconductive layer158 operates as an RDL or runner to extend the conductivity ofconductive pillars128.

InFIG. 3l, an insulating orpassivation layer160 is formed overpassivation layer156 andconductive layer158 using PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. Thepassivation layer160 can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties. A portion ofpassivation layer160 is removed by an etching process to exposeconductive layer158.

An electricallyconductive layer162 is formed overpassivation layer160 andconductive layer158 using patterning with PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process.Conductive layer162 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.Conductive layer162 is a UBM in electrical contact withconductive layer158 andconductive pillars128.UBM162 can be a multi-metal stack with adhesion layer, barrier layer, and seed or wetting layer. The adhesion layer is formed overconductive layer158 and can be Ti, TiN, TiW, Al, or Cr. The barrier layer is formed over the adhesion layer and can be made of Ni, NiV, Pt, Pd, TiW, or CrCu. The barrier layer inhibits the diffusion of Cu into the active area of the die. The seed layer can be Cu, Ni, NiV, Au, or Al. The seed layer is formed over the barrier layer and acts as an intermediate conductive layer betweenconductive layer158 and subsequent solder bumps or other interconnect structure.UBM162 provides a low resistive interconnect toconductive layer158, as well as a barrier to solder diffusion and seed layer for solder wettability.

InFIG. 3m,carrier150 andadhesive layer152 is removed by chemical wet etching, plasma dry etching, mechanical peel-off, CMP, mechanical grinding, thermal bake, laser scanning, or wet stripping. The bottom-side build-upinterconnect structure142 includesconductive layer144,passivation layer146, andUBM148. The topside build-upinterconnect structure154 includespassivation layer156,conductive layer158,passivation layer160, andUBM162.

An electrically conductive bump material is deposited overUBM148 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded toUBM148 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps164. In some applications, bumps164 are reflowed a second time to improve electrical contact toUBM148. The bumps can also be compression bonded toUBM148.Bumps164 represent one type of interconnect structure that can be formed overUBM148. The interconnect structure can also use bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.

Semiconductor die130 are singulated with saw blade or laser cutting tool intoindividual semiconductor devices168. After singulation, theindividual semiconductor devices168 can be stacked, as shown inFIG. 4.Conductive pillars128 provide vertical, z-direction interconnect between topside build-upinterconnect layer154 and bottom-side build-upinterconnect layer142.Conductive layer158 is electrically connected throughconductive pillars128 toconductive layer122 andcontact pads134 of eachsemiconductor device168.

The thick protectiveinsulating layer140 disposed overactive surface136 reduces stress caused by CTE mismatch between semiconductor die130 and bottom-side build-upinterconnect structure142. The stress buffering provided by insulatinglayer140 reduces joint failure rate ofconductive pillars138 and delamination between semiconductor die130 and build-upinterconnect structure142.

FIG. 5 shows a variation of the process flow ofFIG. 3j.Encapsulant138 andconductive pillars128 undergo grinding or plasma etching to planarize the surface of the encapsulant for the topside build-upinterconnect layer154. The grinding operation exposes a back surface of semiconductor die130 coplanar with the exposed surface ofconductive pillars128. The remainder of the process follows the description ofFIGS. 3k-3m.

FIG. 6 illustrates an embodiment of the vertical interconnect structure with multiple IPD formed in the topside interconnect structure. Similar to the process described inFIGS. 3a-3m,semiconductor device170 uses a sacrificial or temporary substrate or carrier with an optional interface layer, which operates as an etch-stop layer. An electricallyconductive layer172 is formed over the carrier using patterning with PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process.Conductive layer172 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, W, poly-silicon, or other suitable electrically conductive material.Conductive layer172 includes wettable contact pads for later formation of conductive pillars.

A plurality of conductive pillars orposts178 is formed over the wettable contact pads ofconductive layer172. In one embodiment,conductive pillars178 are formed by depositing one or more layers of photoresist over the carrier and interface layer. The portion of photoresist overconductive layer172 is exposed and removed by an etching development process. Conductive material is deposited in the removed portion of the photoresist layer using a selective plating process. The photoresist layer is stripped away leaving behind individualconductive pillars178.Conductive pillars178 can be Cu, Al, W, Au, solder, or other suitable electrically conductive material.Conductive pillars178 have a height ranging from 2-120 μm. In another embodiment,conductive pillars178 can be formed as stud bumps or stacked bumps.

A plurality of semiconductor die orcomponents180 is mounted to the interface layer with a protective adhesive layer in a flipchip arrangement. Contactpads184 andactive surface186 are oriented downward over the interface layer and carrier. The protective adhesive layer can be one or more layers of UV curable and thermal stable adhesive tape. The protective adhesive layer creates a vertical offset betweenactive surface186 andconductive layer172. Semiconductor die180 includes anactive surface186 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed withinactive surface186 to implement baseband analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit. Semiconductor die180 may also contain IPD, such as inductors, capacitors, and resistors, for RF signal processing. In another embodiment, a discrete semiconductor component can be mounted to the interface layer or carrier.

An encapsulant ormolding compound188 is deposited over semiconductor die180 andconductive pillars178 using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, or other suitable applicator.Encapsulant188 can be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler.Encapsulant188 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.

The carrier, interface layer, and protective adhesive layer are removed by chemical wet etching, plasma dry etching, mechanical peel-off, CMP, mechanical grinding, thermal bake, laser scanning, or wet stripping.Encapsulant188 provides structural support for semiconductor die180 after removal of the carrier.Conductive layer172 andcontact pads184 of semiconductor die180 are exposed following removal of the carrier and interface layer.

The structure is inverted and an insulatinglayer190 is formed overencapsulant188,conductive layer172, andactive surface186. The insulatinglayer190 is thicker overactive region186, due to vertical offset of the protective adhesive layer, than overencapsulant188 andconductive layer172. A portion of insulatinglayer190 is removed by a patterning and etching process to exposeconductive layer172 andcontact pads184.

A bottom-side build-upinterconnect structure192 is formed overinsulating layer190. The build-upinterconnect structure190 includes an electricallyconductive layer194, insulating orpassivation layer196, andUBM198.

Encapsulant188 undergoes grinding or plasma etching to planarize the surface for the topside build-up interconnect structure. The grinding operation exposes the top surface ofconductive pillars178 and, optionally, the back surface of semiconductor die180, as described inFIG. 5. An optional process carrier can be mounted topassivation layer196 andconductive layer198 for additional structural support during the grinding operation.

The structure is inverted and a topside build-upinterconnect structure200 is formed overencapsulant188 andconductive pillars178. The build-upinterconnect structure200 includes one or more IPDs. An insulating orpassivation layer202 is formed overencapsulant188 andconductive pillars178 using spin coating, PVD, CVD, printing, sintering, or thermal oxidation. Thepassivation layer202 can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having suitable insulating properties. A portion ofpassivation layer202 is removed to exposeconductive pillars178.

An electricallyconductive layer204 is formed overinsulating layer202 using patterning with PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process to form individual portions or sections. The individual portions ofconductive layer204 can be electrically common or electrically isolated depending on the connectivity of the individual semiconductor die.Conductive layer204 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. One portion ofconductive layer204 is electrically connected toconductive pillars178. Other portions ofconductive layer204 can be electrically common or electrically isolated depending on the design and function of the semiconductor device.

A resistive layer206a-206bare patterned and deposited overconductive layer204 and insulatinglayer202, respectively, using PVD or CVD. Resistive layer206 is tantalum silicide (TaxSiy) or other metal silicides, TaN, nickel chromium (NiCr), TiN, or doped poly-silicon having a resistivity between 5 and 100 ohm/sq. An insulatinglayer208 is formed overresistive layer206ausing PVD, CVD, printing, sintering, or thermal oxidation. The insulatinglayer208 can be one or more layers of Si3N4, SiO2, SiON, Ta2O5, ZnO, ZrO2, Al2O3, polyimide, BCB, PBO, or other suitable dielectric material. Resistive layer206 and insulatinglayer208 can be formed with the same mask and etched at the same time. Alternatively, resistive layer206 and insulatinglayer208 can be patterned and etched with a different mask.

An insulating orpassivation layer210 is formed overpassivation layer202,conductive layer204, resistive layer206, and insulatinglayer208 using spin coating, PVD, CVD, printing, sintering, or thermal oxidation. Thepassivation layer210 can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having suitable insulating properties. A portion ofpassivation layer210 is removed to exposeconductive layer204, resistive layer206, and insulatinglayer208.

An electricallyconductive layer212 is patterned and deposited overpassivation layer210,conductive layer204, resistive layer206, and insulatinglayer208 using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process to form individual portions or sections for further interconnectivity. The individual portions ofconductive layer212 can be electrically common or electrically isolated depending on the connectivity of the individual semiconductor die.Conductive layer212 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.

An insulating orpassivation layer214 is formed overconductive layers212 andpassivation layer210 using spin coating, PVD, CVD, printing, sintering, or thermal oxidation. Thepassivation layer214 can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having suitable insulating properties. A portion ofpassivation layer214 is removed to exposeconductive layer212.

An electricallyconductive layer216 is patterned and deposited overpassivation layer214 andconductive layer212 using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process.Conductive layer216 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.Conductive layer216 is a UBM in electrical contact withconductive layers212 and204 andconductive pillars178.

The structures described in build-upinterconnect structure200 constitute one or more passive circuit elements or IPDs. In one embodiment,conductive layer204,resistive layer206a, insulatinglayer208, andconductive layer212 is a metal-insulator-metal (MIM) capacitor.Resistive layer206bis a resistor element in the passive circuit. The individual sections ofconductive layer212 can be wound or coiled in plan-view to produce or exhibit the desired properties of an inductor.

The IPD structure provides electrical characteristics needed for high frequency applications, such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetric Hi-Q resonant transformers, matching networks, and tuning capacitors. The IPDs can be used as front-end wireless RF components, which can be positioned between the antenna and transceiver. The inductor can be a hi-Q balun, transformer, or coil, operating up to 100 Gigahertz. In some applications, multiple baluns are formed over a same substrate, allowing multi-band operation. For example, two or more baluns are used in a quad-band for mobile phones or other global system for mobile (GSM) communications, each balun dedicated for a frequency band of operation of the quad-band device. A typical RF system requires multiple IPDs and other high frequency circuits in one or more semiconductor packages to perform the necessary electrical functions.

The IPDs can be formed in either or both of the topside build-up interconnect structure and bottom-side build-up interconnect structure.

The optional carrier and adhesive layer overpassivation layer196 andUBM198 are removed by chemical wet etching, plasma dry etching, mechanical peel-off, CMP, mechanical grinding, thermal bake, laser scanning, or wet stripping. An electrically conductive bump material is deposited overUBM198 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded toUBM198 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps218. In some applications, bumps218 are reflowed a second time to improve electrical contact toUBM198. The bumps can also be compression bonded toUBM198. Bumps218 represent one type of interconnect structure that can be formed overUBM198. The interconnect structure can also use bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.

Conductive pillars178 provide vertical, z-direction interconnect between topside build-upinterconnect layer200 and bottom-side build-upinterconnect layer192.Conductive layers204 and212 are electrically connected throughconductive pillars178 toconductive layer172 andcontact pads184 of semiconductor die180.

The thick protectiveinsulating layer190 disposed overactive surface186 reduces stress caused by CTE mismatch between semiconductor die180 and bottom-side build-upinterconnect structure192. The stress buffering provided by insulatinglayer190 reduces joint failure rate ofconductive pillars178 and delamination between semiconductor die180 and build-upinterconnect structure192.

While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.

Claims (25)

1. A method of making a semiconductor device, comprising:

providing a temporary carrier;

forming a first conductive layer over the temporary carrier;

forming a conductive pillar over the first conductive layer;

mounting an active surface of a semiconductor die to the temporary carrier with an adhesive layer, the semiconductor die being vertically offset from the first conductive layer by the adhesive layer;

depositing an encapsulant over the semiconductor die and around the conductive pillar;

removing the temporary carrier and adhesive layer;

forming a stress relief insulating layer over the active surface of the semiconductor die and a first surface of the encapsulant, the stress relief insulating layer having a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant;

forming a first interconnect structure over the stress relief insulating layer; and

forming a second interconnect structure over a second surface of the encapsulant opposite the first interconnect structure, the first and second interconnect structures being electrically connected through the conductive pillar.

2. The method ofclaim 1, wherein the second interconnect structure includes an integrated passive device electrically connected to the conductive pillar.

3. The method ofclaim 1, further including removing a portion of the encapsulant to form a planar surface for the first interconnect structure.

4. The method ofclaim 3, wherein a back surface of the semiconductor die opposite the active surface of the semiconductor die is coplanar with a surface of the conductive pillar.

5. The method ofclaim 1, further including:

stacking a plurality of the semiconductor devices; and

electrically connecting the semiconductor devices through the conductive pillar.

6. A method of making a semiconductor device, comprising:

providing a first carrier;

forming a conductive pillar over the first carrier;

mounting a semiconductor component to the first carrier;

depositing an encapsulant over the semiconductor component and around the conductive pillar;

removing the first carrier;

forming a stress relief insulating layer over the semiconductor component and a first surface of the encapsulant, the stress relief insulating layer having a first thickness over the semiconductor component and a second thickness less than the first thickness over the encapsulant;

forming a first interconnect structure over the stress relief insulating layer; and

forming a second interconnect structure over a second surface of the encapsulant opposite the first interconnect structure, the first and second interconnect structures being electrically connected through the conductive pillar.

7. The method ofclaim 6, wherein the second interconnect structure includes an integrated passive device electrically connected to the conductive pillar.

8. The method ofclaim 6, further including removing a portion of the encapsulant to form a planar surface for the first interconnect structure.

9. The method ofclaim 6, further including mounting a second carrier to the first interconnect structure prior to forming the second interconnect structure.

10. The method ofclaim 6, further including:

stacking a plurality of the semiconductor devices; and

electrically connecting the semiconductor devices through the conductive pillar.

11. The method ofclaim 6, wherein forming the first interconnect structure includes:

forming a first conductive layer over the stress relief insulating layer, the first conductive layer being electrically connected to the conductive pillar;

forming a first insulating layer over the stress relief insulating layer and first conductive layer; and

forming a second conductive layer over the first conductive layer, the second conductive layer being electrically connected to the conductive pillar.

12. A method of making a semiconductor device, comprising:

providing a first carrier;

forming a conductive pillar over the first carrier;

mounting a semiconductor component to the first carrier with an active surface of the semiconductor component oriented toward the first carrier;

depositing an encapsulant over the semiconductor component and around the conductive pillar;

removing the first carrier;

forming a stress relief insulating layer contacting the active surface of the semiconductor component and over a first surface of the encapsulant; and

forming a first interconnect structure over the stress relief insulating layer, the first interconnect structure being electrically connected to the conductive pillar.

13. The method ofclaim 12, further including forming a second interconnect structure over a second surface of the encapsulant opposite the first interconnect structure, the first and second interconnect structures being electrically connected through the conductive pillar.

14. The method ofclaim 13, wherein the second interconnect structure includes an integrated passive device electrically connected to the conductive pillar.

15. The method ofclaim 12, wherein the semiconductor component is vertically offset from the first carrier.

16. The method ofclaim 12, wherein the stress relief insulating layer has a first thickness over the semiconductor component and a second thickness less than the first thickness over the encapsulant.

17. The method ofclaim 12, further including removing a portion of the encapsulant to form a planar surface for the first interconnect structure.

18. The method ofclaim 13, further including mounting a second carrier to the first interconnect structure prior to forming the second interconnect structure.

19. The method ofclaim 12, further including:

stacking a plurality of the semiconductor devices; and

electrically connecting the semiconductor devices through the conductive pillar.

20. The method ofclaim 12, wherein forming the first interconnect structure includes:

forming a first conductive layer over the stress relief insulating layer, the first conductive layer being electrically connected to the conductive pillar;

forming a first insulating layer over the stress relief insulating layer and first conductive layer; and

forming a second conductive layer over the first conductive layer, the second conductive layer being electrically connected to the conductive pillar.

21. A method of making a semiconductor device, comprising:

providing a first carrier;

forming a conductive pillar over the first carrier;

mounting a semiconductor component over the first carrier;

depositing an encapsulant over the semiconductor component and around the conductive pillar;

removing the first carrier;

forming a stress relief insulating layer over an active surface of the semiconductor component and over a first surface of the encapsulant; and

forming a first interconnect structure over the stress relief insulating layer, the first interconnect structure being electrically connected to the conductive pillar.

22. The method ofclaim 21, further including forming a second interconnect structure over a second surface of the encapsulant opposite the first interconnect structure, the first and second interconnect structures being electrically connected through the conductive pillar.

23. The method ofclaim 22, wherein the second interconnect structure includes an integrated passive device electrically connected to the conductive pillar.

24. The method ofclaim 21, wherein the stress relief insulating layer has a first thickness over the semiconductor component and a second thickness less than the first thickness over the encapsulant.

25. The method ofclaim 21, wherein forming the first interconnect structure includes:

forming a first conductive layer over the stress relief insulating layer, the first conductive layer being electrically connected to the conductive pillar;

forming a first insulating layer over the stress relief insulating layer and first conductive layer; and

forming a second conductive layer over the first conductive layer, the second conductive layer being electrically connected to the conductive pillar.

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