US8009725B2 - Translational switching system and signal distribution system employing same - Google Patents

Abstract

A translational switch system includes first and second translational switches, and a signal bus coupled therebetween. The first translational switch includes one or more inputs configured to receive a respective one or more first input signals, a first plurality of outputs, and a second plurality of outputs. The second translational switch includes one or more inputs configured to receive a respective one or more second input signals, a first output, and a second output. The signal bus, coupled between the first and second translational switches, includes (i) a first bus line coupled to a first one of the first plurality of outputs of the first translational switch, and to the first output of the second translational switch, and (ii) a second bus line coupled to a first one of the second plurality of outputs of the first translational switch, and to the second output of the second translational switch.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority of each of the following applications, and incorporates by reference the contents of each of the following applications for all purposes:

U.S. Provisional Application No. 60/885,814, filed Jan. 19, 2007, entitled “Circuits, Systems and Methods for Constructing a Composite Signal;” and

U.S. Provisional Application No. 60/886,933, filed Jan. 28, 2007, entitled “Circuits, Systems and Methods for Frequency Translation and Signal Distribution.”

BACKGROUND

The present invention relates to circuits and systems for processing signals, and particularly with circuits and systems for constructing composite signals.

Composite signals are formed by assembling two or more signals into a combined signal spectrum, and find utility in many applications. For example, systems used to distribute satellite television signals often employ means to construct composite signals, whereby various channels or bands of channels originating from several different satellites are assembled into a composite signal over which a user's set top box or other receiver can tune. Switch matrices are often used in such systems, whereby a particular input signal (e.g., a Ku or Ka-band satellite signal) is supplied to an input of a switch matrix, and the switch matrix controlled so as to provide that signal to one or more of the switch matrix outputs. Two or more of such signals, each typically representing a different signal spectrum (i.e., containing different channels, or bands of channels) are combined (using, e.g., a diplexer or signal combiner network) and possibly frequency-translated to a second frequency (e.g., upper and lower L-band frequencies, 950 MHz-1450 MHz and 1650 MHz-2150 MHz), the combination of the two signals representing a composite signal that is supplied to a user for demodulation and/or baseband processing.

FIG. 1 illustrates a conventional satellite television distribution system operable to construct and distribute a composite signal. The system is configured to receive signals from two satellite signal sources and to output two composite signals, each composite signal typically including a portion of each of the two satellite signals, and each composite signal supplied to a dual channel tuner (or two individual tuners). Each antenna receives two signals of different polarizations, typically having channel frequencies offset by half-channel width or having the same channel frequencies. In direct broadcast satellite (DBS) applications, the polarization is typically circular, having right-hand (R1 and R2) and left-hand (L1 and L2) polarized signals as labeled inFIG. 1. Signals can also be linearly polarized with horizontal and vertical polarizations.

The received signals are processed in a low noise block-converter108 consisting of low noise amplifiers107 (typically 2 or 3 amplifiers in a cascade), filters109 (typically bandpass filters providing image rejection and reducing out of band power) andfrequency converter block110. Theconverter block110, performing frequency down conversion, containslocal oscillators LO1114 andLO2112 typically of the DRO (dielectric-resonator oscillator) types, mixers and post-mixer amplifiers. The two mixers driven by LO1 down convert the signals to one frequency band (lower—L) while the mixers driven by LO2 down convert to a different frequency band (higher—H). The L and H bands are mutually exclusive, do not overlap and have a frequency guard-band in between. The L and H band signals are then summed together in aseparate combiner116 in each arm, forming a composite signal having both frequency bands (“L+H”, which is often referred to as a “band-stacked signal” when the added signal components are bands of channels, or a “channel-stacked signal” when the added signal components are individual channels) which is then coupled to a 2×4 switch matrix/converter block120.

Theswitch matrix130 routes each of the two input signals to selected one or more of the 4 outputs, either by first frequency converting the signals in themixers128 driven byLO3132 or directly via the bypass switches around the mixers (the controls for the switch and mixer bypass not shown in the figure). The frequency of the LO3 is chosen such that the L-band converts into the H band, and vice versa, which is referred to as the “band-translation.” This is accomplished when the LO3 frequency is equal to the difference of the LO2 and LO1 frequencies.

The outputs of the matrix switch/converter block120 are coupled through diplexers consisting of a high-pass filter122, low-pass filter124 and a combiner126 (as shown in the upper arm, the lower arm being the same) providing twodual tuner outputs118 and134. Thefilters122 and124 remove the undesired portion of the spectrum, i.e. the unwanted bands in each output. Each of the twooutputs118 and134 feeds via a separate coaxial cable a dual tuner, for a total capability of four tuners. By controlling the matrix switch routing and the mixer conversion/bypass modes, a frequency translation is accomplished and each of the four tuners can independently tune to any of the channels from either polarization of either satellite.

While operational, the conventional system suffers from some disadvantages, one of which is the relatively low source-to-source isolation the system exhibits. In particular, the lownoise converter block108 and the switchmatrix converter block120 each may exhibit low isolation between their respective signal paths, which may lead to cross-coupling of the signals, and contamination of the composite signal with unwanted signal content. This cross-coupling effect becomes especially acute when the sources operate at high frequencies and over the same band, conditions which exist in the aforementioned satellite TV distribution system, whereby both satellite sources operate over the same Ku or Ka-band.

Another disadvantage of the conventional system is that multiple frequency translations are needed to provide the desired composite output signal. In particular, the lownoise block converter108 provides a first frequency translation, e.g., to down convert the received satellite signal from Ku-band to L-band, and the switch matrix/converter120 provides a second frequency translation, e.g., to translate the down converted signal from a lower band to an upper band, or visa versa. Multiple frequency conversions increase the system's complexity, cost, and power consumption, as well as degrade signal quality.

SUMMARY

As one embodiment of the present invention, a translational switch system is presented and includes first and second translational switches, and a signal bus coupled therebetween. The first translational switch includes one or more inputs configured to receive a respective one or more first input signals, a first plurality of outputs, and a second plurality of outputs, the first translational switch configured to switchably output a first frequency version of the first input signal to any of the first plurality of outputs, and to switchably output a second frequency version of the first input signal to any of the second plurality of outputs. The second translational switch includes one or more inputs configured to receive a respective one or more second input signals, a first output, and a second output, the second translational switch configured to switchably output a first frequency version of the second input signal to the first output, and to switchably output a second frequency version of the second input signal to the second output. The signal bus, coupled between the first and second translational switches, includes: (i) a first bus line coupled to a first one of the first plurality of outputs of the first translational switch, and to the first output of the second translational switch, and (ii) a second bus line coupled to a first one of the second plurality of outputs of the first translational switch, and to the second output of the second translational switch.

These and other features of the invention will be better understood in view of the following description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a conventional satellite television distribution system operable to construct and distribute a composite output signal.

FIG. 2 illustrates a first exemplary system for constructing a composite signal in accordance with one embodiment of the present invention.

FIG. 3 illustrates a second exemplary system for constructing a composite signal in accordance with one embodiment of the present invention.

FIG. 4 illustrates an exemplary embodiment of a partial translational switch shown inFIG. 3.

FIG. 5 illustrates an exemplary embodiment of a full translational switch shown inFIG. 3.

FIG. 6A illustrates an exemplary partial translational switch employing automatic gain control circuitry in accordance with one embodiment of the present invention.

FIG. 6B illustrates an exemplary full translational switch employing automatic gain control in accordance with one embodiment of the present invention.

FIG. 7A illustrates a detailed partial view of the signal bus implemented within the translational switching system ofFIG. 3.

FIG. 7B illustrates an exemplary embodiment of an output switch in accordance with one embodiment of the present invention.

FIG. 7C illustrates an exemplary layout of the signal bus in accordance with one embodiment of the present invention.

FIG. 7D illustrates an exemplary output switch employing automatic gain control in accordance with one embodiment of the present invention.

FIGS. 7E and 7F illustrate exemplary embodiments of driver circuits for signal bus lines in accordance with embodiments of the present invention.

FIG. 8 illustrates a partial detailed view of the signal bus implemented within the translational switching system ofFIG. 3.

FIG. 9 illustrates a third exemplary system for constructing a composite signal in accordance with one embodiment of the present invention.

FIG. 10 illustrates a fourth exemplary system for constructing a composite signal in accordance with one embodiment of the present invention.

FIG. 11 illustrates an exemplary embodiment of the full translational switch shown inFIG. 10.

FIG. 12 illustrates a partial detailed view of the signal bus implemented within the translational switching system ofFIG. 10.

FIG. 13 illustrates a fifth exemplary system for constructing a composite signal in accordance with one embodiment of the present invention.

For clarity, previously-described features retain their reference numbers in subsequent drawings.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 2 illustrates a firstexemplary system200 for constructing a composite signal in accordance with one embodiment of the present invention. Theexemplary system200 includes one ormore receiving modules220, a translational switch system301 (herein “translator”), afilter bank250, signal combiningnetwork260, andoutput amplifiers270. Power and control signals (not shown in order to simplify the drawing) are routed to each of the components to activate and control the operating states of such components to perform the operations as described herein.

The receivingmodule220 includes anantenna221,amplifiers222,223,224, and225, and filters226 and227 for receiving and conditioning one or more signals. The signal may be in the form of one or more individual channels, one or more bands of channels (each band including, e.g., a group of two, three, four, five, ten or more channels), or a combination of both channels and bands. Furthermore, the received signals221aand221bmay originate from a terrestrial or satellite source, be analog or digital in format, and be transmitted in any particular modulation format at the desired carrier frequency, e.g., in the radio frequency, optical, or infrared signal ranges.

In a particular embodiment, theantenna221 is operable to independently twosignals221aand221b, e.g., two substantially orthogonal signal components such as left and right hand circularly polarized signals or vertical and horizontally polarized signals. Along these lines,amplifiers222 and224 andfilter226 is operable to condition thefirst signal component221ato provide aninput signal228ato thetranslator301. Similarly,amplifiers223 and225 andfilter227 is operable to condition thesecond signal component221bto provide aninput signal228bto thetranslator301. In another embodiment, the receivingmodule220 provides an antenna or other receiving means to collect one signal, in which case only one branch of signal conditioning components (amplifiers, filters, etc.) is needed. In another embodiment, three or more signal components are collected from the antenna or other receiving means (operable to detect analog or digital formatted signal in the radio frequency, optical, or infrared ranges), in which case additional signal conditioning branches operable to provide the necessary signal filtering and amplification may be employed. Moreover, while the exemplary system employs a single receive module, a plurality of receive modules, for example, 2, 3, 4, 6, 8, 10, 20 or more may be implemented, and exemplary embodiments of system implementing multiple receive modules are described below.

Thesystem200 further includes a translational switch system301 (“translator”) operable to perform frequency translation of the input signal228. Thetranslator301 may provide any plurality of frequency translations, and in a particular embodiment provides two different frequency translations to the input signal(s). In other embodiments, thetranslator301 provides 3, 4, 5, 6, 8, 10, 20, 50, 100, 1000, or more frequency translations to the input signal(s). In some embodiments of the invention, thetranslator301 operates as a partial translational switch, whereby the two or more frequency versions of the input signals includes a non-translated version of the input signal, e.g., the non-translated version of the input signal serves as the first frequency version of the input signal. An example of this embodiment if further described below.

In one exemplary embodiment, thetranslator301 operates to translate Ku- or Ka-band satellite signals (Ku-band satellite signals exemplified by the frequency ranges of 11.7 GHz-12.7 GHz, and Ka-band satellite signals exemplified by the frequency range of 17.3 GHz-17.8 GHz herein), or externally supplied L-band signals to either a lower L-band frequency (950-1450 MHz, indicated as signals along circuit branches labeled “L”) or an upper L-band frequency (1650-2150 MHz, indicated as signals along circuit branches labeled “H”) signals. Thetranslator301 may, of course, be used to provide other translation to and/or from other frequencies. The construction and operation of thetranslator301 is further described below.

Thesystem200 optionally includes afilter bank250, in which filters251,253 and255 are illustrated as low pass filters and filters252,254 and256 are indicated as high pass filters. Low pass filters251,253 and255 operate to attenuate signal power at frequencies above the high end of the 950-1450 lower L-band, and high pass filters252,254 and256 operate to attenuate signal power at frequencies below the low end of the 1650-2150 MHz upper L-band. Other filter structures, such as bandpass filters or notch/bandstop filters may be alternatively implemented. Further, the degree of filtering may vary along each of the outputs, with some outputs requiring little or no filtering, and some outputs requiring some filtering or perhaps multiple stages of filtering. The filter types used may also vary, some examples being elliptical, chebychev, butterworth, as well as other types. Moreover, whilefilters250, signalcombiners260, andamplifiers270 are illustrated as being outside of thetranslator301, one, some or all of these components may be included within thetranslator301.

Due to the architecture of the present invention, post-conversion filtering viafilters250 may be reduced or obviated all together on one or more of theoutput lines390, as the down conversion architecture results in very little signal power residing outside of the intended frequency range of the signals supplied to the combiner circuits260₁-260₃. The architecture provides a relatively large frequency separation of LO and RF frequency from the output IF frequency, resulting in large separation of the undesired mixer images/unwanted sidebands from the desired IF. For instance, at Ku band the signal is around 12 GHz and the LO around 14 GHz, producing the desired IF at the difference frequency of about 2 GHz at L-band, while the undesired sideband falling to the sum frequency is around 26 GHz, far away from the desired L-band. At this high frequency, the undesired signal will typically naturally decay due to inherent high frequency roll-off properties of most elements in the system, including the receiver, and as such typically does not need much filtering for separation and removal from the desired signal. In one exemplary application in which the input signals are Ku/Ka band signals and thetranslator301 is operable to down convert the Ku/Ka band signals to upper and lower L-band signals of 1650-2150 MHz (signals “H”) and 950-1450 MHz (signals “L”), respectively, very little signal power resides in the 950-1450 MHz range for the upper band signals “H” supplied to the combiners260₁-260₃, and similarly very little signal power resides in the 1650-2150 MHz frequency range for the lower band signals “L” supplied to combiners260₁-260₃.

Signal combiners261,262 and263 are each operable to combine the different frequency versions of the input signals to provide a composite signal. The term “composite signal” refers to a signal formed from the combination of two or more (e.g., 3, 4, 5, 10, 20, 50 or more) signals. In a particular embodiment, the signals which are to be combined may have non-overlapping frequency ranges.

In the illustrated embodiment in which two frequency translations are performed, each of thesignal combiners261,262 and263 include two respective inputs for receiving each of the two frequency versions of the input signal. In other embodiments in which thetranslator301 provides N different frequency translations (N, being for example, 3, 4, 5, 6, 8, 10, 20, 50, 100 or more frequency translations), each signal combiner will include N inputs, each input coupled to receive a respective frequency translated output signal. While three signal combiners are illustrated, any number may be implemented as needed to supply the requisite number of receivers (e.g., set top boxes).Output amplifiers271,272 and273 are optionally used to boost signal level and/or to improve output-to-output signal isolation. Once constructed, the composite signal is supplied to one or more receivers either via a wired connection (e.g., coaxial or fiber cable) or wireless connection (e.g. RF, infrared, optical link, etc.).

FIG. 3 illustrates a secondexemplary system300 for constructing a composite signal in accordance with one embodiment of the present invention. Theexemplary system300 includes four receivemodules220,320,340 and360, a translational switching system301 (“translator”), filters250, signalcombiners260, andoutput amplifiers270. Power and control signals (not shown in order to simplify the drawing) are routed to each of the components to activate and control the operating states of such components to perform the operations as described herein.

The receivemodule220 is as described above inFIG. 2. In the illustrated embodiment, receivemodules320 and340 are constructed similar to that of receivemodule220, although some aspects, such as the received signal's frequency, modulation, polarization, or orbital slot position (when the source is a satellite) may dictate a corresponding difference in the receive modules' circuitry, for example, differences in the antenna shape/size (when the source is a satellite), differences in the gain/attenuation of the amplifiers, and/or differences in the pass band, and/or type of filters used in each of the receivemodules220,320 and340. Each of the receivemodules220,320 and340 receives and conditions (i.e., amplifies/attenuates, filters, etc.) its respective received signal(s), and outputs a corresponding signal(s). As shown, receivemodule220 receivesorthogonal signals221aand221b, andoutputs corresponding signals228a,bto thetranslator301. In a similar manner, each of the receivemodules320 and340 process their respective received signals321a,band341a,bto providerespective signals328a,band348a,bto thetranslator301.

Exemplary system300 further includes a receivemodule360 operable to receive a signal operating at a previously-translated frequency, whereby the receivemodule360 includes a plurality of filters operable to deconstruct a signal supplied thereto into separate signal components. In the illustrated exemplary embodiment, alow pass filter365 and ahigh pass filter366 are implemented to provide a lowfrequency signal component368a, and a highfrequency signal component368b, respectively. In alternative embodiments, three or more filters (e.g., 4, 5, 6, 8, 10, or more filters) may be used to separate the supplied signal into a respective three or more signal components. As an exemplary embodiment,system300 employs receivemodules220,320 and340 to receive and process RF frequency signals, e.g., Ku or Ka-band signals, and the receivemodule360 to receive and process an IF frequency signal, e.g., a band stacked L-band signal, the receivemodule360 operating to deconstruct the bandstacked L-band signal into a low L-band signal368a, and a high L-band signal368b.

Construction of the receivemodels220,320,340 and360 will usually be dictated by the particular application; e.g., possibly a discrete or hybrid construction when thesystem300 is used to process satellite signals, or possibly an integrated circuit when thesystem300 is implemented as part of an integrated receiver. The skilled person will appreciate that the receive modules may be constructed at any level of integration suitable and desirable for the particular application in which they are used.

Theexemplary system300 further includes thetranslator301, which in one embodiment includes a partialtranslational switch310a, three fulltranslational switches310b₁,310b2 and310b3, and areference module370. As shown, the partialtranslational switch310areceivessignals368a,bfrom the receivemodule360. The first, second, and third fulltranslational switches310b₁,310b₂and310b₃receive respective input signals228a,b,328a,b, and348a,b. The term “partial” in the descriptor “partial translational switch” refers to the operation of this translator, in which one or more of its input signals are not translated in the conventional sense to another frequency (e.g., through a mixing process), but are instead coupled through the circuit at its original input frequency. The term “full” in the descriptor “full translational switch” refers to the operation of this translator, in which all of its input signals are translated to another frequency, e.g., through a mixing process. An exemplary embodiment of the partialtranslational switch310ais illustrated inFIG. 4, and an exemplary embodiment of the fulltranslational switches310b₁,310b₂, and310b₃is illustrated inFIG. 5.

Each of the partial and full translational switches (collectively referred to as “translational switches” for brevity) also receives a reference signal from thereference module370. In the exemplary embodiment shown, thereference module370 includes threereference frequency generators372,374 and376 operating at 11.25 GHz, 3.1 GHz, and 14.35 GHz, respectively. These particular reference frequencies enable the processing of Ku-band satellite signals received by receivemodules220,320, and340, and a band-stacked L-band signal received by receivemodule360. The person skilled in the art will appreciate that different reference frequencies, and/or a different number of reference sources and mixers can be employed for systems designed to process signals at other frequencies.

Eachtranslational switch310a,310b₁-310b₃processes theirrespective signals368a,b,228a,b,328a,b, and348a,bin a manner as further described inFIG. 4. In general, each of the translational switches produces a plurality of different frequency versions of their received signal(s); i.e., each translational switch produces its input signal(s) at two or more different frequencies. In the exemplary embodiment ofFIG. 3, each translational switch produces two different frequency versions of their respective input signals, although inother embodiments 3, 4, 5, 6, 8, 10, 20 or more frequency translations may be performed. Each translation switch produces a first frequency version of its input signal(s) within the lower L-band range of 950-1450 MHz (signals indicated by the letter “L”, and a second frequency version of its input signal(s) within the upper L-band range of 1650-2150 MHz (signals indicated by the letter “H”). In the exemplary embodiment ofFIG. 3, each translational switch is provided with two input signals, and correspondingly, each translational switch provides a first frequency version for each input signal, indicated by “L” for low L-band signal (total of two “L” signals provided per translational switch), and a second frequency version for each input signal, indicated by “H” for upper or high L-band signal (total of two “H” signals provided per translational switch).

Thetranslator301 further includes areference source370, for providing the reference signals used by thetranslational switches310aand310b. In the exemplary embodiment shown,reference source370 includes threesignal generators372,374 and376 operable to generate a respective three reference signals. In one embodiment, thereference sources372,374 and376 are PLL-controlled oscillators. Alternatively, thereference sources372 and374 may be dielectric resonator oscillators. One or more of thereference sources372,374 and376 may be of a fixed frequency or variable frequency type.

Further exemplary of thetranslator301 is asignal bus380, which couples to eachtranslational switch310aand310b₁-b₃. The construction and operation of the signal bus is further described inFIG. 6, but in general thesignal bus380 operates to selectively couple any of the H or L signals to any one of the output lines390 (hollow circles indicating a controllable or selectively-coupled connection that is presently open, and a darkened circle indicating selectively-coupled connection that is presently closed/made).

In the exemplary arrangement ofFIG. 3, eachoutput line391a,392a, and393ais selectively coupled, viasignal bus380, to receive a respective one of the low L-band signals provide by the translational switches, and eachoutput line391b,392b,393bis selectively coupled, viasignal bus380, to receive a respective one of the high L-band signals provided by the translational switches. As can be seen, the first and second versions of the input signals may be supplied to alternating bus lines, so as to improve signal isolation between lines carrying the same frequency signals. Similarly, thesignal bus380 may be operable to supply the first and second versions of the input signals to alternatingoutput lines390 to improve signal isolation. Collectively, theoutput lines391a,b,392a,band393a,bare arranged such that each receiver (viasignal combiner261, or262, or263) is supplied with any one of a low L-band signal and any one of a high L-band signal. In this manner, each receiver can independently receive a composite signal formed by any one of the low L-band signals and any one of the high L-band signals. Of course, information included within each of the low and high L-band signals, e.g., one or more television channels, could thus be supplied to any receiver of thesystem300, independent of the television channel(s) (i.e., the composite signal) delivered to another receiver of the system.

FIG. 4 illustrates an exemplary embodiment of a partialtranslational switch310ashown inFIG. 3. Power and control signals (not shown in order to simplify the drawing) are routed to each of the components to activate and control the operating states of such components to perform the operations as described herein.

The partialtranslational switch310aincludes afirst input422afor receivingsignal368a,second input422bfor receivingsignal368b(signals368aand368bbeing, for example, lower and upper L-band signals provided via an external source), output ports422c₁-422c₃for providing a first frequency version of the received signals368aand/or368b, andoutput ports422d₁-422d₃for providing a second frequency version of the received signals368aand/or368b.

Internally within the partialtranslational switch310a, receivedsignals368aand368bare processed in parallel. A non-frequency translated version ofsignal368ais supplied to thefirst output switch420.Signal368ais additionally supplied to amixer408, which produces a frequency-translated version ofsignal368a, that signal supplied to thesecond output switch425. Similarly, a non-frequency translated version ofsignal368bis supplied to thesecond output switch425. Signal368bis additionally supplied to amixer409, which produces a frequency-translated version ofsignal368b, that signal supplied to thefirst output switch420.Mixers408 and409 are supplied with reference signal fromsource374, a signal at 3.1 GHz in the illustrated embodiment. Optional circuitry (amplifiers402,403,410,411,412,413, and atuned resonators405 and404) may be used to provide the required signal level/characteristics.

In the illustrated embodiment, signal368ais a lower L-band signal that is frequency-translated (up converted) to the upper L-band (1650-2150 MHz) bymixer408. Further exemplary, signal368bis an upper L-band signal that is frequency-translated (down converted) to the lower L-band (950-1450 MHz) bymixer409.Mixers408 and409 may be configured to differently in alternative embodiments to provide either signal up conversion or down conversion.

The levels of integration for thetranslational switch310amay vary. In a particular embodiment,frequency source370 is implemented outside thetranslational switch310aand can be shared with other translational switches, as shown inFIG. 3. Further exemplary, the first and second output switches420 and425 are implemented on the same semiconductor die, and coupled to the semiconductor die housing circuitry of the system with thefrequency source370 in a manner described inFIG. 7C. The skilled person will appreciate that other levels of integration are possible (for example, an IC integrating all of the illustrated components), as well as the variety of integrated circuit fabrication techniques and materials (e.g., Si, SiGe, or GaAs, etc.) that may be used to form such devices. For example, thetranslator301 may be constructed in a system-in-package (SIP) form, in whichtranslational switches310a,310b₁-310b₃, andfrequency source370 are implemented as discrete circuits of dice/ICs interconnected via a routing plane on a substrate, such as a printed circuit board and assembled in a separate package.

As shown inFIG. 4, the first frequency versions ofsignal368a(signal416) and signal368b(signal417) are each supplied to afirst output switch420, and the second frequency versions ofsignal368a(signal418) and signal368b(signal419) are each supplied to asecond output switch425. In an exemplary embodiment, thefirst switch420 operates to apply signal416 or signal417 to any one, some, or all of the outputs422c₁-422c₃, concurrently supplyingsignals416 and417 to different outputs422c₁-422c₃not excluded. Further exemplary, thesecond switch425 operates to apply either signal418 or signal419 on any one, some, or all of theoutputs422d₁-422d₃, concurrently supplyingsignals418 and419 todifferent outputs422d₁-422d₃not excluded. In this manner, thetranslational switch310ais operable to output any of the first frequency (lower L-band) versions ofsignals368aor368bon any one or more of the output ports422c₁-422c₃, as well as output any of the second frequency (upper L-band) versions of the receivedsignal368aor368bon any one or more of theoutput ports422d₁-422d₃. Optionally, each of the first and second output switches420 and425 is operable to provide the possibility of different combinations of impedance states versus signal states. While the signal can be either on (passed) or off (null output signal), in either of these two states the switch output impedance (seen as the source impedance driving the subsequent load) can be designed to assume any desired impedance level (low, medium or high impedance), depending on the specific design goals and requirements. The switch can be designed to stay in the same impedance condition upon switching on or off, or it can be designed to change the impedance as the signal state is changed, the choice depending on the specifics of the bus structure/load arrangement. For example, the impedance state/signal state combination may represent a matched impedance state when the signal is on, but a high impedance, or a low impedance state when the signal is off, or any combination thereof. Further discussion on the switch and bus impedance conditions is provided in conjunction withFIGS. 7E and 7F. The off state or null output signal may be defined as a signal which does not exceed a predefined signal level. For example, the null output signal may be a signal substantially at ground potential, or it may be defined as a signal having an amplitude which is below that of a predefined detection level (e.g., a signal level more than 10 dB below a reference level known to correspond to a received valid or “on” signal). Further exemplary, the null output signal may have a predefined level around (i.e., above or below) the signal ground (e.g., a predefined DC offset), or the null output signal may consist of a zero differential signal. The foregoing serves only as a few examples known to the skilled person, although other representations of a null output signal can also be used as well.

In the foregoing description, output switches420 and425 are included within the fulltranslational switch310a. In another embodiment, switches420 and425 are components which are discrete from the fulltranslational switch310a. In still another embodiment, switches420 and425 are included within thesignal bus380.

FIG. 5 illustrates an exemplary embodiment of a fulltranslational switch310b₁shown inFIG. 3. In a specific embodiment of the invention,translational switches310b₁,310b₂and310b₃are identically constructed, although this is not necessary in all instances, and thetranslational switches310bmay differ between them as to the number of inputs, number of outputs, or both. Power and control signals (not shown in order to simplify the drawing) are routed to each of the components to activate and control the operating states of such components to perform the operations as described herein.

The fulltranslational switch310b₁includes afirst input522afor receivingsignal228a, and asecond input522bfor receivingsignal228b(signals228aand228bbeing, for example, orthogonal signals transmitted from a common source, such as a satellite, in an exemplary embodiment), output ports522c₁-522c₃for providing a first frequency version of the received signals228aand/or228b, andoutput ports522d₁-522d₃for providing a second frequency version of the received signals228aand/or228b.

Internally within the fulltranslational switch310b₁, receivedsignals228aand228bare processed in parallel.Signal228ais supplied to an optional amplifier (e.g., a low noise amplifier)502 andtuned resonator504. The resultant signal is subsequently supplied to each of twomixers506 and508 for providing the first and second frequency versions ofsignal228a, respectively.Mixer506 is supplied with reference signal fromsource372, 11.25 GHz in an exemplary embodiment, andmixer508 is supplied with reference signal fromsource376, a signal operating at 14.35 GHz in the exemplary embodiment.

Each of themixers506 and508 may perform any particular frequency translation, and in a particular embodiment, each mixer performs a down conversion of the received signal to respective first and second IF frequencies. In an alternative embodiment, each of themixers506 and508 performs an up conversion process in which the respective first and second output frequencies are higher in frequency than the supplied input signal228a.

A first frequency version (e.g., a lower band) of the receivedsignal228a(signal516) is output frommixer506, and a second frequency version of the receivedsignal228a(signal518) is output frommixer508.Optional amplifiers510 and512 may be used to provide amplification and buffering to each of thesignals516 and518.

Along a parallel path, signal228bis similarly processed by means of anoptional input amplifier503, tunedresonator505, and twomixers507 and509, thus resulting in a first frequency version ofsignal228boutput from mixer507 (signal717), and a second frequency version ofsignal228boutput from mixer509 (signal519).Optional amplifiers511 and513 may be employed to provide amplification and buffering to each of thesignals517 and519.Mixer507 is supplied with reference signal fromsource372, 11.25 GHz in an exemplary embodiment, andmixer509 is supplied with reference signal fromsource376, a signal operating at 14.35 GHz in the exemplary embodiment.

As shown, the first frequency versions ofsignal228a(signal516) and signal228b(signal517) are each supplied to afirst output switch520, and the second frequency versions ofsignal228a(signal518) and signal228b(signal519) are each supplied to asecond output switch525. In an exemplary embodiment, thefirst switch520 operates to apply signal516 or signal517 to any one, some, or all of the outputs522c₁-522c₃, concurrently supplyingsignals516 and517 to different outputs522c₁-522c₃not excluded. Further exemplary, thesecond output switch525 operates to apply either signal518 or signal519 on any one, some, or all of theoutputs522d₁-522d₃, concurrently supplyingsignals518 and519 todifferent outputs522d₁-522d₃not excluded. In this manner, thetranslational switch310b₁is operable to output any of the first frequency (lower L-band) versions ofsignals228aor228bon any one or more of the output ports522c₁-522c₃, as well as output any of the second frequency (upper L-band) versions of the receivedsignal228aor228bon any one or more of theoutput ports522d₁-522d₃. Regarding output impedance and signal conditions, the same considerations as in conjunction withFIG. 4 described above are applicable.

In the foregoing description, output switches520 and525 are included within the fulltranslational switch310b1. In another embodiment, switches520 and525 are components which are discrete from the fulltranslational switch310b₁. In still another embodiment, switches520 and525 are incorporated within thesignal bus380.

In a particular embodiment, receivedsignals228aand228bare orthogonal Ku-band signals, mixers506-509 are operable as down converters for down converting the received signals into L-band signals516,517,518 and519, and the first and second output switches520 and525 are L-band 2×3 switches. Further exemplary, the illustrated circuit (either in its entirety or in part) may be realized in either a differential signal construction or a single-ended signal construction. Alternative embodiments may be practiced in accordance with the invention. For example, the mixers506-509 may be made operable as up-converting mixers, and the first andsecond switches520 and525 may be made operable at other frequencies. In addition, oscillators/PLL530 and540 can be implemented in or outside the IC and can be shared with other frequency translation devices in the system. Furthermore, the circuit may be fabricated as a monolithic integrated circuit in any particular base substrate material, a few examples being Si, SiGe, or GaAs.

FIG. 6A illustrates an exemplary partial translational switch employing automatic gain control (AGC) circuitry in the pre- and post-mixing stages in accordance with one embodiment of the present invention. The AGC circuitry includes a firststage AGC circuit610, a secondstage AGC circuit620, and an optionalvariable attenuator625 controllable by the firststage AGC circuit610 or alternatively by the second stage620 (the former shown in the figure). Power and control signals (not shown in order to simplify the drawing) are routed to each of the components to activate and control the operating states of such components to perform the operations as described herein.

In the exemplary embodiment ofFIG. 6A, AGC control is provided at both the input (front-end) of the mixing/conversion process, as well as at the output (back-end), after the mixing. Both front and back AGC stages can be used, although depending on the signal characteristics and/or requirements, only one AGC (or none) of the AGC stages610 or620 may be used.

The firststage AGC circuit610 includes variable gain amplifiers (VGA)611 and612 coupled to the input lines carrying the L and H signals,368a, and368b, earlier described. Thefirst AGC circuit610 further includes a detector andloop circuitry613 operable to sample the signal from eachVGA611 and612. The AGC loop circuitry (which typically consists of a loop amplifier and a loop filter) generates control signals controlling theVGAs611 and612. While asingle detector613 is illustrated, separate detectors measuring separate input lines can be used. The implementation of a single detector monitoring one of the input lines provides benefits, e.g. simpler circuitry and lower power dissipation. Such an arrangement can be useful in the case when the signals in both input lines are equal or correlated to each other, when one level can be estimated based on the measurement of the other. Alternatively, before detection, the two signals can be summed or combined together, then fed to a common detector (e.g.,613), in which case theAGC circuit610 tracks the average level (or weighted average) of the two input signals. If high isolation between the two signals must be maintained, to avoid potential isolation degradation due to summing amplifiers, two separate detectors can be used with their outputs combined together, requiring only one, common loop amplifier/filter, thus saving the hardware. In the case of separate detectors, either individual AGC loops can be used to control each VGA separately/independently, or a common loop amplifier/filter can be used to control both. Optionally, avariable attenuator625 can be used (e.g., an external PIN diode attenuator), the control of which is provided by either the first AGC circuit610 (illustrated via a dashed line), or alternatively by thesecond VGA circuit620.

The second or post-mixeroutput AGC circuit620 is placed in each of the output lines (only one output shown for clarity) supplied to thesignal bus380. ThisAGC circuit620 includes aVGA621 and detector and a loop amplifier/filter623. Detector/loop and VGA arrangements similar to those described forAGC circuit610 above can be deployed for theAGC circuit620 as well.

Because AGC removes substantially all gain/loss uncertainty accumulated before the point of detection, the detector is typically located further downstream the signal path. Accordingly, the back-end AGC620 is more effective than the front-end in absorbing the gain/loss variability in the system. However, the back-end AGC620 puts more burden on the dynamic range of the devices upstream from theVGA621, since, in this case the upstream components (i.e.,VGAs611 and612) need to handle wider signal range levels. TheAGC circuit620 can be optimized based on the trade-off of these and other considerations for each particular design case. The detection point and the location of the VGA are not required to be adjacent or close to each other in the signal path. For example, sensing the signal level at far downstream point and feeding the signal back into a variable gain element at an upstream position in the signal flow, even at the very input may be beneficial in optimizing the signal level distribution and dynamic range of the system.

FIG. 6B illustrates an exemplary full translational switch employing automatic gain control in the pre- and post-mixing stages in accordance with one embodiment of the present invention. The AGC circuitry includes a firststage AGC circuit630, and a secondstage AGC circuit640. Power and control signals (not shown in order to simplify the drawing) are routed to each of the components to activate and control the operating states of such components to perform the operations as described herein.

The first (front-side) and second (back-side)AGC circuits630 and640 operate in a manner similar to theAGC circuits610 and620 shown inFIG. 6A. Both front and back AGC stages630 and640 can be used, although depending on the signal characteristics and/or requirements, only one AGC (or none) of the AGC stages may be used.

The firststage AGC circuit630 includes variable gain amplifiers (VGA)631 and632 coupled to the input lines carrying the L and H signals,228a,bor328a,bor348a, earlier described. Thefirst AGC circuit630 further includes a detector andloop circuitry633 operable to sample the signal from eachVGA631 and632. The AGC loop circuitry (which typically consists of a loop amplifier and a loop filter) generates control signals controlling theVGAs631 and632. The VGA/detector configurations can be arranged in the manners as described above inFIG. 6A

The second or post-mixeroutput AGC circuit640 is placed in each of the output lines (only one output shown for clarity) supplied to thesignal bus380. ThisAGC circuit640 includes aVGA641 and detector and a loop amplifier/filter643. Detector/loop arrangements similar to those described forAGC circuit610 above can be deployed for theAGC circuit640 as well.

FIG. 7A illustrates a detailed partial view of the signal bus implemented within thetranslator301 ofFIG. 3. The view represents a portion of the schematic shown inFIG. 3, and illustrates thesignal bus380 coupled between two fulltranslational switches310b₁and310b₂. Other features of the schematic are omitted to facilitate presentation and description of the illustrated features. Power and control signals (not shown in order to simplify the drawing) are routed to each of the components to activate and control the operating states of such components to perform the operations as described herein.

As shown, thetranslator301 includes a first translational switch (shown as the fulltranslational switch310b₁, although in another embodiment the partialtranslational switch310amay be implemented as shown below), a second translational switch (shown as the fulltranslational switch310b₂), and asignal bus380. The firsttranslational switch310b₁includes one or more inputs (two shown522a,b) configured to receive a respective one or more first input signals (two shown228a,b), a first plurality of outputs (three shown,522c₁-522c₃), and a second plurality of outputs (three shown,522d₁-522d₃). As noted, the firsttranslational switch310b₁is configured to switchably output a first frequency version of the first input signal (e.g., low L-band signal) to any of the first plurality of outputs522c₁-522c₃, and to switchably output a second frequency version of the first input signal (e.g., low L-band signal) to any of the second plurality ofoutputs522d₁-522d₃.

The secondtranslational switch310b₂is structured and functions similarly to the firsttranslational switch310b1, having one ormore inputs724a,bconfigured to receive a respective one or more second input signals328a,b, a first plurality of outputs (three shown,724c₁-724c₃), and a second plurality of outputs (three shown,724d₁-724d₃). The secondtranslational switch310b₂is configured to switchably output a first frequency version of the second input signal328a,bto any of the first plurality of outputs724c₁-724c₃, and to switchably output a second frequency version of the second input signal328a,bto any of the second plurality ofoutputs724d₁-724d₃.

Thesignal bus380 is coupled between the first and secondtranslational switches310b₁,310b₂, and includes at least afirst bus line731 and asecond bus line732. Thefirst bus line731 is selectively coupled to a first one of the first plurality of outputs (shown as output522c₁) of the firsttranslational switch310b₁, and also to a first one of the first plurality of outputs (shown as output724c₁) of the secondtranslational switch310b₂. Thesecond bus line732 is selectively coupled between a first one of the second plurality of outputs (shown asoutput522d₁) of the firsttranslational switch310b₁, and to a first one of the second plurality of outputs (shown asoutput724d₁) of the secondtranslational switch310b₂.Switches520 and720 are collectively controlled to determine which of the outputs522c₁or724c₁is to be coupled to thefirst bus line731. In the exemplary embodiment ofFIG. 7A where hollow circles indicating a switchably-coupled, open connection, and a darkened circle indicating a switchably-coupled, closed connection, output522c₁of firsttranslational switch310b₁is coupled to thefirst bus line731, and therethrough to thefirst output line391a, andoutput522d₂of firsttranslational switch310b₁is coupled to thesecond bus line732, and therethrough to thesecond output line391b. The foregoing arrangement is merely exemplary, and other connection arrangements may be employed in alternative embodiments.

As further illustrated, thesignal bus380 includes at least third andfourth bus lines733 and734. Thethird bus line733 is selectively coupled to a second one of the first plurality of outputs (shown as output522c₂) of the firsttranslational switch310b₁, and to a second one of the first plurality of outputs (shown as output724c₂) of the secondtranslational switch310b₂. Thefourth bus line734 is coupled to a second one of the second plurality of outputs (shown as522d₂) of the firsttranslational switch310b₁and to a second one of the second plurality of outputs (shown asoutput724d₂) of the secondtranslational switch310b₂. In this arrangement, the first andthird bus lines731,733 are each operable to support the propagation of the first frequency version (e.g., the low L-band version) of the first or second input signals228a,b, or328a,b, and the second andfourth bus lines732,734 are each operable to support the propagation of the second frequency version (e.g., the upper/high L-band version) of the first or second input signals228a,bor328a,b. Further particularly, the first andthird bus lines731,733 may be interleaved with the second andfourth bus lines732,734, thereby providing an additional degree of signal isolation between the two bus lines carrying the signals of the same frequency band. In particular, at least one line of a different frequency is interposed between bus lines carrying signals at the same frequency.

As noted above, output switches520,525,720 and725 may be included within the respectivetranslational switches310b₁and310b₂, or provided as discrete components therefrom, or be included within thesignal bus380. In the exemplary embodiment ofFIG. 7A in which thetranslational switches310b₁and310b₂includeoutput switches520,525 and720,725, respectively,output switch520 includes first andsecond inputs516 and517 for receiving the first frequency version (low L-band signal “L”) of the first input signal228 (first signal portion228asupplied tofirst input516, andsecond signal portion228bsupplied to the second input517), and a plurality of outputs522c₁-c₃. Thesecond output switch525 includes first andsecond inputs518 and519 for receiving a second frequency version (upper/high L-band signal “H”) of the first input signal228 (first signal portion228asupplied tofirst input518, andsecond signal portion228bsupplied to the second input519), and a plurality ofoutputs522d₁-d₃.

The secondtranslational switch310b₂includes first andoutput switches720 and725, thefirst output switch720 including first andsecond inputs716 and717 for receiving a first frequency version (lower L-band signal “L”) of the second input signal328 (first signal portion328asupplied tofirst input716, andsecond signal portion328bsupplied to the second input717), and a plurality of outputs724c₁-c₃. Thesecond output switch725 includes first andsecond inputs718 and719 for receiving the second frequency version (upper/high L-band signal “H”) of the second input signal328 (e.g.,first signal portion328asupplied tofirst input718, andsecond signal portion328bsupplied to the second input719), and a plurality ofoutputs724d₁-d₃.

In the exemplary embodiment ofFIG. 7A,signal bus380 includes bus lines731-736,bus lines731,733, and735 operable to route the first frequency version (e.g., the low L-band signal version) of either the first or second signals228 or328 to any of theoutput lines391aor392a. Similarly,bus lines732,734, and736 operate to route the second frequency version (e.g., the upper L-band signal version) of either the first or second signals228 or328 to any of theoutput lines391bor392b. In particular,bus line731 is shown coupled to output522c₁andoutput line391a, thus supplyingreceivers1 and2 with the first frequency version of the first input signal228 (either signal228aor228bas selected by switch520).Bus line732 is shown coupled tooutput522d₁andoutput line391b, thus supplyingreceivers1 and2 with the second frequency version of the first input signal228 (either signal228aor228bas selected by switch520).Bus line733 is shown coupled to output724c₂andoutput line392a, thus supplyingreceivers3 and4 with the first frequency version of the second input signal328 (either signals328aor328bas selected by switch720).Bus line734 is shown coupled tooutput724d₂andoutput line392b, thus supplyingreceivers3 and4 with the second frequency version of the second input signal328 (either signals328aor328bas selected by switch720). As noted above, the first and second versions of the input signals may be supplied to alternating bus lines, so as to improve signal isolation between lines carrying the same frequency signals. Similarly, thesignal bus380 may be made operable to supply the first and second versions of the input signals to alternating output lines to improve signal isolation.

FIG. 7B illustrates an exemplary embodiment of an output switch in accordance with one embodiment of the present invention. Power and control signals (not shown in order to simplify the drawing) are routed to each of the components to activate and control the operating states of such components to perform the operations as described herein. The structure and operation of the output switch is described in terms of the 2×3switch matrix520 presented inFIGS. 3 and 7A, although the same components (or minor modifications thereof) may be employed in the construction and operation of any of the output switches described herein.

The switch includesinputs516,517, and outputs522c₁-522c₃, and a bank of six, single-pole single-throw (SPST) switches740a-f. Power signals (not shown in order to simplify the drawing) are routed to each of the components to activate and control the operating states of such components to perform the operations as described herein. In a specific embodiment of the invention, output switches525,720, and725 are similarly configured asswitch520, although this is not necessary in all instances, and the translational switches output switches520,525,720 and725 may differ between them as to the number of inputs, number of outputs, or both.

As shown, eachinput516,517 is coupled to three of the sixSPST switches740a-f, which, responsive to acontrol signal742, sets the states of each of the SPST switches740a-f, so that any of theinputs516,517 can be switched to any one, two, or all three outputs522c₁-522c₃. Each of the SPST switch pairs (740a,b;740c,d;740e,f) are coupled together at their outputs, and these outputs coupled to thesignal bus lines731,733 and735, respectively; i.e. SPST pair740a,bcoupled to signalbus line731 atnodes744a, SPST pair740c,dcoupled to signalbus line733 atnodes744b, and SPST pair740e,fcoupled to signalbus line735 atnodes744c. Further particularly, the SPST switch pairs are controlled, so that bothinputs516,517 are not supplied to the same output simultaneously. However, both inputs may be concurrently active to supply their inputs to different outputs.

FIG. 7C illustrates an exemplary layout of a signal bus line in accordance with one embodiment of the present invention. Power and control signals (not shown in order to simplify the drawing) are routed to each of the components to activate and control the operating states of such components to perform the operations as described herein. The structure and operation of the signal bus line is described in terms of thesignal bus line380 presented inFIGS. 3 and 7A, although the same components (or minor modifications thereof) may be employed in the construction and operation of the signal bus line described inFIGS. 10 and 12 below.

FIG. 7C shows an interleaved signal bus line arrangement, withsignal bus lines731,733,735 interleaved withbus lines732,734 and736. The bus lines are shown on top ofsubstrate746 which has the ground plane at the bottom side. The bus lines731-736 as well as the ground plane may be made of electrically conductive material, each bus line forming a signal transmission line (perpendicular to the drawing plane). It is well known in the art that the characteristic impedance and signal transmission properties of the lines are determined by the geometry and physical size of the structure, as well as the electrical properties, such as the dielectric constant of the substrate, conductive material type (e.g. copper, aluminum, conductive polymer), etc. Other embodiment of the bus structure may include multi-layer substrate with bus lines located at different layers, possibly with ground plane layers in-between to achieve desired properties, such as improved signal isolation, impedance levels, etc. Other components, such as passive discrete components (e.g. capacitors, inductors, resistors) installed on the top of the substrate along with the chip dice, or embedded/printed on different substrate layers can be utilized.

In this exemplary embodiment,switch520 is illustrated as a discrete component (e.g. a flip-chip device) having conductive balls or bumps which serve to provide an interconnect between the switch outputs522c₁-522c₃and thebus lines731,733 and735 (depicted by the darker bumps, thus completing the electrical connection atnodes744a-c. The lighter shaded bumps are not connected toexemplary switch520; they depict the bus connection to other die in thetranslator301.

FIG. 7D illustrates an exemplary output switch employing automatic gain control in accordance with one embodiment of the present invention. Power and control signals (not shown in order to simplify the drawing) are routed to each of the components to activate and control the operating states of such components to perform the operations as described herein. The structure and operation of the output switch is described in terms of the 2×3switch matrix520 presented in FIGS.3 and7A-7C, although the same components (or minor modifications thereof) may be employed in the construction and operation of any of the output switches (e.g.,420,425,525,720 and725) described herein.

In an alternative technique of applying back-end AGC (i.e., post mixer stage AGC), an AGC function is inserted between theoutput switch520 and thebus line380. This AGC location provides further refinement of the level control, stabilizing the level at farther downstream point. The arrangement employs one AGC block per each bus line781-786 (three bus lines shown781-783), requiring a total of 6 blocks for a 6-wire bus example. In this illustrated embodiment, AGC blocks750,760 and770 are coupled to respectivesignal bus line731,733 and735. An exemplary construction of each AGC block750,760, and770 includes aVGA751 and detector and a loop amplifier/filter753. Detector/loop arrangements similar to those described forAGC circuit610 above can be deployed for theAGC circuit640 as well. Further exemplary an output buffer (755,765, and775) is inserted between each AGC block and corresponding bus line in order to provide the bus driving function as well as to ensure sufficient isolation of the AGC and the switch circuitry from the bus. As described below, this buffer can be in the form of a voltage source or a current source, or the combination of the two.

FIGS. 7E and 7F illustrate exemplary embodiments of driver circuits for signal bus lines in accordance with embodiments of the present invention. Power and control signals (not shown in order to simplify the drawing) are routed to each of the components to activate and control the operating states of such components to perform the operations as described herein. The structure and operation of the illustrated signal bus line is described in terms of thesignal bus line731 presented in FIGS.3 and7A-7D, although the same components (or minor modifications thereof) may be employed in the construction and operation of any of the signal bus lines described herein.

FIG. 7E illustrates a firstexemplary driver circuit780 for asignal bus731, thedrive circuitry780 implementing asource781 having aninternal impedance Rn782, thesource781 operable to signalbus line731 via acontrollable SPST switch783. Thesignal bus line731 is implemented in the form of a transmission line with a characteristic impedance Zc. Exemplary values for this impedance (and the resistance value of Rn) include 50 or 75 Ohms, although other impedances (higher or lower) may be employed as well.Signal bus line731 is selectively coupled to an output of several output switches, for example, output522c1 ofoutput switch520 and output724c1 fromoutput switch720. The impedances of outputs522c1 and724c1 are shown as R1 and R2, respectively, although their impedances may be complex as well. In general, sources are substantially resistive but may include parasitics that result in a collective complex load impedance. In an exemplary embodiment consistent withFIGS. 7E and 7F, each bus line731-736 has adedicated driver circuit780 with one source being operational and coupled to the bus at any one time; all other sources are decoupled and/or deactivated, e.g., their respective switches in the off position.

When a signal is launched fromsource781 into thesignal bus line380, it splits two ways, one towards Zload785 (i.e., the load of thebus line731 and components coupled thereto, e.g.,output line391a, output filter251) while the other travels to the opposite end of the line. The opposite end is open-circuited and the signal reflects back towards the load, as depicted by the dashed line. The electrical distance or electrical length traveled to the open circuited end one way is d1, and round trip back to the point of insertion is 2·d1. In an exemplary embodiment, the electrical roundtrip length of 2·d1 is designed such that it is smaller than the half-wavelength of the signal: 2·d1<<½ of the signal wavelength, in order to prevent cancellation (or reduction) of the signal power delivered to Zload due to phase reversal (or substantial phase shift). Further exemplary, the electrical length of thesignal bus line731 is designed to be much shorter than the quarter wave length of the signal (d1<<¼ of the signal wavelength). Because different switches couple into the bus line at different positions with respect to the open circuited end, minimizing the phase shift of the reflected signal to each of the switch positions by keeping the line short will prevent any significant difference between the signal level delivered to the load from any of the switch positions. The electrical distance between the switch and the bus, i.e. the electrical length d2 may also be designed such that it is much smaller than the quarter wavelength. Such a criterion aids to prevent the transformation of the impedance presented by the switch and voltage source into a different impedance as seen by the bus line. If length d2 electrically approaches a quarter wavelength, the open circuit switch impedance would appear as a low impedance, which could load thesignal bus line731. The source impedance Rn would be transformed into a different impedance, its value depending on the characteristic impedance of the physical interconnecting structure, as a transmission line connecting the switch to the bus. Both cases would cause a loss of signal power that is transferred to the load, increasing the insertion loss of the system and degrading performance. Further exemplary, the load impedance Zload is chosen so as to be substantially matched to the characteristic impedance Zc of the line, this condition allowing the maximum power transfer to the load.

A further advantage of shorter bus lines is reduced mutual coupling and improved signal isolation. As an example, a quarter wavelength of a 2 GHz signal propagating in a transmission medium of effective dielectric constant of 3.3 is about 20 mm. At this frequency, a physical size of bus and chip interconnect structures of a few millimeters should be adequate.

FIG. 7F illustrates a secondexemplary driver circuit790 for a signal bus line, thedrive circuit790 implementing acurrent source791 having an internal source admittance G, thesource791 operable to drivesignal bus line731 via acontrollable SPST switch783. Thesignal bus line731 is implemented in the form of a transmission line with a characteristic impedance Zc. Exemplary values for this impedance (and the resistance value of Rn) include 50 or 75 Ohms, although other impedances (lower or higher) may be employed as well.Signal bus line731 is selectively coupled to an output of several output switches, for example, output522c1 ofoutput switch520 and output724c1 fromoutput switch720.

In this embodiment, thesignal bus line731 is terminated at both ends. A signal applied from thesource791 splits in two directions as shown by dashed lines, one traveling towards the load795 (representing the load present on theoutput line391a), and the other traveling to the opposite end of the line, where the signal portion gets absorbed by thetermination load Zt797. In one embodiment, theterminal impedance Zt797 is chosen so as to be substantially equal to the characteristic impedance Zc of thesignal bus line731 to minimize signal reflections. Implementation of theload termination797 enables the implementation of different length bus lines, although the aforementioned electrical length d2 remains sensitive to impedance transformation, and may be designed as noted above. An advantage of thedriver circuit790 is that when the switch is turned off, i.e. open, the switch favorably stays in the same high-impedance state (assuming thesource791 has a high G/admittance792). The change of the impedance seen by thesignal bus line731 is small, thus the switching transients and post-switching static changes are minimized. To maximize the power transfer to the load, like in the previous case, theload impedance Zload795 should be substantially matched to the characteristic impedance Zc of the line (or alternatively, the characteristic impedance of the line designed to match the load impedance Zload795).

FIG. 8 illustrates a detailed partial view of the signal bus implemented within thetranslator301 ofFIG. 3. The view represents a portion of the schematic shown inFIG. 3, and illustrates thesignal bus380 coupled between the partialtranslational switch310aand the fulltranslational switch310b₂. Other features of the schematic are omitted to facilitate presentation and description of the illustrated features. Power and control signals (not shown in order to simplify the drawing) are routed to each of the components to activate and control the operating states of such components to perform the operations as described herein.

As shown, thetranslator301 includes a first translational switch (shown as the partialtranslational switch310aalthough in another embodiment the fulltranslational switch310b₂may be implemented as the first translational switch, as described above), a second translational switch (shown as the fulltranslational switch310b₂), and asignal bus380. The partialtranslational switch310aincludes one or more inputs (two shown,422a,b) configured to receive a respective one or more first input signals (two shown368a,b), a first plurality of outputs (three shown,422c₁-422c₃), and a second plurality of outputs (three shown,422d₁-422d₃). As noted, the firsttranslational switch310ais configured to switchably output a first frequency version of the first input signal (e.g., low L-band signal) to any of the first plurality of outputs422c₁-422c₃, and to switchably output a second frequency version of the first input signal (e.g., low L-band signal) to any of the second plurality ofoutputs422d₁-422d₃.

The secondtranslational switch310b₂is as described previously inFIG. 7A, having one ormore inputs724a,bconfigured to receive a respective one or more second input signals328a,b, a first plurality of outputs (three shown,724c₁-724c₃), and a second plurality of outputs (three shown,724d₁-724d₃). The secondtranslational switch310b₂is configured to switchably output a first frequency version of the second input signal328a,bto any of the first plurality of outputs724c₁-724c₃, and to switchably output a second frequency version of the second input signal328a,bto any of the second plurality ofoutputs724d₁-724d₃. In an alternative embodiment,translational switch310b₁may be employed as the second translational switch.

Thesignal bus380 is coupled between the first and secondtranslational switches310a,310b₂, and includes at least afirst bus line731 and asecond bus line732. Thefirst bus line731 is selectively coupled to a first one of the first plurality of outputs (shown as output422c₁) of the firsttranslational switch310a, and also to a first one of the first plurality of outputs (shown as output724c₁) of the secondtranslational switch310b₂. Thesecond bus line732 is selectively coupled between a first one of the second plurality of outputs (shown asoutput422d₁) of the firsttranslational switch310a, and to a first one of the second plurality of outputs (shown asoutput724d₁) of the secondtranslational switch310b₂. Output switches420 and720 are collectively controlled to determine which of the outputs422c₁or724c₁is to be coupled to thefirst bus line731. In the exemplary embodiment ofFIG. 8 where hollow circles indicating a switchably-coupled, open connection, and a darkened circle indicating a switchably-coupled, closed connection, output724c₁of the fulltranslational switch310b₂is coupled to thefirst bus line731, and therethrough to thefirst output line392a, andoutput724d₂of the fulltranslational switch310b₂is coupled to thesecond bus line732, and therethrough to thesecond output line391b. The foregoing arrangement is merely exemplary, and other connection arrangements may be employed in alternative embodiments.

As further illustrated, thesignal bus380 includes at least third andfourth bus lines733 and734. Thethird bus line733 is selectively coupled to a second one of the first plurality of outputs (shown as output422c₂) of the firsttranslational switch310a, and to a second one of the first plurality of outputs (shown as output724c₂) of the secondtranslational switch310b₂. Thefourth bus line734 is selectively coupled to a second one of the second plurality of outputs (shown as422d₂) of the firsttranslational switch310aand to a second one of the second plurality of outputs (shown asoutput724d₂, switched-open) of the secondtranslational switch310b₂. In this arrangement, the first andthird bus lines731,733 are each operable to support the propagation of the first frequency version (e.g., the low L-band version) of the first or second input signals368a,b, or328a,b, and the second andfourth bus lines732,734 are each operable to support the propagation of the second frequency version (e.g., the upper/high L-band version) of the first or second input signals368a,bor328a,b. Further particularly, the first andthird bus lines731,733 may be interleaved with the second andfourth bus lines732,734, thereby providing a degree of signal isolation between the two bus lines carrying the signal signals. In particular, at least one line of a different frequency is interposed between bus lines carrying signals at the same frequency.

As noted above, output switches420,425,720 and725 may be included within the respectivetranslational switches310aand310b₂, or provided as discrete components therefrom, or be included within thesignal bus380. In the exemplary embodiment ofFIG. 8 in which translational switch310 includes output switches420 and425, respectively,output switch420 includes first andsecond inputs416 and417 for receiving the first frequency version (low L-band signal “L”) of the first input signal368 (first signal portion368asupplied tofirst input416, andsecond signal portion368bsupplied to the second input417), and a plurality of outputs422c₁-422c₃. Thesecond output switch425 includes first andsecond inputs418 and419 for receiving a second frequency version (upper/high L-band signal “H”) of the first input signal368 (first signal portion368asupplied tofirst input418, andsecond signal portion368bsupplied to the second input419), and plurality ofoutputs422d₁-422d₃. In this particular embodiment, the non-translated version ofsignal368a(externally supplied low L-band signal) serves as the first frequency version ofsignal368awhich is supplied to input416, and the non-translated version ofsignal368b(externally supplied high L-band signal) serves as the second frequency version ofsignal368b.

The secondtranslational switch310b₂includes output switches720 and725, thefirst output switch720 including first andsecond inputs716 and717 for receiving a first frequency version (lower L-band signal “L”) of the second input signal328 (first signal portion328asupplied tofirst input716, andsecond signal portion328bsupplied to the second input717), and a plurality of outputs724c₁-724c₃. Thesecond output switch725 includes first andsecond inputs718 and719 for receiving the second frequency version (upper/high L-band signal “H”) of the second input signal328 (e.g.,first signal portion328asupplied tofirst input718, andsecond signal portion328bsupplied to the second input719), and the plurality ofoutputs724d₁-724d₃.

In the exemplary embodiment ofFIG. 8,signal bus380 includes bus lines731-736,bus lines731,733, and735 operable to route the first frequency version (e.g., the low L-band signal version) of either the first or second signals368 or328 to any of theoutput lines392aor393a. Similarly,bus lines732,734, and736 operate to route the second frequency version (e.g., the upper L-band signal version) of either the first or second signals368 or328 to any of theoutput lines392bor393b. In particular,bus line731 is shown coupled to output724c₁andoutput line392a, thus supplyingreceivers3 and4 with the first frequency version of the second input signal328 (either signal328aor328bas selected by switch720).Bus line732 is shown coupled tooutput724d₁andoutput line392b, thus supplyingreceivers3 and4 with the second frequency version of the second input signal328 (either signal328aor328bas selected by switch720).Bus line735 is shown coupled to output422c₃andoutput line393a, thus supplyingreceivers5 and6 with the first frequency version of the first input signal368 (either signals368aor368bas selected by switch420).Bus line736 is shown coupled tooutput724d₃andoutput line393b, thus supplyingreceivers5 and6 with the second frequency version of the first input signal368 (either signal368aor368bas selected by switch420). As noted above, the first and second versions of the input signals may be supplied to alternating bus lines, so as to improve signal isolation between lines carrying the same frequency signals. Similarly, thesignal bus380 may be made operable to supply the first and second versions of the input signals to alternating output lines to improve signal isolation.

FIG. 9 illustrates a thirdexemplary system900 for constructing a composite signal in accordance with one embodiment of the present invention. Thesystem900 includes the previously-described receivemodules220,320,340, and360, and a new frequency translation system (“translator”)901 implementing the previously-described components of thereference source370, the partial and fulltranslational switches310a,310b₁,310b₂,310b₃,optional filters250, and signalcombiners260, along with a newsignal combiner network910. Power and control signals (not shown in order to simplify the drawing) are routed to each of the components to activate and control the operating states of such components to perform the operations as described herein.

In comparison to the bus-based architectures shown inFIGS. 3,7A, and8, thetranslator901 is based on signal combination architecture. This architecture may provide benefits in particular implementations in which the signal lines can be isolated from each other. For example, thetranslator901 may be formed frommultilayer board920 in which signals are formed on different layers to improve line-to-line isolation. Other substrate materials may be used to provide similar isolation improvement.

Signal combiner network910 includes six signal combiners911-916, threesignal combiners911,913, and915 operable to receive each of the first frequency versions (e.g., the low L-band “L”) of the input signals228,328,348, and368, and threesignal combiners912,914, and916 operable to receive each of the second frequency versions (e.g. the upper/high L-band “L”) of the input signals228,328,348 and368. As shown, each of the translator output lines may be alternating arranged such that adjacent lines carry two different frequency signals.

The output of each of the six signal combiners911-916 is coupled (via optional filters250) to one of two inputs ofsignal combiners261, or262, or263. Assembly of the composite signal having first and second frequency versions of the input signals228,328,348, and368 are as described previously.

FIG. 10 illustrates a fourthexemplary system1000 for constructing a composite signal in accordance with one embodiment of the present invention. Thesystem1000 includes the previously-described receivemodules220,320,340, and360, and a new frequency translation system (“translator”)1001 implementing the previously-described components of thereference source370, and the partialtranslational switch310a, along with new full translation switches1101b₁,1101b₂, and1101b₃, anew signal bus1280, and a newinput switch matrix1120.Output lines390,optional filters250, and signalcombiners260 are illustrated outside of thetranslator1001, although in other embodiments these components may be included within the structure of thetranslator1001. Power and control signals (not shown in order to simplify the drawing) are routed to each of the components to activate and control the operating states of such components to perform the operations as described herein.

In comparison to the back-end switched architectures shown inFIGS. 3,7A, and8, thetranslator1001 is based on a front-end switched architecture. This architecture provides benefits in requiring fewer mixers within the fulltranslational switches1101b₁,1110b₂,1110b₃, resulting in a lower component count, cost, and power consumption of thetranslator1001.

Each translational switch110b₁-1110b₃operates to provide a frequency version of the signals received. The operation ofsystem1000 differs from thesystems300 and900 shown inFIGS. 3 and 9, respectively, in that insystem1000, any signal (or signal component) may be applied to any translational signal input, via theinput switch matrix1120. Control as to what signal (or signal component of a received signal) is to be processed insystem1000 is made through control ofinput switch1120, and through control of the output switches in the partialtranslational switch310a, as will be further described below. Insystems300 and900 control as to what signal (or signal component) is to be processed is made using the output switches of the translational switches.

Theinput switch matrix1120 is a 6×6 switch matrix, operable to switchably couple any of the six inputs to any one or more of the six outputs. In a particular embodiment, theinput switch1120 is operable at RF frequencies, for example in the Ku- or Ka-bands described herein. Further particularly, thereference source370,translational switches310a,1110b₁-1110b₃, and theinput switch matrix1120 may be integrated with the same package/substrate, e.g. a Si, SiGe, or GaAs IC. Further optionally, thetranslator1001 may be constructed in a system-in-package (SIP) form, in whichtranslational switches310aand1110b₁-1110b₃,switch matrix1120, andfrequency source370 are implemented as discrete circuits of dice/ICs interconnected via a routing plane on a substrate, such as a printed circuit board and assembled in a separate package.

To facilitate the understanding of thesystem1000, one ofsignals228a,boutput from the first receivemodule220 is shown as being switched to either of the inputs of fulltranslational switch1110b₁, e.g., each input oftranslational switch1110b₁receivessignal component228a. Similarly,signal component328ais shown as being applied to both of the two inputs of fulltranslational switch1110b₂, andsignal components348ais shown as being applied to both of the two inputs of fulltranslational switch1110b₃. This output signal arrangement is only exemplary, and those skilled in the art will appreciate that theinput switch matrix1120 may be controlled to provide any of its input signals to any one or more of its output ports. The structure and operation of thetranslational switches1110b₁-1110b₃is described in further detail inFIG. 11.

Further exemplary of thetranslator1001 is asignal bus1280, which couples to eachtranslational switch310aand1110b₁-1110b₃. The construction and operation of thesignal bus1280 is further described inFIG. 12, but in general thesignal bus1280 operates to selectively couple any of the H or L signals of the partialtranslational switch310aand any one of the fulltranslational switches1110b₁-1110b₃to any one of the output lines390 (hollow circles indicating a controllable or selectively-coupled connection that is presently open, and a darkened circle indicating a selectively-coupled connection that is presently closed/made).

In the exemplary arrangement ofFIG. 10, eachoutput line391a,392a, and393ais selectively coupled to receive a respective one of the low L-band signals provided by either the partialtranslational switch310aand one of the fulltranslational switches1110b, and eachoutput line391b,392b,393bis selectively coupled to receive a respective one of the high L-band signals provided by either the partial translational switch310 or one of the fulltranslational switches1110b. The process by which each of the translational switch outputs is selectively coupled to theoutput lines390 will be described inFIG. 12, but in general, the state of the output switches420 and425 within the partialtranslational switch310aand the SPST switches1113 and1114 within each of the full translational switches are collectively controlled to determine which couples its respective signal to the each of the bus lines1281-1286.

As shown inFIG. 10, the first and second versions of the input signals may be supplied to alternating bus lines, so as to improve signal isolation between lines carrying the same frequency signals. Similarly, thesignal bus1280 may be operable to supply the first and second versions of the input signals to alternatingoutput lines390 to improve signal isolation. Collectively, theoutput lines391a,b,392a,band393a,bare arranged such that each receiver (viasignal combiner261, or262, or263) is supplied with any one of a low L-band signal and any one of a high L-band signal. In this manner, each receiver can independently receive a composite signal formed by any one of the low L-band signals and any one of the high L-band signals. Of course, information included within each of the low and high L-band signals, e.g., one or more television channels, could thus be supplied to any receiver of thesystem1000, independent of the television channel(s) (i.e., the composite signal) delivered to another receiver of the system.

FIG. 11 illustrates an exemplary embodiment of thetranslational switch1110b₁shown inFIG. 10. In a specific embodiment of the invention,translational switches1110b₁,1110b₂and1110b₃are identically constructed, although this is not necessary in all instances, and thetranslational switches1110bmay differ between them as to the number of inputs, number of outputs, or both. The power and control signals (not shown in order to simplify the drawing) are routed to each of the components to activate and control the operating states of such components to perform the operations as described herein.

The fulltranslational switch1110b₁includes first andsecond inputs1122aand1122bfor receiving first and second signals (shown exemplary as thesame signal228a) anoutput port1116 for providing a first frequency version of the receivedsignal228a, andoutput port1119 for providing a second frequency version of the receivedsignal228a.

Internally within the fulltranslational switch1110b₁, the receivedsignal228ais processed. Along different branches,signal component228ais supplied to an amplifier (e.g., a low noise amplifier)1102,1103 and atuned resonator1104,1105, the resultant signals supplied tomixers1106 and1109, respectively. A first frequency version ofsignal228ais generated bymixer1106, optionally amplified byamplifier1111, and switchably coupled to theoutput1116 via aSPST switch1113. A second frequency version ofsignal228ais generated bymixer1109, optionally amplified byamplifier1112, and switchably coupled to theoutput1119 via aSPST switch1114.Mixer1106 is supplied with reference signal fromsource372, 11.25 GHz in an exemplary embodiment, andmixer1109 is supplied with reference signal fromsource376, a signal operating at 14.35 GHz in the exemplary embodiment.

FIG. 12 illustrates a partial detailed view of the signal bus implemented1280 within thetranslator1001 ofFIG. 10. The view represents a portion of the schematic shown inFIG. 10, and illustrates thesignal bus1280 coupled between the partialtranslational switch310aand the fulltranslational switch1110b₁. Other features of the schematic are omitted to facilitate presentation and description of the illustrated features. Power and control signals (not shown in order to simplify the drawing) are routed to each of the components to activate and control the operating states of such components to perform the operations as described herein.

Thetranslator1001 includes a first translational switch (shown as the partialtranslational switch310aalthough in another embodiment, one of the fulltranslational switches1110b₁-1110b₃may be implemented as the first translational switch), a second translational switch (shown as the fulltranslational switch1110b₁), and asignal bus1280. The partialtranslational switch310aincludes one or more inputs (two shown,422a,b) configured to receive a respective one or more first input signals (two shown368a,b), a first plurality of outputs (three shown,422c₁-422c₃), and a second plurality of outputs (three shown,422d₁-422d₃). The firsttranslational switch310ais configured to switchably output a first frequency version of the first input signal (e.g., low L-band signal) to any of the first plurality of outputs422c₁-422c₃, and to switchably output a second frequency version of the first input signal (e.g., low L-band signal) to any of the second plurality ofoutputs422d₁-422d₃.

The secondtranslational switch1110b₁is as described previously inFIG. 11, having one ormore inputs1122a,bconfigured to receive a respective one or more second input signals (shown assignal component228a) afirst output1116, and asecond output1119. The secondtranslational switch310b₁is configured to switchably output a first frequency version of the second input signal228 (particularly,signal portion228a) to itsoutput1116, and to switchably output a second frequency version of the second input signal228 (particularly,signal portion228a) to itssecond output1119.

Thesignal bus1280 is coupled between the first and secondtranslational switches310a,1110b₁, and includes at least afirst bus line1281 and asecond bus line1282. Thefirst bus line1281 is selectively coupled to a first one of the first plurality of outputs (shown as output422c₁) of the firsttranslational switch310a, and coupled (shown as a fixed connection) to thefirst output line391aat node a. Thefirst output1116 of the secondtranslational switch1110b₁is switchably coupled, viaSPST1113 to the first frequency version path of the secondtranslational switch1110b₁. In this arrangement, a first frequency version (e.g., a low L-band version) of either the first or second signals368 or228 may be supplied to thefirst output signal391a(the first frequency version ofsignal component228bavailable for coupling tooutput line391awhen theinput switch matrix1120 switchably couples signalcomponent228bto the inputs oftranslational switch1110b₁). Particularly, switches420 and1113 are collectively controlled to determine which of theoutputs422c₁or1116 is to be coupled to thefirst bus line731. In the exemplary embodiment ofFIG. 12 where hollow circles indicating a switchably-coupled, open connection, and a darkened circle indicating a switchably-coupled, closed connection, output522c₁of the fulltranslational switch310b₁is coupled to thefirst bus line731, and therethrough to thefirst output line391a, and switch1113 of the fulltranslational switch1110b₁is open. Alternatively or in addition,mixer1106 and any optional circuitry (amplifiers, active filters, etc.) may be deactivated to minimize power consumption.

Thesecond bus line1282 is coupled in a similar manner, thesecond bus line1282 selectively coupled to a first one of the second plurality of outputs (shown asoutput422d₁) of the firsttranslational switch310a, and coupled (shown as a fixed connection) to thesecond output line391bat node b. Thesecond output1119 of the secondtranslational switch1110b₁is switchably coupled, viaSPST1114 to the second frequency version path of the secondtranslational switch1110b₁. In this arrangement, a second frequency version (e.g., a high L-band version) of either the first or second signals368 or228 may be supplied to thesecond output signal391b(the second frequency version ofsignal component228bavailable for coupling tooutput line391bwhen theinput switch matrix1120 switchably couples signalcomponent228bto the inputs oftranslational switch1110b₁). Particularly, switches425 and1114 are collectively controlled to determine which of theoutputs422d₁or1119 is to be coupled to thesecond bus line732. In the exemplary embodiment ofFIG. 12 where hollow circles indicate a switchably-coupled, open connection, and a darkened circle indicating a switchably-coupled, closed connection,output1119 of the fulltranslational switch1110b₁is coupled to thesecond bus line732, and therethrough to thesecond output line391b, and theoutput switch425 of the fulltranslational switch1110b₁provides no connection (i.e., the aforementioned null signal/state) tooutput422d₁. The foregoing arrangement is merely exemplary, and other connection arrangements may be employed in alternative embodiments.

As further illustrated, thesignal bus1280 includes at least third andfourth bus lines1283 and1284. Thethird bus line1283 is selectively coupled to a second one of the first plurality of outputs (shown as output422c₂, switchably-coupled closed) of the firsttranslational switch310a, and to thethird output line392aat node c. Thefourth bus line1284 is selectively coupled to a second one of the second plurality of outputs (shown as422d₂, switchably-coupled closed) of the firsttranslational switch310aand to thefourth output lines392bat node d. As shown inFIG. 10, the first and second outputs of the fulltranslational switch1110b₂are decoupled from nodes c and d, as their respective SPST switches are controlled to an open state. In this arrangement, the first andthird bus lines1281,1283 are each operable to support the propagation of the first frequency version (e.g., the low L-band version) of the first or second input signals368a,b, or228a,b, and the second andfourth bus lines1282,1284 are each operable to support the propagation of the second frequency version (e.g., the upper/high L-band version) of the first or second input signals368a,bor228a,b. Further particularly, the first andthird bus lines1281,1283 may be interleaved with the second andfourth bus lines1282,1284, thereby providing a degree of signal isolation between the two bus lines carrying signals of the same frequency band. In particular, at least one line of a different frequency is interposed between bus lines carrying signals at the same frequency.

FIG. 13 illustrates a fifthexemplary system1300 for constructing a composite signal in accordance with one embodiment of the present invention. Thesystem1300 includes two frequency translation systems (translators)1301 and1302. Thefirst translator1301 is coupled to the previously-described receivemodules220,320,340, and360, and implements the previously describedreference source370 and either: (i) the set of translational switches illustrated inFIGS. 3-5 and7-8 implementing the partialtranslational switch310aand back-end switched fulltranslational switches310b₁-310b₃, or (ii) the set of translational switches illustrated inFIGS. 10-12 implementing the partialtranslational switch310aand front-end switched fulltranslational switches1110b₁-1110b₃with the input switch matrix1120 (a combination of these two sets also being implemented in an alternative embodiment). The second translator1302 is coupled to new receivemodules1320,1340, and1360, implements two modified versions of reference source370 (1370a,1370b), and either: (i) the set of translational switches illustrated inFIGS. 3-5 and7-8 implementing the back-end switched fulltranslational switches310b₁-310b₃, or (ii) the set of translational switches illustrated inFIGS. 10-12 implementing the front-end switched fulltranslational switches1110b₁-1110b₃with the input switch matrix1120 (a combination of these two sets also being implemented in an alternative embodiment).Signal combiner network910,optional filters250, and signalcombiners260 are illustrated outside of thetranslator1001, although in other embodiments portions of all of these components may be included within the structures of the twotranslators1301 and1302. While thesignal combiner network910 is shown, themultiple translator system1300 may implement a signal bus similar to that described inFIGS. 3,7A,8,10, and12. Power and control signals (not shown in order to simplify the drawing) are routed to each of the components to activate and control the operating states of such components to perform the operations as described herein.

The multi-translator system employs twotranslational switch systems1301 and1302 to process different sets of input signal frequencies. In the exemplary embodiment shown, the firsttranslational switch system1301 operates to received Ku-band signals using a first set of reference signals operating at 11.25 GHz (for low L-band translation), and 14.35 GHz (for high L-band translation). A third reference signal operable at 3.1 GHz is supplied to the partialtranslational switch310awithin the first translator.

The second translational switch system1302 employs two sets of reference signals. The first set of signals operate at 3.1 GHz (for partial translation switch operation), 10.75 GHz (for low L-band translation), and 13.85 GHz (for high L-band translation) to enable translation to the upper and lower L-bands of received signals operating within the Ku fixed service satellite (FSS-US) band of 11.7 GHz-12.2 GHz. The second set of signals operate at 3.1 GHz (for partialtranslation switch operation310a), 16.35 GHz (for low L-band translation), and 19.45 GHz (for high L-band translation) to enable translation to the upper and lower L-bands of received signals operating within the Ka-band of 17.3 GHz-17.8 GHz. WhileFIG. 13 illustrates a two translator system, the skilled person will draw from the present invention that any number of translators may be coupled in parallel, for example, 3, 4, 6, 8, 10, or more.

Blocks370,1370a,bas earlier described provide reference signals, i.e. local oscillator LO signals required by the mixers for the conversion function. As shown, thefrequency translation systems1301 and1302 each may be constructed in a system-in-package (SIP) form, in which translational switches and frequency sources of each system are implemented as discrete circuits or dice/ICs interconnected via a routing plane on a substrate, such as a printed circuit board and assembled in a separate package.

As taken from the exemplary embodiments above, a translational switch system of the present invention includes first and second translational switches, and a signal bus coupled therebetween. The first translational switch includes one or more inputs configured to receive a respective one or more first input signals, a first plurality of outputs, and a second plurality of outputs, the first translational switch configured to switchably output a first frequency version of the first input signal to any of the first plurality of outputs, and to switchably output a second frequency version of the first input signal to any of the second plurality of outputs. Particular embodiments of the first translation switch include a “partial” translational switch such as310a, exemplary embodiments of which are shown inFIGS. 3,4,6A,8-10,12 and13 illustrated and described below, and a “full” translational switch such as310b1, exemplary embodiments of which are shown inFIGS. 3,5,6B,7A,9, and13 shown above.

The second translational switch includes one or more inputs configured to receive a respective one or more second input signals, a first output (i.e., at least one first output), and a second output (i.e., at least one second output), the second translational switch configured to switchably output a first frequency version of the second input signal to the first output, and to switchably output a second frequency version of the second input signal to the second output. An exemplary embodiment of the second translational switch includes1110b₁, which implements a singlefirst output1116, and a single second output1119), further described inFIG. 11 below. Another exemplary embodiment of the second translational switch includes310b₂illustrated inFIGS. 3,6B,7A,8-10, and13. In this embodiment, each of the first and second outputs of the second translational switch are included within a group of first and second outputs.

The signal bus, coupled between the first and second translational switches, includes at least: (i) a first bus line coupled to a first one of the first plurality of outputs of the first translational switch, and to the first output of the second translational switch, and (ii) a second bus line coupled to a first one of the second plurality of outputs of the first translational switch, and to the second output of the second translational switch. In a further embodiment of the invention, the signal bus includes third and fourth signal bus lines. In one embodiment in which the second translational switch includes a single first output and a single second output, as exemplified bytranslational switch1110b₁inFIG. 11, the third bus line is coupled to a second one of the first plurality of outputs of the first translational switch, and to a first output of a third translational switch (1110b₂). Similarly, the fourth bus line is coupled to a second one of the second plurality of outputs of the first translational switch and to a second output of the third translational switch (1110b₂). In another embodiment in which the second translational switch includes a group of first outputs and a group of second outputs, as exemplified by the fulltranslational switch310b₂inFIG. 8, the aforementioned first output of the second translational switch serves as one of a plurality of first outputs, and similarly the second output operates as one of a plurality of second outputs. The third bus line is arranged coupled to a second one of the first plurality of outputs of the first translational switch, and to a second one of the first plurality of outputs of the second translational switch. The fourth bus line is coupled to a second one of the second plurality of outputs of the first translational switch and to a second one of the second plurality of outputs of the second translational switch.

As readily appreciated by those skilled in the art, the described processes may be implemented in hardware, software, firmware or a combination of these implementations as appropriate. In addition, some or all of the described processes may be implemented as computer readable instruction code resident on a computer readable medium, the instruction code operable to program a computer of other such programmable device to carry out the intended functions. The computer readable medium on which the instruction code resides may take various forms, for example, a removable disk, volatile or non-volatile memory, etc., or a carrier signal which has been impressed with a modulating signal, the modulating signal corresponding to instructions for carrying out the described operations.

The terms “a” or “an” are used to refer to one, or more than one feature described thereby. Furthermore, the term “coupled” or “connected” refers to features which are in communication with each other (electrically, mechanically, thermally, as the case may be), either directly, or via one or more intervening structures or substances. The sequence of operations and actions referred to in method flowcharts are exemplary, and the operations and actions may be conducted in a different sequence, as well as two or more of the operations and actions conducted concurrently. Reference indicia (if any) included in the claims serve to refer to one exemplary embodiment of a claimed feature, and the claimed feature is not limited to the particular embodiment referred to by the reference indicia. The scope of the claimed feature shall be that defined by the claim wording as if the reference indicia were absent therefrom. All publications, patents, and other documents referred to herein are incorporated by reference in their entirety. To the extent of any inconsistent usage between any such incorporated document and this document, usage in this document shall control.

The foregoing exemplary embodiments of the invention have been described in sufficient detail to enable one skilled in the art to practice the invention, and it is to be understood that the embodiments may be combined. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined solely by the claims appended hereto.

Claims (24)

1. A translational switch system, comprising:

a first translational switch having one or more inputs configured to receive a respective one or more first input signals, a first plurality of outputs, and a second plurality of outputs, the first translational switch configured to switchably output a first frequency version of the first input signal to any of the first plurality of outputs, and to switchably output a second frequency version of the first input signal to any of the second plurality of outputs;

a second translational switch having one or more inputs configured to receive a respective one or more second input signals, a first output, and a second output, the second translational switch configured to switchably output a first frequency version of the second input signal to the first output, and to switchably output a second frequency version of the second input signal to the second output; and

a signal bus coupled between the first and second translational switch, the signal bus having a first bus line coupled to a first one of the first plurality of outputs of the first translational switch, and to the first output of the second translational switch and a second bus line coupled to a first one of the second plurality of outputs of the first translational switch, and to the second output of the second translational switch.

2. The translational switch system ofclaim 1,

wherein the first translation switch is configured to switchably output, on any of the first plurality of outputs, either a first frequency version of any one of the first input signals, or a null output signal, the first translational switch further configured to switchably output on the second plurality of outputs either a second frequency version of any one of the first input signals, or a null output signal.

3. The translational switch system ofclaim 1,

wherein the first input signal has a plurality of signals including at least a first signal and a second signal, and

wherein the first translational switch has a first output switch having a first input for receiving the first frequency version of the first signal, a second input for receiving the first frequency version of the second signal, and a plurality of outputs and a second output switch having a first input for receiving the second frequency version of the first signal, a second input for receiving the second frequency version of the second signal, and a plurality of outputs.

4. The translational switch system ofclaim 3, wherein at least one of the first or second output switches includes an AGC block coupled to a respective signal bus line, each AGC block operable to control the level of the signal supplied to said respective bus lines.

5. The translation switch system ofclaim 1, wherein the first translational switch includes an AGC circuit operable to receive and perform automatic gain control on at least one of the first input signals.

6. The translation switch system ofclaim 5 further comprising a variable attenuator coupled to, and located in the signal path ahead of the AGC circuit, the variable attenuator controllable by the AGC circuit to set the input signal level of the one or more first input signals supplied to the first translational switch.

7. The translation switch system ofclaim 1, wherein the first translational switch includes an AGC circuit operable to receive and perform automatic gain control on at least one of the first or second frequency versions of the first input signals.

8. The translational switch system ofclaim 1, wherein the electrical length of each of the first and second signal bus lines is less than one quarter wavelength of the highest frequency signal propagated there along.

9. The translational switch system ofclaim 8, wherein each of the first and second signal bus lines are terminated in a high impedance.

10. The translational switch system ofclaim 1,

wherein the electrical length of the connection between the first signal bus line and the first translational switch and between the first signal bus line and the second translational switch is less than one quarter wavelength of the highest frequency signal propagated there along, and

wherein the electrical length of the connection between the second signal bus line and the first translational switch and between the second signal bus line and the second translational switch is less than one quarter wavelength of the highest frequency signal propagated there along.

11. The translational switch system ofclaim 9,

wherein the first signal bus line exhibits a characteristic impedance, and wherein the first signal bus line is terminated by a load having an impedance which substantially matches the characteristic impedance of the first signal bus line, and

wherein the second signal bus line exhibits a characteristic impedance, and wherein the second signal bus line is terminated by a load having an impedance which substantially matches the characteristic impedance of the second signal bus line.

12. The translational switch system ofclaim 1, wherein in the second translational switch, the first output is included within a first plurality of outputs, and the second output is included within a second plurality of outputs, the second translational switch configured to switchably output a first frequency version of the second input signal to any of the first plurality of outputs, and to switchably output a second frequency version of the second input signal to any of the second plurality of outputs.

13. The translational switch system ofclaim 12, wherein the signal bus further comprises:

a third bus line coupled to a second one of the first plurality of outputs of the first translational switch, and to a second one of the first plurality of outputs of the second translational switch; and

a fourth bus line coupled to a second one of the second plurality of outputs of the first translational switch and to a second one of the second plurality of outputs of the second translational switch.

14. The translational switch system ofclaim 13,

wherein the first and third bus lines are each operable to support the propagation of the first frequency version of the first or second input signals there along;

wherein the second and fourth bus lines are each operable to support the propagation of the second frequency version of the first or second input signals there along; and

wherein the first and third bus lines are interleaved with the second and fourth bus lines.

15. The translational switch system ofclaim 12, wherein the second translational switch is configured to switchably output on the first plurality of outputs either a first frequency version of any of the second input signals, or a null output signal, the second translational switch further configured to switchably output on the second plurality of outputs either a second frequency version of any one of the second input signals, or a null output signal.

16. The translational switch system ofclaim 12,

wherein the second input signal comprises a plurality of signals including at least a first signal and a second signal, and

wherein the second translational switch has a first output switch having a first input for receiving the first frequency version of the first signal, a second input for receiving the first frequency version of the second signal, and a plurality of outputs; and a second output switch, the second output switch having a first input for receiving the second frequency version of the first signal, a second input for receiving the second frequency version of the second signal, and a plurality of outputs.

17. The translational switch system ofclaim 12, wherein each of the first and second output switches of each of the first and second translational switches comprises a discrete circuit.

18. The translation switch system ofclaim 12, wherein the second translational switch includes an AGC circuit coupled to receive and perform automatic gain control on at least one of the second input signals.

19. The translation switch system ofclaim 12, wherein the second translational switch includes an AGC circuit coupled to receive and perform automatic gain control on at least one of the first or second frequency versions of the second input signals.

20. The translational switch system ofclaim 1, further comprising a third translational switch having one or more inputs configured to receive a respective one or more third input signals, a first output, and a second output, the third translational switch configured to switchably output a first frequency version of the third input signal to the first output, and to switchably output a second frequency version of the third input signal to the second output.

21. The translational switch system ofclaim 20, wherein the signal bus further comprises:

a third bus line coupled to a second one of the first plurality of outputs of the first translational switch, and to the first output of the third translational switch; and

a fourth bus line coupled to a second one of the second plurality of outputs of the first translational switch and to the second output of the third translational switch.

22. The translational switch system ofclaim 21,

wherein the first and third bus lines are each operable to support the propagation of the first frequency version of the first or second input signals there along;

wherein the second and fourth bus lines are each operable to support the propagation of the second frequency version of the first or second input signals there along; and

wherein the first and third bus lines are interleaved with the second and fourth bus lines.

23. A system operable to construct a composite signal, the system comprising:

a translational switching system as claimed inclaim 1; and

a signal combiner having a first input coupled to the first signal bus line, a second input coupled to the second bus line, and an output for providing a composite output signal.

24. A system operable to construct a composite signal, the system comprising:

a first receive module for coupling one or more first input signals to the first translational switch;

a second receive module for coupling one or more second input signal to the first translational switch;

a translational switching system as claimed inclaim 1;

a first filter having an input coupled to the first bus line, and an output;

a second filter having an input coupled to the second bus line, and an output; and

a signal combiner having a first input coupled to the first filter output, a second input coupled to the second filter output, and an output for providing a composite output signal.

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