US7902679B2 - Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump - Google Patents

Abstract

A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

Description

RELATED PATENT APPLICATION

This application is a Continuation application of Ser. No. 09/837,007, filed on Apr. 18, 2001, now pending, which is a Continuation-in-part of Ser. No. 09/798,654, filed on Mar. 5, 2001, now U.S. Pat. No. 6,818,545.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and package for packaging semiconductor devices.

(2) Description of the Prior Art

Semiconductor device performance improvements are largely achieved by reducing device dimensions, a development that has at the same time resulted in considerable increases in device density and device complexity. These developments have resulted in placing increasing demands on the methods and techniques that are used to access the devices, also referred to as Input/Output (I/O) capabilities of the device. This has led to new methods of packaging semiconductor devices whereby structures such as Ball Grid Array (BGA) devices and Column Grid Array (CGA) devices have been developed. A Ball Grid Array (BGA) is an array of solder balls placed on a chip carrier. The balls contact a printed circuit board in an array configuration where, after reheat, the balls connect the chip to the printed circuit board. BGA's are known with 40, 50 and 60 mil spacings. Due to the increased device miniaturization, the impact that device interconnects have on device performance and device cost has also become a larger factor in package development. Device interconnects, due to their increase in length in order to package complex devices and connect these devices to surrounding circuitry, tend to have an increasingly negative impact on the package performance. For longer and more robust metal interconnects, the parasitic capacitance and resistance of the metal interconnection increase, which degrades the chip performance significantly. Of particular concern in this respect is the voltage drop along power and ground buses and the RC delay that is introduced in the critical signal paths.

One of the approaches that has been taken to solve these packaging problems is to develop low resistance metals (such as copper) for the interconnect wires, while low dielectric constant materials are being used in between signal lines. Another approach to solve problems of I/O capability has been to design chips and chip packaging techniques that offer dependable methods of increased interconnecting of chips at a reasonable manufacturing cost.

One of the more recent developments that is aimed at increasing the Input-Output (I/O) capabilities of semiconductor device packages is the development of Flip Chip Packages. Flip-chip technology fabricates bumps (typically Pb/Sn solders) on aluminum pads on a semiconductor device. The bumps are interconnected directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package medium through the shortest paths. These technologies can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger, and to more sophisticated substrates that accommodate several chips to form larger functional units.

In general, Chip-On-Board (COB) techniques are used to attach semiconductor die to a printed circuit board; these techniques include the technical disciplines of flip chip attachment, wirebonding, and tape automated bonding (TAB). Flip chip attachment consists of attaching a flip chip to a printed circuit board or to another substrate. A flip chip is a semiconductor chip that has a pattern or arrays of terminals that are spaced around an active surface area of the flip chip, allowing for face down mounting of the flip chip to a substrate.

Generally, the flip chip active surface has one of the following electrical connectors: BGA (wherein an array of minute solder balls is created on the surface of the flip chip that attaches to the substrate); Slightly Larger than Integrated Circuit Carrier (SLICC) (which is similar to the BGA but has a smaller solder ball pitch and diameter than the BGA); a Pin Grid Array (PGA) (wherein an array of small pins extends substantially perpendicularly from the attachment surface of a flip chip, such that the pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto). With the BGA or SLICC, the solder or other conductive ball arrangement on the flip chip must be a mirror image of the connecting bond pads on the printed circuit board so that precise connection can be made.

In creating semiconductor devices, the technology of interconnecting devices and device features is a continuing challenge in the era of sub-micron devices. Bond pads and solder bumps are frequently used for this purpose, whereby continuous effort is dedicated to creating bond pads and solder bumps that are simple, reliable and inexpensive.

Bond pads are generally used to wire device elements and to provide exposed contact regions of the die. These contact regions are suitable for wiring the die to components that are external to the die. An example is where a bond wire is attached to a bond pad of a semiconductor die at one end and to a portion of a Printed Circuit Board at the other end of the wire. The art is constantly striving to achieve improvements in the creation of bond pads that simplify the manufacturing process while enhancing bond pad reliability.

Materials that are typically used for bond pads include metallic materials, such as tungsten and aluminum, while heavily doped polysilicon can also be used for contacting material. The bond pad is formed on the top surface of the semiconductor device whereby the electrically conducting material is frequently embedded in an insulating layer of dielectric. In using polysilicon as the bond pad material, polysilicon can be doped with an n-type dopant for contacting N-regions while it can be doped with p-type dopant for contacting P-regions. This approach of doping avoids inter-diffusion of the dopants and dopant migration. It is clear that low contact resistance for the bond pad area is required while concerns of avoidance of moisture or chemical solvent absorption, thin film adhesion characteristics, delamination and cracking play an important part in the creation of bond pads.

The conventional processing sequence that is used to create an aluminum bond pad starts with a semiconductor surface, typically the surface of a silicon single crystalline substrate. A layer of Intra Metal Dielectric (IMD) is deposited over the surface, a layer of metal, typically aluminum, is deposited over the surface of the layer of IMD. The layer of metal is patterned and etched typically using a layer of photoresist and conventional methods of photolithography and etching. After a bond pad has been created in this manner, a layer of passivation is deposited over the layer of IMD. An opening that aligns with the bond pad is created in the layer of passivation, again using methods of photolithography and etching.

A conventional method that is used to create a solder bump over a contact pad is next highlighted.FIGS. 1 through 4 show an example of one of the methods that is used to create an interconnect bump. Asemiconductor surface10 has been provided with ametal contact pad14; thesemiconductor surface10 is protected with alayer12 of passivation. Anopening19 has been created in thelayer12 of passivation; the surface of themetal contact pad14 is exposed through thisopening19. Next, inFIG. 2, adielectric layer16 is deposited over the surface of thelayer12 of passivation. Thelayer16 of dielectric is patterned and etched, creating anopening21 in thelayer16 of dielectric that aligns with themetal pad14 and that partially exposes the surface of themetal pad14. Alayer18 of metal, typically using Under-Bump-Metallurgy (UBM), is created over thelayer16 of dielectric;layer18 of metal is in contact with the surface of themetal pad14 inside opening21. The region oflayer18 of metal that is above themetal pad14 will, at a later point in the processing, form a pedestal over which the interconnect bump will be formed. This pedestal can be further extended in a vertical direction by the deposition and patterning of one or more additional layers that may contain a photoresist or a dielectric material; these additional layers are not shown inFIG. 2. These layers essentially have the shape oflayer16 and are removed during one of the final processing steps that is applied for the formation of the interconnect bump.

A layer of photoresist (not shown) is deposited, patterned and etched, creating an opening that aligns with thecontact pad14. Alayer20 of metal, such as copper or nickel, shown inFIG. 3, that forms an integral part of the pedestal of the to be created interconnect bump, is next electroplated in the opening created in the layer of photoresist and on the surface of thelayer18 of metal, whereby thelayer18 serves as the lower electrode during the plating process.Layer20 in prior art applications has a thickness of between about 1 and 10 μm with a typical value of about 5 μm. Thefinal layer22 of solder is electroplated on the surface oflayer20. The patterned layer of photoresist is then removed.

Thelayer18 of metal is next etched, as inFIG. 4, leaving in place only the pedestal for the interconnect bump. During this etch process the depositedlayers20 and22 serve as a mask. If, as indicated above, additional layers of dielectric or photoresist have been deposited for the further shaping ofpedestal18 inFIG. 2, these layers are also removed at this time.

A solder paste or flux (not shown) is now applied to thelayer22 of solder, and thesolder22 is melted in a reflow surface typically under a nitrogen atmosphere, creating the spherically shapedinterconnect bump22 that is shown inFIG. 4.

In addition to the above indicated additional layers of dielectric or photoresist that can be used to further shape the pedestal of the interconnect bump, many of the applications that are aimed at creating interconnect bumps make use of layers of metal that serve as barrier layers or that have other specific purposes, such as the improvement of adhesion of the various overlying layers or the prevention of diffusion of materials between adjacent layers. These layers collectively formlayer18 ofFIG. 4 and have, as is clear from the above, an effect on the shape of the completed bump and are therefore frequently referred to as Ball Limiting Metal (BLM) layer. Frequently used BLM layers are successive and overlying layers of chrome, copper and gold, whereby the chrome is used to enhance adhesion with an underlying aluminum contact pad, the copper layer serves to prevent diffusion of solder materials into underlying layers, while the gold layer serves to prevent oxidation of the surface of the copper layer. The BLM layer islayer18 ofFIGS. 2 through 4.

Increased device density brings with it increased closeness of components and elements that are part of the created semiconductor devices. This increased closeness is expressed as a reduction in the spacing or “pitch” between elements of a semiconductor device. State-of-the-art technology uses solder bumps having a pitch of about 200 μm, which imposes a limitation on further increasing device density. The limitation in further reducing the pitch of solder bumps is imposed by concerns of reliability, which impose a relatively large ball size for the solder bump. This relatively large solder ball restricts further reducing the solder ball pitch.

In the majority of applications, solder bumps are used as interconnections between I/O bond pads and a substrate or printed circuit board. A large solder ball brings with it high standoff since a solder ball with high standoff has better thermal performance (CTE mismatching is easier to avoid resulting in reduced thermal stress on the solder balls). Large solder balls are therefore required in order to maintain interconnect reliability. Low-alpha solder is applied to avoid soft error (electrical or functional errors) from occurring, thereby eliminating the potential for inadvertent memory discharge and incorrect setting of the voltage (1 or 0).

U.S. Pat. No. 6,169,329 (Farnworth et al.) shows standardized die to substrate bonding locations (Ball grid or other array).

U.S. Pat. No. 5,741,726 (Barber) shows an assembly with minimized bond finger connections.

U.S. Pat. No. 5,744,843 (Efland et al.), U.S. Pat. No. 5,172,471 (Huang), U.S. Pat. No. 6,060,683 (Estrade), U.S. Pat. No. 5,643,830 (Rostoker et al.), and U.S. Pat. No. 6,160,715 (Degani et al.) are related patents.

The invention addresses concerns of creating a BGA type package whereby the pitch of the solder ball or solder bump of the device interconnect is in the range of 200 μm or less. The conventional, state-of-the-art solder process runs into limitations for such a fine interconnect pad pitch, the invention provides a method and a package for attaching devices having very small ball pitch to an interconnect medium such as a Printed Circuit Board.

SUMMARY OF THE INVENTION

A principal objective of the invention is to provide a method of creating a fine-pitch solder bump.

Another objective of the invention is to provide a method of creating smaller solder bumps, further allowing for the creation of fine-pitched solder bumps.

Another objective of the invention is to provide a cost-effective method to create a fine-pitch solder bump of high reliability, due to the increased height of the solder bump. This objective is based on the belief that solder bump reliability improves proportionally to the square of the distance between the solder ball and the underlying substrate.

Another objective of the invention is to provide a cost-effective way of creating a solder bump. This cost-effective way is realized by using standard solder material and therewith eliminating the need for expensive “low-α solder”.

Another objective of the invention is to provide a cost-effective method of creating a fine-pitch solder bump by reducing the alpha-effect on memory products.

Another objective of the invention is to provide a method of creating solder bumps which allows an easy method of cleaning flux after the process of creating the solder bump has been completed.

Another objective of the invention is to provide a method of creating solder bumps which allows easy application of underfill.

Another objective of the invention is to provide a method for applying fine pitch solder bumps directly to the I/O pads of a semiconductor device, without a redistribution interface, and bonding the semiconductor device directly to a Ball Grid Array substrate using the flip-chip bonding approach.

Another objective of the invention is to provide a method for shortening the interconnection between a semiconductor device and the substrate on which the device is mounted, thus improving the electrical performance of the device.

Yet another objective of the invention is to eliminate conventional methods of re-distribution of device I/O interconnect, thereby making packaging of the device more cost-effective and eliminating performance degradation.

A still further objective of the invention is to improve chip accessibility during testing of the device, thus eliminating the need for special test fixtures.

A still further objective of the invention is to improve performance and device reliability of BGA packages that are used for the mounting of semiconductor devices having small-pitch I/O interconnect bumps.

A still further objective of the invention is to perform Chip Scale Packaging (CSP) without re-distribution, including for various pad designs such as peripheral or central pad designs.

A still further objective of the invention is to provide a method of mounting small-pitch semiconductor devices in such a manner that flux removal and the dispensing of device encapsulants is improved.

In accordance with the objectives of the invention a new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 through 4 show a prior art method of creating a solder bump overlying a point of electrical contact, as follows:

FIG. 1 shows a cross section of a semiconductor surface on the surface of which a contact pad has been created; the semiconductor surface is covered with a patterned layer of passivation.

FIG. 2 shows the cross section ofFIG. 1 after a patterned layer of dielectric and a layer of metal have been created on the semiconductor surface.

FIG. 3 shows a cross section ofFIG. 2 after a layer of bump metal and solder compound have been selectively deposited.

FIG. 4 show a cross section after excessive layers have been removed from the semiconductor surface and, after the solder has been reflowed, forming the interconnect bump.

FIG. 5 shows a cross section of the BGA package of the invention; the semiconductor device is encapsulated in a molding compound.

FIG. 6 shows a cross section of the BGA package of the invention; underfill is provided to the semiconductor device.

FIGS. 7 through 16 address the invention, as follows:

FIG. 7 shows a cross section of a semiconductor surface, a layer of dielectric has been deposited, metal pads have been created, a layer of passivation has been deposited and patterned, and a layer of barrier material has been deposited.

FIG. 8 shows a cross section after a patterned layer of photoresist has been created over the structure ofFIG. 7.

FIG. 9 shows a cross section after pillar metal has been created aligned with the metal pads and under bump metal has been deposited over the surface of the pillar metal.

FIG. 10 shows a cross section after solder metal has been plated over the under bump metal.

FIG. 11 shows a cross section after the patterned layer of photoresist has been removed from the surface.

FIG. 12 shows a cross section after the diameter of the pillar metal has been reduced.

FIG. 13 shows a cross section after the barrier layer has been etched using isotropic etching, creating a first profile.

FIG. 14 shows a cross section after the barrier layer has been etched using anisotropic etching or RIE, creating a second profile.

FIG. 15 shows a cross-section of a completed first solder bump of the present invention.

FIG. 16 shows a cross-section of a completed second solder bump of the present invention.

FIG. 17 shows a cross section of the BGA package of the invention; the semiconductor device is encapsulated in a molding compound.

FIG. 18 shows a cross section of the BGA package of the invention; underfill is provided to the semiconductor device.

FIG. 19 shows a top view of an array type I/O pad configuration of a semiconductor device.

FIG. 20 shows a top view of a peripheral type I/O pad configuration of a semiconductor device.

FIG. 21 shows a top view of a center type I/O pad configuration of a semiconductor device.

FIG. 22 shows a top view of a center type I/O pad configuration of a semiconductor device; dummy solder bumps have been provided in support of the semiconductor device.

FIG. 23 shows a top view of the substrate with exposed I/O contact pads; this exposure is accomplished by not depositing the solder mask in close proximity to the contact pads of the semiconductor device.

FIG. 24 shows a cross section of the substrate ofFIG. 23.

FIG. 25 shows a top view of a prior art substrate with exposed I/O contact pads; the solder mask is in close proximity to the contact pads of the semiconductor device.

FIG. 26 shows a cross section of the substrate ofFIG. 25.

FIGS. 27athrough27fshow examples of applications of the invention.

FIGS. 28aand28bdemonstrate how the invention leads to the ability to reduce the pitch between I/O pads.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The above stated objective of improving chip accessibility during testing of the device, thus eliminating the need for special test fixtures, can further be highlighted as follows. The disclosed method of the invention, using Chip Scale Packaging (CSP), can control the cost of testing CSP devices by keeping the same body size of the chip and by using the same size substrate. For conventional CSP packages, the chip may have different body sizes, which imposes the requirement of different size test fixtures. With the continued reduction of the size of semiconductor devices, additional and varying device sizes are expected to be used. This would result in ever increasing costs for back-end testing of the devices in a production environment. The invention provides a method where these additional back-end testing costs can be avoided.

Referring now toFIG. 5, there is shown a cross section of a typical flip chip package with the semiconductor device being encapsulated in a molding compound. The Integrated Circuit (IC)device10 enters the process as a separate unit with the contact points (balls16) attached to the bottom of thechip10. TheIC10 is placed on the surface of aBGA substrate12, an (optional)interconnect substrate14 has been provided for additional routing of the electrical network to whichdevice10 is attached. Theballs18 that are connected to the lower surface of thesubstrate12 make contact with surrounding circuitry (not shown). The paths of electrical interconnect ofdevice10 as shown in cross section inFIG. 5 are as follows: contact bumps (points of I/O interconnect, not shown inFIG. 5) are provided on the surface of device that facessubstrate12 andcontact balls16 are connected to these contact bumps. Contactballs16 interface with points of contact (contact pads) provided in the surface of the (optional)interconnect network14 or, for applications where theinterconnect interface14 is not provided, with points of contact (contact pads) provided in the surface of the Ball Grid Array (BGA)substrate12.BGA substrate12 may further have been provided with one or more layers of interconnect metal, all of the interfaces (theinterconnect substrate12 and the optional redistribution lines provided in BGA substrate12) result in interconnectingballs16 withballs18.Balls18 are the contact points that connect the package that is shown in cross section inFIG. 5 to surrounding circuitry.

Whereas the cross section that is shown inFIG. 5 showscontact balls16 for the establishment of contacts betweendevice10 and theunderlying substrate12, some prior art applications still used wire bond connections (not shown inFIG. 5), this in order to achieve optimum electrical performance of the device package.

Further shown in the cross section ofFIG. 5 islayer19, which may be provided over the surface ofsemiconductor device10 facing thesubstrate12. This re-distribution layer provides interconnect lines over the surface ofdevice10 and is required in prior art applications if solder bumps are required on current pad layout for wire bonding purposes. The main purpose of the redistribution layer is to enlarge the pitch of solder bump interconnects if the bond pads are originally designed for wire bonding applications. It will be clear from later explanations that the invention removes the need for the redistribution layer.

FIG. 6 shows a cross section of a conventional BGA package whereby thesemiconductor device10 is provided withunderfill22, no molding compound (20,FIG. 5) has been provided in the package that is shown in cross section inFIG. 6. All the other statements that relate to the electrical interconnection of thedevice10 ofFIG. 6 are identical to the statements that have been made in the description provided for the package ofFIG. 5. It should be noted inFIG. 6 that the sides of theunderfill22 are sloping such that the physical contact between theunderfill22 and thesubstrate12 is extended beyond the dimensions of the bottom surface of thechip10. This is a normal phenomenon with liquid underfill, which enhances the mechanical strength between thesubstrate12 and theIC chip10.

Referring now toFIG. 15, there is shown a cross section of a first solder bump that has been created in accordance with the above referenced related application. The elements that are shown inFIG. 15 that form part of the solder bump of the related application are the following:

• • 10, a semiconductor surface such as the surface of a substrate
  • 30, a layer of dielectric that has been deposited over thesemiconductor surface10
  • 32, contact pads that have been created on the surface of thelayer30 of dielectric
  • 34, a patterned layer of passivation that has been deposited over the surface of thelayer30 of dielectric; openings have been created in thelayer34 of passivation, partially exposing the surface ofcontact pads32
  • 36, an isotropically etched layer of barrier metal; this layer of barrier metal has been isotropically etched; that is, the barrier metal has been completely removed from the surface of thelayer34 of passivation except where the barrier metal is covered by the overlying pillar metal (38) of the solder bump
  • 38, the pillar metal of the solder bump
  • 40, a layer of under bump metal created overlying thepillar metal38 of the solder bump, wherein the distance between an edge of the under bump metal layer and an edge of the metal pillar of the solder bump is greater than 0.2 microns
  • 42, the solder metal.

The cross section that is shown inFIG. 16 is similar to the cross section ofFIG. 15 with the exception oflayer35, which is an anisotropically etched layer of barrier metal (etched after thesolder bump42 has been created) which, due to the nature of the anisotropic etch, protrudes from thepillar metal38 as shown in the cross section ofFIG. 16.

The cross sections that are shown inFIGS. 15 and 16 and that have been extracted from the above referenced related application have been shown in order to highlight that the referenced application provides of method of creating:

a fine-pitch solder bump

smaller solder bumps

a fine-pitch solder bump of high reliability due to the increased height of the solder bump

a cost-effective solder bump by using standard solder material and eliminating the need for expensive “low-α solder”

a solder bump that allows easy cleaning of flux after the process of flip chip assembly and before the process of underfill and encapsulation

a solder bump which allows easy application of underfill.

FIGS. 7 through 16 provide details of the process of the invention which leads to the solder bumps that have been shown in cross section inFIGS. 5 and 6.

FIG. 7 shows a cross section ofsubstrate10 on the surface, wherein he following elements are highlighted:

• • 10, a silicon substrate over the surface of whichmetal contact pads32 have been created
  • 30, a layer of dielectric that has been deposited over the surface ofsubstrate10
  • 32, the metal contact pads, typically comprising aluminum, created over the surface of thelayer30 of dielectric
  • 34, a layer of passivation that has been deposited over the surface of thelayer30 of dielectric. Openings have been created in thelayer34 of passivation that align with themetal contact pads32, partially exposing the surface of thecontact pads32
  • 36, a layer of barrier metal that has been created over the surface oflayer34 of passivation, including the openings that have been created in thelayer34 of passivation, contacting theunderlying contact pads32.

As dielectric material forlayer30 can be used any of the typically applied dielectrics such as silicon dioxide (doped or undoped), silicon oxynitride, parylene or polyimide, spin-on-glass, plasma oxide or LPCVD oxide. The material that is used for the deposition oflayer30 of dielectric of the invention is not limited to the materials indicated above but can include any of the commonly used dielectrics in the art.

The creation ofmetal contact pads32 can use conventional methods of metal rf sputtering at a temperature between about 100 and 400 degrees C. and a pressure between about 1 and 100 mTorr using as source, for instance, aluminum-copper material (for the creation of aluminum contact pads) at a flow rate of between about 10 and 400 sccm to a thickness between about 4000 and 11000 Angstroms. After a layer of metal has been deposited, the layer must be patterned and etched to create thealuminum contact pads32. This patterning and etching uses conventional methods of photolithography and patterning and etching. A deposited layer of AICu can be etched using Cl₂/Ar as an etchant at a temperature between 50 and 200 degrees C., an etchant flow rate of about 20 sccm for the Cl₂and 1000 sccm for the Ar, a pressure between about 50 mTorr and 10 Torr, a time of the etch between 30 and 200 seconds.

In a typical application insulating layers, such as silicon oxide and oxygen-containing polymers, are deposited using Chemical Vapor Deposition (CVD) technique over the surface of various layers of conducting lines in a semiconductor device or substrate to separate the conductive interconnect lines from each other. The insulating layers can also be deposited over patterned layers of interconnecting lines; electrical contact between successive layers of interconnecting lines is established with metal vias created in the insulating layers. Electrical contact to the chip is typically established by means of bonding pads or contact pads that form electrical interfaces with patterned levels of interconnecting metal lines. Signal lines and power/ground lines can be connected to the bonding pads or contact pads. After the bonding pads or contact pads have been created on the surfaces of the chip, the bonding pads or contact pads are passivated and electrically insulated by the deposition of a passivation layer over the surface of the bonding pads. A passivation layer can contain silicon oxide/silicon nitride (SiO₂/Si₃N₄) deposited by CVD. The passivation layer is patterned and etched to create openings in the passivation layer for the bonding pads or contact pads after which a second and relatively thick passivation layer can be deposited for further insulation and protection of the surface of the chips from moisture and other contaminants and from mechanical damage during assembling of the chips.

Various materials have found application in the creation of passivation layers. The passivation layer can contain silicon oxide/silicon nitride (SiO₂/Si₃N₄) deposited by CVD, or a passivation layer can be a layer of photosensitive polyimide or can comprise titanium nitride. Another material often used for a passivation layer is phosphorous doped silicon dioxide that is typically deposited over a final layer of aluminum interconnect using a Low Temperature CVD process. In recent years, photosensitive polyimide has frequently been used for the creation of passivation layers. Conventional polyimides have a number of attractive characteristics for their application in a semiconductor device structure which have been highlighted above. Photosensitive polyimides have these same characteristics but can, in addition, be patterned like a photoresist mask and can, after patterning and etching, remain on the surface on which it has been deposited to serve as a passivation layer. Typically and to improve surface adhesion and tension reduction, a precursor layer is first deposited by, for example, conventional photoresist spin coating. The precursor is, after a low temperature pre-bake, exposed using, for example, a step and repeat projection aligner and Ultra Violet (UV) light as a light source. The portions of the precursor that have been exposed in this manner are cross-linked, thereby leaving unexposed regions (that are not cross-linked) over the bonding pads. During subsequent development, the unexposed polyimide precursor layer (over the bonding pads) is dissolved, thereby providing openings over the bonding pads. A final step of thermal curing leaves a permanent high quality passivation layer of polyimide over the substrate.

The preferred material of the invention for the deposition oflayer34 of passivation is Plasma Enhanced silicon nitride (PE Si₃N₄), deposited using PECVD technology at a temperature between about 350 and 450 degrees C. with a pressure of between about 2.0 and 2.8 Torr for the duration between about 8 and 12 seconds.Layer32 of PE Si₃N₄can be deposited to a thickness between about 200 and 800 Angstroms.

Layer34 of PE Si₃N₄is next patterned and etched to create openings in thelayer34 that overlay and align with theunderlying contact pads32.

The etching oflayer34 of passivation can use Ar/CF₄as an etchant at a temperature of between about 120 and 160 degrees C. and a pressure of between about 0.30 and 0.40 Torr for a time of between about 33 and 39 seconds using a dry etch process.

The etching oflayer34 of passivation can also use He/NF₃as an etchant at a temperature of between about 80 and 100 degrees C. and a pressure of between about 1.20 and 1.30 Torr for a time of between about 20 and 30 seconds using a dry etch process.

Barrier layers, such aslayer36, are typically used to prevent diffusion of an interconnect metal into surrounding layers of dielectric and silicon. Some of the considerations that apply in selecting a material for the barrier layer become apparent by using copper for interconnect metal as an example. Although copper has a relatively low cost and low resistivity, it has a relatively large diffusion coefficient into silicon dioxide and silicon and is therefore not typically used as an interconnect metal. Copper from an interconnect may diffuse into the silicon dioxide layer causing the dielectric to be conductive and decreasing the dielectric strength of the silicon dioxide layer. Copper interconnects should be encapsulated by at least one diffusion barrier to prevent diffusion into the silicon dioxide layer. Silicon nitride is a diffusion barrier to copper, but the prior art teaches that the interconnects should not lie on a silicon nitride layer because it has a high dielectric constant compared with silicon dioxide. The high dielectric constant causes a desired increase in capacitance between the interconnect and the substrate.

A typical diffusion barrier layer may contain silicon nitride, phosphosilicate glass (PSG), silicon oxynitride, aluminum, aluminum oxide (Al_xO_y), tantalum, Ti/TiN or Ti/W, nionbium, or molybdenum and is more preferably formed from TiN. The barrier layer can also be used to improve the adhesion of the subsequent overlying tungsten layer.

A barrier layer is preferably between about 500 and 2000 Angstroms thick and more preferably about 300 Angstroms thick and can be deposited using rf sputtering.

After the creation ofbarrier layer36, a seed layer (not shown inFIG. 7) can be blanket deposited over the surface of the wafer. For a seed layer that is blanket deposited over the surface of the wafer any of the conventional metallic seed materials can be used. The metallic seed layer can be deposited using a sputter chamber or an Ion Metal Plasma (IMP) chamber at a temperature of between about 0 and 300 degrees C. and a pressure of between about 1 and 100 mTorr, using (for instance) copper or a copper alloy as the source (as highlighted above) at a flow rate of between about 10 and 400 sccm and using argon as an ambient gas.

FIG. 8 shows a cross section of the substrate after alayer37 of photoresist has been deposited over the surface of thebarrier layer36. Thelayer37 of photoresist has been patterned and etched, creatingopenings31 in thelayer37 of photoresist.Openings31 partially expose the surface of thebarrier layer36.Layer37 of photoresist is typically applied to a thickness of between about 100 and 200 μm but more preferably to a thickness of about 150 μm.

Layer37 of photoresist is typically applied to a thickness of between about 100 and 200 μm but more preferably to a thickness of about 150 μm. The methods used for the deposition and development of thelayer37 of photoresist uses conventional methods of photolithography. Photolithography is a common approach wherein patterned layers are formed by spinning on a layer of photoresist, projecting light through a photomask with the desired pattern onto the photoresist to expose the photoresist to the pattern, developing the photoresist, washing off the undeveloped photoresist, and plasma etching to clean out the areas where the photoresist has been washed away. The exposed resist may be rendered soluble (positive working) and washed away, or insoluble (negative working) and form the pattern.

The depositedlayer37 of photoresist can, prior to patterning and etching, be cured or pre-baked further hardening the surface of thelayer37 of photoresist.

Layer37 of photoresist can be etched by applying O₂plasma and then wet stripping by using H₂SO₄, H₂O₂and NH₄OH solution. Sulfuric acid (H₂SO₄) and mixtures of H₂SO₄with other oxidizing agents such as hydrogen peroxide (H₂O₂) are widely used in stripping photoresist after the photoresist has been stripped by other means. Wafers to be stripped can be immersed in the mixture at a temperature between about 100 degrees C. and about 150 degrees C. for 5 to 10 minutes and then subjected to a thorough cleaning with deionized water and dried by dry nitrogen. Inorganic resist strippers, such as the sulfuric acid mixtures, are very effective in the residual free removal of highly postbaked resist. They are more effective than organic strippers and the longer the immersion time, the cleaner and more residue free wafer surface can be obtained.

Thephotoresist layer37 can also be partially removed using plasma oxygen ashing and careful wet clean. The oxygen plasma ashing is heating the photoresist in a highly oxidized environment, such as an oxygen plasma, thereby converting the photoresist to an easily removed ash. The oxygen plasma ashing can be followed by a native oxide dip for 90 seconds in a 200:1 diluted solution of hydrofluoric acid.

FIG. 9 shows a cross section of thesubstrate10 after alayer38 of pillar metal has been deposited (electroplated) over the surface of thelayer36 of barrier material and bounded byopenings31 that have been created in thelayer37 of photoresist. Over the surface of thelayers38 of metal, which will be referred to as pillar metal in view of the role these layers play in the completed structure of the solder bumps of the invention, layers40 of under bump metal have been deposited using deposition methods such as electroplating.

Layer36 preferably comprises titanium or copper and is preferably deposited to a thickness of between about 500 and 2000 Angstroms and more preferably to a thickness of about 1000 Angstroms.

Layer38 preferably comprises copper and is preferred to be applied to a thickness of between about 10 and 100 μm but more preferably to a thickness of about 50 μm.

Layer40 preferably comprises nickel and is preferred to be applied to a thickness of between about 1 and 10 μm but more preferably to a thickness of about 4 μm.

FIG. 10 shows a cross section where the process of the invention has further electroplatedlayers42 of solder metal over the surface oflayers40 of under bump metal (UBM) and bounded by theopenings31 that have been created in thelayer37 of photoresist.

Layer40 of UBM, typically of nickel and of a thickness between about 1 and 10 μm, is electroplated over thelayer38 of pillar metal. Thelayer42 of bump metal (typically solder) is electroplated in contact with thelayer40 of UBM to a thickness of between about 30 and 100 μm but more preferably to a thickness of about 50 μm. Thelayers38,40 and42 of electroplated metal are centered in theopening31 that has been created in thelayer37 of photoresist.

In the cross section that is shown inFIG. 11, it is shown that the patternedlayer37 of photoresist has been removed from above the surface of thebarrier layer36. The previously highlighted methods and processing conditions for the removal of a layer of photoresist can be applied for the purpose of the removal oflayer37 that is shown in cross section inFIG. 11. The invention further proceeds with the partial etching of thepillar metal38, as shown in cross section inFIG. 12, using methods of wet chemical etching or an isotropic dry etch, selective to the pillar metal material. It is clear that, by adjusting the etching parameters, of which the time of etch is most beneficial, the diameter of thepillar metal38 can be reduced by almost any desired amount. The limitation that is imposed on the extent to which the diameter of thepillar metal38 is reduced is not imposed by the wet etching process but by concerns of metal bump reliability and functionality. Too small a remaining diameter of thepillar metal38 will affect the robustness of the solder bumps while this may also have the effect of increasing the resistance of the metal bump.

The final two processing steps of the invention, before the solder metal is reflowed, are shown in the cross section ofFIGS. 13 and 14 and affect the etching of the exposed surface of thebarrier layer36. Using isotropic etching, the exposed barrier layer is completely removed as is shown inFIG. 13. Using anisotropic etching, inFIG. 14, the etching of the barrier layer is partially impeded by the presence of thecolumns42 of solder metal.

It is believed that the undercut shape ofpillar38 will prevent wetting ofpillar38 and theUBM layer40 during subsequent solder reflow. It is also believed that exposure to air will oxidize the sidewalls ofpillar38 andUBM layer40 and therefore prevent wetting of these surfaces during subsequent solder reflow. Optionally, the sidewalls ofpillar38 andUBM layer40 may be further oxidized by, for example, a thermal oxidation below reflow temperature of about 240 degrees C. such as heating in oxygen ambient at about 125 degrees C.

FIGS. 15 and 16 show the final cross section of the solder bump of the invention after the solder metal has been reflowed.FIG. 15 corresponds toFIG. 13 whileFIG. 16 corresponds toFIG. 14, this relating to the etch in thebarrier layer36 that has been explained usingFIGS. 13 and 14. It is noted that the etchedlayer36 of barrier material that is shown in cross section inFIG. 15 corresponds to the etched layer of barrier material that is shown inFIG. 13. The same correspondence exists betweenFIGS. 16 and 14.

The above summarized processing steps of electroplating that are used for the creation of a metal bump can be supplemented by the step of curing or pre-baking of the layer of photoresist after this layer has been deposited.

To review and summarize the invention:

• • prior to and in preparation for the invention, a semiconductor surface is provided, a layer of dielectric has been deposited over the semiconductor surface, a contact pad has been provided on the layer of dielectric, the contact pad has an exposed surface, a layer of passivation has been deposited over a semiconductor surface including the surface of said contact pad, and the layer of passivation has been patterned and etched, creating an opening in the layer of passivation, partially exposing the surface of the contact pad, the opening in the layer of passivation is centered with respect to the contact pad
  • the invention starts with a barrier layer deposited over the surface of the layer of passivation, making contact with the contact pad through the opening created in the layer of passivation
  • a layer of photoresist is deposited over the surface of the barrier layer
  • the layer of photoresist is patterned and etched, creating an opening through the layer of photoresist, wherein the opening in the layer of photoresist aligns with and is centered with respect to the contact pad
  • in sequence are deposited, bounded by the opening created in the layer of photoresist, a layer of pillar metal, a layer of under bump metal and a layer of solder metal
  • the patterned layer of photoresist is removed from the surface of the barrier layer
  • the layer of pillar metal is etched, reducing the diameter of the pillar metal
  • the barrier layer is etched, using either isotropic or anisotropic etching
  • the solder metal is reflowed.

The invention offers the following advantages:

• • ball height is a very important reliability concern; in order to prevent thermal mismatch between overlying layers of a package (such as a semiconductor device and an underlying printed circuit board and the like) it is important to increase the distance between overlying elements; the invention provides this ability
  • a larger solder ball (for better thermal or reliability performance) results in increased pitch; this is contrary to state of the art design requirements
  • if small solder balls are used without providing height, it is very difficult to underfill the small gaps
  • the solder is, using the invention, relatively far removed from the semiconductor device which means that the application of low-alpha solder is not required (alpha-particles create soft errors in memory products; lead is known to emit alpha-particles when lead decays)
  • for the pillar metal a metal needs to be selected that has good conductivity and good ductility, such as copper. This is in order to provide improved thermal performance by counteracting thermal stress
  • the height of the pillar of the solder bump of the invention is important and should be between about 10 to 100 μm in order to achieve objectives of high stand-off
  • the metal that is used for the under bump metal layer is important in that this metal must have good adhesion with the overlying solder during solder reflow while this metal must not solve too fast and in so doing form a barrier to the solder; in addition, the UBM metal when exposed to air can form a layer of protective oxide thus preventing solder wetting to the pillar metal around the perimeter of the UBM metal during the reflow process; nickel is therefore preferred for the UBM metal

Now the packaging of the invention using the solder bumps described above will be discussed. Referring now to the cross section that is shown inFIG. 17, there is shown a cross section of the BGA package of the invention whereby the semiconductor device has been encapsulated in a molding compound. The elements that are highlighted in the cross section ofFIG. 5 are the following:

• • 50, a semiconductor device that is mounted in the package of the invention shown in cross section inFIG. 17
  • 52, the (BGA) substrate on the surface of whichdevice50 is mounted
  • 54, the pillar metal of the interface between thedevice50 and theBGA substrate52, similar topillar metal38 ofFIGS. 15 and 16
  • 56, the solder bump of the interface between thedevice50 and theBGA substrate52, similar tosolder bump42 ofFIGS. 15 and 16
  • 58, the contact balls that are used to interconnect the package of the invention with surrounding circuitry
  • 60, molding compound into which thedevice50 is embedded for protection against the environment.

Thecolumns54 of pillar metal typically have a height of between about 10 and 100 μm and more preferably about 50 μm.

The cross section that is shown inFIG. 18 is identical to the cross section ofFIG. 17 with the exception of theunderfill62 which is used instead of themolding compound60 ofFIG. 17.

The following comment applies: the creation of thepillar metal54 and thesolder bump56 starts using the I/O contact pads of device50 (not shown in FIGS.17,18) as the contact pads; that is the I/O contact pads ofdevice50 take the place of thecontact pad32 ofFIGS. 15 and 16 in the creation of thepillar metal54 and thesolder bump56. The process of creating thepillar metal54 and thesolder bump56 therefore is as follows:

• • a layer of dielectric is deposited over the active surface ofdevice50; the active surface ofdevice50 is the surface in which I/O contact points have been provided; this surface will face theBGA substrate52 after mounting of thedevice50 onBGA substrate52
  • openings are created in the layer of dielectric, exposing the I/O contact pads ofdevice50; this brings the process of the invention to the point of the related application where contact pads32 (FIGS. 15,16) have been created on the surface of thelayer30 of dielectric
  • a layer of passivation is deposited over the surface of the layer of dielectric, similar tolayer34,FIGS. 15,16
  • openings are created in the layer of passivation, partially exposing the surface of the device I/O contact pads
  • a barrier layer is deposited over the surface of the layer of passivation, identical tolayer36,FIGS. 15,16
  • thepillar metal54 of the solder bump is formed, identical tolayer38,FIGS. 15,16
  • the layer of under bump (not shown inFIGS. 17,18) is created overlying the pillar metal, identical tolayer40,FIGS. 15,16
  • thesolder bump56 is formed, identical tolayer42,FIGS. 15,16
  • the layer of barrier metal is isotropically (FIG. 15) or anisotropically (FIG. 16) etched.

Referring now toFIG. 19, there is shown a top view of an array type arrangement of I/O contact points66 that form the contact points ofdevice50. This top view of the array type contact points66 is shown as one example of where the process of creating pillar metal and solder bumps can be applied.

FIGS. 20 and 21 show two more examples of arrangements of I/O contact pads that are provided on the surface ofdevice50, where the process of the invention can be applied.FIG. 20 shows a peripheral I/O pad design68 whileFIG. 21 shows a centertype pad design70.

While the peripheral I/O pad design that is shown inFIG. 20 provides evenly distributed mechanical support fordevice50, this is not the case for the center pad design that is shown inFIG. 21. For this kind of design, additional mechanical support can be provided todevice50; this is shown in top view inFIG. 22. The elements highlighted as70 inFIG. 22 are the solder bumps that have been created on the I/O contact pads ofdevice50;elements72 are dummy solder bumps that can be provided in order to lend mechanical support todevice50. The symmetry of the dummy bumps72 as shown inFIG. 22 makes clear thatdevice50 is, with the dummy bumps72, adequately and symmetrically supported.

In mounting semiconductor devices on the surface of a BGA substrate, it is important from a manufacturing point of view that solder flux, after the process of solder flow has been completed, can be readily removed. This requires easy access to the surface areas of the BGA substrate where solder flux has been able to accumulate. In addition, the device interconnects (consisting of pillar metal and solder bumps) must, after the pillar metal and the solder bumps have been formed in accordance with the related application, be readily available so that device encapsulants can be adequately applied. More importantly, after flip-chip assembly and solder reflow, the flux that has accumulated in the gap between the semiconductor die and the substrate must be cleaned. For these reasons, it is of value to apply the solder mask not across the entire surface of the substrate (blank deposition) but to leave open the surface areas of the substrate that are immediately adjacent to the I/O interconnects (of pillar metal and solder bumps). This design will create a channel though which the cleaning solution can flow easily. This is highlighted in the top view ofFIGS. 23 and 24, where is shown:

• • 52, the BGA substrate on the surface of which device50 (not shown) is mounted
  • 74, I/O contact pads provided on the surface ofsubstrate52
  • 76, interconnect traces provided on the surface ofsubstrate52, connected withcontact pads74
  • 79, the surface region of thesubstrate52 over which no solder mask is applied
  • 80, the surface region of thesubstrate52 over which a solder mask is applied.

This is further highlighted in the cross section ofsubstrate52 that is shown inFIG. 24. It is clear that over theregion79, which is the region where no solder mask is applied, themetal pads74 are readily available so that removal of solder flux and the dispensing of encapsulants can be performed. It must be remembered that this is possible due to the height of the combinedpillar metal54 and thesolder bump56, which results in adequate spacing between thedevice50 and the surface ofsubstrate52. Further shown inFIG. 24 are routingtraces82 that are provided on the surface ofsubstrate52 for additional interconnect.

FIGS. 25 and 26 show how prior art procedures and conventions are applied to affect flux removal and encapsulant application. In the prior art application, themetal pads74 are typically surrounded by thesolder mask78, even for small pitch I/O pad designs. Typically, the solder mask is determined by the type of contact pad design (FIGS. 19 through 21), whereby thecontact pads74 require about 60 μm clearance for reasons of proper alignment registration. This results in the substrate design rule being more critical, allowing for less error and smaller tolerance in the design parameters. In addition, the height of thesolder mask78 is generally about 10 μm larger than the height of thecontact pad74, further forming an obstacle in applying molding compound or in removing flux after the solder process has been completed. These aspects of the prior art are shown inFIGS. 25 and 26, where themetal pads74 are completely surrounded by thesolder mask78. The present invention negates the highlighted negative effects of the solder mask on flux cleaning and on dispensing molding compound.

FIGS. 27athrough27fshow examples of applications of the invention, as follows:

FIG. 27ashows the application of a solder mask over the surface that has previously been shown inFIG. 19, the solder mask has been indicated withcross-hatched regions90, the regions where no solder mask is present have been highlighted with91.

FIGS. 27band27crelate to the previousFIG. 20, the solder mask has been highlighted asregions90 while the regions where no solder mask is present have been highlighted with91. The design that is shown inFIG. 27cis considered a “partial” peripheral type I/O pad configuration of a semiconductor device since I/O pads68 are only provided along two opposing sides of thesemiconductor device50.

It must be noted that the designs that are shown inFIGS. 27band27ccan further be provided with supporting dummy solder bumps in the regions of thesolder mask90, these supporting solder bumps have not been shown inFIGS. 27band27c.

FIG. 27dshows the design that has previously been shown inFIG. 21,FIG. 27eshows a design that is similar to the design ofFIG. 27dwith the exception that the contact points70 have now been provided in two columns. It is clear from these two drawings that channels have been created in the solder mask that are in line with and include the contact pads. These channels allow for easy flow of cleaning fluid and therefore allow for easy removal of solder flux after the process of chip encapsulation and solder flow has been completed.

FIG. 27frelates to the previously shownFIG. 22, the above observation relating to the creation of a channel through the solder flux and the therefrom following easy flow of cleaning fluid equally applies to the design that is shown inFIG. 27f.

FIGS. 28aand28bdemonstrate how the invention leads to the ability to reduce the pitch between I/O pads.

FIG. 28ashows how in prior art applications thesolder mask90 is provided, further shown inFIG. 28aare:

• • 94, the circumference of the opening that is created in thesolder mask90
  • 95, the circumference of the bond pad on the surface of a semiconductor device
  • 92, the distance (or spacing) S between two adjacent contact pads
  • 93, the diameter D of a contact pad.

In prior art applications as shown inFIG. 28a, the pitch between adjacent contact pads is P=D+S+2×(the required clearance between adjacent contact pads). The required clearance is needed by the solder mask and requires that extra space is required between thecircumference95 of the contact pad and thecircumference94 of the opening created in the solder mask.

With the wide channel created by the invention through the solder mask, highlighted aschannel91 inFIG. 28b, the conventional clearance is not required, resulting in the ability to reduce the pitch betweenadjacent contact pads95. This leads to adistance92′,FIG. 28b, which is smaller thandistance92 ofFIG. 28a.

Although the invention has been described and illustrated with reference to specific illustrative embodiments thereof, it is not intended that the invention be limited to those illustrative embodiments. Those skilled in the art will recognize that variations and modifications can be made without departing from the spirit of the invention. It is therefore intended to include within the invention all such variations and modifications which fall within the scope of the appended claims and equivalents thereof.

Claims (20)

1. A chip package comprising:

a substrate;

a semiconductor device comprising a polymer layer and a metal pad having a contact point aligned with an opening in said polymer layer;

a copper pillar between said contact point and said substrate, wherein said copper pillar has a height between 10 and 100 micrometers, wherein said copper pillar is connected to said contact point through said opening;

a titanium-containing layer between said contact point and said copper pillar, wherein said titanium-containing layer is on said contact point, on said polymer layer and in said opening, wherein said copper pillar is connected to said contact point through said titanium-containing layer;

a solder between said copper pillar and said substrate, wherein said solder joins said substrate, wherein said solder is connected to said copper pillar; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts said semiconductor device and said substrate and covers a sidewall of said copper pillar.

2. The chip package ofclaim 1 further comprising a nickel-containing layer between said solder and said copper pillar.

3. The chip package ofclaim 2, wherein said nickel-containing layer has a thickness between 1 and 10 micrometers.

4. The chip package ofclaim 2, wherein said sidewall of said copper pillar is recessed from a sidewall of said nickel-containing layer.

5. The chip package ofclaim 1, wherein said titanium-containing layer comprises titanium nitride.

6. A chip package comprising:

a substrate;

a semiconductor device comprising a polymer layer and a metal pad having a contact point aligned with an opening in said polymer layer;

a copper pillar between said contact point and said substrate, wherein said copper pillar has a height between 10 and 100 micrometers, wherein said copper pillar is connected to said contact point through said opening;

a solder between said copper pillar and said substrate, wherein said solder joins said substrate, wherein said solder is connected to said copper pillar; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts said semiconductor device and said substrate and covers a sidewall of said copper pillar.

7. The chip package ofclaim 6 further comprising a nickel-containing layer between said solder and said copper pillar.

8. The chip package ofclaim 7, wherein said nickel-containing layer has a thickness between 1 and 10 micrometers.

9. The chip package ofclaim 7, wherein said sidewall of said copper pillar is recessed from a sidewall of said nickel-containing layer.

10. The chip package ofclaim 6 further comprising a metal layer between said contact point and said copper pillar, wherein said metal layer is on said contact point, on said polymer layer and in said opening, wherein said copper pillar is connected to said contact point through said metal layer.

11. A chip package comprising:

a substrate;

a semiconductor device comprising a polymer layer and a metal pad having a contact point aligned with an opening in said polymer layer;

a solder between said contact point and said substrate, wherein said solder joins said substrate, wherein said solder is connected to said contact point through said opening;

a titanium-containing layer between said contact point and said solder, wherein said titanium-containing layer is on said contact point, on said polymer layer and in said opening;

a copper-containing layer between said solder and said titanium-containing layer, wherein said solder is connected to said copper-containing layer, wherein said copper-containing layer has a first sidewall recessed from a second sidewall of said titanium-containing layer; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts said semiconductor device and said substrate and covers a surface of said solder.

12. The chip package ofclaim 11, wherein said copper-containing layer has a thickness between 10 and 100 micrometers.

13. The chip package ofclaim 11 further comprising a nickel-containing layer between said copper-containing layer and said solder.

14. The chip package ofclaim 13, wherein said nickel-containing layer has a thickness between 1 and 10 micrometers.

15. The chip package ofclaim 11, wherein said titanium-containing layer comprises a titanium-tungsten alloy.

16. A chip package comprising:

a substrate;

a semiconductor device comprising a polymer layer and a metal pad having a contact point aligned with an opening in said polymer layer;

a solder between said contact point and said substrate, wherein said solder joins said substrate, wherein said solder is connected to said contact point through said opening;

a first metal layer between said contact point and said solder, wherein said first metal layer is on said contact point, on said polymer layer and in said opening;

a second metal layer between said solder and said first metal layer, wherein said solder is connected to said second metal layer, wherein said second metal layer has a first sidewall recessed from a second sidewall of said first metal layer; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts said semiconductor device and said substrate and covers a surface of said solder.

17. The chip package ofclaim 16, wherein said first metal layer comprises tungsten.

18. The chip package ofclaim 16, wherein said second metal layer comprises a copper layer between said first metal layer and said solder.

19. The chip package ofclaim 16 further comprising a nickel-containing layer between said second metal layer and said solder.

20. The chip package ofclaim 16, wherein said first metal layer comprises titanium.

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