US7723790B2 - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a divisional of U.S. application Ser. No. 11/677,956 filed Feb. 22, 2007 now U.S. Pat. No. 7,439,587, which is a divisional of U.S. application Ser. No. 11/108,843 filed on Apr. 19, 2005 now U.S. Pat. No. 7,193,272, which is a divisional of U.S. application Ser. No. 09/802,886 filed on Mar. 12, 2001 now abandoned, and in turn claims priority to JP 2000-080096 filed on Mar. 22, 2000, and JP 2000-342937 filed on Nov. 10, 2000, the entire contents of each of which are hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a structure of a semiconductor device and a method of manufacturing the same, and more particularly to a structure of a semiconductor device using an SOI substrate and a method of manufacturing the same.

2. Description of the Background Art

FIG. 47 is a cross section showing a structure of a semiconductor device using an SOI substrate in accordance with a first background art. As shown inFIG. 47, the semiconductor device of the first background art comprises anSOI substrate101 having a multilayered structure in which asilicon substrate102, aninsulating layer103 and asilicon layer104 are layered in this order. In an upper surface of thesilicon layer104, a plurality ofisolation insulating films105 of partial-trench type are selectively formed. In an element formation region of theSOI substrate101 defined by theisolation insulating films105, an NMOS transistor (hereinafter, referred to as “NMOS”) is formed. The NMOS has an n⁺-type source region109sand an n⁺-type drain region109dwhich are formed in thesilicon layer104 and paired with each other with a p-type channel region110 interposed therebetween. Further, the NMOS has a gate structure which is formed on thechannel region110 and has a multilayered structure in which a gateinsulating film106 and agate electrode107 are layered in this order andsidewalls108 formed on side surfaces of the multilayered structure. Furthermore, in thesilicon layer104, a p⁻-type body region111 is selectively formed.

Aninterlayer insulating film120 is formed on the NMOS, theisolation insulating film105 and thebody region111. On the interlayerinsulating film120,wires113 and117 are selectively formed. In the interlayerinsulating film120, acontact hole112 filled with a conductive plug therein is selectively formed to electrically connect thewire113 and thedrain region109d. Further, in theinterlayer insulating film120, acontact hole116 filled with a conductive plug therein is selectively formed to electrically connect thewire117 and thesource region109s.

Aninterlayer insulating film121 is formed on theinterlayer insulating film120, and apower supply line115 and aground line119 are selectively formed on theinterlayer insulating film121. In theinterlayer insulating film121, acontact hole114 filled with a conductive plug therein is selectively formed to electrically connect thepower supply line115 and thewire113. Further, in theinterlayer insulating film121, acontact hole118 filled with a conductive plug therein is selectively formed to electrically connect theground line119 and thewire117.

FIG. 48 is a plan view showing a structure of a semiconductor device using an SOI substrate in accordance with a second background art. As shown inFIG. 48, the semiconductor device of the second background art comprises two CMOS transistors (hereinafter, referred to as “CMOS”)140 and141 formed adjacently to each other with the isolationinsulating film105 of partial-trench type interposed therebetween.

The semiconductor device of the first background art shown inFIG. 47, however, has the following problem.FIGS. 49 and 50 are timing charts used for explaining the problem of the semiconductor device in accordance with the first background art. In a logic circuit using the semiconductor device ofFIG. 47, if a reference clock rises when an input potential is “H”, an output potential shifts from “L” to “H” (for example, time T1 ofFIG. 49 and time T3 ofFIG. 50) and if the reference clock falls when the input potential is “L”, the output potential shifts from “H” to “L” (for example, time T2 ofFIG. 49 and time T4 ofFIG. 50). As shown inFIG. 47, in the semiconductor device of the first background art, thepower supply line115 and theground line119 are formed above thebody region111. Therefore, when the potentials of thepower supply line115 and theground line119 are affected by the effect of some external noise to vary, the potential of thebody region111 also varies due to capacitive coupling. The variation in potential of thebody region111 appears as aninput noise130 in an operation of the above logic circuit.

At this time, as shown inFIG. 49, if the operating frequency of the logic circuit is low, ranging from about several KHz to several MHz, and the cycle of the reference clock is sufficiently longer than the waveform of thenoise130, the operation of the logic circuit is hard to be affected by thenoise130. As shown inFIG. 50, however, if the operating frequency of the logic circuit is high, about several GHz, the operation of the logic circuit is likely to be affected by thenoise130. In the case ofFIG. 50, the output potential at time T5 shifts from “L” to “H” and the output potential at time T6 shifts from “H” to “L”, and as a result awrong output pulse131 is generated.

Thus, the semiconductor device of the first background art, which is likely to be affected by variation in potential of the body region and potential of the power supply line and the ground line, has a problem that malfunction is likely to occur as the operating frequency of the semiconductor device becomes high.

The semiconductor device of the second background art ofFIG. 48 has the following problem.FIG. 51 is a cross section used for explaining the problem of the semiconductor device in accordance with the second background art.FIG. 51 corresponds to a cross-sectional structure of the semiconductor device ofFIG. 48 taken along the line L100, and a left-side transistor ofFIG. 51 corresponds to the NMOS included in theCMOS140 and a right-side transistor corresponds to the NMOS included in theCMOS141.

It is generally known that an operation of a transistor is likely to be affected by temperature and a current flowing in the transistor is reduced as the ambient temperature gets higher. In the semiconductor device ofFIG. 48, it is assumed that theCMOS140 has a relatively high operating threshold voltage and a large calorific value with large current flow while theCMOS141 has a relatively low operating threshold voltage and a small calorific value. In this case, the heat generated in theCMOS140 is conducted to theCMOS141 through thesilicon layer104 below theisolation insulating film105 as represented by anarrow150 ofFIG. 51. Then, the heat works to reduce the current in theCMOS141, making the operation of theCMOS141 unstable. As a result, malfunction occurs to deteriorate the circuit characteristics especially in a circuit whose operation sensitively depends on magnitude of current such as an analog circuit and an RF circuit.

Thus, in the semiconductor device of the second background art, if two semiconductor elements having different calorific values are formed adjacently to each other, the heat generated in one of the semiconductor elements affects the operation of the other to disadvantageously cause a malfunction.

SUMMARY OF THE INVENTION

The present invention is directed to a semiconductor device. According to a first aspect of the present invention, the semiconductor device comprises: an SOI substrate having a structure in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order; a partial-isolation insulating film formed in a main surface of the semiconductor layer; a first semiconductor element formed in an element formation region defined by the partial-isolation insulating film in the semiconductor layer; an interlayer insulating film formed on the first semiconductor element and the partial-isolation insulating film; at least one of a power supply line and a ground line formed on the interlayer insulating film; and a first complete-isolation insulating film formed extending from the main surface of the semiconductor layer, reaching an upper surface of the insulating layer below at least one of the power supply line and ground line.

According to a second aspect of the present invention, the semiconductor device of the first aspect further comprises: a second semiconductor element formed adjacently to the first semiconductor element in the semiconductor layer, having an operating threshold voltage different from that of the first semiconductor element; and a second complete-isolation insulating film formed extending from the main surface of the semiconductor layer, reaching the upper surface of the insulating layer between the first semiconductor element and the second semiconductor element.

According to a third aspect of the present invention, the semiconductor device of the first aspect further comprises: a second semiconductor element formed adjacently to the first semiconductor element in the semiconductor layer, having an operating frequency different from that of the first semiconductor element; and a second complete-isolation insulating film formed extending from the main surface of the semiconductor layer, reaching the upper surface of the insulating layer between the first semiconductor element and the second semiconductor element.

According to a fourth aspect of the present invention, the semiconductor device of any one of the first to third aspects further comprises: a signal line formed on the interlayer insulating film, being electrically connected to the first semiconductor element; and a third complete-isolation insulating film formed extending from the main surface of the semiconductor layer, reaching the upper surface of the insulating layer below the signal line.

According to a fifth aspect of the present invention, the semiconductor device of any one of the first to fourth aspects further comprises: a bonding pad formed on the interlayer insulating film, for electrically connecting the first semiconductor element and an outer element; and a fourth complete-isolation insulating film formed extending from the main surface of the semiconductor layer, reaching the upper surface of the insulating layer below the bonding pad.

According to a sixth aspect of the present invention, the semiconductor device comprises: an SOI substrate having a structure in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order; a partial-isolation insulating film formed in a main surface of the semiconductor layer; a first semiconductor element formed in an element formation region defined by the partial-isolation insulating film in the semiconductor layer; a second semiconductor element formed adjacently to the first semiconductor element in the semiconductor layer, having an operating threshold voltage different from that of the first semiconductor element; and a complete-isolation insulating film formed extending from the main surface of the semiconductor layer, reaching the upper surface of the insulating layer between the first semiconductor element and the second semiconductor element.

According to a seventh aspect of the present invention, the semiconductor device comprises: an SOI substrate having a structure in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order; a partial-isolation insulating film formed in a main surface of the semiconductor layer; a first semiconductor element formed in an element formation region defined by the partial-isolation insulating film in the semiconductor layer; a second semiconductor element formed adjacently to the first semiconductor element in the semiconductor layer, having an operating frequency different from that of the first semiconductor element; and a complete-isolation insulating film formed extending from the main surface of the semiconductor layer, reaching the upper surface of the insulating layer between the first semiconductor element and the second semiconductor element.

According to an eighth aspect of the present invention, the semiconductor device comprises: an SOI substrate having a structure in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order; a partial-isolation insulating film formed in a main surface of the semiconductor layer; a semiconductor element formed in an element formation region defined by the partial-isolation insulating film in the semiconductor layer; an interlayer insulating film formed on the semiconductor element and the partial-isolation insulating film; a signal line formed on the interlayer insulating film, being electrically connected to the semiconductor element; and a complete-isolation insulating film formed extending from the main surface of the semiconductor layer, reaching the upper surface of the insulating layer below the signal input line.

According to a ninth aspect of the present invention, in the semiconductor device of the eighth aspect, the signal line has a plurality of wires constituting a multilayer interconnection structure, and the complete-isolation insulating film is formed below at least one of the plurality of wires which exists in the lowest layer.

According to a tenth aspect of the present invention, in the semiconductor device of the ninth aspect, the complete-isolation insulating film is also formed below one of the plurality of wires which exists in the layer nearest to the SOI substrate but the lowest layer.

According to an eleventh aspect of the present invention, in the semiconductor device of any one of the eighth to tenth aspects, the signal line propagates a signal having a frequency not less than GHz order.

According to a twelfth aspect of the present invention, in the semiconductor device of the eighth aspect, the semiconductor element is a buffer circuit, and the signal line connects the buffer circuit and a bonding pad connected to an external device.

According to a thirteenth aspect of the present invention, the semiconductor device comprises: an SOI substrate having a structure in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order; a partial-isolation insulating film formed in a main surface of the semiconductor layer; a semiconductor element formed in an element formation region defined by the partial-isolation insulating film in the semiconductor layer; an interlayer insulating film formed on the semiconductor element and the partial-isolation insulating film; a bonding pad formed on the interlayer insulating film, for electrically connecting the first semiconductor element and an outer element; and a complete-isolation insulating film formed extending from the main surface of the semiconductor layer, reaching the upper surface of the insulating layer below the bonding pad.

According to a fourteenth aspect of the present invention, the semiconductor device comprises: an SOI substrate having a structure in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order; a partial-isolation insulating film formed in a main surface of the semiconductor layer; a semiconductor element including a channel region formed in the semiconductor layer in an element formation region defined by the partial-isolation insulating film; an interlayer insulating film formed on the semiconductor element and the partial-isolation insulating film; at least one of a power supply line and a ground line formed on the interlayer insulating film; and a high-resistance region formed below at least one of the power supply line and ground line in the semiconductor layer, having a resistance higher than that of the channel region.

The present invention is also directed to a method of manufacturing a semiconductor device. According to a fifteenth aspect of the present invention, the method of manufacturing a semiconductor device comprises the steps of: (a) preparing an SOI substrate having a structure in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order; (b) forming a partial-isolation insulating film in a main surface of the semiconductor layer and forming a first complete-isolation insulating film so as to extend from the main surface of the semiconductor layer and reach an upper surface of the insulating layer below a region in which at least one of a power supply line and a ground line is to be formed; (c) forming a first semiconductor element in an element formation region defined by the partial-isolation insulating film in the semiconductor layer; (d) forming an interlayer insulating film on the first semiconductor element, the partial-isolation insulating film and the first complete-isolation insulating film; and (e) forming at least one of the power supply line and the ground line on the interlayer insulating film.

According to a sixteenth aspect of the present invention, the method of manufacturing a semiconductor device of the fifteenth aspect further comprises the steps of: (f) forming a second semiconductor element adjacently to the first semiconductor element in the semiconductor layer, to have an operating threshold voltage different from that of the first semiconductor element; and (g) forming a second complete-isolation insulating film so as to extend from the main surface of the semiconductor layer and reach the upper surface of the insulating layer between the first semiconductor element and the second semiconductor element.

According to a seventeenth aspect of the present invention, the method of manufacturing a semiconductor device of the fifteenth aspect further comprises the steps of: (f) forming a second semiconductor element adjacently to the first semiconductor element in the semiconductor layer, to have an operating frequency different from that of the first semiconductor element; and (g) forming a second complete-isolation insulating film so as to extend from the main surface of the semiconductor layer and reach the upper surface of the insulating layer between the first semiconductor element and the second semiconductor element.

According to an eighteenth aspect of the present invention, the method of manufacturing a semiconductor device of any one of the fifteenth to seventeenth aspects further comprises the steps of: (h) forming a third complete-isolation insulating film so as to extend from the main surface of the semiconductor layer and reach the upper surface of the insulating layer below a region in which a signal line electrically connected to the first semiconductor element is to be formed; and (i) forming the signal line on the interlayer insulating film.

According to a nineteenth aspect of the present invention, the method of manufacturing a semiconductor device of any one of the fifteenth to eighteenth aspects further comprises the steps of: (j) forming a fourth complete-isolation insulating film so as to extend from the main surface of the semiconductor layer and reach the upper surface of the insulating layer below a region in which a bonding pad for electrically connecting the first semiconductor element and an outer element is to be formed; and (k) forming the bonding pad on the interlayer insulating film.

According to a twentieth aspect of the present invention, in the method of manufacturing a semiconductor device of the fifteenth aspect. the step (b) has the steps of (x) excavating the main surface of the semiconductor layer by a predetermined film thickness in a region in which the partial-isolation insulating film is to be formed and a region in which the first complete-isolation insulating film is to be formed, to form a first recess; (y) selectively excavating a bottom surface of the first recess exposed in the step (x) in the region in which the first complete-isolation insulating film is to be formed until the upper surface of the insulating layer is exposed, to form a second recess; and (z) burying an insulating film in the first recess and the second recess.

According to a twenty-first aspect of the present invention, in the method of manufacturing a semiconductor device of the twentieth aspect, the step (y) has the steps of (y−1) forming a photoresist on a structure obtained in the step (x); (y−2) exposing the photoresist by using a photomask having a predetermined mask pattern; (y−3) developing the photoresist after being exposed; and (y−4) etching the semiconductor layer with the photoresist after being developed used as an etching mask, to form the second recess, and in the method of the seventeenth aspect, the predetermined mask pattern is automatically formed on the basis of a wiring layout representing a region in which at least one of the power supply line and the ground line is to be formed.

In the semiconductor device of the first aspect of the present invention, the first complete-isolation insulating film is formed below at least one of the power supply line and the ground line. Therefore, even if the potential of at least one of the power supply line and ground line varies due to the effect of some external noise, it is possible to prevent variation in potential of the semiconductor layer caused by the above potential variation.

In the semiconductor device of the second aspect of the present invention, the second complete-isolation insulating film is formed between the first semiconductor element and the second semiconductor element having different operating threshold voltages. Therefore, since conduction of the heat generated in one of the first and second semiconductor elements to the other semiconductor element can be suppressed, it is possible to prevent unstable operations of the first and second semiconductor elements due to the heat.

In the semiconductor device of the third aspect of the present invention, the second complete-isolation insulating film is formed between the first semiconductor element and the second semiconductor element having different operating frequencies. Therefore, it is possible to prevent the potential at the semiconductor layer in a portion where the first semiconductor element is formed and that at the semiconductor layer in a portion where the second semiconductor element is formed from affecting each other due to the difference in operating frequency.

In the semiconductor device of the fourth aspect of the present invention, the third complete-isolation insulating film is formed below the signal line. Therefore, even if the potential of the signal line varies due to the effect of external noise, it is possible to prevent variation in potential of the semiconductor layer caused by the potential variation of the signal line.

In the semiconductor device of the fifth aspect of the present invention, the fourth complete-isolation insulating film is formed below the bonding pad. Therefore, even if some external noise is propagated from the outer element through the bonding pad, it is possible to prevent variation in potential of the semiconductor layer caused by the noise.

In the semiconductor device of the sixth aspect of the present invention, the complete-isolation insulating film is formed between the first semiconductor element and the second semiconductor element having different operating threshold voltages. Therefore, since conduction of the heat generated in one of the first and second semiconductor elements to the other semiconductor element can be suppressed, it is possible to prevent unstable operations of the first and second semiconductor elements due to the heat.

In the semiconductor device of the seventh aspect of the present invention, the complete-isolation insulating film is formed between the first semiconductor element and the second semiconductor element having different operating frequencies. Therefore, it is possible to prevent the potential at the semiconductor layer in a portion where the first semiconductor element is formed and that at the semiconductor layer in a portion where the second semiconductor element is formed from affecting each other due to the difference in operating frequency.

In the semiconductor device of the eighth aspect of the present invention, the complete-isolation insulating film is formed below the signal line. Therefore, even if the potential of the signal line varies due to the effect of external noise, it is possible to prevent variation in potential of the semiconductor layer caused by the potential variation of the signal line.

In the semiconductor device of the ninth aspect of the present invention, the complete-isolation insulating film is formed below the wire in the lowest layer of the multilayer interconnection structure, which is likely to affect the potential of the semiconductor layer. Therefore, even if the potential of the wire in the lowest layer varies due to the effect of some external noise, it is possible to prevent variation in potential of the semiconductor layer caused by the above potential variation.

In the semiconductor device of the tenth aspect of the present invention, even if the potentials of the wire in the lowest layer and the wire in the layer nearest to the SOI substrate but the lowest layer vary due to the effect of some external noise, it is possible to prevent variation in potential of the semiconductor layer caused by the above potential variation.

In the semiconductor device of the eleventh aspect of the present invention, the complete-isolation insulating film is formed below the signal line in the first region which incorporates the first circuit which is more affected by some noise than the second circuit. Therefore, since it is possible to prevent variation in potential of the semiconductor layer caused by the variation in potential of the signal line, the first circuit which is likely to be affected by some noise can be stably operated.

In the semiconductor device of the twelfth aspect of the present invention, the complete-isolation insulating film is formed below the signal line which connects the buffer circuit and the bonding pad. Therefore, even if the potential of the wire varies due to the effect of some noise inputted from the external device, it is possible to prevent variation in potential of the semiconductor layer which exists below the wire caused by the above potential variation.

In the semiconductor device of the thirteenth aspect of the present invention, the complete-isolation insulating film is formed below the bonding pad. Therefore, even if some external noise is propagated from the outer element through the bonding pad, it is possible to prevent variation in potential of the semiconductor layer caused by the noise.

In the semiconductor device of the fourteenth aspect of the present invention, even if the potential of at least one of the power supply line and ground line varies due to the effect of some external noise, since capacitive coupling is hard to occur between the high-resistance region and at least one of the power supply line and ground line, it is possible to prevent variation in potential of the semiconductor layer caused by the potential variation of at least one of the power supply line and ground line.

In the method of the fifteenth aspect of the present invention, the first complete-isolation insulating film, instead of a partial-isolation insulating film, is formed below at least one of the power supply line and the ground line, Therefore, it is possible to obtain a semiconductor device in which the potential of the semiconductor layer does not vary in response to the variation in potential of at least one of the power supply line and ground line caused by external noise.

In the method of the sixteenth aspect of the present invention, the second complete-isolation insulating film, instead of a partial-isolation insulating film, is formed between the first semiconductor element and the second semiconductor element having different operating threshold voltages. Therefore, since conduction of the heat generated in one of the first and second semiconductor elements to the other semiconductor element can be suppressed, it is possible to obtain a semiconductor device capable of performing a stable operation against heat generation.

In the method of the seventeenth aspect of the present invention, the second complete-isolation insulating film, instead of a partial-isolation insulating film, is formed between the first semiconductor element and the second semiconductor element having different operating frequencies. Therefore, it is possible to obtain a semiconductor device which can prevent the potential at the semiconductor layer in a portion where the first semiconductor element is formed and that at the semiconductor layer in a portion where the second semiconductor element is formed from affecting each other due to the difference in operating frequency.

In the method of the eighteenth aspect of the present invention, the third complete-isolation insulating film, instead of a partial-isolation insulating film, is formed below the signal line. Therefore, it is possible to obtain a semiconductor device in which the potential of the semiconductor layer does not vary in response to the variation in potential of the signal line caused by external noise.

In the method of the nineteenth aspect of the present invention, the fourth complete-isolation insulating film, instead of a partial-isolation insulating film, is formed below the bonding pad. Therefore, it is possible to obtain a semiconductor device in which the potential of the semiconductor layer does not vary due to some external noise even if the external noise is propagated from the outer element through the bonding pad.

In the method of the twentieth aspect of the present invention, the first complete-isolation insulating film can be formed as the complete isolation portion selectively formed in the partial-isolation insulating film together with the partial-isolation insulating film.

In the method of the twenty-first aspect of the present invention, it is possible to easily form the mask pattern of the photomask used in exposing the photoresist with reference to the wiring layout representing a region in which at least one of the power supply line and ground line is to be formed.

The present invention has two objects. The first object of the present invention is to provide a semiconductor device which can suppress variation in potential of a body region caused by variation in potential of the power supply line and ground line to prevent malfunction even if an operating frequency of the semiconductor device is high, and provide a method of manufacturing the semiconductor device. The second object of the present invention is to provide a semiconductor device which can relieve an effect produced by the heat generated in one of two semiconductor elements which have different calorific values and are formed adjacently to each other on the operation of the other of the semiconductor elements to prevent malfunction, and provide a method of manufacturing the semiconductor device.

These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing a structure of a semiconductor device in accordance with a first preferred embodiment of the present invention;

FIG. 2 is a cross section showing a cross-sectional structure of the semiconductor device ofFIG. 1;

FIGS. 3 to 16 are cross sections showing a method of manufacturing the semiconductor device in accordance with the first preferred embodiment of the present invention step by step;

FIG. 17 is a plan view showing a structure of a semiconductor device in accordance with a second preferred embodiment of the present invention;

FIG. 18 is a cross section showing a cross-sectional structure of the semiconductor device ofFIG. 17;

FIG. 19 is a plan view showing a structure of a semiconductor device in accordance with a third preferred embodiment of the present invention;

FIG. 20 is a cross section showing a cross-sectional structure of the semiconductor device ofFIG. 19;

FIG. 21 is a plan view showing a structure of a semiconductor device in accordance with a fourth preferred embodiment of the present invention;

FIG. 22 is a cross section showing a cross-sectional structure of the semiconductor device ofFIG. 21;

FIG. 23 is a plan view showing a structure of a semiconductor device in accordance with a fifth preferred embodiment of the present invention;

FIG. 24 is a cross section showing a cross-sectional structure of the semiconductor device ofFIG. 23;

FIG. 25 is a plan view showing a structure of a semiconductor device in accordance with a sixth preferred embodiment of the present invention;

FIG. 26 is a cross section showing a cross-sectional structure of the semiconductor device ofFIG. 25;

FIGS. 27(A) and 27(B),28 and29 are conceptional diagrams showing a method of forming a mask pattern in accordance with a seventh preferred embodiment of the present invention;

FIGS. 30(A) to (C) and31 are conceptional diagrams showing another method of forming a mask pattern in accordance with the seventh preferred embodiment of the present invention;

FIG. 32 is a plan view showing a structure of a semiconductor device in accordance with an eighth preferred embodiment of the present invention;

FIG. 33 is a cross section showing a cross-sectional structure of the semiconductor device ofFIG. 32;

FIG. 34 is a plan view showing a structure of a semiconductor device in accordance with a ninth preferred embodiment of the present invention;

FIG. 35 is a cross section showing a cross-sectional structure of the semiconductor device ofFIG. 34;

FIG. 36 is a plan view showing a structure of a semiconductor device in accordance with a tenth preferred embodiment of the present invention;

FIGS. 37 and 38 are cross sections each showing a cross-sectional structure of the semiconductor device ofFIG. 36;

FIG. 39 is a plan view showing another structure of a semiconductor device in accordance with the tenth preferred embodiment of the present invention;

FIGS. 40 and 41 are cross sections each showing a cross-sectional structure of the semiconductor device ofFIG. 39;

FIG. 42 is a plan view showing a structure of a semiconductor device in accordance with an eleventh preferred embodiment of the present invention;

FIG. 43 is a plan view showing another structure of a semiconductor device in accordance with the eleventh preferred embodiment of the present invention;

FIG. 44 is a plan view showing a structure of a semiconductor device in accordance with a twelfth preferred embodiment of the present invention;

FIG. 45 is an enlarged plan view showing a connection between a bonding pad and an input buffer circuit;

FIG. 46 is a cross section showing a cross-sectional structure of the semiconductor device ofFIG. 45;

FIG. 47 is a cross section showing a structure of the semiconductor device in accordance with the first background art;

FIG. 48 is a plan view showing a structure of the semiconductor device in accordance with the second background art;

FIGS. 49 and 50 are timing charts used for explaining the problem of the semiconductor device in accordance with the first background art; and

FIG. 51 is a cross section used for explaining the problem of the semiconductor device in accordance with the second background art.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, the preferred embodiments of the present invention will be specifically discussed, taking a case of CMOS as an example.

The First Preferred Embodiment

FIG. 1 is a plan view showing a structure of a semiconductor device in accordance with the first preferred embodiment of the present invention, andFIG. 2 is a cross section showing a cross-sectional structure of the semiconductor device ofFIG. 1 taken along the line L1. InFIG. 1,interlayer insulating films13 and20 and asidewall8 described later are not shown, for convenience of illustration. With reference toFIGS. 1 and 2, the semiconductor device of the first preferred embodiment comprises anSOI substrate1 having a multilayered structure in which asilicon substrate2, an insulatinglayer3 and asilicon layer4 are layered in this order. In an upper surface of thesilicon layer4,isolation insulating films5 of partial-trench type are selectively formed. In element formation regions of theSOI substrate1 defined by theisolation insulating films5, a PMOS and an NMOS are formed.

The NMOS has n⁺-type source/drain regions28 which are formed in thesilicon layer4 and paired with each other with a p-type impurity introduction region (channel region)10 interposed therebetween. Further, the NMOS has a gate structure including a multilayered structure in which agate insulating film6 and agate electrode7 are layered in this order which is formed on theimpurity introduction region10 and thesidewalls8 formed on side surfaces of the multilayered structure.

Similarly, the PMOS has p⁺-type source/drain regions27 which are formed in thesilicon layer4 and paired with each other with an n-type impurity introduction region (channel region)9 interposed therebetween. Further, the PMOS has a gate structure including a multilayered structure in which thegate insulating film6 and thegate electrode7 are layered in this order which is formed on theimpurity introduction region9 and thesidewalls8 formed on side surfaces of the multilayered structure. Thegate electrode7 extends on theisolation insulating film5 between the PMOS and NMOS and thegate electrode7 of the PMOS and that of NMOS are formed as a unit. Furthermore. in thesilicon layer4, a p⁺-type body region12 and an n⁺-type body region11 are selectively formed.

On the NMOS, the PMOS, theisolation insulating film5 and thebody regions11 and12, theinterlayer insulating film13 is formed. On theinterlayer insulating film13,wires15,17,19 and26 are selectively formed. In theinterlayer insulating film13, contact holes14,16 and18 each filled with conductive plugs therein are selectively formed to electrically connect thewire15 and thebody region11, thewire17 and thebody region12, and thewire19 and thegate electrode7, respectively. Further, with reference toFIG. 1, thewires15 and17 are electrically connected to the source/drain regions27 and28, respectively, through contact holes (not shown) which are selectively formed in theinterlayer insulating film13 and filled with conductive plugs therein, and thewire26 is electrically connected to the source/drain regions27 and28 through contact holes (not shown) which are selectively formed in theinterlayer insulating film13 and filled with conductive plugs therein.

With reference toFIG. 2, theinterlayer insulating film20 is formed on theinterlayer insulating film13. On theinterlayer insulating film20, apower supply line21 and aground line22 are selectively formed. Both thepower supply line21 and theground line22 are formed above theisolation insulating film5. Below thepower supply line21, acomplete isolation portion23 reaching an upper surface of the insulatinglayer3 is formed in theisolation insulating film5. In other words, the semiconductor device of the first preferred embodiment comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of thesilicon layer4 and reach the upper surface of the insulatinglayer3 below thepower supply line21. Thecomplete isolation portion23 ofFIG. 2 is formed in acomplete isolation region24 ofFIG. 1 and the partial-isolation insulating film5 ofFIG. 2 is formed in apartial isolation region25 ofFIG. 1. With reference toFIG. 1, thepower supply line21 and theground line22 are electrically connected to thewires15 and17, respectively, through contact holes (not shown) which are selectively formed in theinterlayer insulating film20 and filled with conductive pluos therein.

FIGS. 3 to 16 are cross sections showing a method of manufacturing the semiconductor device in accordance with the first preferred embodiment of the present invention step by step. First prepared is theSOI substrate1 having the multilayered structure in which thesilicon substrate2, the insulatinglayer3 which is made of a silicon oxide film and has a film thickness of about 4000 angstroms and thesilicon layer4 which has a film thickness of about 2000 angstroms are layered in this order (FIG. 3). Next, asilicon oxide film30 having a thickness of about 200 angstroms is entirely formed on thesilicon layer4. After that, asilicon nitride film31 having a thickness of about 2000 angstroms is entirely formed on the silicon oxide film30 (FIG. 4).

Next, after a photoresist is entirely formed on thesilicon nitride film31, the photoresist is exposed by using a photomask (not shown) having a mask pattern corresponding to a formation layout of theisolation insulating film5. After that, the photoresist is developed to form aphotoresist32 having an opening pattern above a region in which theisolation insulating film5 is to be formed. Then, thesilicon nitride film31, thesilicon oxide film30 and thesilicon layer4 are anisotropically dry-etched with thephotoresist32 used as an etching mask. This etching is performed until thesilicon layer4 is etched up to the depth of about 500 to 1000 angstroms from its upper surface. Through this etching, arecess33 is selectively formed in the upper surface of the silicon layer4 (FIG. 5).

Next, after removing thephotoresist32, aphotoresist34 having an opening pattern above a region in which thecomplete isolation portion23 is to be formed (FIG. 6). For example, after entirely applying a positive-type photoresist, the photoresist is exposed by using a photomask (not shown) having a mask pattern with an opening portion above the region in which thecomplete isolation portion23 is to be formed, and then the photoresist in the exposed portion is removed by dissolution with a developer.

Next, thesilicon layer4 is etched with thephotoresist34 used as the etching mask. Through this etching, a bottom surface of therecess33 in the region in which thecomplete isolation portion23 is to be formed is excavated and the upper surface of the insulatinglayer3 is thereby exposed, to form arecess35. After that, thephotoresist34 is removed (FIG. 7). Subsequently, asilicon oxide film36 having a thickness of about 5000 angstroms is entirely deposited by the CVD method. Therecesses33 and35 are thereby filled with the silicon oxide film36 (FIG. 8).

Next, thesilicon oxide film36 is polished by the CMP method to be removed until an upper surface of the silicon nitride film31 (FIG. 9). Subsequently, after removing an upper portion of thesilicon oxide film36 by wet etching, thesilicon nitride film31 and thesilicon oxide film30 are removed. Through this removing, theisolation insulating film5 is obtained as thesilicon oxide film36 left in therecesses33 and35 (FIG. 10).

Next, after forming aphotoresist37 having an opening pattern above a region in which the NMOS is to be formed, animpurity38 such as boron is ion-implanted at an energy of several tens keV at a dose of several e12 cm⁻², to form theimpurity introduction region10 in thesilicon layer4. Subsequently, after removing thephotoresist37, aphotoresist39 having an opening pattern above a region in which the PMOS is to be formed and then animpurity40 such as phosphorus is ion-implanted at an energy of several hundreds keV at a dose of several e12 cm⁻², to form theimpurity introduction region9 in the silicon layer4 (FIG. 12).

Next, after thegate insulating film6 is formed on the upper surface of thesilicon layer4 by the thermal oxidation method, a polysilicon film having a thickness of about 3000 angstroms is deposited by the CVD method and the polysilicon film is patterned to form thegate electrode7. Thereby obtained is the gate structure having the multilayered structure in which thegate insulating film6 and thegate electrode7 are layered in this order (FIG. 13).

Next, after thesidewall8 is formed on the side surface of the gate structure, formed is aphotoresist41 having an opening pattern above regions in which thebody region11 and the source/drain regions28 are to be formed. After that, animpurity42 such as arsenic is ion-implanted at an energy of several tens keV at a dose of several e15 cm⁻²with thephotoresist41 and thegate electrode7 used as a mask, to form thebody region11 and the source/drain regions28 in the silicon layer4 (FIG. 14). Subsequently, after removing thephotoresist41, formed is a photoresist43 having an opening pattern above regions in which thebody region12 and the source/drain regions27 are to be formed. After that, animpurity44 such as boron fluoride (BF₂) is ion-implanted at an energy of several tens keV at a dose of several e15 cm⁻²with the photoresist43 and thegate electrode7 used as a mask, to form thebody region12 and the source/drain regions27 in the silicon layer4 (FIG. 15).

Next, after removing the photoresist43, an upper surface of thegate electrode7, upper surfaces of the source/drain regions27 and28 and an upper surface of thebody region11 are silicified to form a cobalt silicide layer (not shown). Then, after entirely depositing a silicon oxide film having a thickness of about 10000 angstroms by the CVD method, the silicon oxide film is polished by the CMP method to be removed by about 5000 angstroms and its surface is thereby planarized, to form theinterlayer insulating film13. After that, theinterlayer insulating film13 is selectively opened to form the contact holes14,16 and18, and conductive plugs are thereafter buried in the contact holes. Then, thewires15,17 and19 made of aluminum, polysilicon or the like are selectively formed on the interlayer insulating film13 (FIG. 16).

Next, after entirely depositing a silicon oxide film by the CVD method, its surface is planarized to form theinterlayer insulating film20. After that, a contact hole filled with a conductive plug therein is selectively formed in theinterlayer insulating film20 and further thepower supply line21 and theground line22 made of aluminum, polysilicon or the like are selectively formed on theinterlayer insulating film20, to obtain the structure ofFIG. 2.

Thus, in the semiconductor device of the first preferred embodiment, theisolation insulating film5 having thecomplete isolation portion23, i.e., the complete-isolation insulating film, instead of thebody region11 or the silicon portion of thesilicon layer4, is formed below thepower supply line21. For this reason, even if variation in potential of thepower supply line21 is caused by some external noise, no variation in potential of thebody region11 is caused by capacitive coupling. Therefore, even if the operating frequency of the semiconductor device is high, it is possible to appropriately prevent malfunction caused by the variation in potential of thebody region11.

The Second Preferred Embodiment

FIG. 17 is a plan view showing a structure of a semiconductor device in accordance with the second preferred embodiment of the present invention, andFIG. 18 is a cross section showing a cross-sectional structure of the semiconductor device ofFIG. 17 taken along the line L2. InFIG. 17, theinterlayer insulating films13 and20 and thesidewall8 are not shown, for convenience of illustration. As shown inFIGS. 17 and 18, the semiconductor device of the second preferred embodiment has a basic structure of the semiconductor device of the first preferred embodiment shown inFIGS. 1 and 2 and is provided with acomplete isolation portion51 below theground line22, instead of thecomplete isolation portion23 below thepower supply line21. Thecomplete isolation portion51 ofFIG. 18 is formed in acomplete isolation region50 ofFIG. 17. The structure of the semiconductor device of the second preferred embodiment other than the above is the same as that of semiconductor device of the first preferred embodiment.

The semiconductor device of the second preferred embodiment can be formed basically through the method of manufacturing the semiconductor device in accordance with the first preferred embodiment shown inFIGS. 3 to 16 step by step and by changing the mask pattern of the photomask used in the step ofFIG. 6. For example, after entirely applying a positive-type photoresist, the photoresist is exposed by using a photomask having a mask pattern with an opening portion above a region in which thecomplete isolation portion51 is to be formed, and then the photoresist in the exposed portion is removed by dissolution with a developer. Thephotoresist34 having an opening pattern above the region in which thecomplete isolation portion51 is to be formed is thereby formed.

Thus, in the semiconductor device of the second preferred embodiment, theisolation insulating film5 having thecomplete isolation portion51, i.e., the complete-isolation insulating film, instead of thebody region12 or the silicon portion of thesilicon layer4, is formed below theground line22. For this reason, even if variation in potential of theground line22 is caused by some external noise, no variation in potential of thebody region12 is caused by capacitive coupling. Therefore, even if the operating frequency of the semiconductor device is high, it is possible to appropriately prevent malfunction caused by the variation in potential of thebody region12.

The Third Preferred Embodiment

FIG. 19 is a plan view showing a structure of a semiconductor device in accordance with the third preferred embodiment of the present invention, andFIG. 20 is a cross section showing a cross-sectional structure of the semiconductor device ofFIG. 19 taken along the line L3. InFIG. 19, theinterlayer insulating films13 and20 and thesidewall8 are not shown, for convenience of illustration. As shown inFIGS. 19 and 20, the semiconductor device of the third preferred embodiment has a basic structure of the semiconductor device of the first preferred embodiment shown inFIGS. 1 and 2 and is provided with thecomplete isolation portion51 below theground line22 like in the semiconductor device of the second preferred embodiment, together with thecomplete isolation portion23 below thepower supply line21. The structure of the semiconductor device of the third preferred embodiment other than the above is the same as that of semiconductor devices of the first and second preferred embodiments.

The semiconductor device of the third preferred embodiment can be formed basically through the method of manufacturing the semiconductor device in accordance with the first preferred embodiment shown inFIGS. 3 to 16 step by step and by changing the mask pattern of the photomask used in the step ofFIG. 6. For example, after entirely applying a positive-type photoresist, the photoresist is exposed by using a photomask having a mask pattern with opening portions above regions in which thecomplete isolation portions23 and51 are to be formed, and then the photoresist in the exposed portion is removed by dissolution with a developer. Thephotoresist34 having opening patterns above the regions in which thecomplete isolation portions23 and51 are to be formed is thereby formed.

Thus, in the semiconductor device of the third preferred embodiment, theisolation insulating film5 having thecomplete isolation portions23 and51, i.e., the complete-isolation insulating film, instead of thebody regions11 and12 or the silicon portion of thesilicon layer4, is formed below thepower supply line21 and theground line22. For this reason, even if variation in potential of thepower supply line21 and theground line22 is caused by some external noise, no variation in potential of thebody regions11 and12 is caused by capacitive coupling. Therefore, even if the operating frequency of the semiconductor device is high, it is possible to appropriately prevent malfunction caused by the variation in potential of thebody regions11 and12.

The Fourth Preferred Embodiment

FIG. 21 is a plan view showing a structure of a semiconductor device in accordance with the fourth preferred embodiment of the present invention, andFIG. 22 is a cross section showing a cross-sectional structure of the semiconductor device ofFIG. 21 taken along the line L4. InFIG. 21, thesidewall8 is not shown, for convenience of illustration. As shown inFIGS. 21 and 22, the semiconductor device of the fourth preferred embodiment comprises two CMOSs55 and56 formed adjacently to each other with theisolation insulating film5 having acomplete isolation portion58 interposed therebetween. Thecomplete isolation portion58 ofFIG. 22 is formed in acomplete isolation region57 ofFIG. 21. The operating threshold voltage of theCMOS55 is lower than that of theCMOS56 and the calorific value of theCMOS55 is larger than that of theCMOS56 when the CMOSs55 and56 operate.

Thecomplete isolation portion58 of theisolation insulating film5 can be formed through the same method as that of manufacturing the semiconductor device in accordance with the first preferred embodiment shown inFIG. 6. For example, after entirely applying a positive-type photoresist, the photoresist is exposed by using a photomask having a mask pattern with an opening portion above a region in which thecomplete isolation portion58 is to be formed, and then the photoresist in the exposed portion is removed by dissolution with a developer. Thephotoresist34 having an opening pattern above the region in which thecomplete isolation portion58 is to be formed is thereby formed.

Furthermore, the invention of the fourth preferred embodiment can be combined with the inventions of the above first to third preferred embodiments for application.

Thus, in the semiconductor device of the fourth preferred embodiment, where the two CMOSs55 and56 having different operating threshold voltages are formed adjacently to each other, theisolation insulating film5 having thecomplete isolation portion58, i.e., the complete-isolation insulating film, instead of the partial-isolation insulating film, is formed between the two CMOSs55 and56. Therefore, since it is possible to suppress conduction of the heat generated in theCMOS55 to theCMOS56, unstable operation of theCMOS56 due to the heat can be appropriately prevented.

The Fifth Preferred Embodiment

FIG. 23 is a plan view showing a structure of a semiconductor device in accordance with the fifth preferred embodiment of the present invention, andFIG. 24 is a cross section showing a cross-sectional structure of the semiconductor device ofFIG. 23 taken along the line L5. InFIG. 23, thesidewall8 is not shown, for convenience of illustration. As shown inFIGS. 23 and 24, the semiconductor device of the fifth preferred embodiment comprises two CMOSs60 and61 formed adjacently to each other with theisolation insulating film5 having acomplete isolation portion63 interposed therebetween. Thecomplete isolation portion63 ofFIG. 24 is formed in acomplete isolation region62 ofFIG. 23. TheCMOSs60 and61 have different operating frequencies, and the operating frequency of theCMOS60 is higher than that of theCMOS61.

Thecomplete isolation portion63 of theisolation insulating film5 can be formed through the same method as that of manufacturing the semiconductor device in accordance with the first preferred embodiment shown inFIG. 6. For example, after entirely applying a positive-type photoresist, the photoresist is exposed by using a photomask having a mask pattern with an opening portion above a region in which thecomplete isolation portion63 is to be formed, and then the photoresist in the exposed portion is removed by dissolution with a developer. Thephotoresist34 having an opening pattern above the region in which thecomplete isolation portion63 is to be formed is thereby formed.

Furthermore, the invention of the fifth preferred embodiment can be combined with the inventions of the above first to third preferred embodiments for application.

Thus, in the semiconductor device of the fifth preferred embodiment, where the two CMOSs60 and61 having different operating frequencies are formed adjacently to each other, theisolation insulating film5 having thecomplete isolation portion63, i.e., the complete-isolation insulating film, instead of the partial-isolation insulating film, is formed between the two CMOSs60 and61.

The variation in body potential of theCMOS60 having a high operating frequency is large while the variation in body potential of theCMOS61 having a low operating frequency is small. Therefore, if the partial-isolation insulating film is formed between theCMOSs60 and61, the body potentials of theCMOSs60 and61 affect each other through thesilicon layer4 between the partial-isolation insulating film5 and the insulatingfilm3. As a result, subtle variation in characteristics caused by mutual effect of the body potentials largely affects the characteristics of the circuit itself in a circuit whose operation sensitively depends on magnitude of current such as an analog circuit and an RF circuit. In contrast, the semiconductor device of the fifth preferred embodiment, in which the complete-isolation insulating film is formed between theCMOSs60 and61, can appropriately prevent the body potentials of theCMOSs60 and61 from affecting each other.

The Sixth Preferred Embodiment

FIG. 25 is a plan view showing a structure of a semiconductor device in accordance with the sixth preferred embodiment of the present invention, andFIG. 26 is a cross section showing a cross-sectional structure of the semiconductor device ofFIG. 25 taken along the line L6. InFIG. 25, theinterlayer insulating films13 and20 and thesidewall8 are not shown, for convenience of illustration. As shown inFIGS. 25 and 26, the semiconductor device of the sixth preferred embodiment has a basic structure of the semiconductor device of the first preferred embodiment shown inFIGS. 1 and 2 and is provided with acomplete isolation portion66 below thewire19 serving as a signal input line of the CMOS, instead of thecomplete isolation portion23 below thepower supply line21. Further, thecomplete isolation portion23 ofFIG. 1 and thecomplete isolation portion51 ofFIG. 17 may be formed together with thecomplete isolation portion66. Thecomplete isolation portion66 ofFIG. 26 is formed in acomplete isolation region65 ofFIG. 25. The structure of the semiconductor device of the sixth preferred embodiment other than the above is the same as that of semiconductor device of the first preferred embodiment.

The semiconductor device of the sixth preferred embodiment can be formed basically through the method of manufacturing the semiconductor device in accordance with the first preferred embodiment shown inFIGS. 3 to 16 step by step and by changing the mask pattern of the photomask used in the step ofFIG. 6. For example, after entirely applying a positive-type photoresist, the photoresist is exposed by using a photomask having a mask pattern with an opening portion above a region in which thecomplete isolation portion66 is to be formed, and then the photoresist in the exposed portion is removed by dissolution with a developer. Thephotoresist34 having an opening pattern above the region in which thecomplete isolation portion66 is to be formed is thereby formed.

Thus, in the semiconductor device of the sixth preferred embodiment, theisolation insulating film5 having thecomplete isolation portion66, i.e., the complete-isolation insulating film below thewire19. Therefore, even if there arises fluctuation in an input signal which is inputted to the CMOS, it is possible to suppress variation in body potential due to the fluctuation. Therefore, since it is possible to suppress variation in drain current Id caused by the variation in body potential in a region where linearity of the drain current Id is needed especially in the analog circuit and the RF circuit, improvement in circuit characteristics can be ensured.

Furthermore, thoughFIGS. 25 and 26 shows the semiconductor device in which thegate electrode7 made of polysilicon and thewire19 for input made of aluminum are connected to each other through thecontact hole18, the semiconductor device in which thegate electrode7 and thewire19 for input both of which are made of polysilicon are formed as a unit may produce the same effect as above by forming the complete-isolation insulating film below thewire19.

The Seventh Preferred Embodiment

The seventh preferred embodiment proposes an automatic formation of a mask pattern of a photomask used in formation of the complete isolation portion in the method of manufacturing the semiconductor device of the above first to third and sixth preferred embodiments or the tenth to twelfth preferred embodiments discussed later, in which the complete isolation portion of the isolation insulating film is formed below the wire.

FIGS. 27(A) and 27(B),28 and29 are conceptional diagrams showing a method of forming a mask pattern in accordance with the seventh preferred embodiment of the present invention. As shown inFIG. 27(A), in awiring layout70 made in a design stage, awire formation region71 and awire non-formation region72 are represented by binary logic values “1” and “0”, respectively. In the seventh preferred embodiment, with reference to thewiring layout70, a mask pattern of a photomask is automatically formed. Specific discussion will be made below, taking a case of formation of a positive-type photoresist as an example.

First, the logic represented in thewiring layout70 is inverted to generate a design layout (not shown) for formation of a mask pattern. In the design layout thus generated, an opening portion of the mask pattern and a non-opening portion are represented by binary logic values “0” and “1”, respectively. Then, on the basis of this design layout, a photomask is formed. As shown inFIG. 27(B), a formedphotomask73 has an openingportion74 corresponding to thewire formation region71 of thewiring layout70 and anon-opening portion75 corresponding to thewire non-formation region72.

Discussion will be made below on a method of applying the above automatic formation of a mask pattern to the method of manufacturing the semiconductor device in accordance with the present invention.FIG. 28 shows aCMOS layout76 corresponding to the semiconductor device of the above first to third and sixth preferred embodiments. First, in theCMOS layout76, a forbiddenregion77 where formation of the complete isolation portion is forbidden is specified. Specifically, the periphery of a CMOS formation region including the source/drain regions27 and28 and thebody regions11 and12 is specified as the forbiddenregion77.

Next, with reference to the wiring layout on thepower supply line21, theground line22 and thewires19 and26 and theCMOS layout76 in which the forbiddenregion77 is specified, the above automatic formation of a mask pattern is applied to a region other than the forbiddenregion77, to form a photomask used in exposing the photoresist in the step ofFIG. 6. After that, an isolation insulating film having a complete isolation portion and a partial isolation portion is formed through the method of the first preferred embodiment.FIG. 29 shows only a portion in which complete isolation portion is formed among anisolation pattern78 of the isolation insulating film thus formed, as acomplete isolation region79. It can be seen fromFIG. 29 that in the region other than the forbiddenregion77 in theCMOS layout76, thecomplete isolation regions79 are formed below thepower supply line21, theground line22 and thewires19 and26.

In the above discussion, since the design layout is generated only by inverting the logic represented in thewiring layout70, the width of the complete isolation portion is equal to that of the wire. Herein, discussion will be made on a method of forming a complete isolation portion whose width is larger than that of the wire on the basis of the above automatic formation of the mask pattern.

FIGS. 30(A) to (C) and31 are conceptional diagrams showing another method of forming a mask pattern in accordance with the seventh preferred embodiment of the present invention. As shown inFIG. 30(A), in thewiring layout70, thewire formation region71 having a width W1 is represented. In generating the design layout, assuming that the width of thewire formation region71 is W2 (>W1) (in other words, the wire width is oversized), the logic of thewiring layout70 is inverted. As shown inFIG. 30(B), in adesign layout81 thus generated, an openingportion82 having the width W2 and other portion, i.e., a not-openingportion83 are represented. Then, a photomask is formed on the basis of thedesign layout81. As shown inFIG. 30(C), a formedphotomask84 has an openingportion85 having the width W2 corresponding to the openingportion82 of thedesign layout81 and a not-openingportion86 corresponding to the not-openingportion83 of thedesign layout81.

FIG. 31 shows a result of application of the above method of forming the mask pattern to the method of manufacturing the semiconductor device in accordance with the present invention. In comparison between theisolation pattern87 ofFIG. 31 and theisolation pattern78 ofFIG. 29, the width of acomplete isolation region88 of theisolation pattern87 is larger than that of thecomplete isolation region79 of theisolation pattern78.

Furthermore, in forming the design layout, by using an undersized wire width, the width of the complete isolation portion can be set smaller than the actual width of the wire.

Thus, the method of forming the mask pattern in accordance with the seventh preferred embodiment allows easy formation of a mask pattern of a photomask used in forming the complete isolation portion with reference to the wiring layout in the method of manufacturing the semiconductor device in which the complete isolation portion of the isolation insulating film is formed below the wire.

The Eighth Preferred Embodiment

FIG. 32 is a plan view showing a structure of a semiconductor device in accordance with the eighth preferred embodiment of the present invention, andFIG. 33 is a cross section showing a cross-sectional structure of the semiconductor device ofFIG. 32 taken along the line L7. In the center portion of anIC chip90, the semiconductor device of the above first to sixth preferred embodiments is incorporated as anLSI91. Further. in the peripheral portion of theIC chip90, a plurality ofbonding pads92 each made of aluminum or the like are arranged to electrically connect theLSI91 and outer elements. Thebonding pad92 is formed on theisolation insulating film20. Furthermore, the semiconductor device of the eighth preferred embodiment comprises theisolation insulating film5 having acomplete isolation portion95 which is so formed as to extend from the upper surface of thesilicon layer4 and reach the upper surface of insulatingfilm3 below a region in which thebonding pads92 are formed. Thecomplete isolation portion95 ofFIG. 33 is formed in acomplete isolation region94 ofFIG. 32.

The semiconductor device of the eighth preferred embodiment can be formed basically through the method of manufacturing the semiconductor device in accordance with the first preferred embodiment shown inFIGS. 3 to 16 step by step and by changing the mask pattern of the photomask used in the step ofFIG. 6. For example, after entirely applying a positive-type photoresist, the photoresist is exposed by using a photomask having a mask pattern with an opening portion above a region in which thecomplete isolation portion95 is to be formed, and then the photoresist in the exposed portion is removed by dissolution with a developer. Thephotoresist34 having an opening pattern above the region in which thecomplete isolation portion95 is to be formed is thereby formed.

Thus, in the semiconductor device of the eighth preferred embodiment, theisolation insulating film5 having thecomplete isolation portion95, i.e., the complete-isolation insulating film is formed below thebonding pads92. For this reason, even if some noise is propagated from the outer elements through thebonding pads92 to theIC chip90, it is possible to appropriately prevent variation in body potential caused by the noise. As a result, the linearity in the analog circuit and the RF circuit can be improved.

The Ninth Preferred Embodiment

FIG. 34 is a plan view showing a structure of a semiconductor device in accordance with the ninth preferred embodiment of the present invention, andFIG. 35 is a cross section showing a cross-sectional structure of the semiconductor device ofFIG. 34 taken along the line L8. InFIG. 34, theinterlayer insulating films13 and20 and thesidewall8 are not shown, for convenience of illustration. As shown inFIGS. 34 and 35, the semiconductor device of the ninth preferred embodiment has a basic structure of the semiconductor device of the first preferred embodiment shown inFIGS. 1 and 2 and is provided with an n⁻-type low-concentration impurity region98, instead of thecomplete isolation portion23. The low-concentration impurity region98 is formed in thesilicon layer4 between a bottom surface of theisolation insulating film5 of partial-trench type and the upper surface of the insulatingfilm3 below thepower supply line21. The low-concentration impurity region98 ofFIG. 35 is formed in a high-resistance region97 ofFIG. 34. The structure of the semiconductor device of the ninth preferred embodiment other than the above is the same as that of semiconductor device of the first preferred embodiment.

Furthermore, though a case where the invention of the ninth preferred embodiment is applied to the basic semiconductor device of the first preferred embodiment shown inFIGS. 1 and 2 has been discussed above, application is not limited to this case and there may be a case where the invention of the ninth preferred embodiment is applied to the basic semiconductor device of the second or third preferred embodiments. In this case, it is only necessary to form a p⁻-type low-concentration impurity region, instead of thecomplete isolation portion51, in thesilicon layer4 between the bottom surface of theisolation insulating film5 of partial-trench type and the upper surface of the insulatingfilm3 below theground line22.

Thus, in the semiconductor device of the ninth preferred embodiment, the n⁻-type low-concentration impurity region98 is formed below thepower supply line21. The low-concentration impurity region98, with a resistance higher than that of theimpurity introduction region10, for example, is close to an insulator in characteristics. For this reason, even if the potential of thepower supply line21 varies due to the effect of some external noise, capacitive coupling is hard to occur between the low-concentration impurity region98 and thepower supply line21. Therefore, it is possible to suppress variation in potential of thebody region11 caused by the variation in potential of thepower supply line21, and as a result, the linearity in the analog circuit and the RF circuit can be improved.

The Tenth Preferred Embodiment

FIG. 36 is a plan view showing a structure of a semiconductor device in accordance with the tenth preferred embodiment of the present invention.FIGS. 37 and 38 are cross sections showing cross-sectional structures of the semiconductor device taken along the lines L9 and L10, respectively, ofFIG. 36. In theFIG. 36, for convenience of illustration, aninterlayer insulating film131 and thesidewall8 are omitted. As shown inFIG. 36, the semiconductor device of the tenth preferred embodiment comprises an NMOS having thegate electrode7 and the source/drain regions28. Awire19a1 is connected to thegate electrode7 and a wire19b1 is connected to the source/drain regions28. The wires connected to thegate electrode7 and the wires connected to the source/drain regions28 constitute multilayer interconnection structures, respectively. Thewires19a1 and19b1 are each a first-layer wire in the lowest layer, which is formed nearest to theSOI substrate1 among a plurality of wires constituting the multilayer interconnection structure. Further, thewires19a1 and19b1 are each made of metal such as aluminum.

Referring toFIG. 37, theinterlayer insulating film131 is formed on the NMOS and theisolation insulating film5. Thewire19a1 is formed on theinterlayer insulating film131. Further, thewire19a1 is connected to thegate electrode7 through a contact hole18a1 which is selectively formed in theinterlayer insulating film131 and filled with a conductive plug therein. Below thewire19a1, acomplete isolation portion66areaching the upper surface of the insulatingfilm3 is formed in theisolation insulating film5. In other words, the semiconductor device ofFIG. 37 comprises a complete-isolation insulating film extending from the upper surface of thesilicon layer4 to reach the upper surface of the insulatingfilm3 below thewire19a1 which is the first-layer wire. Thecomplete isolation portion66ashown inFIG. 37 is formed in acomplete isolation region65ashown inFIG. 36.

Referring toFIG. 38, the wire19b1 is formed on theinterlayer insulating film131. Further, the wire19b1 is connected to the source/drain regions28 through a contact hole18b1 which is selectively formed in theinterlayer insulating film131 and filled with a conductive plug therein. Below the wire19b1, acomplete isolation portion66breaching the upper surface of the insulatingfilm3 is formed in theisolation insulating film5. In other words, the semiconductor device ofFIG. 38 comprises a complete-isolation insulating film extending from the upper surface of thesilicon layer4 to reach the upper surface of the insulatingfilm3 below the wire19b1 which is the first-layer wire. Thecomplete isolation portion66bshown inFIG. 38 is formed in acomplete isolation region65bshown inFIG. 36.

FIG. 39 is a plan view showing another structure of a semiconductor device in accordance with the tenth preferred embodiment of the present invention.FIGS. 40 and 41 are cross sections showing cross-sectional structures of the semiconductor device taken along the lines L11 and L12, respectively, ofFIG. 39. In theFIG. 39, for convenience of illustration,interlayer insulating films131 and132 and thesidewall8 are omitted. The semiconductor device ofFIG. 39 has a basic structure of the semiconductor device shown inFIG. 36 and further comprises awire19a2 connected to thewire19a1 and a wire19b2 connected to the wire19b1. As discussed above, the wires connected to thegate electrode7 and the wires connected to the source/drain regions28 constitute multilayer interconnection structures, respectively. Thewires19a2 and19b2 are second-layer wires in the layers nearest to theSOI substrate1 but thewires19a1 and19a2 which are the first-layer wires, respectively, among a plurality of wires constituting the multilayer interconnection structures. Further, thewires19a2 and19b2 are each made of metal such as aluminum.

Referring toFIG. 40, theinterlayer insulating film132 is formed on thewire19a1 and theinterlayer insulating film131. Thewire19a2 is formed on theinterlayer insulating film132. Further, thewire19a2 is connected to thewire19a1 through a contact hole18a2 which is selectively formed in theinterlayer insulating film132 and filled with a conductive plug therein. Below thewires19a1 and19a2, acomplete isolation portion66creaching the upper surface of the insulatingfilm3 is formed in theisolation insulating film5. In other words, the semiconductor device ofFIG. 40 comprises a complete-isolation insulating film extending from the upper surface of thesilicon layer4 to reach the upper surface of the insulatingfilm3 below thewire19a1 which is the first-layer wire and thewire19a2 which is the second-layer wire. Thecomplete isolation portion66cshown inFIG. 40 is formed in acomplete isolation region65cshown inFIG. 39.

Referring toFIG. 41, theinterlayer insulating film132 is formed on the wire19b1 and theinterlayer insulating film131. The wire19b2 is formed on theinterlayer insulating film132. Further, the wire19b2 is connected to the wire19b1 through a contact hole18b2 which is selectively formed in theinterlayer insulating film132 and filled with a conductive plug therein. Below the wires19b1 and19b2, acomplete isolation portion66dreaching the upper surface of the insulatingfilm3 is formed in theisolation insulating film5. In other words, the semiconductor device ofFIG. 41 comprises a complete-isolation insulating film extending from the upper surface of thesilicon layer4 to reach the upper surface of the insulatingfilm3 below the wire19b1 which is the first-layer wire and the wire19b2 which is the second-layer wire. Thecomplete isolation portion66dshown inFIG. 41 is formed in acomplete isolation region65dshown inFIG. 39.

Thus, in the semiconductor device of the tenth preferred embodiment, theisolation insulating film5 having thecomplete isolation portions66ato66d, i.e., the complete-isolation insulating film, instead of the silicon portion of thesilicon layer4, is formed below the first-layer wire or below the first-layer wire and the second-layer wire. For this reason, even if the potentials of thewires19a1 and19b1 or thewires19a1,19b1,19a2 and19b2 vary due to some external noise, no variation in potential of the body region is caused by capacitive coupling. Therefore, even if the operating frequency of the semiconductor device is high, it is possible to appropriately prevent malfunction caused by the variation in potential of the body region.

In the semiconductor device of the tenth preferred embodiment, particularly, the complete-isolation insulating film is formed below the lower wires (the first-layer wire or the first-layer wire and the second-layer wire) of the multilayer interconnection structure which are likely to affect the potential of the body region. Therefore, a great effect of preventing the malfunction is achieved. Forming the complete-isolation insulating film not only below the lower wires of the multilayer interconnection structure but also below the upper wires is possible and produces a greater effect of preventing the malfunction.

The Eleventh Preferred Embodiment

FIG. 42 is a plan view showing a structure of a semiconductor device in accordance with the eleventh preferred embodiment of the present invention. TheIC chip90 comprises a high-speed operation portion90bincorporating a circuit which operates with a high operating frequency not less than GHz order and a low-speed operation portion90aand a middle-speed operation portion90ceach incorporating a circuit which operates with an operating frequency less than GHz order. “Operating with a high operating frequency not less than GHz order” is equivalent to that a signal having a frequency not less than GHz order is propagated through thewire19a1 inFIG. 36, for example.

Among the high-speed operation portion90b, the low-speed operation portion90aand the middle-speed operation portion90c, the invention of the tenth preferred embodiment is applied only to the high-speed operation portion90b. Specifically, in the high-speed operation portion90b, the complete-isolation insulating film is formed below the lower wires of the multilayer interconnection structure and in the low-speed operation portion90aand the middle-speed operation portion90c, a partial-isolation insulating film is formed below the lower wires of the multilayer interconnection structure. The invention of the tenth preferred embodiment has to be applied to at least the high-speed operation portion90b, and may be applied to all the high-speed operation portion90b, the low-speed operation portion90aand the middle-speed operation portion90c.

A circuit which operates with a high operating frequency, generally, is more affected by some noise than a circuit which operates with a low operating frequency. In the semiconductor device of the eleventh preferred embodiment, to solve this problem. the complete-isolation insulating film is formed below the lower wires of the multilayer interconnection structure at least in the high-speed operation portion90bamong the high-speed operation portion90b, the low-speed operation portion90aand the middle-speed operation portion90cof theIC chip90. Therefore, in the semiconductor device of the eleventh preferred embodiment, it is possible to stably operate the circuit in the high-speed operation portion90bwhich is likely to be affected by some noise.

FIG. 43 is a plan view showing another structure of a semiconductor device in accordance with the eleventh preferred embodiment of the present invention. The semiconductor device ofFIG. 43 has a basic structure of the semiconductor device shown inFIG. 42 and further comprises acomplete isolation region94bsurrounding the high-speed operation portion90b. Alternately, thecomplete isolation region94bsurrounding the high-speed operation portion90bmay be formed without forming the complete-isolation insulating film below the lower wires of the multilayer interconnection structure in the high-speed operation portion90b. In thecomplete isolation region94b(i.e., the hatched portion inFIG. 43), a complete-isolation insulating film is formed. Thus, by forming the complete-isolation insulating film surrounding the high-speed operation portion90b, it is possible to avoid the effect of variation in potential of the body region in the high-speed operation portion90bon the potential of the body regions in the low-speed operation portion90aand the middle-speed operation portion90c.

The Twelfth Preferred Embodiment

FIG. 44 is a plan view showing a structure of a semiconductor device in accordance with the twelfth preferred embodiment of the present invention. TheIC chip90 comprises a plurality ofbonding pads92aconnected to an external device (not shown), aninput buffer circuit15 la connected to thebonding pads92athrough thewires152a, aninternal processing circuit150 connected to the input buffer circuit151 throughwires153a, anoutput buffer circuit151bconnected to theinternal processing circuit150 throughwires153band a plurality ofbonding pads92bconnected to theoutput buffer circuit151bthroughwires152b. Thebonding pads92bare connected to an external device (not shown). Further, theinput buffer circuit151 a and theoutput buffer circuit151bare formed in an element formation region defined by the partial-isolation insulating film5 in thesilicon layer4.

FIG. 45 is an enlarged plan view showing a connection between thebonding pad92aand theinput buffer circuit151aandFIG. 46 is a cross section showing a cross-sectional structure of the semiconductor device taken along the like L13 ofFIG. 45. In theFIG. 45, for convenience of illustration,interlayer insulating films155 to157 are omitted.

Referring toFIG. 45, theinput buffer circuit151acomprises a PMOS having a pair of p⁺ source/drain regions27, an NMOS having a pair of n⁺ source/drain regions28 and a CMOS having thegate electrode7 shared by the PMOS and the NMOS. One of the pair of the source/drain regions27 is connected to thewire15 and the other is connected to thewire153a. One of the pair of the source/drain regions28 is connected to thewire17 and the other is connected to thewire153a. Thegate electrode7 is connected to one end of awire152a1, the other end of thewire152a1 is connected to one end of awire152a2, the other end of thewire152a2 is connected to one end of awire152a3 and the other end of thewire152a3 is connected to thebonding pad92a. Thewires152a1 to152a3 are each made of metal such as aluminum.

Referring toFIG. 46, thegate electrode7 is formed on theisolation insulating film5. Theinterlayer insulating film155 is formed on thegate electrode7 and theisolation insulating film5, and thewires152a1 and153aare formed on theinterlayer insulating film155. Thewire152a1 is connected to thegate electrode7 through a contact hole154a1 which is selectively formed in theinterlayer insulating film155 and filled with a conductive plus therein. Theinterlayer insulating film156 is formed on thewires152a1 and153aand theinterlayer insulating film155, and thewire152a2 is formed on theinterlayer insulating film156. Thewire152a2 is connected to thewire152a1 through a contact hole154a2 which is selectively formed in theinterlayer insulating film156 and filled with a conductive plug therein. Theinterlayer insulating film157 is formed on thewires152a2 and theinterlayer insulating film156, and thebonding pad92aand thewire152a3 are formed on theinterlayer insulating film157. Thewire152a3 is connected to thewire152a2 through a contact hole154a3 which is selectively formed in theinterlayer insulating film157 and filled with a conductive plug therein.

Below thewires152a1 to152a3, acomplete isolation portion95areaching the upper surface of insulatingfilm3 is formed in theisolation insulating film5. In other words, the semiconductor device ofFIG. 46 comprises a complete-isolation insulating film extending from the upper surface of thesilicon layer4 to reach the upper surface of the insulatingfilm3 below thewires152a1 to152a3 connecting thebonding pad92aand theinput buffer circuit151a. Thecomplete isolation portion95ashown inFIG. 46 is formed in acomplete isolation region94ashown inFIGS. 44 and 45. Further, in the example shown inFIGS. 45 and 46, a complete-isolation insulating film is formed also below thebonding pad92a.

Similarly, the semiconductor device ofFIG. 44 comprises a complete-isolation insulating film extending from the upper surface of thesilicon layer4 to reach the upper surface of the insulatingfilm3 below thewire152bconnecting theoutput buffer circuit151band thebonding pad92b. Specifically, a complete isolation portion of theisolation insulating film5 is formed in thecomplete isolation region94bshown inFIG. 44.

Theinput buffer circuit151a, which is connected to the external device through thewire152aand thebonding pad92a, is likely to be affected by some noise inputted from the external device. In the semiconductor device of the twelfth preferred embodiment, to solve this problem, a complete-isolation insulating film is formed, instead of the silicon portion of thesilicon layer4, is formed below thewire152aconnecting thebonding pad92aand theinput buffer circuit151a. For this reason, in the semiconductor device of the twelfth preferred embodiment, even if the potential of thewire152avaries due to some noise, no variation in potential of thesilicon layer4 below thewire152ais caused by the above potential variation. As a result, it is possible to suppress propagation of the noise inputted from the external device to theinternal processing circuit150.

Similarly, theoutput buffer circuit151b, which is connected to the external device through thewire152band thebonding pad92b, is likely to be affected by some noise inputted from the external device. In the semiconductor device of the twelfth preferred embodiment, to solve this problem, a complete-isolation insulating film is formed, instead of the silicon portion of thesilicon layer4, is formed below thewire152bconnecting thebonding pad92band theoutput buffer circuit151b. For this reason, in the semiconductor device of the twelfth preferred embodiment, even if the potential of thewire152bvaries due to some noise, no variation in potential of thesilicon layer4 below thewire152bis caused by the above potential variation. As a result, it is possible to suppress propagation of the noise inputted from the external device to theinternal processing circuit150.

Further, both the complete-isolation insulating film below thewire152aand the complete-isolation insulating film below thewire152bdo not necessarily have to be formed, but either one may be formed depending on the purpose.

Furthermore, as shown inFIG. 43, a complete-isolation insulating film surrounding theinput buffer circuit151amay be further formed. This can eliminate mutual effect on the variation in body potential between theinput buffer circuit151aand theinternal processing circuit150. Similarly, a complete-isolation insulating film surrounding theoutput buffer circuit151bmay be further formed. This can eliminate mutual effect on the variation in body potential between theoutput buffer circuit151band theinternal processing circuit150.

While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.

Claims (8)

1. A semiconductor device comprising:

an SOI substrate having a structure in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order, the semiconductor substrate being in contact with the insulating layer;

a first insulating film arranged in a main surface of said semiconductor layer and not reaching said insulating layer;

a first MOS transistor arranged in an element formation region defined by said first insulating film in said semiconductor layer,

a second MOS transistor arranged adjacently to said first MOS transistor in said semiconductor layer, having an operating threshold voltage different from that of said first MOS transistor; and

a second insulation film arranged extending from said main surface of said semiconductor layer, reaching said insulating layer between said first MOS transistor and said second MOS transistor.

2. The semiconductor device according toclaim 1, further comprising:

an interlayer insulating film formed on said first semiconductor element and said first insulating film;

a signal line formed on said interlayer insulating film, being electrically connected to said first semiconductor element; wherein

said second insulating film formed extending from said main surface of said semiconductor layer, reaching an upper surface of said insulating layer below said signal line.

3. The semiconductor device according toclaim 2, wherein

said signal line is made of metal.

4. The semiconductor device according toclaim 2, wherein

said signal line is made of polysilicon.

5. A semiconductor device comprising:

an SOI substrate having a structure in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order, the semiconductor substrate being in contact with the insulating layer;

said semiconductor layer includes a first region and a second region, wherein said first region is arranged adjacently to said second region;

a first MOS transistor arranged in said first region and a second MOS transistor arranged in said second region, each of said first MOS transistor and said second MOS transistor includes a gate and a first conductivity type of source and drain region;

a first insulating film arranged in a main surface of said semiconductor layer,

said semiconductor layer between said first insulating film and said insulating layer being of a second conductivity type opposite said first conductivity type;

said first MOS transistor and said first insulating film around said first MOS transistor being arranged in said first region;

said second MOS transistor being arranged in said second region, having an operating threshold voltage different from that of said first MOS transistor; and

a second insulation film is arranged extending from said main surface of said semiconductor layer, reaching said insulating layer between said first region and said second region.

6. The semiconductor device according toclaim 5, further comprising:

an interlayer insulating film formed on said first semiconductor element and said first insulating film;

a signal line formed on said interlayer insulating film, being electrically connected to said first semiconductor element; wherein

said second insulating film is formed extending from said main surface of said semiconductor layer, reaching an upper surface of said insulating layer below said signal line.

7. The semiconductor device according toclaim 6, wherein said signal line is made of metal.

8. The semiconductor device according toclaim 6, wherein said signal line is made of polysilicon.

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