US7522529B2 - Method and system for detecting congestion and over subscription in a fibre channel network - Google Patents

Abstract

A method and system for detecting congestion and over-subscription in a fiber channel switch element is provided. A counter is updated if a frame cannot be transmitted due to lack of credit; then the counter value is compared to a threshold value; and an event is triggered if the counter value varies from the threshold value. Also, provided is a first register that maintains information regarding a rate at which a source port can transfer data; a counter that counts entries corresponding to a number of frames to be transmitted at a given time; and a second register that determines an over-subscription rate.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C.§ 119(e)(1) to the following provisional patent applications:

Filed on Sep. 19, 2003, Ser. No. 60/503,812, entitled “Method and System for Fibre Channel Switches”;

Filed on Jan. 21, 2004, Ser. No. 60/537,933 entitled “Method And System For Routing And Filtering Network Data Packets In Fibre Channel Systems”;

Filed on Jul. 21, 2003, Ser. No. 60/488,757, entitled “Method and System for Selecting Virtual Lanes in Fibre Channel Switches”;

Filed on Dec. 29, 2003, Ser. No. 60/532,965, entitled “Programmable Pseudo Virtual Lanes for Fibre Channel Systems”;

Filed on Sep. 19, 2003, Ser. No. 60/504,038, entitled “Method and System for Reducing Latency and Congestion in Fibre Channel Switches”;

Filed on Aug. 14, 2003, Ser. No. 60/495,212, entitled “Method and System for Detecting Congestion and Over Subscription in a Fibre channel Network”

Filed on Aug. 14, 2003, Ser. No. 60/495,165, entitled “LUN Based Hard Zoning in Fibre Channel Switches”;

Filed on Sep. 19, 2003, Ser. No. 60/503,809, entitled “Multi Speed Cut Through Operation in Fibre Channel Switches”

Filed on Sep. 23, 2003, Ser. No. 60/505,381, entitled “Method and System for Improving bandwidth and reducing Idles in Fibre Channel Switches”;

Filed on Sep. 23, 2003, Ser. No. 60/505,195, entitled “Method and System for Keeping a Fibre Channel Arbitrated Loop Open During Frame Gaps”;

Filed on Mar. 30, 2004, Ser. No. 60/557,613, entitled “Method and System for Congestion Control based on Optimum Bandwidth Allocation in a Fibre Channel Switch”;

Filed on Sep. 23, 2003, Ser. No. 60/505,075, entitled “Method and System for Programmable Data Dependent Network Routing”;

Filed on Sep. 19, 2003, Ser. No. 60/504,950, entitled “Method and System for Power Control of Fibre Channel Switches”;

Filed on Dec. 29, 2003, Ser. No. 60/532,967, entitled “Method and System for Buffer to Buffer Credit recovery in Fibre Channel Systems Using Virtual and/or Pseudo Virtual Lane”

Filed on Dec. 29, 2003, Ser. No. 60/532,966, entitled “Method And System For Using Extended Fabric Features With Fibre Channel Switch Elements”

Filed on Mar. 4, 2004, Ser. No. 60/550,250, entitled “Method And System for Programmable Data Dependent Network Routing”

Filed on May 7, 2004, Ser. No. 60/569,436, entitled “Method And System For Congestion Control In A Fibre Channel Switch”

Filed on May 18, 2004, Ser. No. 60/572,197, entitled “Method and System for Configuring Fibre Channel Ports” and

Filed on Dec. 29, 2003, Ser. No. 60/532,963 entitled “Method and System for Managing Traffic in Fibre Channel Switches”.

The disclosure of the foregoing applications is incorporated herein by reference in their entirety.

BACKGROUND

1. Field of the Invention

The present invention relates to fibre channel systems, and more particularly, to detecting congestion and oversubscription in fibre channel switches.

2. Background of the Invention

Fibre channel is a set of American National Standard Institute (ANSI) standards, which provide a serial transmission protocol for storage and network protocols such as HIPPI, SCSI, IP, ATM and others. Fibre channel provides an input/output interface to meet the requirements of both channel and network users.

Fibre channel supports three different topologies: point-to-point, arbitrated loop and fibre channel fabric. The point-to-point topology attaches two devices directly. The arbitrated loop topology attaches devices in a loop. The fibre channel fabric topology attaches host systems directly to a fabric, which are then connected to multiple devices. The fibre channel fabric topology allows several media types to be interconnected.

Fibre channel is a closed system that relies on multiple ports to exchange information on attributes and characteristics to determine if the ports can operate together. If the ports can work together, they define the criteria under which they communicate.

In fibre channel, a path is established between two nodes where the path's primary task is to transport data from one point to another at high speed with low latency, performing only simple error detection in hardware.

Fibre channel fabric devices include a node port or “N_Port” that manages fabric connections. The N_port establishes a connection to a fabric element (e.g., a switch) having a fabric port or F_port. Fabric elements include the intelligence to handle routing, error detection, recovery, and similar management functions.

A fibre channel switch is a multi-port device where each port manages a simple point-to-point connection between itself and its attached system. Each port can be attached to a server, peripheral, I/O (input/output) subsystem, bridge, hub, router, or even another switch. A switch receives messages from one port and automatically routes it to another port. Multiple calls or data transfers happen concurrently through the multi-port fibre channel switch.

Fibre channel switches use memory buffers to hold frames received and sent across a network. Associated with these buffers are credits, which are the number of frames a Fibre Channel port can transmit without overflowing the receive buffers at the other end of the link. Receiving an R_RDY primitive signal increases the credit, and sending a frame decreases the credit. The initial amount of credit is negotiated by two ends of the link during login. Credit counts can be implemented on a transmit port by starting at zero and counting up to the maximum, or by starting at the maximum and counting down to zero.

When using large networks, bottlenecks may occur that could reduce the performance of a network. Fibre Channel networks use flow control to make sure that for every transmitted frame there is a receive buffer at the other end of the link.

Congestion on a Fibre Channel network will prevent ports from transmitting frames while waiting for flow control signals (the R_RDY primitive signal in Fibre Channel).

In a Fabric with multiple switches, congestion may occur if more traffic is being routed through an E-port than it can handle. The use of frame counts or byte counts is not sufficient to detect congestion.

Often a fibre channel switch is coupled between devices that use varying data rates to transfer data. The mismatch in the data transfer rates can result in inefficient use of the overall bandwidth. An illustration of this problem is shown inFIG. 2.FIG. 2 showsswitches207 and209 coupled by a 10 G (gigabytes)link208.Host systems203 and202 are coupled to switch207 by 2G links204 and205, respectively.Host system201 is coupled by a 1G link206. Atarget213 is coupled to switch209 by a 1G link210, whiletargets214 and215 are coupled by 2G links211 and212, respectively. Host system may be any computing device and a target may be any device with which a host or another target can communicate.

Host203 can send data at 2 G to target213 that can receive data at 1 G. Sincetarget213 receives data at a lower rate that can overfill the receive buffers inswitch209 resulting in congestion.

As data rates increase (for example, from 1 G to 10 G), Fibre Channel networks will need efficient congestion and over subscription detection techniques. Therefore, what is required is a process and system that efficiently detects congestion and over subscription.

SUMMARY OF THE INVENTION

In one aspect of the present invention, a method for detecting congestion in a transmit side of a fibre channel switch element is provided. The method includes, updating a counter if a frame cannot be transmitted from a transmit side of a switch due to lack of credit; comparing the counter value to a threshold value; and triggering a threshold event if the counter value varies from the threshold value.

In another aspect, a method for detecting congestion on a receive segment of a fibre channel switch element is provided. The method includes, comparing a counter value to a threshold value, if a receive buffer is full; and triggering a threshold event if the counter value varies from the threshold value.

In yet another aspect of the present invention, a method for detecting congestion in a transmit segment of a fibre channel switch element is provided. The method includes, determining if credit is available for transmitting a frame; triggering an event based on a duration that the frame waits for transmission; and notifying a processor based on such event. A first counter value is compared to a threshold value to trigger the event.

In yet another aspect of the present invention, a method for detecting congestion at a receive segment of a fibre channel switch element is provided. The method includes, determining if a receive buffer has been full for a certain duration; and triggering an event if the duration varies from a threshold value.

In yet another aspect, a system for detecting congestion in a fibre channel switch element is provided. The system includes, a first counter that counts a duration for which a frame waits for transmission, and the duration is compared to a threshold value to detect congestion. The threshold value may be programmed by firmware used by the fibre channel switch element and if the first counter value is greater than the threshold value, an event is triggered.

In yet another aspect of the present invention, a system for detecting congestion at a receive segment of a fibre channel switch element is provided. The system includes, a receive buffer log that indicates how quickly frames are moving through the receive segment. The system also includes, a first counter that is incremented when a receive buffer is full and if the counter value varies from a threshold value, an event is generated; and a register that maintains count for frames that are routed to another switch element.

In yet another aspect of the present invention, a system for determining over-subscription in a transmit segment of a fibre channel switch element is provided. The system includes a first register that maintains information regarding a rate at which a source port can transfer data; a first counter that counts entries corresponding to a number of frames to be transmitted at a given time; and a second register that determines an over-subscription rate.

In yet another aspect of the present, a method for determining over-subscription in a transmit port of a fibre channel switch element is provided. The method includes, determining an over-subscription value based on a source port's data rate, a transmit port's data rate and an entry corresponding to a number of frames that are to be transmitted from the transmit port at a given time; and notifying a processor of the over-subscription rate if the over-subscription value is different from a threshold value.

This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof concerning the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing features and other features of the present invention will now be described with reference to the drawings of a preferred embodiment. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures:

FIG. 1A shows an example of a Fibre Channel network system;

FIG. 1B shows an example of a Fibre Channel switch element, according to one aspect of the present invention;

FIG. 1C shows a block diagram of a 20-channel switch chassis, according to one aspect of the present invention;

FIG. 1D shows a block diagram of a Fibre Channel switch element with sixteen GL_Ports and four 10 G ports, according to one aspect of the present invention;

FIGS.1E-1/1E-2 (jointly referred to asFIG. 1E) show another block diagram of a Fibre Channel switch element with sixteen GL_Ports and four 10 G ports, according to one aspect of the present invention;

FIG. 2 show a topology highlighting congestion and oversubscription in Fibre Channel networks;

FIGS.3A/3B (jointly referred to asFIG. 3) show a block diagram of a GL_Port, according to one aspect of the present invention;

FIGS.4A/4B (jointly referred to asFIG. 3) show a block diagram of XG_Port (10 G) port, according to one aspect of the present invention;

FIG. 5 shows a block diagram of the plural counters and registers at a transmit port, according to one aspect of the present invention;

FIG. 6 shows a process flow diagram for detecting congestion on the transmit side, according to one aspect of the present invention;

FIG. 7 is a block diagram of a system with the registers/counters used according to one aspect of the present invention to detect congestion;

FIG. 8 shows a flow diagram of a process flow diagram for detecting congestion at a receive port, according to one aspect of the present invention;

FIGS. 9A-9B show examples of how the adaptive aspects of the present invention are used to minimize congestion;

FIG. 10 shows how a counter adjustment is used, according to one aspect of the present invention;

FIG. 11 is a block diagram of an over subscription detection system/logic, according to one aspect of the present invention; and

FIG. 12 shows a flow diagram for determining over subscription, according to one aspect of the present invention; and

FIG. 13 provides a graphical illustration of how the adaptive aspects of the present invention assist in improving congestion management in Fibre Channel networks.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Definitions:

The following definitions are provided as they are typically (but not exclusively) used in the fibre channel environment, implementing the various adaptive aspects of the present invention.

“E-Port”: A fabric expansion port that attaches to another Interconnect port to create an Inter-Switch Link.

“F_Port”: A port to which non-loop N_Ports are attached to a fabric and does not include FL_ports.

“Fibre channel ANSI Standard”: The standard (incorporated herein by reference in its entirety) describes the physical interface, transmission and signaling protocol of a high performance serial link for support of other high level protocols associated with IPI, SCSI, IP, ATM and others.

“FC-1”: Fibre channel transmission protocol, which includes serial encoding, decoding and error control.

“FC-2”: Fibre channel signaling protocol that includes frame structure and byte sequences.

“FC-3”: Defines a set of fibre channel services that are common across plural ports of a node.

“FC-4”: Provides mapping between lower levels of fibre channel, IPI and SCSI command sets, HIPPI data framing, IP and other upper level protocols.

“Fabric”: A system which interconnects various ports attached to it and is capable of routing fibre channel frames by using destination identifiers provided in FC-2 frame headers.

“Fabric Topology”: This is a topology where a device is directly attached to a fibre channel fabric that uses destination identifiers embedded in frame headers to route frames through a fibre channel fabric to a desired destination.

“FL_Port”: A L_Port that is able to perform the function of a F_Port, attached via a link to one or more NL_Ports in an Arbitrated Loop topology.

“Inter-Switch Link”: A Link directly connecting the E_port of one switch to the E_port of another switch.

“Port”: A general reference to N. Sub.--Port or F.Sub.--Port.

“L_Port”: A port that contains Arbitrated Loop functions associated with the Arbitrated Loop topology.

“N_Port”: A direct fabric attached port.

“NL_Port”: A L_Port that can perform the function of a N_Port.

“Over subscription”: is defined herein as data arriving at a Fibre Channel transmit port faster than the port can transmit it. It is noteworthy that the over subscribed transmit port itself may not be congested and may be sending at its full data rate. But an over subscribed transmit port will cause congestion at the ports that are sending frames routed to the oversubscribed port.

“Switch”: A fabric element conforming to the Fibre Channel Switch standards.

“VL”: Virtual Lane: A portion of the data path between a source and destination port.

Fibre Channel System:

To facilitate an understanding of the preferred embodiment, the general architecture and operation of a fibre channel system will be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general architecture of the fibre channel system.

FIG. 1A is a block diagram of afibre channel system100 implementing the methods and systems in accordance with the adaptive aspects of the present invention.System100 includes plural devices that are interconnected. Each device includes one or more ports, classified as node ports (N_Ports), fabric ports (F_Ports), and expansion ports (E_Ports). Node ports may be located in a node device,e.g. server103,disk array105 andstorage device104. Fabric ports are located in fabric devices such asswitch101 and102. Arbitratedloop106 may be operationally coupled to switch101 using arbitrated loop ports (FL_Ports).

The devices ofFIG. 1A are operationally coupled via “links” or “paths”. A path may be established between two N_ports, e.g. betweenserver103 andstorage104. A packet-switched path may be established using multiple links, e.g. an N-Port inserver103 may establish a path withdisk array105 throughswitch102.

Fabric Switch Element

FIG. 1B is a block diagram of a 20-port ASIC fabric element according to one aspect of the present invention.FIG. 1B provides the general architecture of a 20-channel switch chassis using the 20-port fabric element. Fabric element includesASIC20 with non-blocking fibre channel class2 (connectionless, acknowledged) and class3 (connectionless, unacknowledged) service between any ports. It is noteworthy thatASIC20 may also be designed for class1 (connection-oriented) service, within the scope and operation of the present invention as described herein.

The fabric element of the present invention is presently implemented as a single CMOS ASIC, and for this reason the term “fabric element” and ASIC are used interchangeably to refer to the preferred embodiments in this specification. AlthoughFIG. 1B shows 20 ports, the present invention is not limited to any particular number of ports.

ASIC20 has 20 ports numbered inFIG. 1B as GL0 through GL19. These ports are generic to common Fibre Channel port types, for example, F_Port, FL_Port and E-Port. In other words, depending upon what it is attached to, each GL port can function as any type of port. Also, the GL port may function as a special port useful in fabric element linking, as described below.

For illustration purposes only, all GL ports are drawn on the same side ofASIC20 inFIG. 1B. However, the ports may be located on both sides ofASIC20 as shown in other figures. This does not imply any difference in port or ASIC design. Actual physical layout of the ports will depend on the physical layout of the ASIC.

Each port GL0-GL19 has transmit and receive connections to switchcrossbar50. One connection is through receive buffer52, which functions to receive and temporarily hold a frame during a routing operation. The other connection is through a transmitbuffer54.

Switch crossbar50 includes a number of switch crossbars for handling specific types of data and data flow control information. For illustration purposes only,switch crossbar50 is shown as a single crossbar.Switch crossbar50 is a connectionless crossbar (packet switch) of known conventional design, sized to connect 21×21 paths. This is to accommodate 20 GL ports plus a port for connection to a fabric controller, which may be external toASIC20.

In the preferred embodiments of switch chassis described herein, the fabric controller is a firmware-programmed microprocessor, also referred to as the input/out processor (“IOP”).IOP66 is shown inFIG. 1C as a part of a switch chassis utilizing one or more ofASIC20. As seen inFIG. 1B, bi-directional connection toIOP66 is routed throughport67, which connects internally to acontrol bus60. Transmit buffer56, receivebuffer58, control register62 and Status register64 connect tobus60. Transmit buffer56 and receivebuffer58 connect the internalconnectionless switch crossbar50 toIOP66 so that it can source or sink frames.

Control register62 receives and holds control information fromIOP66, so thatIOP66 can change characteristics or operating configuration ofASIC20 by placing certain control words inregister62.IOP66 can read status ofASIC20 by monitoring various codes that are placed instatus register64 by monitoring circuits (not shown).

FIG. 1C shows a 20-channel switch chassisS2 using ASIC20 andIOP66. S2 will also include other elements, for example, a power supply (not shown). The 20 GL ports correspond to channel C0-C19. Each GL port has a serial/deserializer (SERDES) designated as S0-S19. Ideally, the SERDES functions are implemented onASIC20 for efficiency, but may alternatively be external to each GL port.

Each GL port has an optical-electric converter, designated as OE0-OE19 connected with its SERDES through serial lines, for providing fibre optic input/output connections, as is well known in the high performance switch design. The converters connect to switch channels C0-C19. It is noteworthy that the ports can connect through copper paths or other means instead of optical-electric converters.

FIG. 1D shows a block diagram ofASIC20 with sixteen GL ports and four 10 G (Gigabyte) port control modules designated as XG0-XG3 for four 10 G ports designated as XGP0-XGP3.ASIC20 include acontrol port62A that is coupled toIOP66 through aPCI connection66A.

FIG.1E-1/1E-2 (jointly referred to asFIG. 1E) show yet another block diagram ofASIC20 with sixteen GL and four XG port control modules. Each GL port control module has a Receive port (RPORT)69 with a receive buffer (RBUF)69A and a transmitport70 with a transmit buffer (TBUF)70A, as described below in detail. GL and XG port control modules are coupled to physical media devices (“PMD”)76 and75 respectively.

Control port module62A includescontrol buffers62B and62D for transmit and receive sides, respectively.Module62A also includes aPCI interface module62C that allows interface withIOP66 via aPCI bus66A.

XG_Port (for example74B) includesRPORT72 withRBUF71 similar to RPORT69 andRBUF69A and a TBUF and TPORT similar toTBUF70A andTPORT70.Protocol module73 interfaces with SERDES to handle protocol based functionality.

GL Port:

FIGS. 3A-3B (referred to asFIG. 3) show a detailed block diagram of a GL port as used inASIC20.GL port300 is shown in three segments, namely, receive segment (RPORT)310, transmit segment (TPORT)312 andcommon segment311.

Receive Segment of GL Port:

Frames enter throughlink301 andSERDES302 converts data into 10-bit parallel data to fibre channel characters, which are then sent to receive pipe (“Rpipe” or “Rpipe1” or “Rpipe2”)303A via a de-multiplexer (DEMUX)303.Rpipe303A includes,parity module305 anddecoder304.Decoder304 decodes10B data to8B andparity module305 adds a parity bit.Rpipe303A also performs various Fibre Channel standard functions such as detecting a start of frame (SOF), end-of frame (EOF), Idles, R_RDYs (fibre channel standard primitive) and the like, which are not described since they are standard functions.

Rpipe303A connects to smoothing FIFO (SMF)module306 that performs smoothing functions to accommodate clock frequency variations between remote transmitting and local receiving devices.

Frames received byRPORT310 are stored in receive buffer (RBUF)69A, (except for certain Fibre Channel Arbitrated Loop (AL) frames).Path309 shows the frame entry path, and allframes entering path309 are written toRBUF69A as opposed to theAL path308.

Cyclic redundancy code (CRC)module313 further processes frames that enterGL port300 by checking CRC and processing errors according to FC_PH rules. The frames are subsequently passed toRBUF69A where they are steered to an appropriate output link.RBUF69A is a link receive buffer and can hold multiple frames.

Reading from and writing toRBUF69A are controlled by RBUF read control logic (“RRD”)319 and RBUF write control logic (“RWT”)307, respectively.RWT307 specifies whichempty RBUF69A slot will be written into when a frame arrives through the data link viamultiplexer313B, CRC generate module313A and EF (external proprietary format)module314.EF module314 encodes proprietary (i.e. non-standard) format frames to standard Fibre Channel8B codes.Mux313B receives input fromRx Spoof module314A, which encodes frames to a proprietary format (if enabled).RWT307 controlsRBUF69A write addresses and provide the slot number to tag writer (“TWT”)317.

RRD319 processes frame transfer requests fromRBUF69A. Frames may be read out in any order and multiple destinations may get copies of the frames.

Steering state machine (SSM)316 receives frames and determines the destination for forwarding the frame.SSM316 produces a destination mask, where there is one bit for each destination. Any bit set to a certain value, for example, 1, specifies a legal destination, and there can be multiple bits set, if there are multiple destinations for the same frame (multicast or broadcast).

SSM316 makes this determination using information fromalias cache315, steering registers316A, control register326 values and frame contents.IOP66 writes all tables so that correct exit path is selected for the intended destination port addresses.

The destination mask fromSSM316 is sent toTWT317 and a RBUF tag register (RTAG)318.TWT317 writes tags to all destinations specified in the destination mask fromSSM316. Each tag identifies its corresponding frame by containing anRBUF69A slot number where the frame resides, and an indication that the tag is valid.

Each slot inRBUF69A has an associated set of tags, which are used to control the availability of the slot. The primary tags are a copy of the destination mask generated bySSM316. As each destination receives a copy of the frame, the destination mask inRTAG318 is cleared. When all the mask bits are cleared, it indicates that all destinations have received a copy of the frame and that the corresponding frame slot inRBUF69A is empty and available for a new frame.

RTAG318 also has frame content information that is passed to a requesting destination to pre-condition the destination for the frame transfer. These tags are transferred to the destination via a read multiplexer (RMUX) (not shown).

Transmit Segment of GL Port:

Transmit segment (“TPORT”)312 performs various transmit functions. Transmit tag register (TTAG)330 provides a list of all frames that are to be transmitted.Tag Writer317 orcommon segment311write TTAG330 information. The frames are provided to arbitration module (“transmit arbiter” (“TARB”))331, which is then free to choose which source to process and which frame from that source to be processed next.

TTAG330 includes a collection of buffers (for example, buffers based on a first-in first out (“FIFO”) scheme) for each frame source.TTAG330 writes a tag for a source andTARB331 then reads the tag. For any given source, there are as many entries inTTAG330 as there are credits inRBUF69A.

TARB331 is activated anytime there are one or more valid frame tags inTTAG330.TARB331 preconditions its controls for a frame and then waits for the frame to be written intoTBUF70A. After the transfer is complete,TARB331 may request another frame from the same source or choose to service another source.

TBUF70A is the path to the link transmitter. Typically, frames don't land inTBUF70A in their entirety. Mostly, frames simply pass throughTBUF70A to reach output pins, if there is a clear path.

Switch Mux332 is also provided to receive output fromcrossbar50.Switch Mux332 receives input from plural RBUFs (shown as RBUF00 to RBUF19), and input fromCPORT62A shown asCBUF1 frame/status.TARB331 determines the frame source that is selected and the selected source provides the appropriate slot number. The output fromSwitch Mux332 is sent toALUT323 for S_ID spoofing and the result is fed intoTBUF Tags333.

TMUX (“TxMux”)339 chooses which data path to connect to the transmitter. The sources are: primitive sequences specified byIOP66 via control registers326 (shown as primitive339A), and signals as specified by Transmit state machine (“TSM”)346, frames following the loop path, or steered frames exiting the fabric viaTBUF70A.

TSM346 chooses the data to be sent to the link transmitter, and enforces all fibre Channel rules for transmission.TSM346 receives requests to transmit fromloop state machine320,TBUF70A (shown asTARB request346A) and from variousother IOP66 functions via control registers326 (shown asIBUF Request345A).TSM346 also handles all credit management functions, so that Fibre Channel connectionless frames are transmitted only when there is link credit to do so.

Loop state machine (“LPSM”)320 controls transmit and receive functions when GL_Port is in a loop mode.LPSM320 operates to support loop functions as specified by FC-AL-2.

IOP buffer (“IBUF”)345 providesIOP66 the means for transmitting frames for special purposes.

Frame multiplexor (“Frame Mux” or “Mux”)336 chooses the frame source, while logic (TX spoof334) converts D_ID and S_ID from public to private addresses.Frame Mux336 receives input fromTx Spoof module334, TBUF tags333, andMux335 to select a frame source for transmission.

EF module338 encodes proprietary (i.e. non-standard) format frames to standard Fibre Channel8B codes andCRC module337 generates CRC data for the outgoing frames.

Modules340-343 put a selected transmission source into proper format for transmission on anoutput link344.Parity340 checks for parity errors, when frames are encoded from8B to10B byencoder341, marking frames “invalid”, according to Fibre Channel rules, if there was a parity error. Phase FIFO342A receives frames from encodemodule341 and the frame is selected byMux342 and passed toSERDES343.SERDES343 converts parallel transmission data to serial before passing the data to the link media.SERDES343 may be internal or external toASIC20.

Common Segment of GL Port:

As discussed above,ASIC20 includecommon segment311 comprising of various modules.LPSM320 has been described above and controls the general behavior ofTPORT312 andRPORT310.

A loop look up table (“LLUT”)322 and an address look up table (“ALUT”)323 is used for private loop proxy addressing and hard zoning managed by firmware.

Common segment311 also includes control register326 that controls bits associated with a GL_Port,status register324 that contains status bits that can be used to trigger interrupts, and interrupt mask register325 that contains masks to determine the status bits that will generate an interrupt toIOP66.Common segment311 also includes AL control andstatus register328 and statistics register327 that provide accounting information for FC management information base (“MIB”).

Output fromstatus register324 may be used to generate a Fp Peek function. This allows astatus register324 bit to be viewed and sent to the CPORT.

Output fromcontrol register326, statistics register327 and register328 (as well as328A for an X_Port, shown inFIG. 4) is sent toMux329 that generates an output signal (FP Port Reg Out).

Output from Interruptregister325 andstatus register324 is sent tologic335 to generate a port interrupt signal (FP Port Interrupt).

BIST module321 is used for conducting embedded memory testing.

XG Port

FIGS. 4A-4B (referred to asFIG. 4) show a block diagram of a 10 G Fibre Channel port control module (XG FPORT)400 used inASIC20. Various components ofXG FPORT400 are similar to GLport control module300 that are described above. For example,RPORT310 and310A,Common Port311 and311A, andTPORT312 and312A have common modules as shown inFIGS. 3 and 4 with similar functionality.

RPORT310A can receive frames from links (or lanes)301A-301D and transmit frames tolanes344A-344D. Each link has a SERDES (302A-302D), a de-skew module, a decode module (303B-303E) and parity module (304A-304D). Each lane also has a smoothing FIFO (SMF)module305A-305D that performs smoothing functions to accommodate clock frequency variations. Parity errors are checked bymodule403, while CRC errors are checked bymodule404.

RPORT310A uses a virtual lane (“VL”)cache402 that stores plural vector values that are used for virtual lane assignment. In one aspect of the present invention,VL Cache402 may have 32 entries and two vectors per entry.IOP66 is able to read or writeVL cache402 entries during frame traffic.State machine401 controls credit that is received. On the transmit side,credit state machine347 controls frame transmission based on credit availability.State machine347 interfaces withcredit counters328A.

Also on the transmit side, modules340-343 are used for eachlane344A-344D, i.e., each lane can have its own module340-343.Parity module340 checks for parity errors and encodemodule341 encodes 8-bit data to 10 bit data. Mux342B sends the 10-bit data to a smoothing (“TxSMF”)module342 that handles clock variation on the transmit side.SERDES343 then sends the data out to the link.

Congestion Detection:

In one aspect of the present invention, the following set of counters and status registers can be used to detect congestion, both at the transmit and receive side.

TPORT Congestion:

The following describes various registers/counters that are used to detect congestion atTPORT312A:

“Transmit Wait Count Register”: This register increments each time a frame is available for transmission but cannot be transmitted due to lack of credit. This time interval may be the time needed to transmit, for example, one word (32 bits).

“Transmit Wait Count Rollover Event”: This status event is set when the transmit wait count register rolls over from its maximum value to zero. This can be set to cause an interrupt toIOP66.

“Transmit wait Count Threshold Register”(FIG. 5,508): This register contains a count that is compared to the transmit wait count threshold counter value.IOP66 can program the register.

“Transmit Wait Count Threshold Counter”(FIG. 5,507): This register increments each time a frame is ready to be transmitted but cannot due to lack of credit. It decrements each time the above condition is not true. If the counter is at its maximum value, then it does not increment. If the counter is at zero, then it does not decrement.

“Transmit Wait Count Threshold Event Status”: This event occurs when the transmit wait count threshold counter value exceeds a threshold value programmed in the transmit wait count threshold register (508). This denotes that frames have been waiting to transmit based on a threshold value. The event can be used to trigger an interrupt toIOP66.

“Congestion count adjustment” (FIG. 5,modules513 and514, &FIG. 10):Logic modules513 and514 allow the rate of counting up or down to be adjusted with a programmed value.Module513 adjusts the rate of counting up, whilemodule514 adjusts the rate of counting down.

FIG. 5 shows a block diagram of the plural counters and registers atTPORT312A that have been described above.FIG. 5 shows signal501 to transfer frames and a “no credit”signal502.Signal501 and502 are sent tologic503. A count up signal504 (from logic513) and count down signal506 (from inverter505) are sent to transmitwait threshold counter507.Counter507 is incremented for each period a frame is ready to be transmitted (signal501) and cannot be transmitted due to lack of credit (signal502). This period could be set to the amount of time required to transmit one word of the frame.

Register508 includes a threshold value that can be programmed byIOP66 using the firmware (or hard coded).Register508output512 and counter507output511 is compared (by logic509), and if the counter value (511) is greater than the threshold value (512) then the threshold wait count event is set, which results in an interrupt to IOP66 (510).

To extend the range of values that can be compared without having to increase the number of bits for threshold count inmodule508, comparemodule509, and counter507 include more bits than the threshold count. Thencounter output511 is shifted down by a programmable number of bits. For instance, ifcounter507 is 2 bits longer thanthreshold count508, then shiftingcounter output511 is shifted down 1 or 2 bits, divides the counter output by 2 or 4, making the range available for the threshold count larger by a factor of 2 or 4, but losing precision in the lowest 1 or 2 bits of the counter.

FIG. 10 shows how counter adjustment is used to change the rate when the wait count goes up or down. The adjustlevel module1001 is programmed by firmware to include a certain adjustment level value. The adjustcounter1002 is incremented whenever a count up signal (if adjusting count up fromFIG. 5,503) or count down signal (if adjusting count down fromFIG. 5,505) is set. The values inmodules1001 and1002 are compared bymodule1003, with the output set, if1002 is greater than or equal to1001.

The output ofmodule1003 is “ANDED” with the original signal by1004 to provide the “adjusted count up” or “count down” output. The adjusted count rolls over when incremented past its maximum (depending on number of bits in count). The result is to change the rate of count up or count down, depending on the adjusted level value and the number of bits in the counter. If there are n bits in the counter, the rate of count signals is modified as follows:
C=r*(1−(a/2**n))

Where C is the effective count rate (rate of signals inFIG. 5,504 or506), r is the raw count rate (rate of signals inFIG. 5 from503 or505), and “a” is the programmed adjust level frommodule1001, which is less than 2**n. In one aspect of the present invention, a 4 bit counter is used for most cases, although the invention is not limited to any particular bit size or counter value.

FIG. 6 is a flow diagram of executable steps for detecting congestion on the transmit side (TPORT312A), according to one aspect of the present invention.

In step S600, frames (or signal to transmit frames) are received for transmission. In step S601, the process determines if credit is available to transmit the frame. If credit is available, then in step S603, the frame is sent andcounter507 is decremented or cleared.

If no credit is available, then in step S602,counter507 is incremented.

In step S604, the process compares counter507value511 to athreshold value512 that can be programmed by firmware inregister508. If thecounter value511 is greater thanthreshold value512, then in step S605, a wait count event is triggered. This can be an interrupt toIOP66 and denotes congestion.

Ifcounter value511 is less thanthreshold value512, then the process goes back to step S601.

RPORT Congestion:

The following describes various registers/counters that are used to detect congestion atRPORT310A:

“Receive Buffer Full Status”: This status is set when all buffers (RBUF69A) for a port are full.

If the credit mechanism per Fibre Channel standards is operative thenTPORT312A cannot transmit because of lack of credit. This status can be programmed by firmware to cause an interrupt forIOP66.

“Receive Buffer Full Threshold Register” (FIG. 7,706): This register maintains a count that is compared to “Receive Buffer Full threshold Counter” value.

“Receive Buffer Full Threshold Counter” (FIG. 7,705): This counter is incremented every time the receive buffers (69A) are full. The counters decrement when the buffer is not full. If the counter is at its maximum value, it stops incrementing. If the counter is at zero, it stops decrementing.

“Receive Buffer Full Threshold Event Status” (709): This event happens if the receive buffer full threshold counter value exceeds the programmed (or hard coded) receive buffer full threshold register value. This occurs if received frames cannot be moved to their destination for a certain period. This event can be used to generate an interrupt forIOP66.

“Receive Buffer Log”: A buffer log can be kept inRBUF69A. The log includes the upper 16 bits of the source and destination addresses (S_ID and D_ID) of the frames that are received inRBUF69A, and the status indicating if data is valid. If the frames are forwarded rapidly, the log values will change quickly. However, due to congestion, if frames do not move quickly, then these values do not change rapidly. Sampling the log values provides a statistical sample of frame sources and destinations at a port. The log allows identifying the destination(s) that are congested. The log can be sent upstream to a device so that the upstream device can alter routing based on congestion.

“E-Port Frame In Count Register”: This register located inCPORT311A, counts received frames that are routed to an E_Port to go to another switch. By comparing this register count to the overall received frame count at a port; the percentage of frames going to another switches, versus local destinations can be determined.

FIG. 7 is a block diagram ofsystem708 showing the registers/counters used according to one aspect of the present invention to detect congestion. A receive bufferfull signal701 is received and based upon that (count up signal704)counter705 is incremented.Counter705 is also decreased (signal703 received via inverter702) when a frame leaves the receive buffer.

Register706 can be programmed with a threshold value by firmware.Counter705 generates avalue710 that is compared withregister706threshold value711. Ifcounter value710 is greater thanthreshold value711, then a “receive buffer full” event is triggered (709). This can be used to generate an interrupt forIOP66.

FIG. 8 shows a flow diagram of a process flow diagram for detecting congestion atRPORT310A, according to one aspect of the present invention. In step S801, the process determines if the receive buffer is full. If the buffer is not full, then in step S802,counter705 is decremented.

If the buffer is full, then in step S803,counter705 is incremented.

In step S804, counter705value710 is compared withthreshold value711. If thecounter value710 is greater thanthreshold value711, then a threshold event is set in step S805, otherwise, the process goes back to step S801.

FIGS. 9A-9B show examples of how the adaptive aspects of the present invention can be used. InFIG. 9A, if some local ports in switches A and B send large amount of data to switch C, and most of the traffic uses link1 between A and C passing throughswitch B. Link2 does not have enough bandwidth for the traffic. In this scenario, the E-Port on switch B-side oflink1 and the local ports on switch B sending to switch C will get receive buffer full threshold events. The E-Port on the side of switch A side oflink1 will get transmit wait count threshold events.

Based on the foregoing adaptive aspects of the present invention, one possible improvement would be to route traffic from A to C overlink3 or to add another link between switches B and C. These improvements are possible because the various counters and registers above can detect congestion in the links.

FIG. 9B shows that local ports on Switch A get receive buffer full threshold events. The E_Port “frame in count” for those local ports can be sampled and compared to the total received frame count. If most frames are going from switch A to switch B, congestion can be relieved by adding links between switches A and B. If most of the frames are going to local destinations, then performance is not limited by the switch fabric, but by the number of devices being used.

Over Subscription Detection:

The following describes various registers/counters that are used to detect over subscription atTPORT312A. In one aspect, the register/counters are implemented in TTAG330:

“Port Rate” register: This register includes the receive speed of the source port associated with that TTAG FIFO.

“Port TTAG Entry Count” counter: This counter provides the number of TTAG FIFO entries representing frames to be transmitted, currently in the TTAG FIFO for a source port.

“Calculate Over Subscription” Register: This register calculates the amount of over subscription by multiplying the port TTAG entry count by the source port rate, adding the result for all ports, then dividing the total by the transmit port's speed rate. If there are n source ports, and if Rx is the rate of source port x, Fx is the number of frames in the TTAG FIFO, and T is the transmit rate for the transmit port, then over subscription is provided by:
((R0*F0)+(R1*F1)+ . . . (R(n−1)*F(n−1)))/T

“Threshold” Value: This value is programmed by firmware and is compared to the calculated over subscription value. If the calculated over subscription value is greater than or equal to the threshold value, then the over subscription status is set. The status is used by firmware and may cause an interrupt forIOP66.

FIG. 11 is a block diagram of the over subscription detection system/logic1100.System1100 may be located inTTAG330. Each TTAG FIFO1106 includes entries representing frames from a particular source port ready for transmission.Port rate1101 includes the rate corresponding to a particular source port. The portTTAG entry count1102 contains the number of TTAG FIFO entries for a particular source port. To calculate over subscription,module1103 calculates the sum of the products of each port's TTAG count and rate, and divides the sum by the transmit port speed rate. Comparemodule1105 compares the result frommodule1103 with the programmed threshold value in module (or register)1104. Ifmodule1103 output is greater than the threshold value inmodule1104, astatus signal1107 is set.

If integer arithmetic is used, any result of the over subscription calculation between 1 and 2 may be rounded down to 1. To increase precision, the sum of the products of the port TTAG counts and rates can be shifted up by 2 or 3 bits (multiplying by 4 or 8) before the division by the transmit rate. Over subscription is determined by:
(((R0*F0)+(R1*F1)+ . . . (R(n−1)*F(n−1))*4)/T

The value selected frommodule1104 takes the foregoing into account.

FIG. 12 shows a flow diagram for determining over subscription.Step1201 initializes the calculation.Step1202 calculates the product of the TTAG FIFO count and the rate for a source port, and is repeated for each port by going throughsteps1203 and1204 until all ports have been added.Step1205 finishes the calculation by dividing the sum by the transmit port rate. The compare instep1206 causes the over subscription status to be set instep1207 if the calculated number is greater than the programmed threshold.

The raw values i.e., (R0*F0) . . . (R(n−1)*F(n−1)) are available toIOP66 as status and used in the determination of which ports have how much over subscription.

It is noteworthy that the term “signal” as used in the foregoing description includes firmware/software commands.

In one aspect of the present invention, congestion can be detected in fibre channel switches and routing changes can be made to improve the overall performance of the networks.

FIG. 13 provides a graphical illustration of how the foregoing adaptive aspects of the present invention assist in improving congestion management.

Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure and the following claims.

Claims (10)

What is claimed is:

1. A system for detecting congestion at a receive segment of a port of a fibre channel switch element, comprising:

a counter at the receive segment that is incremented when an indicator is set indicating that a receive buffer at the receive segment is full; wherein the receive buffer is used for temporarily storing fibre channel frames at the receive segment;

a threshold register for storing a threshold value for detecting congestion at the receive segment; wherein an output value from the counter is compared with the threshold value and if the output value is greater than the threshold value, then congestion is detected at the receive segment; and

a receive buffer log that stores a destination identifier value and a source identifier value for frames received at the receive segment; and the rate at which the receive buffer log changes, indicates how quickly frames are moving through the receive segment to a transmit segment of the port.

2. The system ofclaim 1, wherein a threshold event is triggered if the output from the counter is greater than the threshold value; and the threshold event generates an interrupt for a processor of the fibre channel switch element, notifying the processor of congestion at the receive segment of the port.

3. The system ofclaim 1, further comprising:

a register that maintains count for frames that are routed to another switch element and by comparing the register count with an overall received frame count, a percentage of frames that are routed within the fibre channel switch element is determined.

4. A system for determining over-subscription in a transmit segment of a port of a fibre channel switch element, comprising:

an over-subscription module that receives information regarding a rate at which a plurality of source ports transmit frames and a number of frames that are waiting to be transmitted by the plurality of source ports, at any given time;

wherein the over-subscription rate is determined by the following:

((R0*F0)+(R1*F1)+ . . . (R(n−1)*F(n−1)))/T;

 where “n” is a number of the plurality of source ports, “R” is a rate at which the plurality of source ports operate, “T” is a number of frames that are waiting to be transmitted at any given time, and “T” is a transmit rate for the transmit segment;

wherein the transmit segment is over-subscribed if frames arrive faster than a rate at which the transmit segment transmit the frames.

5. The system ofclaim 4, further comprising:

a register that stores information regarding a rate at which the plurality of source ports transfer data; and

a counter that counts entries indicating a number of frames waiting to be transmitted at each of the plurality of source ports, at any given time;

wherein values from the register and the counter are input into the over-subscription module for determining the over-subscription rate.

6. The system ofclaim 4, wherein the determined over-subscription value is compared to a stored threshold value and if the determined over-subscription value is greater than the threshold value, then an over-subscription status is set for the port.

7. A method for determining over-subscription in a transmit segment of a port for a fibre channel switch element, comprising:

determining an over-subscription value based on following:

((R0*F0)+(R1*F1)+ . . . (R(n−1)*F(n−1)))/T;

 where “n” is a number of a plurality of source ports sending frames to the port, “R” is a rate at which the plurality of source ports operate, “F” is a number of frames that are waiting to be transmitted at any given time, and “T” is a transmit rate for the transmit segment;

wherein the transmit segment is over-subscribed if frames arrive faster than a rate at which the transmit segment transmits the frames; and

notifying a processor for the fibre channel switch element of the over-subscription, if the determined over-subscription value is different from a stored threshold value.

8. The method ofclaim 7, wherein the threshold value is programmable.

9. The method ofclaim 7, wherein a register stores information regarding a rate at which the plurality of source ports transfer data; and a counter counts entries indicating a number of frames waiting to be transmitted at each of the plurality of source ports, at any given time; wherein values from the register and the counter are input into an over-subscription module for determining the over-subscription value.

10. The method ofclaim 7, wherein if the determined over-subscription value is greater than the threshold value, then an over-subscription status is set for the port.

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