US7510943B2 - Semiconductor devices and methods of manufacture thereof - Google Patents

Abstract

A first gate dielectric of a first transistor is disposed over a workpiece in a first region, and a second gate dielectric of a second transistor is disposed over the workpiece in a second region. The second gate dielectric comprises a different material than the first gate dielectric. A first dopant-bearing metal comprising a first dopant is disposed in recessed regions of the workpiece proximate the first gate dielectric, and a second dopant-bearing metal comprising a second dopant is disposed in recessed regions of the workpiece proximate the second gate dielectric. A first doped region comprising the first dopant is disposed in the workpiece adjacent the first dopant-bearing metal. A second doped region comprising the second dopant is disposed in the workpiece adjacent the second dopant-bearing metal. The dopant-bearing metals and the doped regions comprise source and drain regions of the first and second transistors.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application relates to the following co-pending and commonly assigned patent applications: Ser. No. 11/187,197, filed on Jul. 21, 2005, entitled, “CMOS Transistors With Dual High-k Gate Dielectric and Methods of Manufacture Thereof”; Ser. No. 10/870,616, filed on Jun. 17, 2004, entitled, “CMOS Transistor With Dual High-k Gate Dielectric and Method of Manufacture Thereof”; Ser. No. 11/017,062, filed on Dec. 20, 2004, entitled, “Transistor Device and Method of Manufacture Thereof”; and Ser. No. 11/005,292, filed on Dec. 6, 2004, entitled, “CMOS Transistor and Method of Manufacture Thereof,” which applications are hereby incorporated herein by reference.

TECHNICAL FIELD

The present invention relates generally to the fabrication of semiconductor devices, and more particularly to transistor devices and the fabrication thereof.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating (or dielectric) layers, conductive layers and semiconductive layers of material over a semiconductor substrate, and patterning the various layers using lithography to form circuit components and elements thereon.

A transistor is an element that is utilized extensively in semiconductor devices. There may be millions of transistors on a single integrated circuit (IC), for example. A common type of transistor used in semiconductor device fabrication is a metal oxide semiconductor field effect transistor (MOSFET).

Early MOSFET processes used one type of doping to create either positive or negative channel transistors. More recent designs, referred to as complementary metal oxide semiconductor (CMOS) devices, use both positive and negative channel devices in complementary configurations. While this requires more manufacturing steps and more transistors, CMOS devices are advantageous because they utilize less power, and the devices may be made smaller and faster.

The gate dielectric for MOSFET devices has in the past typically comprised silicon dioxide, which has a dielectric constant of about 3.9. However, as devices are scaled down in size, using silicon dioxide as a gate dielectric material becomes a problem because of gate leakage current, which can degrade device performance. Therefore, there is a trend in the industry towards the development of the use of high dielectric constant (k) materials for use as the gate dielectric material of MOSFET devices. The term “high k material” as used herein refers to a dielectric material having a dielectric constant of about 4.0 or greater. If high k materials are successfully implemented in transistor designs, the effective oxide thickness of the gate dielectric is expected to be reduced, increasing device performance.

However, using high k dielectric materials as a gate dielectric of transistors can present problems. Some high k dielectric materials have been found to pin the work function of a transistor to undesirable levels. The work function of the transistor affects the threshold voltage. For example, in CMOS devices, it is desirable to achieve a symmetric threshold voltage V_tfor the PMOS transistor and the NMOS transistor. If high k dielectric materials are used for the gate dielectric, a symmetric threshold voltage V_tmay not be achievable.

U.S. patent application Ser. No. 11/187,197 filed on Jul. 21, 2005, entitled, “CMOS Transistors With Dual High-k Gate Dielectric and Methods of Manufacture Thereof,” and U.S. patent application Ser. No. 10/870,616, filed on Jun. 17, 2004, entitled, “CMOS Transistor With Dual High-k Gate Dielectric and Method of Manufacture Thereof,” which applications are incorporated herein by reference, disclose CMOS devices having PMOS transistors and NMOS transistors with different high k gate dielectric materials used as a gate dielectric, to avoid problems with the pinning of the work function.

Another problem in the design and manufacture of transistor devices is that in advanced technologies, a reduced junction depth X_jand sheet resistance R_sare required. The thicker the junction depth X_j, the more the short channel effects such as hot carrier effects become severe and degrade transistor reliability, causing source and drain leakage and/or punch-through. If a transistor has a high sheet resistance R_s, then drive current and circuit speed are degraded, thus making the transistor less reliable for use in high-performance and/or high-speed applications.

U.S. Pat. No. 6,921,691 issued on Jul. 26, 2005 issued to Li, et al., which is hereby incorporated herein by reference, discloses forming recesses in a workpiece and filling the recesses with a dopant-bearing metal. An anneal process is used to form doped regions within the workpiece.

What are needed in the art are CMOS designs and fabrication methods wherein the effective gate dielectric thickness, the junction depth, and the sheet resistance are reduced, and wherein the threshold voltages for the PMOS and NMOS transistors are symmetric.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention which provide novel methods of manufacturing semiconductor devices and structures thereof.

In accordance with a preferred embodiment of the present invention, a workpiece includes a first region and a second region, a first gate dielectric of a first transistor disposed over the workpiece in the first region of the workpiece, and a second gate dielectric of a second transistor disposed over the workpiece in the second region of the workpiece, the second gate dielectric comprising a different material than the first gate dielectric. The workpiece includes recessed regions proximate each of the first gate dielectric and the second gate dielectric. A first dopant-bearing metal is disposed in the recessed regions of the workpiece proximate the first gate dielectric, the first dopant-bearing metal comprising a first dopant. A second dopant-bearing metal is disposed in the recessed regions of the workpiece proximate the second gate dielectric, the second dopant-bearing metal comprising a second dopant, the second dopant being different than the first dopant. A first doped region is disposed in the workpiece adjacent the first dopant-bearing metal, the first doped region comprising the first dopant. A second doped region is disposed in the workpiece adjacent the second dopant-bearing metal, the second doped region comprising the second dopant. The first dopant-bearing metal and the first doped region comprise a source region and a drain region of the first transistor, and the second dopant-bearing metal and the second doped region comprise a source region and a drain region of the second transistor.

The foregoing has outlined rather broadly the features and technical advantages of embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of embodiments of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGS. 1 through 16 show cross-sectional views of a semiconductor device at various stages of manufacturing in accordance with preferred embodiments of the present invention, wherein a first transistor and a second transistor are formed that have different gate dielectric materials, and wherein the source and drain regions of the first and second transistors include a recessed region in the workpiece filled with a dopant-bearing metal;

FIGS. 17 through 19 show cross-sectional views of an embodiment of the present invention, wherein a sidewall spacer is formed over sidewalls of the gate dielectric and gate of the first and second transistors before forming the recess for the dopant-bearing metal;

FIG. 20 shows an embodiment of the present invention wherein a thin layer of silicon is formed between the gate dielectric and the gate of the first and second transistors; and

FIG. 21 shows an embodiment of the present invention wherein the gates of the first transistor and the second transistor are doped with different materials.

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

Embodiments of the present invention achieve technical advantages by providing novel CMOS devices having a different dielectric material for the PMOS transistor than for the NMOS transistor, and having source and drain regions that include a dopant-bearing metal.

The present invention will be described with respect to preferred embodiments in a specific context, namely CMOS devices. The invention may also be applied, however, to other semiconductor devices and applications that require two or more transistors.

FIGS. 1 through 16 show cross-sectional views of asemiconductor device100 at various stages of manufacturing in accordance with preferred embodiments of the present invention. Thesemiconductor device100 comprises a CMOS device comprising dual high k dielectric materials for the gate dielectric; for example, the PMOS transistor preferably has a gate dielectric comprising a high k dielectric material that is different from a high k dielectric material used for the NMOS transistor gate dielectric. The source and drain regions of the CMOS device comprise dopant-bearing metals that are filled in a recess formed in the workpiece, in accordance with preferred embodiments of the present invention. Preferred methods of manufacturing the CMOS device will next be described.

With reference now toFIG. 1, there is shown asemiconductor device100 in a cross-sectional view including aworkpiece102. Theworkpiece102 may include a semiconductor substrate comprising silicon or other semiconductor materials covered by an insulating layer, for example. Theworkpiece102 may also include other active components or circuits, not shown. Theworkpiece102 may comprise silicon oxide over single-crystal silicon, for example. Theworkpiece102 may include other conductive layers or other semiconductor elements, e.g., transistors, diodes, etc. Compound semiconductors, GaAs, InP, Si/Ge, or SiC, as examples, may be used in place of silicon. Theworkpiece102 may also comprise bulk Si, SiGe, Ge, SiC, or a silicon-on-insulator (SOI) substrate, as examples.

Theworkpiece102 includes afirst region104 and asecond region106. Thefirst region104 comprises a region where a first transistor comprising a PMOS device or PMOSFET, as examples, will be formed. Thesecond region106 comprises a region where a second transistor comprising an NMOS device or NMOSFET will be formed, as examples. The PMOS device and NMOS device are not shown inFIG. 1: seeFIG. 6 at136 and138, respectively.

Thefirst region104 and thesecond region106 may be separated from one another and from adjacent devices or active areas (not shown) by an optional shallow trench isolation (STI)region108 formed in theworkpiece102, as shown. Thefirst region104 may be lightly doped with N type dopants, and thesecond region106 may be lightly doped with P type dopants, for example. In general, theworkpiece102 is doped with N or P type dopants depending on whether the junctions (e.g., formed by the source and drain regions) of the transistor to be formed will be P or N type, respectively.

Theworkpiece102 is preferably cleaned using a pre-gate clean process to remove any contaminant or native oxide from the top surface of theworkpiece102. The pre-gate treatment may comprise an HF, HCl, or ozone based cleaning treatment, as examples, although the pre-gate treatment may alternatively comprise other chemistries.

Ahard mask112 is deposited over theworkpiece102, also shown inFIG. 1. Thehard mask112 preferably comprises afirst layer114 and asecond layer116 disposed over thefirst layer114, as shown. Alternatively, thehard mask112 may comprise a single layer of an oxide or a nitride material, for example. In the embodiment shown inFIG. 1, thefirst layer114 of thehard mask112 preferably comprises about 300 Angstroms (Å) of an oxide material such as tetraethoxysilate (TEOS), although alternatively, thefirst layer114 may comprise other insulating materials deposited in other dimensions, for example. Thefirst layer114 may be deposited by plasma-enhanced chemical vapor deposition (PECVD) or by other deposition techniques, as examples. Thesecond layer116 preferably comprises about 1,500 Å of a nitride material such as Si_xN_y, for example, although alternatively, thesecond layer116 may comprise other insulating materials deposited in other dimensions, for example. Thesecond layer116 may be deposited by PECVD or by other deposition techniques, as examples.

A first layer ofphotoresist118 is deposited over thesecond layer116 of thehard mask112, as shown inFIG. 1. The first layer ofphotoresist118 may patterned with a mask using traditional lithography techniques to remove the first layer ofphotoresist118 from thesecond region106 of theworkpiece102, as shown. Alternatively, the first layer ofphotoresist118 may be directly patterned using electron beam lithography (EBL) or other direct etching technique, as examples.

The first layer ofphotoresist118 is used to pattern at least thesecond layer116 of thehard mask112. For example, exposed portions of thesecond layer116 in thesecond region106 may be etched using the first layer ofphotoresist118 remaining over thefirst region104 as a mask. The etch process may be designed to stop when thefirst layer114 of thehard mask112 is reached. The first layer ofphotoresist118 is then stripped or removed, and thesecond layer116 is then used as a mask to pattern thefirst layer114. Alternatively, the first layer ofphotoresist118 may be used as a mask to etch both thesecond layer116 and thefirst layer114 of thehard mask112, for example. The first layer ofphotoresist118 is then stripped or removed.

A firstgate dielectric material120 is deposited over the patternedhard mask112 and exposed portions of theworkpiece102, as shown inFIG. 2. The firstgate dielectric material120 preferably comprises a high-k dielectric material having a dielectric constant of about 4.0 or greater, in one embodiment. The firstgate dielectric material120 preferably comprises HfO₂, HfSiO_X, Al₂O₃, ZrO₂, ZrSiO_X, Ta₂O₅, La₂O₃, SiO₂, TiO₂, CeO₂, Bi₄Si₂O₁₂, WO₃, Y₂O₃, LaAlO₃, BST (Ba_(a-x)Sr_xTiO₃), PST (PbSc_xTa_(1-a)O₃), nitrides thereof, Si_xN_y, SiON, HfAlO_x, HfAlO_xN_1-x-y, ZrAlO_x, ZrAlO_xN_y, SiAlO_x, SiAlO_xN_1-x-y, HfSiAlO_x, HfSiAlO_xN_y, ZrSiAlO_x, ZrSiAlO_xN_y, PZN (PbZn_xNb_(1-x)O₃), PZT (PbZr_xTi_(1-x)O₃), PMN (PbMg_xNb_(1-x)O₃), combinations thereof, or multiple layers thereof, as examples, although alternatively, the firstgate dielectric material120 may comprise other high k insulating materials or other dielectric materials. The firstgate dielectric material120 may comprise a single layer of material, or alternatively, the firstgate dielectric material120 may comprise two or more layers. In one embodiment, one or more of these materials can be included in the firstgate dielectric material120 in different combinations or in stacked layers. The firstgate dielectric material120 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), or jet vapor deposition (JVD), as examples, although alternatively, the firstgate dielectric material120 may be deposited using other suitable deposition techniques. The firstgate dielectric material120 preferably comprises a thickness of about 10 Å to about 60 Å in one embodiment, although alternatively, the firstgate dielectric material120 may comprise other dimensions, such as about 80 Å or less, as an example.

In some embodiments, the firstgate dielectric material120 preferably comprises a first element comprising Hf, La, Sc, Y, Lu, Lr, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Zr, or Yb. The first element may comprise an element from Column IIIb of the Periodic Table, or a Lanthanoid from the Periodic Table, as examples. In one embodiment, the firstgate dielectric material120 preferably comprises a La-containing insulating material, for example. The firstgate dielectric material120 preferably comprises a first material such as the first element combined with a second material, such as Hf, Zr, Ta, Ti, Al, or Si, and also combined with either O, N, or both O and N. In another embodiment, the firstgate dielectric material120 preferably comprises a first material comprising a first element, a second material comprising Hf, Zr, Ta, Ti, Al, or Si, and also either O, N, or both O and N, and further comprising a third material, such as Ti, Sr, or Sc. As examples, the firstgate dielectric material120 may comprise LaHfO or LaHfTiO, although alternatively, the firstgate dielectric material120 may comprise other La-containing insulating materials or first element-containing materials.

Advantageously, if the second transistor138 (seeFIG. 6) to be formed in thesecond region106 comprises an NMOS transistor, and if the firstgate dielectric material120 comprises La, then the La shifts the flatband voltage V_FBof theNMOS transistor138, allowing tunability of the threshold voltage V_t. The other types of first elements of the firstgate dielectric material120 described herein also are preferably adapted to tune the V_tof theNMOS transistor138, for example.

Afirst gate material122 is deposited over the firstgate dielectric material120, also shown inFIG. 2. Thefirst gate material122 preferably comprises a conductor, such as a metal or polysilicon, although alternatively, other conductive and semiconductive materials may be used for thefirst gate material122. For example, thefirst gate material122 preferably comprises Au, NiCu, NiTi, PtTa, RuTi, TaAlN_x, TaC, TaCN, MoSi_x, IrO₂, RuO₂, HfSi_x, NbSi_x, TaSi_x, TiN, TiCN, HfN, TaN, W, Al, Ru, RuN, RuSiN, RuTa, TaSiN, TiSiN, TaCN, NiSi_x, CoSi_x, TiSi_x, Ir, Y, Pt, Ti, PtTi, Pd, Re, Rh, (borides, phosphides, or antimonides of Ti), Hf, Zr, TiAlN, Mo, MoN, ZrSiN, ZrN, HfN, HfSiN, WN, Ni, Pr, VN, TiW, LaN, LaSiN, WSiN, WSi, polysilicon, a partially silicided material, a fully silicided material (FUSI), other metals, and/or combinations and multiple layers thereof, although alternatively, other materials may also be used. If thegate material122 comprises FUSI, for example, polysilicon may be deposited over thegate dielectric material120, and a metal such as nickel may be deposited over the polysilicon, although other metals may be used. Theworkpiece102 may then be heated to about 600 or 700 degrees C. to form a single layer of nickel silicide.

Thefirst gate material122 may comprise a plurality of stacked gate materials, such as a metal underlayer with a polysilicon cap layer disposed over the metal underlayer, or a combination of a plurality of metal layers that form a gate electrode stack. Thefirst gate material122 may be deposited using CVD, PVD, ALD, or other deposition techniques, as examples. Thefirst gate material122 preferably comprises a thickness of about 1,500 Å, although alternatively, thefirst gate material122 may comprise about 1,000 Å to about 2,000 Å, or other dimensions, for example.

If thefirst gate material122 comprises a semiconductive material, preferably, thefirst gate material122 is N-doped, by doping thefirst gate material122 with N type dopants such as phosphorous or antimony, for example. Doping thefirst gate material122 makes the semiconductive material conductive or more conductive. Alternatively, thefirst gate material122 may be doped with a P type dopant, for example, as described in Ser. No. 11/017,062, filed on Dec. 20, 2004, entitled, “Transistor Device and Method of Manufacture Thereof,” which is incorporated herein by reference.

A second layer ofphotoresist124 is deposited over thefirst gate material122, as shown inFIG. 2. The second layer ofphotoresist124 may patterned using a mask using traditional lithography techniques to remove the second layer ofphotoresist124 from over thefirst region104 of theworkpiece102, as shown, although alternatively, the second layer ofphotoresist124 may be directly patterned.

The second layer ofphotoresist124 is used as a mask to pattern thefirst gate material122 and the firstgate dielectric material120, and to remove thehard mask112 from thefirst region104 of theworkpiece102, as shown inFIG. 3. For example, exposed portions of thefirst gate material122, firstgate dielectric material120, andhard mask112 may be etched away from thefirst region104 of theworkpiece102 using the second layer ofphotoresist124 as a mask. The second layer ofphotoresist124 is then stripped or removed from over thesecond region106 of theworkpiece102. Any excessfirst gate material122 and firstgate dielectric material120 may be removed from over theoptional STI region108 using a chemical-mechanical polish (CMP) process or an etch process, for example. The exposed surface of theworkpiece102 may be cleaned using a pre-gate clean process.

Next, a secondgate dielectric material126 is deposited over exposed portions of theworkpiece102 in thefirst region104 and over the patternedfirst gate material122 and firstgate dielectric material120 in thesecond region106, as shown inFIG. 4. The secondgate dielectric material126 preferably comprises a different material than the firstgate dielectric material120 in accordance with an embodiment of the present invention. The secondgate dielectric material126 preferably comprises a high-k dielectric material having a dielectric constant of about 4.0 or greater, in one embodiment. The secondgate dielectric material126 preferably comprises HfO₂, HfSiO_x, Al₂O₃, ZrO₂, ZrSiO_x, Ta₂O₅, La₂O₃, SiO₂, TiO₂, CeO₂, Bi₄Si₂O₁₂, WO₃, Y₂O₃, LaAlO₃, BST (Ba_(a-x)Sr_xTiO₃), PST (PbSc_xTa_(1-a)O₃), nitrides thereof, Si_xN_y, SiON, HfAlO_x, HfAlO_xN_1-x-y, ZrAlO_x, ZrAlO_xN_y, SiAlO_x, SiAlO_xN_1-x-y, HfSiAlO_x, HfSiAlO_xN_y, ZrSiAlO_x, ZrSiAlO_xN_y, PZN (PbZn_xNb_(1-x)O₃), PZT (PbZr_xTi_(1-x)O₃), PMN (PbMg_xNb_(1-x)O₃), combinations thereof, or multiple layers thereof, as examples, although alternatively, the secondgate dielectric material126 may comprise other high k insulating materials or other dielectric materials.

The secondgate dielectric material126 may comprise a single layer of material, or alternatively, the secondgate dielectric material126 may comprise two or more layers, wherein the top layer comprises a Fermi-pinning material. In one embodiment, one or more of these materials can be included in the secondgate dielectric material126 in different combinations or in stacked layers. The secondgate dielectric material126 may be deposited by CVD, ALD, MOCVD, PVD, or JVD, as examples, although alternatively, the secondgate dielectric material126 may be deposited using other suitable deposition techniques. The secondgate dielectric material126 preferably comprises a thickness of about 10 Å to about 60 Å in one embodiment, although alternatively, the secondgate dielectric material126 may comprise other dimensions, such as about 80 Å or less, as an example. In some embodiments, the secondgate dielectric material126 preferably comprises a Fermi-pinning material such as an aluminum-containing material disposed at the top surface thereof, for example.

In some embodiments, the secondgate dielectric material126 preferably comprises an insulating material comprising a second element, the second element being different than the first element of the firstgate dielectric material120, for example. The second element in these embodiments preferably comprises Al, Y, Sc, Lu, Lr, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Zr, or Yb, as examples. The second element may comprise an element from Column IIIb of the Periodic Table, a Lanthanoid from the Periodic table, Al or an Al-containing material, as examples. In one embodiment, e.g., when thefirst transistor136 comprises a PMOS transistor (seeFIG. 6) the secondgate dielectric material126 preferably comprises a Y-containing insulating material or an Al-containing insulating material, for example. These materials are particularly beneficial for tuning or shifting the V_FBand thus provide tunability of the V_tof the PMOS transistor136 (shown inFIG. 6), for example. The other types of second elements described herein are also preferably adapted to provide the ability to tune the V_tof thePMOS transistor136 by varying the amount of the second element in the secondgate dielectric material126, for example.

In some embodiments, the secondgate dielectric material126 preferably comprises a first material such as Y or Al combined with a second material, such as Hf, Zr, Ta, Ti, Al, or Si, and also combined with either O, N, or both O and N, as example, as another example. In another embodiment, the secondgate dielectric material126 preferably comprises a first material comprising Y or Al, a second material comprising Hf, Zr, Ta, Ti, Al, or Si, and also either O, N, or both O and N, and further comprising a third material, such as Ti, Sr, or Sc. As examples, the secondgate dielectric material126 may comprise YHfO, YHfTiO, or AlO, although alternatively, the secondgate dielectric material126 may comprise other materials.

Next, asecond gate material128 is deposited over the secondgate dielectric material126, also shown inFIG. 4. Thesecond gate material128 preferably comprises a conductor, such as a metal or polysilicon, although alternatively, other conductive and semiconductive materials may be used for thesecond gate material128. Thesecond gate material128 preferably comprises Au, NiCu, NiTi, PtTa, RuTi, TaAlN_x, TaC, TaCN, MoSi_x, IrO₂, RuO₂, HfSi_x, NbSi_x, TaSi_x, TiN, TiCN, HfN, TaN, W, Al, Ru, RuN, RuSiN, RuTa, TaSiN, TiSiN, TaCN, NiSi_x, CoSi_x, TiSi_x, Ir, Y, Pt, Ti, PtTi, Pd, Re, Rh, (borides, phosphides, or antimonides of Ti), Hf, Zr, TiAlN, Mo, MoN, ZrSiN, ZrN, HfN, HfSiN, WN, Ni, Pr, VN, TiW, LaN, LaSiN, WSiN, WSi, polysilicon, a partially silicided material, a fully silicided material (FUSI), other metals, and/or combinations and multiple layers thereof, although other materials may also be used. Thesecond gate material128 may comprise a plurality of stacked gate materials, such as a metal underlayer with a polysilicon cap layer disposed over the metal underlayer, or a combination of a plurality of metal layers that form a gate electrode stack. Thesecond gate material128 may be deposited using CVD, PVD, ALD, or other deposition techniques, as examples. Thesecond gate material128 preferably comprises a thickness of about 1,500 Å, although alternatively, thesecond gate material128 may comprise about 1,000 Å to about 2,000 Å, or other dimensions, for example. Thesecond gate material128 may comprise the same material as thefirst gate material122, or alternatively, thesecond gate material128 may comprise a different material than thefirst gate material122, for example.

If thesecond gate material128 comprises a semiconductive material, then preferably, thesecond gate material128 is P-doped, by doping thesecond material128 with a P type dopant such as boron, as an example. Doping thesecond gate material128 makes the semiconductive material conductive or more conductive. In one embodiment, thesecond gate material128 is preferably doped with an N type dopant, for example. Thesecond gate material128 may be doped with the same dopant type or a different dopant type than thefirst gate material122 is doped with, for example.

A third layer ofphotoresist130 is deposited over thesecond gate material128, as shown inFIG. 4. The third layer ofphotoresist130 may be patterned using a mask by traditional lithography techniques to remove the third layer ofphotoresist130 from thesecond region106 of theworkpiece102, as shown, although alternatively, the third layer ofphotoresist130 may be directly patterned.

The third layer ofphotoresist130 is then used as a mask to pattern thesecond gate material128 and secondgate dielectric material126, as shown inFIG. 5. For example, exposed portions of thesecond gate material128 and secondgate dielectric material126 may be etched away from thesecond region106 of theworkpiece102 using the third layer ofphotoresist130 as a mask. The third layer ofphotoresist130 is then stripped or removed from over thefirst region104 of theworkpiece102.

Any excesssecond gate material128 and secondgate dielectric material126 may be removed from over theoptional STI region108 proximate the interface of thefirst region104 andsecond region106 using a chemical-mechanical polish (CMP) process or an etch process, for example (not shown), leaving the structure shown inFIG. 5.

Preferably using a single lithography step, e.g., using a single layer of photoresist and using a single mask to pattern the photoresist, thefirst gate material120, the firstgate dielectric material122, thesecond gate material126, and the secondgate dielectric material128 are simultaneously patterned with a desired pattern for a CMOS device, leaving the structure shown inFIG. 6, wherein aPMOS transistor136 is formed in thefirst region104, and anNMOS transistor138 is formed in thesecond region106. The gate dielectric of thePMOS transistor136 comprises the secondgate dielectric material126, and the gate dielectric of theNMOS transistor138 comprises the firstgate dielectric material120. The gate or gate electrode of thePMOS transistor136 comprises thesecond gate material128, and the gate of theNMOS transistor138 comprises thefirst gate material122. Thegate dielectric126 of thePMOS transistor136 preferably comprises an insulating material that is different than the insulating material of thegate dielectric120 of theNMOS transistor138.

Other methods may be used to form thePMOS transistor136 andNMOS transistor138 havingdifferent gate dielectrics126 and120. For example, some alternative methods that may be used to form thedifferent gate dielectrics126 and120 are described in U.S. patent application Ser. No. 10/870,616, filed on Jun. 17, 2004, entitled, “CMOS Transistor With Dual High-k Gate Dielectric and Method of Manufacture Thereof,” which is incorporated herein by reference. For example, a first insulating layer may be deposited over the entire workpiece, (not shown in the drawings), and the first insulating layer may be removed in one region, such asfirst region104, but not the other region, such assecond region106. A second insulating layer may then be deposited over the first insulating layer in thesecond region106 and over theworkpiece102 in thefirst region104. Then a single layer of gate material is formed over the second insulating layer. The gate material and insulating layers are then patterned to form a PMOS transistor having a gate dielectric comprising the second insulating layer, and an NMOS transistor having a gate dielectric comprising both the first and second insulating layers.

Alternatively, a single layer of insulating material may be deposited over theworkpiece102, and a gate material comprising a conductive material, for example, may be deposited over the insulating material (also not shown). One region, such as thefirst region104, may be masked, while the other region, such assecond region106, is implanted with a Fermi-pinning material. For example, at least the gate material may be implanted with the Fermi-pinning material. In some embodiments, the insulating material is also implanted with the Fermi-pinning material, for example. The gate material of the PMOS transistor may be implanted with a different material than the gate material of the NMOS transistor is implanted with, for example.

Next, in accordance with a preferred embodiment of the present invention, theworkpiece102 is recessed in the source and drain regions, as shown inFIG. 7. The source regions and drain regions (e.g., source region S₁and drain region D₁of thePMOS transistor136, and source region S₂and drain region D₂of the NMOS transistor138) may be recessed using a dry etch process containing argon as an example, although alternatively, other etch chemistries may also be used to form the recesses. The etch process in one embodiment is preferably substantially anisotropic, to avoid reducing the horizontal dimensions (e.g., lateral etching) of thegates128 and122 and thegate dielectric126 and120, for example. Alternatively, the etch process to create the recesses may comprise an isotropic etch, such as an etch process referred to as “chemical downstream etching,” which is a technique employing microwave plasma source, low bias RF power, or a combination of both, for isotropic recessing of silicon in theworkpiece102 selective to theisolation oxide108, as an example, although other isotropic etch processes may alternatively be used. The depth d₁of the recesses in the source S₁/S₂and drain D₁/D₂regions preferably comprises about 200 Å or less below the top surface of theworkpiece102, as an example. Preferably, the source S₁/S₂regions and the drain D₁/D₂regions are recessed simultaneously in a single processing step, e.g., they are recessed at the same time. The source S₁/S₂regions and drain D₁/D₂regions may be recessed using an additional separate etch process, or alternatively, the source S₁/S₂regions and the drain D₁/D₂regions may be recessed during thegate128/122 and gate dielectric126/120 patterning process, for example.

Two recesses are preferably formed for eachtransistor136 and138, as shown. For example, for thePMOS transistor136, a first recess is formed in theworkpiece102 on a first side of thegate dielectric126 proximate thegate dielectric126, and a second recess is formed in theworkpiece102 on a second side of thegate dielectric126 proximate thegate dielectric126, for example, opposite from the first side of thegate dielectric126. Likewise, for theNMOS transistor138, a third recess is formed in theworkpiece102 on a first side of thegate dielectric120 proximate thegate dielectric120, and a fourth recess is formed in theworkpiece102 on a second side of thegate dielectric120 proximate thegate dielectric120, for example, opposite from the first side of thegate dielectric120, as shown.

In some embodiments, the recesses in theworkpiece102 of thePMOS transistor136 are filled with a first dopant-bearing metal while theNMOS transistor138 is masked, and then the recesses in theworkpiece102 of theNMOS transistor138 are filled with a second dopant bearing metal, to be described next with reference toFIGS. 8 through 10. For example, a maskingmaterial139athat may comprise a hard mask including about 5,000 Å of an oxide, a nitride, or combinations thereof, as examples, is deposited over thefirst region104 and thesecond region106 of theworkpiece102, and then the maskingmaterial139ais removed from over thefirst region104, e.g., using lithography, as shown inFIG. 8. A first dopant-bearingmetal140 is deposited over exposed portions of theworkpiece102, the top surface of thegate128, andisolation regions108, in thefirst region104, and over the maskingmaterial139ain thesecond region106, as shown inFIG. 8.

The first dopant-bearingmetal140 preferably comprises a metal that includes a first dopant comprising boron (B), phosphorous (P), arsenic (As), or antimony (Sb), as examples, although alternatively, the dopant may comprise other dopant materials. If thetransistor136 in thefirst region104 comprises a PMOS transistor, for example, preferably theworkpiece102 is lightly doped with an N type material in thefirst region104, and the first dopant preferably comprises a P type material, for example.

The first dopant-bearingmetal140 preferably comprises TiB₂, ZrB₂, HfB₂, ZrP, TiP, ZrSb₂, TiSb₂, HfSb₂, or arsinides of Zr or Hf, as examples, although alternatively, the dopant-bearingmetal140 may comprise other metals containing a first dopant. In some embodiments, for example, the first dopant-bearingmetal140 preferably comprises Au, NiCu, NiTi, PtTa, RuTi, TaAlN_x, TaC, TaCN, MoSi_x, IrO₂, RuO₂, HfSi_x, NbSi_x, TaSi_x, TiN, TiCN, HfN, TaN, W, Al, Ru, RuN, RuSiN, RuTa, TaSiN, TiSiN, TaCN, NiSi_x, CoSi_x, TiSi_x, Ir, Y, Pt, Ti, PtTi, Pd, Re, Rh, (borides, phosphides, or antimonides of Ti), Hf, Zr, TiAlN, Mo, MoN, ZrSiN, ZrN, HfN, HfSiN, WN, Ni, Pr, VN, TiW, LaN, LaSiN, WSiN, WSi_x, a partially silicided material, a fully silicided material (FUSI), other metals, and/or combinations and multiple layers thereof. The first dopant-bearingmetal140 preferably comprises a thickness greater than the depth d₁of the recesses, for example.

The metal portion (e.g., Ti, Zr, Hf, or other materials listed) of the first dopant-bearingmetal140 causes the source S₁and drain D₁regions to have a lower sheet resistance R_s, and the first dopant portion (e.g., B, P, Sb, As) creates the junction of the source S₁and drain D₁. Preferably, in accordance with embodiments of the present invention, the first dopant-bearingmetal140 is selected to provide a reduced sheet resistance R_sfor thesemiconductor device100.

The recesses in the source S₁and drain D₁regions are preferably back-filled with the first dopant-bearingmetal140. For example, the first dopant-bearingmetal140 may be deposited using electron beam evaporation, CVD, or PVD, although alternatively, other methods of deposition may be used to deposit the first dopant-bearingmetal140.

The first dopant-bearingmetal140 may be substantially conformal when deposited, as shown inFIG. 8. Excess portions of the first dopant-bearingmetal140 are removed from over theisolation regions108, top surface and sidewalls of thegates128, and sidewalls of thegate dielectric126, as shown inFIG. 9. The excess portions of the first dopant-bearingmetal140 may be removed using an anisotropic etch process or an isotropic etch process, as examples. As examples, the excess portions of the first dopant-bearingmetal140 may be removed using wet, dry, electrochemical or chemical etch processes, although other etch processes may alternatively be used. The top surface of the first dopant-bearingmetal regions140 formed in the source S₁and drain D₁regions may be substantially planar with the top surface of theworkpiece102, as shown inFIG. 9, although alternatively, the first dopant-bearingmetal regions140 may be slightly recessed or concaved slightly within the recesses of the workpiece102 (not shown). The maskingmaterial139ais removed from thesecond region106 of theworkpiece102.

Asecond masking material139bcomprising similar materials and thicknesses as described for the maskingmaterial139ais formed or deposited over thefirst region104 and thesecond region106 of theworkpiece102. The maskingmaterial139bis removed from over thesecond region106, as shown inFIG. 9, leaving thegate material122 and portions of theworkpiece102 exposed. A second dopant-bearingmetal141 is deposited over the exposed portions of theworkpiece102, top surface and sidewalls of thegate material122, and sidewalls of thegate dielectric120 in thesecond region106, and also over the maskingmaterial139bin the first region, as shown inFIG. 9.

The second dopant-bearingmetal141 preferably comprises similar materials and dimensions as described for the first dopant-bearingmetal140, for example. The second dopant-bearingmetal141 preferably comprises a different material than the first dopant-bearingmetal140, for example. The second dopant-bearingmetal141 preferably comprises a second dopant, wherein the second dopant is different than the first dopant of the first dopant-bearingmetal140, for example. In some embodiments, if thetransistor138 in thesecond region106 comprises an NMOS transistor, then theworkpiece102 is preferably lightly doped with a P type dopant in thesecond region106, and the second dopant-bearingmetal141 preferably comprises an N type material, for example.

Excess portions of the second dopant-bearingmetal141 are removed from over theisolation regions108 in thesecond region106, top surface and sidewalls of thegates122, and sidewalls of thegate dielectric120, using the methods described for the first dopant-bearingmetal140, and leaving the structure shown inFIG. 10, wherein the first dopant-bearingmetal140 fills the recesses in theworkpiece102 in thefirst region104, and wherein the second dopant-bearingmetal141 fills the recesses in theworkpiece102 in thesecond region106. The top surface of the second dopant-bearingmetal regions141 formed in the source S₂and drain D₂regions may be substantially planar with the top surface of theworkpiece102, as shown inFIG. 10, although alternatively, the second dopant-bearingmetal regions141 may be slightly recessed or concaved slightly within the recesses of the workpiece102 (not shown). The maskingmaterial139bshown inFIG. 9 is removed from thefirst region106 of theworkpiece102, as shown inFIG. 10.

In another embodiment, to fill the recesses in the workpiece with a dopant-bearing metal, asingle metal layer143 is deposited over thefirst region104 and thesecond region106 of theworkpiece102, as shown inFIG. 11. Themetal layer143 may be masked in thesecond region106 while a first dopant is implanted into themetal layer143 in thefirst region104, and themetal layer143 may be masked in thefirst region104 while a second dopant is implanted into themetal layer143 in thesecond region106. Excess portions of themetal layer143 are then removed from above a top surface of theworkpiece102, leaving the structure shown inFIG. 13, wherein themetal layer143 implanted with the first dopant comprises a first dopant-bearingmetal140 in thefirst region104 and themetal layer143 implanted with the second dopant comprises a second dopant-bearingmetal141 in thesecond region106. Advantageously, thegates128 and122 are not implanted with the first dopant and second dopant, respectively, in this embodiment, so that thegate128 may be doped with a different type dopant than the first dopant-bearingmetal140, and thegate122 may be doped with a different type dopant than the second dopant-bearingmetal141, for example.

In another embodiment, before thesingle metal layer143 is implanted with the first dopant and the second dopant, excess portions of themetal layer143 are removed from above the top surface of theworkpiece102, leaving the structure shown inFIG. 12. Themetal layer143 is masked in thesecond region106 while afirst dopant145 is implanted into themetal layer143 in thefirst region104, forming a first dopant-bearingmetal140 as shown inFIG. 13. Thegate128 in thefirst region104 is also implanted with thefirst dopant145 in this embodiment. Themetal layer143 may be masked in thefirst region104 while asecond dopant147 is implanted into themetal layer143 in thesecond region106, forming a second dopant-bearingmetal141 as shown inFIG. 13. Thegate122 in thesecond region106 is also implanted with thesecond dopant147 in this embodiment.

In one embodiment, the first and second dopant-bearingmetal regions140 and141 may be doped using an additional ion implantation step (e.g., masking oneregion104 while implanting the other region106), not shown. This is an optional step that is not required in embodiments of the present invention but may be appropriate for some transistor designs. In this optional step, dopant ions are introduced into the dopant-bearingmetal regions140 and141 using ion implantation. This increases the dopant concentration in the dopant-bearingmetal regions140 and141, resulting in an increase in dopant concentration of the underlying dopant region during the diffusion of the dopant of the dopant-bearingmetal regions140 and141 into theunderlying substrate102 in subsequent processing steps. When this optional ion implantation step is included in the manufacturing process, preferably, the implantation is performed at an energy level of about 1 KeV or below at an implantation dose of about 1×10¹⁵ions/cm²or less, as examples.

Theworkpiece102 is then subjected to a low-temperature anneal process to cause out-diffusion of the first and second dopants in the dopant-bearingmetal regions140 and141, respectively. The out-diffusion of the first dopant in thefirst region104 forms a dopedregion144 comprising the first dopant in the source S₁region and drain D₁region within theworkpiece102 adjacent the dopant-bearingmetal regions140, as shown inFIG. 14. The anneal process also causes out-diffusion of the second dopant in thesecond region106, forming adoped region149 comprising the second dopant in the source S₂region and drain D₂region within theworkpiece102 adjacent the dopant-bearingmetal regions141. The dopedregions144 and149 preferably extend beneath the dopant-bearingmetal regions140 and141, and also extend laterally (to the side of the dopant-bearingmetal regions140 and141) beneath thegates128/122 and gate dielectric126/120 by about 70 Å or less, as shown at d₂. The low-temperature anneal process preferably comprises a temperature of about 900° C. or less for about 1 hour or less, and more preferably comprises a temperature of about 900° C. for about 20 minutes or less, as examples. The dopedregions144 preferably comprise a thickness of about 100 Å or less, as an example.

Thus, the source S₁/S₂and the drain D₁/D₂regions each comprise a dopant-bearingmetal140/141 and a dopedregion144/149 disposed adjacent (e.g., below and extending laterally from) the dopant-bearingmetal140/141, as shown. The source S₁/S₂and drain D₁/D₂regions preferably comprise a total thickness d₃of about 300 Å below the top surface of theworkpiece102, comprising the dopant-bearingmetal140/141 and the dopedregions144/149.

Note that the dopedregions144/149 include an extension region that extends beneath thegate dielectric126/120 and extends towards the channel regions C₁and C₂. One advantage of thetransistors136 and138 formed in accordance with embodiments of the present invention is that the extension region can be made smaller than in traditional transistor designs. For example, the extension region may extend beneath thegates128/122 on either side by a distance d₂, which may comprise about 70 Å or less, e.g., about 20 to about 50 Å. This is advantageous because the resistance of the extension region is low, resulting from the reduced amount of overlap d₂, which reduces hot carrier effects of thetransistors136 and138.

In one embodiment, the dopant-bearingmetal140/141 preferably comprises a higher atomic percentage of the dopant than would be found in a natural state of the dopant-bearingmetal140/141, and the percentage of the dopant in the dopant-bearingmetal140/141 is reduced after the low-temperature anneal, resulting from dopant ions diffusing into theworkpiece102 to form the dopedregions144/149. For example, if the dopant-bearingmetal140 in thefirst region104 comprises Ti bearing the dopant B, the dopant-bearingmetal140 may comprise TiB_x, where x>2, e.g., 3, 4, etc. In this embodiment, after the low temperature anneal to form the dopedregions144, the dopant-bearingmetal140 comprises a reduced atomic percentage of the first dopant, and may comprise, for example, TiB₂. Note that while there is less of the dopant species (e.g., the first dopant) left residing in the dopant-bearingmetal140 after the low-temperature anneal because some dopant atoms migrate to thedopant region144, some dopant species are still left residing in the dopant-bearingmetal140.

The manufacturing process for thedevice100 is then continued to complete thedevice100, preferably without subjecting thesemiconductor device100 to high temperatures, e.g., preferably without exposing thesemiconductor device100 to a temperature greater than about 900° C. For example, aspacer material146 comprising a dielectric material such as SiO₂, SiN, or SiON, as examples, although other insulating materials may also be used, may be deposited over exposed portions of theworkpiece102. Thesidewall spacer146 material may be exposed to an etch process such as an anisotropic etch to formsidewall spacers146 on thetransistors136 and138 in the first andsecond regions104 and106 of theworkpiece102, as shown inFIG. 15.

Thus, in accordance with an embodiment of the invention,transistors136 and138 are formed that includegates128/122, source regions S₁/S₂, and drain regions D₁/D₂, wherein the source S₁/S₂and drain D₁/D₂comprise the dopant-bearingmetal regions140/141 and the dopedregions144/149. Thetransistors136 and138 have a thin effective oxide thickness which includes thegate dielectric126/120 and in some embodiments also includes a thin interface region disposed between theworkpiece102 and thegate dielectric126/120 (not shown). The thin interface region may form during the deposition process of the gatedielectric materials126 and120, for example, and may comprise a thin oxide layer, for example. Advantageously, because thetransistors136 and138 are not exposed to a high-temperature anneal process, e.g., at temperatures of about 1,000° C. or more, increasing the thickness of the interface region, if present, is avoided, thus decreasing the effective oxide thickness of thetransistors136 and138.

Furthermore, because a low-temperature anneal process is preferably used to form the dopedregions144/149 of the source S₁/S₂and drain D₁/D₂regions, this results in a shallower junction depth (e.g., depth d₃of the source and drain regions S₁/S₂and D₁/D₂) of thetransistors136 and138.

Thetransistors136 and138 are particularly advantageous in applications wherein a high drive current and minimal effective oxide thickness are important, such as in high performance (e.g., high speed) applications, for example, in use with memory and other devices.

FIG. 16 shows an embodiment of the present invention, in which a similar process flow may be used as was described forFIGS. 1 through 15. In the embodiment shown inFIG. 15, after thesidewall spacers146 are formed over the sidewalls of thegates128 and122 and thegate dielectrics126 and120, anion implantation process150 and151 is used to implant a dopant into the first andsecond regions104 and106, respectively (e.g., while the other region not being implanted is covered by a mask), followed by a high temperature anneal process, at a temperature of about 1,000° C. or more, to form deep source and drainimplantation regions152/153 in the source S₁/S₂and drain D₁/D₂regions, as shown. The target depth of this optional ion implantation process is preferably greater than the depth of thedopant bearing metal140 and dopedregion144, in one embodiment, as an example. The deep source and drainimplantation regions152/153 may comprise a depth d₄of about 500 Å or greater beneath theworkpiece102 top surface, for example. ThePMOS transistor136 may be implanted with adopant150 comprising BF₂, and theNMOS transistor138 may be implanted with adopant151 comprising As, as examples, at an energy level of about 10 KeV at an implantation dosage of about 1×10⁵ions/cm², as examples. In some embodiments, thedopant150 preferably comprises the same dopant type as the first dopant of the first dopant-bearingmetal140, and thedopant151 preferably comprises the same dopant type as the second dopant of the second dopant-bearingmetal141, as example.

In the embodiment shown inFIG. 16, the resultingtransistors136 and138 may have a thicker interface region (not shown) than the interface region of thetransistors136 and138 inFIG. 15, and may also have an additional interface region comprising an oxide formed between thegate dielectrics126/120 and thegates128/120 (also not shown), yet thetransistors136 and138 inFIG. 16 benefit from a further reduction in sheet resistance R_sdue to the presence of the dopant-bearingmetal140 and141 of the source S₁/S₂and drain D₁/D₂. ThisCMOS device100 is advantageous in some transistor applications that require a deeper source S₁/S₂and drain D₁/D₂implantation process to prevent junction leakage current from the source S₁/S₂and drain D₁/D₂to theworkpiece102, such as in low power applications. In these applications, a higher effective oxide thickness does not deleteriously affect thetransistor136 and138 performance, for example.

FIGS. 17 through 19 show additional preferred embodiments of the present invention, in which adouble spacer260/246 is used adjacent the gate dielectric and gate, along the sidewalls. A similar process flow and structure may be used as was described forFIGS. 1 through 15 and16 for the embodiments shown inFIGS. 17 through 18 and19. Similar reference numbers are designated for the various elements inFIGS. 17 through 18 and19 as were used inFIGS. 1 through 11 and12. To avoid repetition, each reference number shown inFIGS. 17 through 18 and19 is not described in detail herein. Rather, similar materials and thicknesses described for x02, x04, etc. . . . are preferably used for the material layers shown as were described forFIGS. 1 through 11 and12, where x=1 inFIGS. 1 through 11 and12 and x=2 inFIGS. 17 through 18 and19. As an example, the preferred and alternative materials listed for the dopant-bearingmetal140 in the description forFIGS. 1 through 11 and12 are preferably also used for the dopant-bearingmetal240 inFIG. 18.

FIGS. 17 through 18 show cross-sectional views of a preferred embodiment of the present invention, wherein afirst spacer260 is formed over the sidewalls of thegates228/222 andgate dielectrics226/220 before forming the recesses in the source S₁/S₂and drain D₁/D₂regions. Thefirst spacers260 preferably comprise a thickness of about 50 Å or less, and may comprise an insulating material such as SiO₂, SiN, or SiON, as examples. Similar manufacturing processes and materials are used as were described for the embodiment shown inFIGS. 7 through 15, resulting in the formation oftransistors236 and238 shown inFIG. 18 in a cross-sectional view.

Asecond spacer246 is formed adjacent and abutting thefirst spacers260, as shown inFIG. 18, after the formation of the source S₁/S₂and drain D₁/D₂regions as described herein. Again, thetransistors236 and238 have a decreased effective oxide thickness of thegate dielectrics226/220, and have a junction depth d₃that is well-controlled and very shallow. This embodiment is advantageous in that the extension regions d₅of the source S₁/S₂and drain D₁/D₂regions are further reduced, extending a distance d₅of about 50 Å or less beneath the edge of thegates228/222 andgate dielectrics226/220, as shown. For example, the low temperature anneal process results in the formation of the dopedregions244 and249 that extend less beneath thegates228/222 andgate dielectrics226/220 due to the presence of thespacer260 on the sidewalls of thegates228/222 andgate dielectrics226/220. The amount that the extension is reduced is substantially the width of thespacer260, or the dimension d₆of the thickness of the dopedregions244 and249 less dimension d₅of the amount that the dopedregions244 and249 extend beneath thegates228/222 andgate dielectrics226/220, for example.

FIG. 19 shows an embodiment of the present invention, wherein afirst spacer260 andsecond spacer246 are used, as described forFIGS. 17 and 18. In addition, theworkpiece202 is subjected to a subsequent ion implantation process to form deep source and drainimplantation regions252/253 in the source S₁/S₂and drain D₁/D₂, as described with reference to the embodiment shown inFIG. 16. This results in thetransistors236/238 being formed having deep source and drainimplantation regions252 and253 in thefirst region204 and thesecond region206, respectively. As described with reference toFIG. 16, the relatively high anneal temperatures required to form the deep source and drainimplantation regions252/253 result in an increased EOT, but this does not present a problem in some applications. Thetransistors236 and238 have a decreased sheet resistance R_s.

Additional embodiments of the present invention are shown in a cross-sectional view inFIGS. 20 and 21. Again, similar reference numbers are designated for the various elements inFIGS. 20 and 21 as were used inFIGS. 1 through 15 and16, andFIGS. 17 through 18 and19; and to avoid repetition, each reference number shown inFIGS. 20 and 21 is not described in detail herein. Rather, similar materials and thicknesses described for x02, x04, etc. . . . are preferably used for the material layers shown as were described forFIGS. 1 through 15 and16, andFIGS. 17 through 18 and19, where x=1 inFIGS. 1 through 15 and16, x=2 inFIGS. 17 through 18 and19, x=3 inFIG. 20, and x=4 inFIG. 21.

In the embodiment shown inFIG. 20, a thin layer ofsilicon370 may be formed between thegate dielectric320 and326 and thegate322 and328 of thetransistors338 and336 in accordance with embodiments of the present invention, as described in U.S. patent application Ser. No. 11/005,292, filed on Dec. 6, 2004, entitled, “CMOS Transistor and Method of Manufacture Thereof,” which is incorporated herein by reference. For example, after forming the gatedielectric materials320 and326, a thin layer ofsilicon370 is formed over the gatedielectric materials320 and326, before depositing thegate materials322 and328, respectively. The thin layer ofsilicon370 may provide pinning of the work function of thePMOS transistor336 and theNMOS transistor338, for example.

Furthermore, in another embodiment,dopants480 and482 may be implanted into thegates428 and422 of thetransistors436 and438, as shown inFIG. 21. Thedopants480 and482 may comprise the same dopant species or different dopant species, for example. ThePMOS transistor436 gate may be implanted with an N type dopant, and theNMOS transistor438 gate may be implanted with a P or N type dopant, as described in Ser. No. 11/017,062, filed on Dec. 20, 2004, entitled, “Transistor Device and Method of Manufacture Thereof,” which is incorporated herein by reference. An advantage of these embodiments is the reduction of a “poly depletion” effect that can occur when polysilicon is used as a gate electrode material. A poly depletion effect can increase the inversion oxide thickness (T_inv) (or capacitance equivalent thickness (CET)) of a transistor by about 4 Å, for example, which results in decreasing the device performance significantly, e.g., by about 20%. In addition, using N type dopant in PMOS transistors can eliminate a boron penetration effect (e.g., which can occur when a polysilicon gate electrode is implanted with boron, because boron diffuses from the gate and into the gate dielectric and/or channel region of the workpiece), which can deteriorate the gate dielectric quality and also increase the off-state leakage current. Furthermore, using polysilicon as a gate electrode material is an advantage, because manufacturing processes using polysilicon materials are mature, making these embodiments more manufacturing-friendly and easily integratable into production processes. However, alternatively, thePMOS transistor436 gate may be implanted with a P type dopant, and theNMOS transistor438 may be implanted with an N type dopant, for example. Thefirst region404 of theworkpiece402 may be masked (not shown) while thesecond region406 is implanted with thedopant482, and vice versa, for example.

Note that the various embodiments described herein may be used in combination. For example, the sidewall spacers described inFIGS. 17 and 18, and the deep implantation regions described inFIG. 19, may also be implemented in the embodiments shown inFIGS. 20 and 21.

Advantages of embodiments of the invention include providing novel CMOS devices and methods of manufacturing thereof. The work functions of the CMOS transistors described herein are tunable by a wide variety of factors, such as the gate dielectric material, gate material, doping, and optional thin layer of silicon. The junction depth X_j(e.g., of the source and drain regions S₁/S₂and D₁/D₂) is reduced, and the effective oxide thickness is reduced, of the novel transistors and CMOS devices described herein.

Embodiments of the present invention provide novel CMOS device structures and methods of manufacture thereof that combine a “dual high-k” structure wherein the PMOS gate dielectric and NMOS gate dielectric comprise different materials, with a “metal junction” structure wherein the source and drain regions comprise a dopant-bearing metal. Advantages of embodiments of the present invention include providing improved EOT scaling because of the lower thermal budget of the metal junction formation process than in traditional implant-anneal junction processes (e.g., used to form source and drain regions). Because of the lower thermal budget, high temperature anneal processes are not required to form the source and drain regions of the transistors, and more band-edge metal gate materials may be used. For example, the work function of metals is a function of the process temperature. Many materials that exhibit band-edge work functions at a low temperature (e.g., less than about 900° C.) become near-mid-gap materials after a high temperature source/drain activation anneal (e.g., of greater than about 900° C.) and therefore, the use of band-edge metals has not been very successful in the prior art, for example. By lowering the thermal process temperature by the use of the novel embodiments of the present invention described herein, there are more choices of the metals that can be used in production, e.g., for the gate electrode and source and drain region materials. Furthermore, by using a dopant-bearing metal in the source and drain regions, the drive current of the transistors is increased (and hence, the circuit speed is increased), the short channel effect is reduced, and junction leakage current is also reduced, as examples.

Although embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present invention. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims (16)

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:

providing a workpiece;

forming a first gate dielectric material over the workpiece in a first region of the workpiece;

forming a second gate dielectric material over the workpiece in a second region of the workpiece, the second gate dielectric material comprising a different material than the first gate dielectric material;

patterning the first gate dielectric material and the second gate dielectric material to form a first gate dielectric of a first transistor and a second gate dielectric of a second transistor;

forming recesses in the workpiece proximate the first gate dielectric and the second gate dielectric;

filling the recesses in the workpiece proximate the first gate dielectric with a first dopant-bearing metal, the first dopant-bearing metal comprising a first dopant;

filling the recesses in the workpiece proximate the second gate dielectric with a second dopant-bearing metal, the second dopant-bearing metal comprising a second dopant, the second dopant being different than the first dopant; and

annealing the workpiece, causing diffusion of the first dopant and second dopant into the workpiece, forming first doped regions within the workpiece adjacent the first dopant-bearing metal and second doped regions within the workpiece adjacent the second dopant-bearing metal, wherein the first dopant-bearing metal and the first doped regions comprise a source region and a drain region of the first transistor, and wherein the second dopant-bearing metal and the second doped regions comprise a source region and a drain region of the second transistor.

2. The method according toclaim 1, further comprising forming a first gate material over the first gate dielectric material and forming a second gate material over the second dielectric material, wherein forming the first gate dielectric material and forming the first gate material comprise forming a hard mask over the second region of the workpiece, depositing the first gate dielectric material over the hard mask in the second region and over the first region, depositing the first gate material over the first gate dielectric material, and removing the first gate material, first gate dielectric material, and the hard mask from over the second region of the workpiece, leaving the first gate material and the first gate dielectric material residing over the first region of the workpiece; and wherein forming the second gate dielectric material and forming the second gate material comprise depositing the second gate dielectric material over the second region of the workpiece and over the first gate material over the first region of the workpiece, depositing the second gate material over the second gate dielectric material, and removing the second gate material and the second gate dielectric material from over the first region of the workpiece, leaving the second gate material and the second gate dielectric material over the second region of the workpiece.

3. The method according toclaim 1, wherein forming the first gate dielectric material comprises forming a first dielectric material over the workpiece, removing the first gate dielectric material from over the first region of the workpiece, and forming a second dielectric material over the workpiece in the first region and over the first dielectric material in the second region, wherein the first gate dielectric material comprises the second dielectric material, and wherein the second gate dielectric material comprises the first dielectric material and the second dielectric material.

4. The method according toclaim 1, wherein forming the first gate dielectric material and forming the second gate dielectric material comprise depositing an insulating layer over the entire top surface of the workpiece, wherein forming the first gate material and forming the second gate material comprise depositing a conductive layer over the insulating layer, further comprising:

implanting a Fermi-pinning material into at least the conductive layer over the first region of the workpiece.

5. The method according toclaim 4, wherein implanting the Fermi-pinning material into at least the conductive layer over the first region of the workpiece comprises implanting the Fermi-pinning material into the insulating layer.

6. The method according toclaim 1, wherein the first transistor is formed in a first region of the workpiece and the second transistor is formed in a second region of the workpiece, wherein filling the recesses in the workpiece proximate the first gate dielectric with the first dopant-bearing metal comprises masking the second region with a first mask, depositing the first dopant-bearing metal over the first transistor in the first region and over the first mask in the second region, removing a portion of the first dopant-bearing metal from over a top surface of the workpiece in the first region, and removing the first dopant-bearing metal and the first mask from over the second region; and wherein filling the recesses in the workpiece proximate the second gate dielectric with the second dopant-bearing metal comprises masking the first region of the workpiece with a second mask, depositing the second dopant-bearing metal over the second transistor in the second region and over the second mask in the first region, removing a portion of the second dopant-bearing metal from over a top surface of the workpiece in the second region, and removing the second dopant-bearing metal and the second mask from over the first region.

7. The method according toclaim 1, wherein the first transistor is formed in a first region of the workpiece and the second transistor is formed in a second region of the workpiece, wherein filling the recesses in the workpiece proximate the first gate dielectric with the first dopant-bearing metal and filling the recesses in the workpiece proximate the second gate dielectric with the second dopant-bearing metal comprise depositing a single metal layer over the first region and the second region, implanting the first dopant into the single metal layer in the first region, and implanting the second dopant into the single metal layer in the second region.

8. The method according toclaim 7, further comprising masking the single metal layer in the second region with a first mask, before implanting the first dopant into the single metal layer in the first region, and removing the first mask from over the second region, and further comprising masking the single metal layer in the first region with a second mask, before implanting the second dopant into the single metal layer in the second region, and removing the second mask.

9. The method according toclaim 8, further comprising removing a portion of the single metal layer from over at least a top surface of the workpiece, before implanting the first dopant and the second dopant.

10. The method according toclaim 9, further comprising forming a first gate material over the first gate dielectric material and forming a second gate material over the second gate dielectric material, wherein implanting the first dopant comprises implanting the first dopant into the first gate material, and wherein implanting the second dopant comprises implanting the second dopant into the second gate material.

11. A method of manufacturing a complementary metal oxide semiconductor (CMOS) device, the method comprising:

providing a workpiece;

forming a first gate dielectric material over the workpiece in a first region of the workpiece, the first gate dielectric material comprising a dielectric material having a dielectric constant of about 4.0 or greater;

forming a second gate dielectric material over the workpiece in a second region of the workpiece, the second gate dielectric material comprising a dielectric material having a dielectric constant of about 4.0 or greater and comprising a different material than the first gate dielectric material;

patterning the first gate dielectric material and the second gate dielectric material to form a first gate dielectric of a p channel MOS (PMOS) transistor and a second gate dielectric of an n channel MOS (NMOS) transistor;

forming two recesses in the workpiece proximate each of the first gate dielectric and the second gate dielectric;

filling the recesses in the workpiece proximate the first gate dielectric with a first dopant-bearing metal;

filling the recesses in the workpiece proximate the second gate dielectric with a second dopant-bearing metal, the second dopant-bearing metal comprising a different dopant than the first dopant-bearing metal; and

annealing the workpiece, causing diffusion of a first dopant of the first dopant-bearing metal into the workpiece, forming first doped regions within the workpiece adjacent the first dopant-bearing metal, wherein the first dopant-bearing metal and the first doped regions comprise a source region and drain region of the PMOS transistor, and causing diffusion of a second dopant of the second dopant-bearing metal into the workpiece, forming second doped regions within the workpiece adjacent the second dopant-bearing metal, wherein the second dopant-bearing metal and the second doped regions comprise a source region and drain region of the NMOS transistor.

12. The method according toclaim 11, further comprising forming a sidewall spacer on sidewalls of at least the first gate dielectric and the second gate dielectric, before forming the recesses in the workpiece.

13. The method according toclaim 11, wherein the first dopant-bearing metal comprises a first dopant, wherein the second dopant-bearing metal comprises a second dopant, further comprising after annealing the workpiece, forming sidewall spacers on sidewalls of at least the first gate dielectric and the second gate dielectric, implanting ions of a third dopant into the source and drain region of the PMOS transistor, implanting ions of a fourth dopant into the source and drain region of the NMOS transistor, and annealing the workpiece again to form a first deep implantation region beneath the first doped region and to form a second deep implantation region beneath the second doped region.

14. The method according toclaim 11, wherein annealing the workpiece comprises annealing the workpiece at a temperature of about 900° C. or less for about 1 hour or less.

15. The method according toclaim 11, wherein forming the recesses comprises forming recesses having a depth of about 200 Å or less.

16. The method according toclaim 11, further comprising forming a first gate material over the first gate dielectric material and forming a second gate material over the second dielectric material, wherein the forming the first gate material and forming the second gate material comprise depositing polysilicon, further comprising:

doping the first gate with a P type dopant or an N type dopant, after forming the first gate material, and;

doping the second gate with a P type or N type dopant, after forming the second gate material, wherein the first gate and the second gate are doped with the same dopant type or a different dopant type.

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