US7453736B2 - Methods of erasing and designing electrically erasable charge trap nonvolatile memory cells having erase threshold voltage that is higher than an initial threshold voltage - Google Patents
Methods of erasing and designing electrically erasable charge trap nonvolatile memory cells having erase threshold voltage that is higher than an initial threshold voltageDownload PDFInfo
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- US7453736B2 US7453736B2US11/611,972US61197206AUS7453736B2US 7453736 B2US7453736 B2US 7453736B2US 61197206 AUS61197206 AUS 61197206AUS 7453736 B2US7453736 B2US 7453736B2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
Definitions
- This inventionrelates to nonvolatile memory devices, and more particularly to electrically erasable charge trap nonvolatile memory devices.
- Integrated circuit memory devicesare widely used in consumer and commercial applications. As is well known to those having skill in the art, integrated circuit memory devices include volatile and nonvolatile memory devices. Volatile memory devices may include Dynamic Random Access Memory (DRAM) devices and Static Random Access Memory (SRAM) devices. These volatile memory devices lose their data when their power supplies are interrupted. Nonvolatile memory devices may include Masked Read-Only Memory (MROM) devices, Programmable Read-Only Memory (PROM) devices, Erasable Programmable Read-Only Memory (EPROM) devices and Electrically Erasable Programmable Read-Only Memory (EEPROM) devices. These nonvolatile memory devices retain their stored data even when their power supplies are interrupted.
- MROMRead-Only Memory
- PROMProgrammable Read-Only Memory
- EPROMErasable Programmable Read-Only Memory
- EEPROMElectrically Erasable Programmable Read-Only Memory
- electrically erasable nonvolatile memory devicesmay include floating gate devices and charge trap devices.
- a floating gate electrically erasable nonvolatile memory devicestores charges in an isolated floating gate.
- a charge trap electrically erasable nonvolatile memory devicestores charges in traps in a charge trapping region.
- charge trap nonvolatile memory devicesalso may be referred to as Metal Nitride Oxide Silicon (MNOS) or (poly)Silicon Oxide Nitride Oxide Semiconductor (SONOS) devices based on the gate structures thereof.
- MNOSMetal Nitride Oxide Silicon
- SONOSPolySilicon Oxide Nitride Oxide Semiconductor
- the floating gate deviceSince the floating gate device stores charges as free carriers, all stored data may be lost if a tunnel oxide layer thereof is even partially defective. In contrast, since the charge trap device stores charges in spatially isolated traps in the charge trapping region, stored data may not be entirely lost even when a tunnel oxide layer is partially defective. Therefore, the tunnel oxide layer of a charge trap memory device may be made thinner than that of a floating gate memory device. Operational voltages of charge trap nonvolatile memory devices therefore may be lower than those of floating gate nonvolatile memory devices.
- a charge trap electrically erasable nonvolatile memory cellgenerally includes a transistor in an integrated circuit substrate.
- the transistorincludes a gate having a charge trapping region therein. More specifically, the transistor may include spaced apart source and drain regions in an integrated circuit substrate, and a gate on the integrated circuit substrate therebetween.
- the gatemay include a tunnel insulating layer on the substrate, a charge trapping region on the tunnel insulating layer, a blocking insulating layer on the charge trapping region, and a gate electrode on the blocking insulating layer.
- nonvolatile memory devicescan include a program operation, an erase operation and a read operation. These operations will be described with reference to FIG. 1 which graphically illustrates drain current (Id) and gate voltage (VG) for a conventional electrically erasable charge trap nonvolatile memory cell.
- Iddrain current
- VGgate voltage
- an electrically erasable charge trap nonvolatile memory cellhas an initial property that is defined by the relationship between the drain current and the gate voltage, as shown by curve 11 of FIG. 1 .
- An initial threshold voltage V Ti of the memory cellmay be defined from the curve 11 .
- the memory cellis initially programmed, for example, by applying a voltage of 0V to the substrate, and applying a program voltage higher than 0V to the gate electrode. As a result, electrons in a channel area between the source and drain regions are injected into deep-level traps through the tunnel insulating layer.
- the programmed cellhas a predefined relationship between the drain current and the gate voltage, as shown by curve 12 . As shown in FIG. 1 , curve 12 is shifted towards positive gate voltage compared to curve 11 . Curve 12 defines a program threshold voltage V TP that is higher than the initial threshold voltage V Ti .
- an erased cellIn order to erase the programmed or unprogrammed cell, a reference voltage is applied to the substrate and an erase voltage, which is lower than the reference voltage, is applied to the gate electrode. As a result, electrons trapped in the charge trapping region are injected into the substrate through the tunnel insulating layer. Holes in the substrate also may be injected into the traps in the charge trapping region through the tunnel insulating layer. As shown in FIG. 1 , an erased cell defines a relationship between the drain current and the gate voltage thereof, as shown by curve 13 of FIG. 1 . This curve is shifted toward a negative gate voltage ( ⁇ V). Thus, an erased cell has an erase threshold voltage V Te that is lower than the initial threshold voltage V Ti and which may be a negative voltage.
- the erase operationcan impact the endurance of the electrically erasable charge trap nonvolatile memory cell by attacking the interface between the substrate and the tunnel insulating layer during the erase operation, which may create interface traps. These interface traps may deteriorate the endurance and/or speed of an electrically erasable charge trap nonvolatile memory cell.
- Some embodiments of the present inventionprovide an electrically erasable charge trap nonvolatile memory cell that has an initial threshold voltage, a program voltage that is higher than the initial threshold voltage, and an erase threshold voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage.
- a reduced time intervalmay be used for erasing compared to conventional electrically erasable charge trap nonvolatile memory cells that have an erase voltage that is lower than the initial threshold voltage and that may be negative.
- the endurance of electrically erasable charge trap nonvolatile memory cellsmay be increased.
- Methods of erasing programmed electrically erasable charge trap nonvolatile memory cellsapply an erase voltage to the gate for a time interval that is sufficient to lower a threshold voltage of the transistor from a program threshold voltage to an erase threshold voltage that is lower than the program threshold voltage, but is higher than an initial threshold voltage.
- the time intervalmay be determined by setting an endurance specification for a memory cell that includes a critical erase threshold voltage, a critical program threshold voltage and a critical number of erase/program cycle operations for the memory cell.
- An endurance test of a memory cellis performed using an initial time interval. The endurance test is repeatedly performed using a time interval that is increased or decreased from the initial time interval, to obtain the time interval that meets the endurance specification. In other embodiments, attempts are made to successfully read the memory cell using increased or decreased time intervals, after performing an endurance test.
- FIG. 1graphically illustrates a relationship between drain current and gate voltage of a transistor of an electrically erasable charge trap nonvolatile memory cell to show a conventional technique for programming and erasing an electrically erasable charge trap nonvolatile memory cell.
- FIG. 2is a cross-sectional view of electrically erasable charge trap nonvolatile memory cells according to embodiments of the present invention.
- FIG. 3is a graph of drain current versus gate voltage for electrically erasable charge trap nonvolatile memory cells according to embodiments of the present invention.
- FIG. 4graphically illustrates parameters of an endurance test for electrically erasable charge trap nonvolatile memory cells, based on an erase time interval.
- FIG. 5is a flowchart of methods of determining a time interval for erasing a programmed electrically erasable charge trap nonvolatile memory cell according to embodiments of the present invention.
- FIG. 6is a flowchart of methods of determining a time interval for erasing a programmed electrically erasable charge trap nonvolatile memory cell according to other embodiments of the present invention.
- Embodiments of the present inventionmay be used with an electrically erasable charge trap nonvolatile memory cell structure of FIG. 1 , which includes a transistor in an integrated circuit substrate 1 , such as a silicon semiconductor substrate.
- the transistorincludes a gate 6 having a charge trapping region 3 therein. More specifically, the transistor can comprise spaced apart source and drain regions 7 and 7 a , respectively, in the integrated circuit substrate 1 and the gate 6 on the integrated circuit substrate.
- the gate 6comprises a tunnel insulating layer 2 on the substrate 1 , the charge trapping region 3 on the tunnel insulating layer 2 , a blocking insulating layer 4 on the charge trapping region 3 , and a gate electrode 5 on the blocking insulating layer 4 .
- the tunnel insulating layer 2comprises oxide
- the blocking insulating layer 4comprises oxide (which may be the same as or different from the tunnel insulating layer)
- the gate electrode 5comprises conductive material.
- the charge trapping region 3comprises nitride.
- the tunnel insulating layer 2comprises silicon dioxide, doped or undoped metallic oxide and/or doped or undoped metallic oxynitride.
- the charge trapping region 3may comprise an insulator, such as silicon nitride, having deep level traps that can store charges, in which an energy band gap is narrow relative to the tunnel insulating layer 2 and the blocking insulating layer 4 .
- the tunnel insulating layer 2may comprise thermal oxide.
- the blocking insulating layer 4cuts off charges flowing into the charge trapping region 3 from the gate electrode 5 when operational voltages are applied to the gate electrode 5 .
- the blocking insulating layer 4may comprise Chemical Vapor Deposition (CVD) silicon oxide.
- the blocking insulating layer 4may comprise an insulator having a dielectric constant that is higher than that of silicon dioxide.
- the blocking insulating layer 4may comprise a metallic oxide layer and/or a metallic oxynitride layer that includes Group III or Group VB metals.
- the metallic oxide or metallic oxynitridemay be doped with a Group IV element such as Zr, Si, Ti and/or Hf.
- the gate electrode 5may comprise metal, doped polysilicon or a structure of doped polysilicon and metallic silicide, also referred to as polycide.
- a voltage of 0Vmay be applied to the substrate 1
- a program voltage higher than 0Vmay be applied to the gate electrode 5 .
- the program threshold voltage V Tpis higher than the initial threshold voltage V Ti . It will be understood that the initial threshold voltage is defined when charge is not stored in the charge trapping region and the program threshold voltage is defined when charge is stored in the charge trapping region.
- an erase voltagewhich may be of uniform or nonuniform level, is applied to the gate 5 for a time interval that is sufficient to lower the threshold voltage of the transistor from the program threshold voltage V Tp to an erase threshold voltage V′ Te that is lower than the program threshold voltage V Tp but is higher than the initial threshold voltage V Ti .
- the erase threshold voltageis defined when an erase voltage is applied to the gate 6 for a time interval that is sufficient to discharge at least some of the charge that is stored in the charge trapping region 3 .
- a reference voltageis applied to the substrate 1 , at least one of the programmed cells is selected, and an erase voltage is applied to the gate electrode 5 of the selected cell for a time interval that lowers the threshold voltage of the selected cell.
- the time intervalis selected such that the erase threshold voltage V′ Te has a higher value than the initial threshold voltage V Ti of the selected cell.
- the erase threshold voltage V′ Teis higher than the initial threshold voltage V Ti of the cell, some electrons may remain in the charge trapping region 3 of the cell.
- the number of electrons discharged into the substrate 1 by tunneling through the tunnel insulating layer 2may be reduced, compared to the erasing operation of FIG. 1 .
- New traps formed at an interface between the tunnel insulating layer 2 and the substrate 1 by high energy electrons that tunnel through the tunnel insulating layer 2 during an erase operationmay be reduced, to enhance the endurance of the electrically erasable charge trap nonvolatile memory cell.
- FIG. 4is a graph that explains an endurance test of an electrically erasable nonvolatile memory cell based on an erase time interval, in which the horizontal axis indicates the cycle number of program and erase operations and the vertical axis indicates threshold voltages of the memory cells.
- FIGS. 5 and 6are flowcharts of operations for determining a time interval for erasing a programmed electrically erasable charge trap nonvolatile memory cell, according to some embodiments of the present invention.
- an endurance specification of the memory cellis set (Block S 100 ).
- the endurance specificationincludes a critical erase threshold voltage V TEC , a critical program threshold voltage V TPC , and a critical cycle number Nc of erase/program operations.
- the critical erase threshold voltage V TECdefines a maximum allowable value for a threshold voltage of an erased cell
- the critical program threshold voltage V TPCdefines a minimum allowable value for a threshold voltage of a programmed cell.
- the critical erase threshold voltage V TECis lower than a sensing voltage Vs, i.e., a read voltage applied to the gate electrode 5 in a read mode, and the critical program threshold voltage V TPC is higher than the sensing voltage Vs. That is, a voltage difference ⁇ V Te between the critical erase threshold voltage V TEC and the sensing voltage Vs and a voltage difference ⁇ V Tp between the critical program threshold voltage and the sensing voltage Vs may be set based on a sensing margin of a sense amplifier.
- the critical erase threshold voltage V TECis defined to be higher than the initial threshold voltage V Ti .
- the endurance testis carried out by applying the critical cycle number Nc of program and erase cycles to the selected cell (Block S 120 ). In this case, the endurance test is carried out by applying an initial erase time interval Te.
- the endurance testincludes a step of measuring threshold voltages, i.e., an erase threshold voltage and a program threshold voltage of a cell when each erase and program cycle is completed.
- the critical cycle numberis 1000
- 1000 erase threshold voltages V Te and 1000 program threshold voltages V Tpare measured for the initial erase time interval Te.
- the program threshold voltage V Tp and the erase threshold voltage V Tevary as the erase/program cycles increase in number.
- the erase threshold voltages and the program threshold voltagesgradually reduce with an increase in the number of the erase/program cycles, as shown in FIG. 4 .
- a maximum erase threshold voltage V TEMX and a minimum program threshold voltage V TPMNare obtained from the endurance test result at Block S 130 .
- the maximum erase threshold voltage V TEMX and the minimum program threshold voltage V TPMNare compared with the critical erase threshold voltage V TEC and the critical program threshold voltage V TPC , respectively, at Block S 140 . If the endurance test result meets the endurance specification, the initial erase time interval Te is determined as a final erase time interval (Block S 160 ). That is, if the maximum erase threshold voltage V TEMX is lower than the critical erase threshold voltage V TEC and the minimum program threshold voltage V TPMN is higher than the critical program threshold voltage V TPC , the initial erase time interval Te corresponds to a practical minimum erase time interval, i.e., the erasing time interval that can be applied to a floating trap type nonvolatile memory device.
- the initial erase time interval Teis increased by a predetermined time ⁇ Te at Block S 150 . Thereafter, the operations of Blocks S 110 -S 140 are repeatedly performed until the endurance test result meets the endurance specification. In this case, a final erase time corresponds to the practical minimum erase time.
- the initial erase time interval Temay be reduced and the operations of Blocks S 110 -S 140 may be performed until it does not meet the endurance specification.
- an erase time intervalis determined by determining an erase time interval that allows a read operation to be performed accurately.
- the operations of Blocks S 100 and S 130 of FIG. 5do not need to be performed.
- a read operationis performed using the sensing voltage Vs at Block S 140 ′. That is, a cell whose endurance test is completed (Block S 120 ) is read after applying the endurance test with the initial erase time interval Te. For example, the cell whose endurance test is completed is programmed (or erased) and data of the programmed (or erased) cell is read out at Block S 140 ′.
- the initial erase time interval applied to the endurance testis defined as a practical minimum erase time (Block S 160 ). If the erase operation failed at Block S 140 ′, the operations for increasing the erase time interval Te (Block S 150 ), the operations of Blocks S 110 and S 120 , and the read operation of Block S 140 ′ are iteratively carried out until the read operation is successfully carried out.
- the erase time interval Teis reduced at Block S 150 and the operations of Blocks S 110 , S 120 and S 140 ′ may be performed until the read operation fails.
- a pair of first curves 1 p and 1 ecorrespond to the result of an endurance test performed by applying the initial erase time interval.
- the curve 1 pindicates program threshold voltages V Tp measured whenever each program operation is completed during the endurance test.
- the curve 1 eindicates erase threshold voltages V Te measured whenever each erase operation is completed during the endurance test.
- a maximum erase threshold voltage V TEMXis lower than a critical erase threshold voltage V TEC and a minimum program threshold voltage V TPMN is lower than a critical program threshold voltage V TPC .
- the endurance of a newly programmed cellis tested by applying a second erase time interval that is shorter than the initial erase time interval.
- a pair of curves 2 p and 2 eindicate the result of an endurance test performed by applying the second erase time interval. As can be seen from the curves 2 p and 2 e , the second erase time interval meets the endurance specification. In this case, the endurance of a newly programmed cell is tested by applying a third erase time interval shorter than the second erase time interval.
- a pair of third curves 3 p and 3 eindicate the result of the endurance test performed by applying the third erase time interval.
- a minimum program threshold voltage V TPMNis higher than a critical program threshold voltage and a maximum erase threshold voltage V TEMX is higher than a critical erase threshold voltage V TEC .
- the third erase time intervalis not appropriate as an erase time interval of the nonvolatile memory cell.
- the second erase time intervalis set as the erase time.
- Embodiments of the inventionare applicable to both a NAND-type nonvolatile memory device and a NOR-type nonvolatile memory device which include the charge trap nonvolatile memory cell.
- an erasing methodmay be performed for each sector comprising a plurality of memory cells.
- a reference voltageis applied to gate electrodes of the memory cells in the sector and an erase voltage is applied to the substrate during the erase time interval.
- a threshold voltage of the respective memory cellsis lowered. Due to the erase time interval, values of the lowered threshold voltages are higher than those of their initial threshold voltages.
- the endurances of the NAND-type nonvolatile memory device and the NOR-type nonvolatile memory devicemay be enhanced.
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Abstract
Description
This application is a continuation of application Ser. No. 11/128,038, filed May 12, 2005 now U.S. Pat. No. 7,170,795, entitled Electrically Erasable Charge Trap Nonvolatile Memory Cells Having Erase Threshold Voltage That is Higher Than An Initial Threshold Voltage, which is a continuation of application Ser. No. 10/401,372, filed Mar. 28, 2003 now U.S. Pat. No. 6,947,330, entitled Electrically Erasable Charge Trap Nonvolatile Memory Cells Having Erase Threshold Voltage That is Higher Than an Initial Threshold Voltage, and claims the benefit of Korean Patent Application No. 2002-0025195, filed May 8, 2002, the disclosures of all of which are hereby incorporated herein by reference in their entirety as if set forth fully herein.
This invention relates to nonvolatile memory devices, and more particularly to electrically erasable charge trap nonvolatile memory devices.
Integrated circuit memory devices are widely used in consumer and commercial applications. As is well known to those having skill in the art, integrated circuit memory devices include volatile and nonvolatile memory devices. Volatile memory devices may include Dynamic Random Access Memory (DRAM) devices and Static Random Access Memory (SRAM) devices. These volatile memory devices lose their data when their power supplies are interrupted. Nonvolatile memory devices may include Masked Read-Only Memory (MROM) devices, Programmable Read-Only Memory (PROM) devices, Erasable Programmable Read-Only Memory (EPROM) devices and Electrically Erasable Programmable Read-Only Memory (EEPROM) devices. These nonvolatile memory devices retain their stored data even when their power supplies are interrupted.
As is also well known to those having skill in the art, electrically erasable nonvolatile memory devices may include floating gate devices and charge trap devices. A floating gate electrically erasable nonvolatile memory device stores charges in an isolated floating gate. A charge trap electrically erasable nonvolatile memory device stores charges in traps in a charge trapping region. These technologies are generally described in Chapter 3.5 of the textbook entitledSemiconductor Memories: Technology, Testing, and Reliabilityby Ashok K. Sharma, 1997, pp. 104-116, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein. As described therein, charge trap nonvolatile memory devices (also called charge trap EEPROMs) also may be referred to as Metal Nitride Oxide Silicon (MNOS) or (poly)Silicon Oxide Nitride Oxide Semiconductor (SONOS) devices based on the gate structures thereof.
Since the floating gate device stores charges as free carriers, all stored data may be lost if a tunnel oxide layer thereof is even partially defective. In contrast, since the charge trap device stores charges in spatially isolated traps in the charge trapping region, stored data may not be entirely lost even when a tunnel oxide layer is partially defective. Therefore, the tunnel oxide layer of a charge trap memory device may be made thinner than that of a floating gate memory device. Operational voltages of charge trap nonvolatile memory devices therefore may be lower than those of floating gate nonvolatile memory devices.
As is well known to those having skill in the art, a charge trap electrically erasable nonvolatile memory cell generally includes a transistor in an integrated circuit substrate. The transistor includes a gate having a charge trapping region therein. More specifically, the transistor may include spaced apart source and drain regions in an integrated circuit substrate, and a gate on the integrated circuit substrate therebetween. The gate may include a tunnel insulating layer on the substrate, a charge trapping region on the tunnel insulating layer, a blocking insulating layer on the charge trapping region, and a gate electrode on the blocking insulating layer.
As is well known to those having skill in the art, operation of nonvolatile memory devices can include a program operation, an erase operation and a read operation. These operations will be described with reference toFIG. 1 which graphically illustrates drain current (Id) and gate voltage (VG) for a conventional electrically erasable charge trap nonvolatile memory cell. In particular, an electrically erasable charge trap nonvolatile memory cell has an initial property that is defined by the relationship between the drain current and the gate voltage, as shown bycurve 11 ofFIG. 1 . An initial threshold voltage VTiof the memory cell may be defined from thecurve 11.
The memory cell is initially programmed, for example, by applying a voltage of 0V to the substrate, and applying a program voltage higher than 0V to the gate electrode. As a result, electrons in a channel area between the source and drain regions are injected into deep-level traps through the tunnel insulating layer. Once programmed, the programmed cell has a predefined relationship between the drain current and the gate voltage, as shown bycurve 12. As shown inFIG. 1 ,curve 12 is shifted towards positive gate voltage compared tocurve 11.Curve 12 defines a program threshold voltage VTPthat is higher than the initial threshold voltage VTi.
In order to erase the programmed or unprogrammed cell, a reference voltage is applied to the substrate and an erase voltage, which is lower than the reference voltage, is applied to the gate electrode. As a result, electrons trapped in the charge trapping region are injected into the substrate through the tunnel insulating layer. Holes in the substrate also may be injected into the traps in the charge trapping region through the tunnel insulating layer. As shown inFIG. 1 , an erased cell defines a relationship between the drain current and the gate voltage thereof, as shown bycurve 13 ofFIG. 1 . This curve is shifted toward a negative gate voltage (−V). Thus, an erased cell has an erase threshold voltage VTethat is lower than the initial threshold voltage VTiand which may be a negative voltage.
Programming and erasing of floating gate EEPROMs are described in U.S. Pat. No. 6,483,752 to Hirano; U.S. Pat. No. 6,442,075 to Hirano; U.S. Pat. Nos. 6,261,884; 6,347,053 to Kim et al.; U.S. Pat. No. 6,261,884 to Ho et al.; U.S. Pat. No. 6,188,609 to Sunkavalli et al.; U.S. Pat. No. 6,169,693 to Chan et al.; U.S. Pat. No. 6,160,740 to Cleveland; U.S. Pat. No. 6,054,732 to Ho et al.; U.S. Pat. No. 6,026,026 to Chan et al.; U.S. Pat. No. 5,923,589 to Kaida et al.; U.S. Pat. No. 5,790,460 to Chen et al.; and U.S. Pat. No. 5,699,298 to Shiau et al. Moreover, programming and erasing of electrically erasable charge trap nonvolatile memory cells are described in U.S. Pat. No. 6,490,205 to Wang et al.; U.S. Pat. No. 6,418,062 to Hayashi et al.; U.S. Pat. No. 6,266,281 to Derhacobian et al.; U.S. Pat. No. and 5,999,444 to Fujiwara et al.
It is well known that the erase operation can impact the endurance of the electrically erasable charge trap nonvolatile memory cell by attacking the interface between the substrate and the tunnel insulating layer during the erase operation, which may create interface traps. These interface traps may deteriorate the endurance and/or speed of an electrically erasable charge trap nonvolatile memory cell.
Some embodiments of the present invention provide an electrically erasable charge trap nonvolatile memory cell that has an initial threshold voltage, a program voltage that is higher than the initial threshold voltage, and an erase threshold voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage. By allowing the erase threshold voltage to be higher than the initial threshold voltage, a reduced time interval may be used for erasing compared to conventional electrically erasable charge trap nonvolatile memory cells that have an erase voltage that is lower than the initial threshold voltage and that may be negative. By reducing the erasing time, the endurance of electrically erasable charge trap nonvolatile memory cells according to some embodiments of the invention may be increased.
Methods of erasing programmed electrically erasable charge trap nonvolatile memory cells according to some embodiments of the present invention apply an erase voltage to the gate for a time interval that is sufficient to lower a threshold voltage of the transistor from a program threshold voltage to an erase threshold voltage that is lower than the program threshold voltage, but is higher than an initial threshold voltage. According to still other embodiments of the present invention, the time interval may be determined by setting an endurance specification for a memory cell that includes a critical erase threshold voltage, a critical program threshold voltage and a critical number of erase/program cycle operations for the memory cell. An endurance test of a memory cell is performed using an initial time interval. The endurance test is repeatedly performed using a time interval that is increased or decreased from the initial time interval, to obtain the time interval that meets the endurance specification. In other embodiments, attempts are made to successfully read the memory cell using increased or decreased time intervals, after performing an endurance test.
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Moreover, each embodiment described and illustrated herein includes its complementary conductivity type embodiment as well.
Embodiments of the present invention may be used with an electrically erasable charge trap nonvolatile memory cell structure ofFIG. 1 , which includes a transistor in anintegrated circuit substrate 1, such as a silicon semiconductor substrate. The transistor includes agate 6 having a charge trapping region3 therein. More specifically, the transistor can comprise spaced apart source anddrain regions 7 and7a, respectively, in theintegrated circuit substrate 1 and thegate 6 on the integrated circuit substrate. Thegate 6 comprises a tunnel insulating layer2 on thesubstrate 1, the charge trapping region3 on the tunnel insulating layer2, a blocking insulatinglayer 4 on the charge trapping region3, and a gate electrode5 on the blocking insulatinglayer 4.
In some embodiments, the tunnel insulating layer2 comprises oxide, the blocking insulatinglayer 4 comprises oxide (which may be the same as or different from the tunnel insulating layer), and the gate electrode5 comprises conductive material. In other embodiments, the charge trapping region3 comprises nitride. In still other embodiments, the tunnel insulating layer2 comprises silicon dioxide, doped or undoped metallic oxide and/or doped or undoped metallic oxynitride. The charge trapping region3 may comprise an insulator, such as silicon nitride, having deep level traps that can store charges, in which an energy band gap is narrow relative to the tunnel insulating layer2 and the blocking insulatinglayer 4. The tunnel insulating layer2 may comprise thermal oxide.
The blocking insulatinglayer 4 cuts off charges flowing into the charge trapping region3 from the gate electrode5 when operational voltages are applied to the gate electrode5. The blocking insulatinglayer 4 may comprise Chemical Vapor Deposition (CVD) silicon oxide. In other embodiments, the blocking insulatinglayer 4 may comprise an insulator having a dielectric constant that is higher than that of silicon dioxide. For example, the blocking insulatinglayer 4 may comprise a metallic oxide layer and/or a metallic oxynitride layer that includes Group III or Group VB metals. In other embodiments, the metallic oxide or metallic oxynitride may be doped with a Group IV element such as Zr, Si, Ti and/or Hf. The gate electrode5 may comprise metal, doped polysilicon or a structure of doped polysilicon and metallic silicide, also referred to as polycide.
Referring now toFIG. 3 , in order to program a memory cell according to some embodiments of the present invention, a voltage of 0V may be applied to thesubstrate 1, and a program voltage higher than 0V may be applied to the gate electrode5. As a result, electrons in the channel tunnel through the tunnel insulating layer2 to migrate to deep level traps in the charge trapping region3. Accordingly, in aprogramming operation 14, the program threshold voltage VTpis higher than the initial threshold voltage VTi. It will be understood that the initial threshold voltage is defined when charge is not stored in the charge trapping region and the program threshold voltage is defined when charge is stored in the charge trapping region.
In an erasingoperation 15 according to embodiments of the present invention, an erase voltage, which may be of uniform or nonuniform level, is applied to the gate5 for a time interval that is sufficient to lower the threshold voltage of the transistor from the program threshold voltage VTpto an erase threshold voltage V′Tethat is lower than the program threshold voltage VTpbut is higher than the initial threshold voltage VTi. In the erasingoperation 15, at least some of the electrons in the charge trapping region3 tunnel through the tunnel insulating layer2 into thesubstrate 1 into a channel in thesubstrate 1 that is formed beneath thegate 6. Thus, the erase threshold voltage is defined when an erase voltage is applied to thegate 6 for a time interval that is sufficient to discharge at least some of the charge that is stored in the charge trapping region3.
Accordingly, in order to erase an electrically erasable charge trap nonvolatile memory cell according to some embodiments of the present invention, a reference voltage is applied to thesubstrate 1, at least one of the programmed cells is selected, and an erase voltage is applied to the gate electrode5 of the selected cell for a time interval that lowers the threshold voltage of the selected cell. The time interval is selected such that the erase threshold voltage V′Tehas a higher value than the initial threshold voltage VTiof the selected cell.
Without wishing to be bound by any theory of operation, since the erase threshold voltage V′Teis higher than the initial threshold voltage VTiof the cell, some electrons may remain in the charge trapping region3 of the cell. Thus, the number of electrons discharged into thesubstrate 1 by tunneling through the tunnel insulating layer2 may be reduced, compared to the erasing operation ofFIG. 1 . New traps formed at an interface between the tunnel insulating layer2 and thesubstrate 1 by high energy electrons that tunnel through the tunnel insulating layer2 during an erase operation may be reduced, to enhance the endurance of the electrically erasable charge trap nonvolatile memory cell.
Methods of determining a time interval for erasing a programmed electrically erasable charge trap nonvolatile memory cell according to some embodiments of the present invention now will be described with reference toFIGS. 2 ,4,5 and6.
Referring toFIG. 2 ,FIG. 4 andFIG. 5 , an endurance specification of the memory cell is set (Block S100). The endurance specification includes a critical erase threshold voltage VTEC, a critical program threshold voltage VTPC, and a critical cycle number Nc of erase/program operations. The critical erase threshold voltage VTECdefines a maximum allowable value for a threshold voltage of an erased cell, and the critical program threshold voltage VTPCdefines a minimum allowable value for a threshold voltage of a programmed cell. In some embodiments, the critical erase threshold voltage VTECis lower than a sensing voltage Vs, i.e., a read voltage applied to the gate electrode5 in a read mode, and the critical program threshold voltage VTPCis higher than the sensing voltage Vs. That is, a voltage difference ΔVTebetween the critical erase threshold voltage VTECand the sensing voltage Vs and a voltage difference ΔVTpbetween the critical program threshold voltage and the sensing voltage Vs may be set based on a sensing margin of a sense amplifier. In addition, the critical erase threshold voltage VTECis defined to be higher than the initial threshold voltage VTi.
At least one of the cells is selected at Block S110. The endurance test is carried out by applying the critical cycle number Nc of program and erase cycles to the selected cell (Block S120). In this case, the endurance test is carried out by applying an initial erase time interval Te. The endurance test includes a step of measuring threshold voltages, i.e., an erase threshold voltage and a program threshold voltage of a cell when each erase and program cycle is completed. Thus, if the critical cycle number is 1000, 1000 erase threshold voltages VTeand 1000 program threshold voltages VTpare measured for the initial erase time interval Te. As shown inFIG. 4 , the program threshold voltage VTpand the erase threshold voltage VTevary as the erase/program cycles increase in number. In particular, for the electrically erasable charge trap nonvolatile memory cell shown inFIG. 2 , the erase threshold voltages and the program threshold voltages gradually reduce with an increase in the number of the erase/program cycles, as shown inFIG. 4 . A maximum erase threshold voltage VTEMXand a minimum program threshold voltage VTPMNare obtained from the endurance test result at Block S130.
The maximum erase threshold voltage VTEMXand the minimum program threshold voltage VTPMNare compared with the critical erase threshold voltage VTECand the critical program threshold voltage VTPC, respectively, at Block S140. If the endurance test result meets the endurance specification, the initial erase time interval Te is determined as a final erase time interval (Block S160). That is, if the maximum erase threshold voltage VTEMXis lower than the critical erase threshold voltage VTECand the minimum program threshold voltage VTPMNis higher than the critical program threshold voltage VTPC, the initial erase time interval Te corresponds to a practical minimum erase time interval, i.e., the erasing time interval that can be applied to a floating trap type nonvolatile memory device.
If the endurance test result does not meet the endurance specification, the initial erase time interval Te is increased by a predetermined time ΔTe at Block S150. Thereafter, the operations of Blocks S110-S140 are repeatedly performed until the endurance test result meets the endurance specification. In this case, a final erase time corresponds to the practical minimum erase time.
In some embodiments, if the result of an endurance test performed by applying an erase time interval Te meets the endurance specification, the initial erase time interval Te may be reduced and the operations of Blocks S110-S140 may be performed until it does not meet the endurance specification.
In other embodiments, an erase time interval is determined by determining an erase time interval that allows a read operation to be performed accurately. In particular, as shown inFIG. 6 , the operations of Blocks S100 and S130 ofFIG. 5 do not need to be performed. Instead of Block S140 ofFIG. 5 , a read operation is performed using the sensing voltage Vs at Block S140′. That is, a cell whose endurance test is completed (Block S120) is read after applying the endurance test with the initial erase time interval Te. For example, the cell whose endurance test is completed is programmed (or erased) and data of the programmed (or erased) cell is read out at Block S140′. If the read operation is successfully carried out, the initial erase time interval applied to the endurance test is defined as a practical minimum erase time (Block S160). If the erase operation failed at Block S140′, the operations for increasing the erase time interval Te (Block S150), the operations of Blocks S110 and S120, and the read operation of Block S140′ are iteratively carried out until the read operation is successfully carried out.
In some embodiments, if the read operation is successfully carried out by applying an erase time interval Te after an endurance test is completed, the erase time interval Te is reduced at Block S150 and the operations of Blocks S110, S120 and S140′ may be performed until the read operation fails.
A hypothetical result of an endurance test performed according to embodiments of the invention shown inFIG. 5 is described below with reference toFIG. 4 . Returning toFIG. 4 , a pair offirst curves curve 1pindicates program threshold voltages VTpmeasured whenever each program operation is completed during the endurance test. Thecurve 1eindicates erase threshold voltages VTemeasured whenever each erase operation is completed during the endurance test. As can be seen from thecurves
A pair ofcurves 2pand2eindicate the result of an endurance test performed by applying the second erase time interval. As can be seen from thecurves 2pand2e, the second erase time interval meets the endurance specification. In this case, the endurance of a newly programmed cell is tested by applying a third erase time interval shorter than the second erase time interval.
A pair ofthird curves third curves FIG. 4 cannot be obtained, the second erase time interval is set as the erase time.
Embodiments of the invention are applicable to both a NAND-type nonvolatile memory device and a NOR-type nonvolatile memory device which include the charge trap nonvolatile memory cell. In the NAND-type nonvolatile memory device and the NOR-type nonvolatile memory device, an erasing method may be performed for each sector comprising a plurality of memory cells. In some embodiments of this erasing method, a reference voltage is applied to gate electrodes of the memory cells in the sector and an erase voltage is applied to the substrate during the erase time interval. Thus, a threshold voltage of the respective memory cells is lowered. Due to the erase time interval, values of the lowered threshold voltages are higher than those of their initial threshold voltages. As a result, the endurances of the NAND-type nonvolatile memory device and the NOR-type nonvolatile memory device may be enhanced.
In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
Claims (27)
1. A method of erasing a programmed electrically erasable charge trap nonvolatile memory cell that includes a transistor in an integrated circuit substrate, the transistor including a gate having a charge trapping region therein, the transistor having an initial threshold voltage and a program threshold voltage that is higher than the initial threshold voltage, the erasing method comprising:
applying an erase voltage to the gate for a time interval that is sufficient to lower a threshold voltage of the transistor from the program threshold voltage to an erase threshold voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage; wherein the time interval is determined by performing the following:
performing an endurance test of a memory cell using an initial time interval;
attempting to successfully read the memory cell; and
repeatedly performing the endurance test of a memory cell using a time interval that is increased or decreased from the initial time interval, based upon whether the attempting was able to successfully read the memory cell.
2. The method according toclaim 1 wherein the initial threshold voltage is defined when charge is not stored in the charge trapping region and the program threshold voltage is defined when charge is stored in the charge trapping region.
3. The method according toclaim 1 :
wherein the transistor comprises spaced apart source and drain regions in the integrated circuit substrate and the gate on the integrated circuit substrate therebetween; and
wherein the gate comprises a tunnel insulating layer on the substrate, the charge trapping region on the tunnel insulating layer, a blocking insulating layer on the charge trapping region and a gate electrode on the blocking insulating layer.
4. The method according toclaim 3 wherein the tunnel insulating layer comprises oxide, the blocking insulating layer comprises oxide and the gate electrode comprises conductive material.
5. The method according toclaim 3 wherein the charge trapping region comprises nitride.
6. The method according toclaim 4 wherein the blocking insulating layer comprises silicon dioxide, doped or undoped metallic oxide and/or doped or undoped metallic oxynitride.
7. The method according toclaim 1 further comprising:
removing the erase voltage from the gate after the time interval.
8. The method according toclaim 1 :
wherein the program threshold voltage also is higher than a sensing voltage of the transistor and wherein the erase threshold voltage also is lower than the sensing voltage.
9. A method of erasing a programmed electrically erasable charge trap nonvolatile memory cell that includes a transistor in an integrated circuit substrate, the transistor including a gate having a charge trapping region therein, the transistor having an initial threshold voltage and a program threshold voltage that is higher than the initial threshold voltage, the erasing method comprising:
applying an erase voltage to the gate for a time interval that is sufficient to lower a threshold voltage of the transistor from the program threshold voltage to an erase threshold voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage; wherein the time interval is determined by performing the following:
setting an endurance specification for a memory cell;
performing an endurance test of a memory cell using an initial time interval; and
repeatedly performing the endurance test of a memory cell using a time interval that is increased or decreased from the initial time interval to obtain the time interval that meets the endurance specification.
10. The method according toclaim 9 wherein the endurance specification includes a critical erase threshold voltage, a critical program threshold voltage and a critical number of erase/program cycle operations for the memory cell.
11. The method according toclaim 10 wherein the critical erase threshold voltage is set to a value obtained by subtracting at least a sensing margin of a sense amplifier from a sensing voltage.
12. The method according toclaim 10 wherein the critical erase threshold voltage is set to a value that is higher than the initial threshold voltage.
13. The method according toclaim 10 wherein the critical program threshold voltage is set to a value obtained by adding at least a sensing margin of a sense amplifier to a sensing voltage.
14. The method according toclaim 10 :
wherein the endurance test determines a maximum erase threshold voltage and a minimum program threshold voltage; and
wherein the endurance specification defines that the maximum erase threshold voltage is lower than the critical erase threshold voltage and the minimum program threshold voltage is higher than the critical program threshold voltage.
15. The method according toclaim 10 wherein the endurance test is performed by applying at least the critical number of erase/program cycle operations.
16. A method of determining a time interval for erasing a programmed electrically erasable charge trap nonvolatile memory cell that includes a transistor in an integrated circuit substrate, the transistor including a gate having a charge trapping region therein, the transistor having an initial threshold voltage and a program threshold voltage that is higher than the initial threshold voltage, the time interval determining method comprising:
setting an endurance specification for a memory cell that includes a critical erase voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage;
performing an endurance test of a memory cell using an initial time interval; and
repeatedly performing the endurance test of a memory cell using a time interval that is increased or decreased from the initial time interval to obtain the time interval that meets the endurance specification including the critical erase voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage.
17. The method according toclaim 16 wherein the initial threshold voltage is defined when charge is not stored in the charge trapping region and the program threshold voltage is defined when charge is stored in the charge trapping region.
18. The method according toclaim 16 wherein the endurance specification also includes a critical program threshold voltage and a critical number of erase/program cycle operations for the memory cell.
19. The method according toclaim 18 wherein the critical erase threshold voltage is set to a value obtained by subtracting at least a sensing margin of a sense amplifier from a sensing voltage.
20. The method according toclaim 18 wherein the critical program threshold voltage is set to a value obtained by adding at least a sensing margin of a sense amplifier to a sensing voltage.
21. The method according toclaim 18 :
wherein the endurance test determines a maximum erase threshold voltage and a minimum program threshold voltage; and
wherein the endurance specification defines that the maximum erase threshold voltage is lower than the critical erase threshold voltage and the minimum program threshold voltage is higher than the critical program threshold voltage.
22. The method according toclaim 18 wherein the endurance test is performed by applying at least the critical number of erase/program cycle operations.
23. The method according toclaim 16 :
wherein the program threshold voltage also is higher than a sensing voltage of the transistor and wherein the erase threshold voltage also is lower than the sensing voltage.
24. A method of determining a time interval for erasing a programmed electrically erasable charge trap nonvolatile memory cell that includes a transistor in an integrated circuit substrate, the transistor including a gate having a charge trapping region therein, the transistor having an initial threshold voltage and a program threshold voltage that is higher than the initial threshold voltage, the time interval determining method comprising:
performing an endurance test of a memory cell using an initial time interval;
attempting to successfully read the memory cell; and
repeatedly performing the endurance test of a memory cell using a time interval that is increased or decreased from the initial time interval, based upon whether the attempting was able to successfully read the memory cell.
25. The method according toclaim 24 wherein the initial threshold voltage is defined when charge is not stored in the charge trapping region and the program threshold voltage is defined when charge is stored in the charge trapping region.
26. The method according toclaim 24 wherein the endurance test is performed by applying a critical number of erase/program cycle operations.
27. The method according toclaim 24 :
wherein the program threshold voltage is also higher than a sensing voltage of the transistor and wherein the erase threshold voltage is also lower than the sensing voltage.
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Also Published As
| Publication number | Publication date |
|---|---|
| US6947330B2 (en) | 2005-09-20 |
| KR100456596B1 (en) | 2004-11-09 |
| US20070103990A1 (en) | 2007-05-10 |
| KR20030087224A (en) | 2003-11-14 |
| US20030210573A1 (en) | 2003-11-13 |
| US7170795B2 (en) | 2007-01-30 |
| US20050237783A1 (en) | 2005-10-27 |
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