US7429747B2 - Sb-based CMOS devices - Google Patents

Abstract

A group III-V material CMOS device may have NMOS and PMOS portions that are substantially the same through several of their layers. This may make the CMOS device easy to make and prevent coefficient of thermal expansion mismatches between the NMOS and PMOS portions.

Description

BACKGROUNDBackground of the Invention

Most integrated circuits today are based on silicon, a Group IV element of the Periodic Table. Compounds of Group III-V elements such as gallium arsenide (GaAs), indium antimonide (InSb), indium phosphide (InP), and indium gallium arsenide (InGaAs) are known to have far superior semiconductor properties than silicon, including higher electron mobility and saturation velocity. These materials may thus provide superior device performance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional side view that illustrates a group III-V material CMOS device.

FIG. 2 is a cross-sectional side view that illustrates the substrate.

FIG. 3 is a cross-sectional side view that illustrates the nucleation layer on the substrate.

FIG. 4 is a cross-sectional side view that illustrates the first buffer layer on the nucleation layer.

FIG. 5 is a cross-sectional side view that illustrates the second buffer layer on the first buffer layer.

FIG. 6 is a cross-sectional side view that illustrates the NMOS and PMOS bottom barrier layers on the bottom buffer layer.

FIG. 7 is a cross-sectional side view that illustrates the NMOS and PMOS quantum well channel layers on the bottom barrier layers.

FIG. 8 is a cross-sectional side view that illustrates the NMOS and PMOS spacer layers on the quantum well channel layers.

FIG. 9 is a cross-sectional side view illustrates the nucleation layer through spacer layer as blanket layers rather than separate layers.

FIG. 10 is a cross-sectional side view that illustrates the NMOS and PMOS delta-doped layers on the spacer layers.

FIG. 11 is a cross-sectional side view that illustrates the NMOS and PMOS top barrier layers on the delta-doped layers.

FIG. 12 is a cross-sectional side view that illustrates the NMOS and PMOS source/drain layers on the top barrier layers.

FIG. 13 is a cross-sectional side view that illustrates trench isolation formed between the NMOS and PMOS portions.

FIG. 14 illustrates a system in accordance with one embodiment of the present invention.

DETAILED DESCRIPTION

In various embodiments, an apparatus and method relating to the formation of a group III-V material semiconductor device are described. In the following description, various embodiments will be described. However, one skilled in the relevant art will recognize that the various embodiments may be practiced without one or more of the specific details, or with other replacement and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the invention. Nevertheless, the invention may be practiced without specific details. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention, but do not denote that they are present in every embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. Various additional layers and/or structures may be included and/or described features may be omitted in other embodiments.

Various operations will be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the invention. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Operations described may be performed in a different order, in series or in parallel, than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.

FIG. 1 is a cross sectional side view that illustrates a group III-Vmaterial CMOS device100 according to one embodiment of the present invention. TheCMOS device100 includes anNMOS portion160 with an NMOS device such as a transistor and aPMOS portion170 with a PMOS device such as a transistor. There is atrench isolation142 between theNMOS portion160 andPMOS portion170 that isolates the NMOS device from the PMOS device.

In this embodiment, thedevice100 includes asilicon substrate102. On thesubstrate102 is an aluminium antimonide (AlSb)nucleation layer104. On thenucleation layer104 is an aluminium antimonide (AlSb)buffer layer108, which may be referred to as thefirst buffer layer108. On thebuffer layer108 is an indium aluminium antimonide (InAlSb)buffer layer112, which may be referred to as thesecond buffer layer112. Thenucleation layer104 is formed at the same time from the same materials in both theNMOS portion160 andPMOS portion170 of thedevice100, which simplifiesdevice100 fabrication. Similarly, thefirst buffer layer108 is formed at the same time from the same materials in both theNMOS portion160 andPMOS portion170 of thedevice100, andsecond buffer layer112 is formed at the same time from the same materials in both theNMOS portion160 andPMOS portion170 of thedevice100. Because theNMOS portion160 andPMOS portion170 are substantially identical up through thesecond buffer layer112, thedevice100 is easier to make and does not have mismatched coefficient of thermal expansion problems that may be found in group III-V devices that have different materials on the N- and P-MOS portions.

In an embodiment, the III-Vnucleation layer104 is formed on a vicinal (offcut) surface of high-resistivity p-type or n-type Si substrate102 having regular arrays of double-stepped (100) terraces across the substrate surface. A vicinal surface is a higher order crystal plane of theSi substrate102, such as, but not limited to the (211), (511), (013), and (711) planes. A vicinal substrate surface having double-stepped terraces is capable of suppressing anti-phase domains (APD) in the first III-V buffer layer108. An APD is created when a first polar crystal domain of a layer having group III atoms attached to thenonpolar silicon substrate102 surface meets a second polar crystal domain of a layer having group V atoms attached to thesilicon substrate102. A crystal discontinuity may form in the layer at the border between these first and second domains providing recombination-generation centers that may be detrimental to the operation of a semiconductor device. The term “polar” refers to the partially ionic bonding character between the constituents of an III-V compound semiconductor.

There is a NMOSbottom barrier layer114 on thesecond buffer layer112 in theNMOS portion160 and a PMOSbottom barrier layer116 on thesecond buffer layer112 in theNMOS portion170. In the illustrated embodiment, the NMOS and PMOSbottom barrier layers114,116 are formed at the same time from the same materials in both theNMOS portion160 andPMOS portion170. Both the NMOS and PMOSbottom barrier layers114,116 are indium aluminium antimonide (InAlSb) layers. In other embodiments, the NMOS and PMOSbottom barrier layers114,116 may be formed at different times and/or from different materials. In one embodiment, thebottom barrier116 is aluminium gallium antimonide (Al_xGa_1-xSb, x=0.2-1.0). In some embodiments thelower barrier layer114 comprises between about 10% and 100% aluminium, (Al_xIn_1-xSb, with x=0.1-1.0). In a particular embodiment, thelower barrier layer114 is Al_xIn_1-xSb with 15% aluminium (Al_0.15In_0.85Sb). In another embodiment, the PMOSbottom barrier layer116 may comprise AlSb with essentially no In present. Thesecond buffer layer112 may comprise the same materials and compositions as thebottom barrier layer114/116 in some embodiments.

There is a NMOSquantum well118 on the NMOSbottom barrier layer114 in theNMOS portion160 and a PMOSquantum well120 on the PMOSbottom barrier layer116 in theNMOS portion170. In the illustrated embodiment, the NMOS and PMOSquantum wells118,120 are formed at the same time from the same materials in both theNMOS portion160 andPMOS portion170. Both the NMOS and PMOSquantum wells118,120 are indium antimonide (InSb) layers in one embodiment. In other embodiments, the NMOS and PMOSquantum wells118,120 may be formed at different times and/or from different materials, to provide improved performance of the PMOS device. In another embodiment, PMOSquantum well layer120 comprises indium gallium antimonide (In_xGa_1-xSb, x=0.1-1).

Quantum wells118 and120 may be of sufficient thickness to provide adequate channel conductance. In a particular embodiment, the thickness of thequantum wells118,120 is between about 10 nm and about 50 nm. In certain embodimentsquantum well layer118,120 is below a critical thickness that would introduce additional defects due to lattice mismatch. Thequantum well layer118,120 may be strained by the lower barrier layers114,116, thetop barrier layer122,124, or both.

In one embodiment, the III-V buffer layer108 has lattice spacing larger than thesilicon substrate102 and the III-V quantum well (QW)layer118/120 has a lattice spacing larger than the III-V buffer layer108. In another embodiment,nucleation layer104 comprises gallium antimonide (GaSb) andbuffer layer108 comprises AlSb formed between thesilicon substrate102 andQW layer118/120. In another embodiment, the lattice constant of thebuffer materials108 may be gradually incremented from the lattice spacing of thesilicon substrate102 to the lattice spacing of theQW device layer118/120.

It should be appreciated that various III-V device layers may be similarly integrated with Si substrates using other III-V buffer architectures. For example, in another embodiment of the present invention,nucleation layer104 andbuffer layer108 comprises composite structures with gallium arsenide (GaAs) and AlSb, formed between thesilicon substrate102 and theQW device layer118/120. The selection of buffer layers may be based on the larger bandgap materials for the device isolation.

There is anNMOS spacer layer122 on the NMOS quantum well118 in theNMOS portion160 and aPMOS spacer layer124 on the PMOS quantum well120 in theNMOS portion170. In the illustrated embodiment, the NMOS and PMOS spacer layers122,124 are formed at the same time from the same materials in both theNMOS portion160 andPMOS portion170. Both the NMOS and PMOS spacer layers122,124 are indium aluminium antimonide (InAlSb) layers. In other embodiments, the NMOS and PMOS spacer layers122,124 may be formed at different times and/or from different materials. In the illustrated embodiment, the NMOS andPMOS portions160,170 are substantially the same through the spacer layers122,124, meaning formation the spacer layers122,124 and layers below the spacer layers122,124 is simple and without CTE problems, compared todevices100 in which theNMOS portion160 is different than thePMOS portion170.

In a particular embodiment, NMOS quantum well118 is InSb andspacer layer122 is InAlSb, and PMOS quantum well120 is InGaSb andspacer layer124 is AlGaSb. An amount of compressive strain may be inside the NMOS and PMOSquantum wells118,120, depending on the materials and composition of the barrier layers114,116, andspacer layers122,124. Additionally, the amount of strain induced in the quantum well layers118/120 may be tailored by controlling the thickness and lattice mismatch with the lower barrier layers114,116 and the spacer layers122,124. In a specific embodiment, wherein thequantum well118 is InSb and thelower barrier layer114,top barrier layer130, andspacer layer122 comprise Al_xIn_1-xSb with 15% aluminum, thequantum well layer118 is compressively strained. For example, the strain between the NMOS quantum well118, InSb and barrier layer of In_xA_1-xSb is depending on the aluminium inside the In_xAl_1-xSb layer. Higher amounts of Al may result in higher compressive strain inside the InSb quantum well118. ForPMOS170 and given composition of barrier layer composition Ga_0.3Al_0.7Sb, compressive strain can be changed by changing the amount of indium in the In_xGa_1-xSb quantum well120 material.

There is an NMOS delta-dopedlayer126 on theNMOS spacer layer122 in theNMOS portion160 and a PMOS delta-dopedlayer128 on thePMOS spacer layer124 in theNMOS portion170. The NMOS delta-dopedlayer126 is doped with tellurium. The PMOS delta-dopedlayer128 is doped with beryllium.

There is an NMOStop barrier layer130 on the NMOS delta-dopedlayer126 and a PMOStop barrier layer132 on the PMOS delta-dopedlayer128. In the illustrated embodiment, the NMOS and PMOStop barrier layers130,132 are formed at the same time from the same materials in both theNMOS portion160 andPMOS portion170. Both the NMOS and PMOStop barrier layers130,132 are indium aluminium antimonide (InAlSb) layers. In other embodiments, the NMOS and PMOStop barrier layers130,132 may be formed at different times and/or from different materials. In some embodiments, the NMOSbottom barrier layer114,spacer layer122, andtop barrier layer130 consist substantially of the same materials, and the PMOSbottom barrier layer116,spacer layer124, andtop barrier layer132 consist substantially of the same materials (although the PMOS layers may be different than the NMOS layers). For example, in an embodiment the NMOS quantum well118 comprises InSb and the NMOSbottom barrier layer114,spacer layer122, andtop barrier layer130 comprise In_0.8Al_0.2Sb.

The device on theNMOS portion160 also has an NMOS source anddrain layer138, agate dielectric layer146, and agate144. Similarly, the device on thePMOS portion170 also has a PMOS source anddrain layer140, agate dielectric layer150, and agate148. As pictured, these devices are recessed-gate devices, but other types of devices may be used instead.

FIG. 2 is a cross-sectional side view that illustrates thesubstrate102, according to one embodiment of the present invention. In the illustrated embodiment, thesubstrate102 comprises a high-resistivity p-type or n-type vicinal silicon material. A vicinal surface may be prepared by offcutting thesubstrate102 from an ingot. In a particular embodiment, the (100) substrate surface is offcut at an angle between 2 and 12 degrees towards the [110] direction. A vicinal surface is a higher order crystal plane of thesilicon substrate102, such as, but not limited to the (211), (511), (013), (711) planes. A vicinal substrate surface having double-stepped terraces is capable of suppressing anti-phase domains (APD) in the first III-V buffer layer108. The high resistivity is achieved by a low dopant concentration, lower than about 10¹⁶carriers/cm³. In other embodiments, other materials could be used. For example, thesubstrate102 could comprise germanium, could be a silicon-on-insulator substrate102, could comprise gallium arsenide (GaAs), or could comprise another material.

FIG. 3 is a cross-sectional side view that illustrates thenucleation layer104 on thesubstrate102, according to one embodiment of the present invention. In the illustrated embodiment, thenucleation layer104 comprises stiochiometric aluminium antimonide (AlSb). It is formed by molecular beam epitaxy (MBE). It has a thickness of between about 100 A and about 500 A. In other embodiments, GaSb orGaAs nucleation layer104 is grown to a thickness of between 100 A and 500 A. In an alternative embodiment, other suitable nucleation layers104 may be used.

The first layer of thebuffer108 may be formed in a manner that avoids antiphase domains (APD) in the buffer film. Thenucleation layer104 may help prevent this. Anucleation layer104 may be formed using migration enhanced epitaxy (MEE) at a temperature of between 300 C and 600 C. MEE proceeds in a fashion similar to that of atomic layer deposition (ALD). MEE has a relatively slower growth rate, approximately 0.1 um/hr, because once the group V element is introduced to thesubstrate102 there is a hold time during which both the group V source and group III source shutters are closed (shuttered). This hold time accommodates the relatively lower mobility of the group V species. No hold time is required for group III species because surface migration of this species relatively higher mobility. In a particular MEE embodiment, thesubstrate102 surface is exposed to an antimony (Sb) source for approximately 10 seconds to form a monolayer of Sb on the lowest terrace level. The Sb source and is then shuttered for a hold time of approximately 60 seconds. This relatively long hold time allows for the Sb species to migrate on the surface of thesilicon substrate102 to ensure the bonding sites of the lowest terrace level are filled. Then, thesubstrate102 surface is exposed to either a gallium (Ga) or aluminium (Al) source for approximately 10 seconds. No hold time is required because of the high surface mobility of Ga or Al. Next, the Sb is reopened for approximately 10 second and then again closed for a hold time. This process is repeated to form either a GaSb orAlSb nucleation layer104 sufficiently thick to fill all the terraces of thesilicon substrate102, approximately150A in a particular embodiment. In an embodiment, AlSb nucleation temperatures are in between 300 C and 600 C. In particular AlSb embodiment, the MEE growth temperature is between approximately 400 C and approximately 570 C. Higher temperature embodiments may enable a higher quality film. In other embodiments, MEE can be utilized to form anucleation layer104 of an alternate buffer material, such as, but not limited to GaAs or GaSb.

In yet another embodiment, anucleation layer104 is formed on thevicinal silicon substrate102 utilizing traditional MBE (without migration enhancement). The relatively higher flux of this particular embodiment using traditional MBE provides higher film growth rates and therefore higher throughput than MEE embodiments. In a particular MBE nucleation embodiment, AlSb is formed on thesilicon substrate102 at a temperature between approximately 400 C and approximately 570 C. The high-flux embodiments are well suited to AlSb because of the relatively low vapor pressure and high sticking coefficient of antimony (Sb) as compared to arsenic (As) of GaAs films. In other embodiments, anucleation layer104 of an alternate buffer material, such as, but not limited to GaAs or GaSb is formed.

FIG. 4 is a cross-sectional side view that illustrates thefirst buffer layer108 on thenucleation layer104, according to one embodiment of the present invention. In the illustrated embodiment, thefirst buffer layer108 comprises aluminium antimonide (AlSb). It has a thickness between about 1 and 5 microns. In other embodiments, it may have sufficient thickness that most defects present at its bottom surface have been reduced to a desired amount at its top surface. Any suitable method may be used to form thefirst buffer layer108.

This growth of thefirst buffer layer108 may be performed at a higher temperature than that used for thenucleation layer104. Whilefirst buffer layer108 may considered and is shown as a separate layer fromnucleation layer104, bothlayers104,108 may be considered buffers, withlayer108 thickening the III-V buffer layer started bynucleation layer104, and gliding dislocations. The film quality oflayer108 may be superior to that of thenucleation layer104 because it is formed at a higher growth temperature. Also, during the formation oflayer108, the flux rate can be relatively high because thepolar nucleation layer104 may eliminate danger of APD formation. In an embodiment,AlSb film108 is grown upon either a GaSb orAlSb nucleation layer104 at a growth temperature in the range of 500 C. and 700 C. In a particular embodiment,AlSb film108 is grown upon aGaSb nucleation layer104 at a growth temperature between approximately 510 C and approximately 570 C.

In still another embodiment, the III-V buffer layer108 is formed on atraditional silicon substrate102 having a lower order plane surface, such as, but not limited to (100), without use ofnucleation layer104. The III-V buffer layer108 is grown without a nucleation step and permitted to formed anti-phase domains. In an embodiment, the single-step growth is performed at a temperature between 500 C. and 700 C. Once the film thickness is greater than approximately 1.5 um, the anti-phase domains are substantially annihilated and thebuffer layer108 becomes single-domain. In a particular embodiment, III-V buffer layer108 comprising between approximately 1.5 and 2.0 um AlSb is formed on a traditional (100)silicon substrate102 that has a 0 degree offcut.

FIG. 5 is a cross-sectional side view that illustrates thesecond buffer layer112 on thefirst buffer layer108, according to one embodiment of the present invention. In the illustrated embodiment, thesecond buffer layer112 comprises indium aluminium antimonide (In_1-xAl_xSb: x=0.1-1.0). It has a thickness between about 1 and 5 microns. In other embodiments, it may have sufficient thickness that most defects present at its bottom surface are not present at its top surface. Any suitable method may be used to form thesecond buffer layer112.

As described above with respect toFIG. 1, in the illustrated embodiment the NMOS andPMOS portions160,170 are substantially identical at this stage of fabrication. Each of thenucleation layer104,first buffer layer108, andsecond buffer layer112 is formed as a blanket layer over both the NMOS andPMOS portions160,170. Thus, the formation of the structure shown inFIG. 5 is relatively simple, and has no coefficient of thermal expansion (CTE) mismatches between the NMOS andPMOS portions160,170.

FIG. 6 is a cross-sectional side view that illustrates the NMOS and PMOS bottom barrier layers114,116 on thebottom buffer layer112, according to one embodiment of the present invention. In the illustrated embodiment, the bottom barrier layers114,116 areseparate layers114,116 laterally adjacent to each other. The separate NMOS and PMOS bottom barrier layers114,116 are formed at different times and/or from different materials. For example, thePMOS portion170 may be masked while the NMOSbottom barrier layer114 is formed, then theNMOS portion160 may be masked while the PMOSbottom barrier layer116 is formed. The NMOSbottom barrier layer114 may comprise InAlSb, while the PMOSbottom barrier layer116 may comprise AlGaSb.

Generally, thebottom barrier layer114,116 is formed of a higher band gap material than the overlying quantum well118,120. Thebottom barrier layer114,116 is of sufficient thickness to provide a potential barrier to charge carriers in the transistor channel. In one embodiment, thebottom barrier114 is InAlSb between 2 um and 5 um thick. In still other embodiments,bottom barrier layer114,116 is microns thick to further reduce defect density in the quantum well118,120. Thebottom barrier114,116 may also be fully relaxed. In some embodiments thebottom barrier layer114,116 comprises between about 10% and 100% aluminum, (Al_xIn_1-xSb, with x=0.1-1.0). In a particular embodiment, thebottom barrier layer114,116 is Al_xIn_1-xSb with 15% aluminum (Al_0.15In_0.85Sb).

In an alternative embodiment,PMOS portion170 comprises anucleation layer104 andbuffer layer108 of GaSb,bottom barrier116 of Al_xGa_1-xSb116 and In_xGa_1-xSb quantum well120. In an embodiment,PMOS portion170 comprises nucleation layer and buffer layer of AlSb, bottom barrier of In_xAl_1-xSb116 and InSb quantum well120.

Additionally, thebottom barrier114 for NMOS may be graded. In one embodiment, thebottom barrier114 is substantially linearly graded from x=1.0 (AlSb) at the interface with thebuffer layer108 to x=0 (InSb) at the interface with thequantum well layer118. In such an embodiment, the gradedlower barrier layer114 and subsequently grown InSbquantum well layer118 may be lattice matched at their interface, and the gradedbottom barrier layer114 does not induce strain into the InSbquantum well layer118.

In another embodiment, theNMOS bottom barrier114 is linearly graded from x=1.0 (AlSb) at the interface with theNMOS buffer layer108 to x=0.15 (Al_0.15In_0.85Sb) at the interface with the NMOSquantum well layer118. In such an embodiment, theNMOS bottom barrier114 induces strain in the subsequently grown NMOSquantum well layer118. In some embodiments the NMOSbottom barrier layer114 is graded at a rate of less than 25% Al/um. In one embodiment, the NMOSbottom barrier layer114 is graded at a rate of 5% Al/um. Alternatively, theNMOS bottom barrier114 may be step graded using a series of layers with decreasing aluminum concentration. In one embodiment, the NMOSlower barrier114 is step graded in a series of decreasing 5% (x=0.05) aluminum increments.

Other materials may also be used for the bottom barrier layers114,116 in other embodiments. Any suitable method may be used to form the NMOS and PMOS bottom barrier layers114,116. The bottom barrier layers114,116 are between 100-500 angstroms thick in some embodiments, although other thickness may be used.

While illustrated asseparate layers114,116 laterally adjacent to each other, theselayers114,116 may be regions of a single blanket layer in other embodiments. Thus, in these other embodiments the NMOS and PMOS bottom barrier layers114,116 are substantially identical because they are formed at the same time from the same materials in both theNMOS portion160 andPMOS portion170. The bottom barrier layers114,116 may comprise In_1-xAl_xSb (x=0.1-1.0) in such an embodiment. In a particular embodiment, the bottom barrier layers114/116 is Al_xIn_1-xSb with 15% aluminum (Al_0.15In_0.85Sb).

FIG. 7 is a cross-sectional side view that illustrates the NMOS and PMOS quantum well channel layers118,120 on the bottom barrier layers114,116, according to one embodiment of the present invention. In the illustrated embodiment, the quantum well channel layers118,120 areseparate layers118,120 laterally adjacent to each other. The separate quantum well channel layers118,120 are formed at different times and/or from different materials. For example, thePMOS portion170 may be masked while the NMOS quantumwell channel layer118 is formed, then theNMOS portion160 may be masked while the PMOS quantumwell channel layer118 is formed. The NMOS quantum well channel layers118 may comprise InSb, while the PMOS quantum well channel layers120 may comprise In_xGa_1-xSb, with between about 20% and 50% In. For PMOS portion,QW channel layer120 may be In_xGa_1-xSb (x=0.2-0.5) andbottom barrier layer116 may be Al_xGa_1-xSb (x=0.3-1.0) in some embodiments. Other materials may also be used in other embodiments. Any suitable method may be used to form the NMOS and PMOS quantum well channel layers118,120. The quantum well channel layers118,120 are between 50-300 angstroms thick in this embodiment, although other thickness may be used.

While illustrated asseparate layers118,120 laterally adjacent to each other, theselayers118,120 may be regions of a single blanket layer in the other embodiments. Thus, in these embodiments the NMOS and PMOS quantum well channel layers118,120 may substantially identical because they are formed at the same time from the same materials in both theNMOS portion160 andPMOS portion170. The quantum well channel layers118,120 may both comprise stoichiometric InSb.

FIG. 8 is a cross-sectional side view that illustrates the NMOS and PMOS spacer layers122,124 on the quantum well channel layers118,120, according to one embodiment of the present invention. In the illustrated embodiment, the NMOS and PMOS spacer layers122,124 are asseparate layers122,124 laterally adjacent to each other. The separate NMOS and PMOS spacer layers122,124 laterally adjacent to each other are formed at different times and/or may comprise different materials. Any suitable method may be used to form the NMOS and PMOS spacer layers122,124. The spacer layers122,124 are between 20 and 100 angstroms thick in this embodiment, although other thickness may be used. The spacer layers122,124 may comprise InAlSb.

Quantum well118/120 may be of a sufficient thickness to provide adequate channel conductance. In a particular embodiment, the thickness of the quantum well118/120 is between about 10 nm and about 50 nm. In certain embodimentsquantum well layer118/120 is below a thickness that would introduce additional defects due to lattice mismatch. Thequantum well layer118/120 may be strained by thebottom barrier layer114/116, thespacer layer122,124, thetop barrier layer130/132, or any combination.

Thespacer layer122/124 may have the same material composition as thetop barrier layer130/132. In some embodiments, thespacer layer122,124 and thetop barrier layer130,132 may be considered to be different portions of the same top barrier layer. They may have the same material composition and work together to perform the same functions.

While illustrated asseparate layers122,124 laterally adjacent to each other, theselayers122,124 may be regions of a single blanket layer in other embodiments. Thus, in these embodiments the NMOS and PMOS spacer layers122,124 are substantially identical because they are formed at the same time from the same materials in both theNMOS portion160 andPMOS portion170.

FIG. 9 is a cross-sectional side view illustrates thenucleation layer104 throughspacer layer122,124 as blanket layers rather than separate layers. As described above, the NMOS andPMOS portions160,170 may be substantially identical up through the spacer layers122,124 because bothportions160,170 of each respective layer may be simultaneously formed by blanket depositions. In other embodiments, blanket depositions may be used for lower layers, while different materials for NMOS andPMOS portions160,170 may be begun to be used at any stage. Making the NMOS andPMOS portions160,170 substantially identical through the use of blanket layers further in the fabrication process may make formation of thedevice100 easier, cheaper, and may reduce CTE mismatches. Device performance may be tuned by using different materials for layers on the NMOS andPMOS portions160,170. These factors may influence at what point in the fabrication process the NMOS andPMOS portions160,170 may begin to differ.

FIG. 10 is a cross-sectional side view that illustrates the NMOS and PMOS delta-dopedlayers126,128 on the spacer layers122,124, according to one embodiment of the present invention. The NMOS delta-dopedlayer126 comprises different materials than the PMOS delta-dopedlayer128. Any suitable method may be used to form the NMOS and PMOS delta-dopedlayers126,128. For example, thePMOS portion170 may be masked while the NMOS delta-dopedlayer126 is formed, then theNMOS portion160 may be masked while the PMOS delta-dopedlayer128 is formed. The NMOS delta-dopedlayer126 is doped with tellurium, while the PMOS delta-dopedlayer128 is doped with beryllium. In other embodiments, other dopants may be used. The delta-dopedlayers126,128 are each just one to a few monolayers thick in some embodiments, although they may have different thicknesses in other embodiments. In one embodiment the dopedlayer126/128 is delta doped and has a thickness of approximately 3 Å to 5 Å. In other embodiments the dopedlayer126/128 is modulation doped and has a thickness between approximately 5 Å and 50 Å.

FIG. 11 is a cross-sectional side view that illustrates the NMOS and PMOStop barrier layers130,132 on the delta-dopedlayers126,128, according to one embodiment of the present invention. In the illustrated embodiment, these areseparate layers130,132 laterally adjacent to each other. They may also be deposited as a single blanket layer in other embodiments. In such embodiments the NMOS and PMOStop barrier layers130,132 are substantially identical because they are formed at the same time from the same materials in both theNMOS portion160 andPMOS portion170. Any suitable method may be used to form the NMOS and PMOStop barrier layers130,132. Thetop barrier layers130,132 are between 100-500 angstroms thick in this embodiment, although other thickness may be used. Thetop barrier layer130/132 may have various thicknesses and in certain embodiments thetop barrier layer130/132 is between about 20 nm and 500 nm thick. Thetop barrier layers130,132 comprise InAlSb, although other materials may be used in other embodiments.

In another embodiment, thetop barrier130/132 is linearly graded from x=0.1 (Al_0.1In_0.9Sb) inregion122 at the interface with thequantum well layer118/120 to x=0.4 (Al_0.4In_0.6Sb) at the opposite surface. In such an embodiment, thetop barrier130/132 and/or thespacer layer122,124 (as mentioned previously, both the spacer layers122,124 andtop barrier layers130,32 may be considered part of the top barrier) may induce a strain in thequantum well layer118/120. In a particular embodiment of PMOS portion,bottom116 andtop barrier132 layers are Al0.7Ga0.3Sb and InxGa1-xSb (x=0.2-0.5) isQW120.

Top barrier layer130/132 (andspacer layers122,124; when discussing properties of one thetop barrier layer130,132 orspacer layers122,124, the description is applicable to the other one of the two layers as well) may have a larger band gap than the quantum well118/120, thereby confining a majority of charge carriers within the quantum well118/120 for reduced device leakage. Thetop barrier layer130/132 may be formed of the same or different materials as thelower barrier layer114/116. In some embodiments thetop barrier layer130/132 comprises between about 10% and 40% aluminum, (Al_xIn_1-xSb, with x=0.1-0.4). At above approximately 40% aluminum, the top device layer may oxidize upon removal from the deposition chamber. In a particular embodiment, thetop barrier layer130/132 is Al_xIn_1-xSb with 15% aluminum (Al_0.15In_0.85Sb). In an alternative embodiment, thetop barrier layer130/132 may contain greater than 40% aluminum.

Additionally, the amount of strain induced in thequantum well layer118/120 may be tailored by controlling the thickness and lattice mismatch with thelower barrier layer114/116 andtop barrier layer130/132 orspacer layer122,124. In a specific embodiment, wherein thequantum well118 is InSb and thelower barrier layer114 andtop barrier layer130 are composed of Al_xIn_1-xSb with 15% aluminum, thequantum well layer118 is compressively strained.

FIG. 12 is a cross-sectional side view that illustrates the NMOS and PMOS source/drain layers138,140 on thetop barrier layers130,132, according to one embodiment of the present invention. The source/drain layers138,140 may be formed by blanket depositing a layer of material, then masking one of the NMOS or PMOS layers138,140 while appropriately doping theunmasked layer138,140. In another embodiment, thelayers138,140 may be separately deposited and doped. Any suitable method may be used to form the NMOS and PMOS source/drain layers138,140, and any suitable materials used. In an alternative embodiment, optional etch stop layers (not shown) are used for NMOS and PMOS in order to etch selectively the top barrier for enhancement mode operation. In another embodiment,top barrier layers130,132 are used for source/drain contact of both NMOS and PMOS.

FIG. 13 is a cross-sectional side view that illustratestrench isolation142 formed between the NMOS andPMOS portions160,170, according to one embodiment of the present invention. Thetrench isolation142 is formed by making a trench then filling it with insulating material. In other embodiments, thetrench isolation142 may be formed differently. In the illustrated embodiment, thetrench isolation142 extends down to thesubstrate102. In other embodiments, thetrench isolation142 may extend to a different depth. For example, thetrench isolation142 may only extend as far as thesecond buffer layer112 in some embodiments.

Further processes may be performed to make the NMOS and PMOS devices shown in the NMOS andPMOS portions160,170 ofFIG. 1. Thegate dielectric146,150 andgates144,148 are formed. In the illustrated embodiment, thegates144,148 are recessed gates of transistors, so portions of the source/drain layers138,140 are removed to recess thegates144,148. In other embodiments, other types of transistors or other devices may be formed, which may lack the recesses in the source/drain layers138,140. Thegates144,148 may be metal gates, withgate dielectrics146,150 that comprise high dielectric constant materials. Other materials may be used for thegates144,148 andgate dielectrics146,150 as well.

FIG. 14 illustrates asystem1400 in accordance with one embodiment of the present invention. One ormore CMOS devices100 may be included in thesystem1400 ofFIG. 14. As illustrated, for the embodiment,system1400 includes acomputing device1402 for processing data.Computing device1402 may include amotherboard1404. Coupled to or part of themotherboard1404 may be in particular aprocessor1406, and anetworking interface1408 coupled to abus1410. A chipset may form part or all of thebus1410.

Depending on the applications,system1400 may include other components, including but are not limited to volatile andnon-volatile memory1412, a graphics processor (integrated with themotherboard1404 or connected to the motherboard as a separate removable component such as an AGP or PCI-E graphics processor), a digital signal processor, a crypto processor, mass storage1414 (such as hard disk, compact disk (CD), digital versatile disk (DVD) and so forth), input and/oroutput devices1416, and so forth.

In various embodiments,system1400 may be a personal digital assistant (PDA), a mobile phone, a tablet computing device, a laptop computing device, a desktop computing device, a set-top box, an entertainment control unit, a digital camera, a digital video recorder, a CD player, a DVD player, or other digital device of the like.

The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the “top” surface of that substrate; the substrate may actually be in any orientation so that a “top” side of a substrate may be lower than the “bottom” side in a standard terrestrial frame of reference and still fall within the meaning of the term “top.” The term “on” as used herein (including in the claims) does not indicate that a first layer “on” a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims (26)

1. A CMOS device with an NMOS portion and a PMOS portion, each of the NMOS portion and PMOS portion comprising:

a nucleation layer on a substrate comprising aluminium antimonide;

a first buffer layer on the nucleation layer comprising aluminium antimonide;

a bottom barrier layer, the bottom barrier layer comprising aluminium indium antimonide;

a quantum well channel on the bottom barrier layer, the quantum well channel comprising indium antimonide;

a spacer layer on the quantum well channel; and

a delta-doped layer on the spacer layer, the delta-doped layer in the NMOS portion comprising a different dopant than the delta-doped layer in the PMOS portion;

a barrier layer on the delta-doped layer; and

wherein the nucleation layer, and the buffer layer each consist of substantially the same materials in both the NMOS portion and the PMOS portion.

2. The device ofclaim 1, wherein each of the NMOS portion and PMOS portion comprises a bottom barrier layer on the buffer layer, the bottom barrier layer comprising indium aluminium antimonide and consisting of substantially the same materials in both the NMOS portion and the PMOS portion.

3. The device ofclaim 2, wherein each of the NMOS portion and PMOS portion comprises a quantum well layer on the bottom barrier layer, the quantum well layer comprising indium antimonide.

4. The device ofclaim 3, wherein each of the NMOS portion and PMOS portion comprises a spacer layer on the quantum well layer, the spacer layer comprising indium aluminium antimonide.

5. The device ofclaim 4, wherein the NMOS portion comprises an N-type delta-doped layer on the spacer layer and the PMOS portion comprises a P-type delta doped layer on the spacer layer.

6. The device ofclaim 5, wherein each of the NMOS portion and PMOS portion comprises a top barrier layer on the spacer layer, the top barrier layer comprising indium aluminium antimonide.

7. The device ofclaim 6, wherein the NMOS portion comprises an N-type source region and an N-type drain region on the top barrier layer, and the PMOS portion comprises a P-type source region and a P-type drain region on the top barrier layer and wherein each of the NMOS portion and PMOS portion comprises a gate electrode.

8. The device ofclaim 1, wherein the each of the NMOS portion and the PMOS comprises a bottom barrier layer on the buffer layer, the bottom barrier layer of the NMOS portion comprising indium aluminium antimonide and the bottom barrier layer of the PMOS portion comprising aluminium gallium antimonide.

9. The device ofclaim 1, wherein:

each of the NMOS portion and PMOS portion comprises a bottom barrier layer on the buffer layer; and

each of the NMOS portion and PMOS portion comprises a quantum well layer on the bottom barrier layer, the quantum well layer of the NMOS portion comprising indium antimonide and the quantum well layer of the PMOS portion comprising indium gallium antimonide.

10. The device ofclaim 1, wherein:

each of the NMOS portion and PMOS portion comprises a bottom barrier layer on the buffer layer;

each of the NMOS portion and PMOS portion comprises a quantum well layer on the bottom barrier layer;

each of the NMOS portion and PMOS portion comprises a spacer layer on the quantum well layer; and

the NMOS portion comprises a delta-doped layer doped with tellurium on the spacer layer and the PMOS portion comprises a delta-doped layer doped with beryllium on the spacer layer.

11. The device ofclaim 1, wherein the NMOS portion comprises an N-type source region and an N-type drain region, and the PMOS portion comprises a P-type source region and a P-type drain region, and wherein each of the NMOS portion and PMOS portion comprises a gate electrode.

12. A CMOS device with an NMOS portion and a PMOS portion, comprising:

a substrate;

a first buffer layer on the substrate, the first buffer layer comprising aluminium antimonide;

a second buffer layer on the first buffer layer, the second buffer layer comprising indium aluminium antimonide;

wherein the first buffer layer in the NMOS portion consists of substantially the same material as the first buffer layer in the PMOS portion, and the second buffer layer in the NMOS portion consists of substantially the same material as the second buffer layer in the PMOS portion;

an NMOS gate, source, and drain in the NMOS portion; and

a PMOS gate, source, and drain in the PMOS portion.

13. The device ofclaim 12, further comprising:

a bottom barrier layer on the second buffer layer, the bottom barrier layer comprising indium aluminium antimonide, wherein the bottom barrier layer in the NMOS portion consists of substantially the same material as the bottom barrier layer in the PMOS portion.

14. The device ofclaim 13, further comprising:

a channel layer on the bottom barrier layer, the channel layer comprising indium antimonide, wherein the channel layer in the NMOS portion consists of substantially the same material as the channel layer in the PMOS portion.

15. The device ofclaim 14, further comprising:

a spacer layer on the channel layer, the spacer layer comprising indium aluminium antimonide, wherein the spacer layer in the NMOS portion consists of substantially the same material as the spacer layer in the PMOS portion.

16. The device ofclaim 12, further comprising a nucleation layer comprising aluminium antimonide between the substrate and the first buffer layer, wherein the nucleation layer in the NMOS portion consists of substantially the same material as the nucleation layer in the PMOS portion.

17. A CMOS device, comprising:

an NMOS device having:

a first buffer layer on a substrate, source, a drain, and a gate;

a second buffer layer on the first buffer layer, the second buffer layer comprising indium aluminium antimonide;

a quantum well channel on the second buffer layer;

a spacer layer on the quantum well channel;

a delta-doped layer on the spacer layer;

an n-type source and drain on the delta-doped layer;

a gate on the delta-doped layer;

a PMOS device having:

a first buffer layer on a substrate, source, a drain, and a gate;

a second buffer layer on the first buffer layer, the second buffer layer comprising indium and antimony;

a quantum well channel on the second buffer layer;

a spacer layer on the quantum well channel;

a delta-doped layer on the spacer layer;

a p-type source and drain on the delta-doped layer;

a gate on the delta-doped layer;

wherein the first buffer layer of the NMOS device consists of substantially the same material as the first buffer layer of the PMOS device, and the second buffer layer of the NMOS device consists of substantially the same material as the second buffer layer of the PMOS device.

18. The device ofclaim 17, wherein the PMOS second buffer layer comprises indium aluminium antimonide.

19. The device ofclaim 17, wherein the PMOS second buffer layer comprises indium gallium antimonide.

20. The device ofclaim 17, wherein each of the NMOS and PMOS devices further comprise a bottom barrier layer between the second buffer layer and the quantum well channel, the bottom barrier layer comprises indium aluminum antimonide, and wherein the bottom barrier layer of the NMOS device consists of substantially the same material as the bottom barrier layer of the PMOS device.

21. The CMOS device ofclaim 17, wherein:

the NMOS device further comprises:

a bottom barrier layer comprising indium aluminium antimonide between the second buffer layer and the quantum well channel;

a top-barrier layer comprising indium aluminium antimonide on the delta-doped layer;

the NMOS quantum well channel comprises indium antimonide;

the NMOS spacer layer comprises indium aluminium antimonide;

the NMOS source, drain and gate are on the top barrier layer;

the PMOS device further comprises:

a bottom barrier layer between the second buffer layer and the quantum well channel;

a top-barrier layer comprising aluminium gallium antimonide on the delta-doped layer;

the PMOS second buffer layer comprises aluminium gallium antimonide;

the PMOS quantum well channel comprises indium gallium antimonide;

the PMOS spacer layer comprises aluminium gallium antimonide;

the PMOS source, drain, and gate are on the top barrier layer;

wherein the first buffer layer of the NMOS device consists of substantially the same material as the first buffer layer of the PMOS device.

22. The device ofclaim 21, wherein the bottom barrier layer of the NMOS device consists of a different material than the bottom barrier layer of the PMOS device.

23. The device ofclaim 21, wherein the second buffer layer of the NMOS device consists of a different material than the second buffer layer of the PMOS device.

24. The device ofclaim 17, wherein each of the NMOS and PMOS devices further comprises the a nucleation layer between the substrate and the first buffer layer, the NMOS nucleation layer consisting of substantially the same material as the PMOS nucleation layer.

25. The device ofclaim 17, further comprising a trench isolation region between the NMOS and PMOS devices, the trench isolation region extending from at least the source and drain to at least second buffer layer.

26. The device ofclaim 17, wherein the gate of each of the NMOS and PMOS devices is a recessed gate.

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