US7317429B2 - Display panel and display panel driving method - Google Patents

Abstract

A display panel includes an optical element which has a pair of electrodes and exhibits an optical operation corresponding to an electric current flowing between the electrodes, and a switch circuit which supplies a memory current having a predetermined current value to a current line during a selection period, and stops the supply of the memory current to the current line during a non-selection period. A current memory circuit stores current data corresponding to the current value of the memory current flowing through the current line during the selection period and, in accordance with the current data stored during the selection period, supplies a display current having a current value substantially equal to the memory current to the optical element during the non-selection period.

Description

This application is a U.S. National Phase Application under 35 USC 371 of International Application PCT/JP02/13034 filed Dec. 12, 2002.

TECHNICAL FIELD

The present invention relates to a display panel having an active driving type optical element and a method of driving the same, and to a driving circuit and the like of, e.g., a light emitting element as the optical element.

BACKGROUND ART

A light emitting element display is conventionally known in which light emitting elements such as organic EL (electroluminescent) elements, inorganic EL elements, or light emitting diodes are arrayed in a matrix manner as optical elements, and the respective light emitting elements emit light to display an image. In particular, an active matrix driving type light emitting element display has advantages such as high luminance, high contrast, high resolution, and low power consumption. Therefore, such displays are developed in recent years, and particularly an organic EL element has attracted attention.

In some displays of this type, organic EL light emitting elements and a thin film transistor for driving this light emitting element by switching are combined in one pixel. A plurality of selection scan lines parallel to each other are formed on a transparent substrate. A plurality of signal lines perpendicular to these selection scan lines are also formed on the substrate. More specifically, two thin film transistors made of amorphous silicon (to be referred to as a-Si hereinafter) are formed in a region surrounded by the selection scan lines and signal lines, and one light emitting element is also formed in this region. That is, two transistors are formed in one pixel. The emission luminance (cd/m²) of an organic EL element is determined by the value per unit area of an electric current flowing through the element.

FIG. 11 shows an equivalent circuit diagram of one pixel in a conventional light emitting element display. As shown inFIG. 11, twotransistors103 and104 are connected to aselection scan line101 andsignal line102 per pixel. One and the other of the source and drain electrodes of thetransistor104 are connected to anemission voltage line106 having a positive constant voltage and to an anode of alight emitting element105, respectively.

In this structure, when theselection scan line101 is selected (when thetransistor103 which is an N-channel transistor is turned on by applying a high-level voltage to the selection scan line101), a signal voltage is applied from thesignal line102 to the gate electrode of thetransistor104 via thetransistor103. Accordingly, thetransistor104 is turned on, an electric current flows from theemission voltage line106 to thelight emitting element105 via thetransistor104, and thus thelight emitting element105 emits light. When theselection scan line101 is unselected, thetransistor103 is turned off, and the voltage of the gate electrode of thetransistor104 is held. An electric current flows from the lightemission voltage line106 to thelight emitting element105 via thetransistor104, and thelight emitting element105 emits light.

In the above structure, the magnitude of an electric current flowing between the drain and source of thetransistor104 is adjusted by adjusting the magnitude of the gate-source voltage of thetransistor104, i.e., the voltage of thesignal line102. That is, the magnitude of the drain-source current of thetransistor104 is adjusted by using an unsaturated gate voltage as the voltage applied to the gate of thetransistor104, thereby adjusting the magnitude of the electric current flowing in thetransistor104 andlight emitting element105. Consequently, the luminance of thelight emitting element105 is adjusted, and tone display is performed. Between selection and non-selection after that, i.e., during one frame period, the gate-source voltage of thetransistor104 is substantially held constant, so the luminance of thelight emitting element105 is also held constant. This driving method is called a voltage driving method by which the luminance tone is controlled by modulation of the output signal voltage from thesignal line102 to thetransistor103.

The channel resistances of thetransistors103 and104 depend upon the ambient temperature and change after a long-term operation. Therefore, it is difficult to display images with a desired luminance tone for long time periods. Also, if the channel layers of thetransistors103 and104 are made of polysilicon, the channel resistances depend upon the numbers of grain boundaries as the interfaces between adjacent crystal grains in these channel layers. This may vary the numbers of crystal grains in the channel layers of a plurality oftransistors103 and a plurality oftransistors104 formed in a single panel. Especially when the grain size is increased to obtain high mobility, the number of grain boundaries in the channel layer inevitably decreases, so even a slight difference between the numbers of grain boundaries in the channel length direction has a large effect on the channel resistance. This varies the magnitudes of the drain-source currents of thetransistors104 in the individual pixels, resulting in variations in the display characteristics of the individual pixels in a single panel. As a consequence, no accurate tone control can be performed. Accordingly, variations in the characteristics of thetransistor104 of each pixel must fall within a range required to control the tone of each pixel. However, as the resolution of an EL element increases, it becomes more difficult to make the characteristics of thetransistors104 of the individual pixels uniform.

As described above, in some active matrix driving EL elements, a plurality of transistors are combined as active elements formed in each pixel. In some cases, a p-channel transistor and n-channel transistor are combined. When the characteristics of carriers are taken into consideration, a polysilicon transistor functions as a p-type transistor. When an amorphous silicon transistor is used, however, good physical properties with which the transistor functions well cannot be obtained. This makes it impossible to apply amorphous silicon transistors which can be fabricated at a relatively low cost.

Some of the active matrix EL display devices as described above are not voltage driven. In some of these display devices, an active element is made up of four or more transistors in one pixel. If these transistors are formed on a substrate, the upper surface is made uneven by the thicknesses of these transistors. Therefore, an organic EL layer is desirably formed on a flat portion other than the transistor formation region. In this case, no light is emitted in this transistor formation region, so a non-light-emitting portion is inevitably formed in the pixel. When one pixel emits light with a predetermined tone luminance, the brightness can be roughly set by (emission luminance per unit area)×(emission area of one pixel)×(emission time). However, when a large number of transistors are formed, the emission area of one pixel decreases. To compensate for this small emission area, the emission luminance per unit area must be increased. Unfortunately, this shortens the light emission life because the organic EL layer is applied with a higher voltage and current. In addition, when the number of transistors in one pixel increases, the fabrication yield lowers exponentially.

Also, if too many transistors are connected in series with an EL element in a pixel, the voltage dividing ratio of these transistors rises. As a consequence, the power consumption is high.

Accordingly, one advantage of the present invention is that pixels stably display images with desired luminance in a display panel.

Another advantage of the present invention is that the display area per pixel of a display panel is increased.

DISCLOSURE OF INVENTION

To achieve the above advantages, a display panel according to one aspect of the present invention comprises:

one or more optical elements which have a pair of electrodes and exhibit an optical operation corresponding to an electric current flowing between the pair of electrodes;

one or more current lines;

one or more switch circuits which supply a memory current having a predetermined current value to the current line during a selection period, and stop supply of a current to the current line during a non-selection period; and

one or more current memory circuits which store current data corresponding to the current value of the memory current flowing through the current line during the selection period and, in accordance with the current data stored during the selection period, supply a display current having a current value substantially equal to the memory current to the optical element during the non-selection period.

In the display panel having the above arrangement, the current memory circuit stores the current data corresponding to the current value of the memory current flowing during the selection period. Accordingly, the display current having a current value substantially equal to the memory current can be supplied to the optical element. Current control is thus performed by the current values, not by voltage values. This suppresses the influence of variations in the voltage-current characteristic of the control system and allows the optical element to stably display images with desired luminance.

In each pixel, the current memory circuit has only one current control transistor connected in series with the optical element. With this arrangement, the voltage between the optical element and current memory circuit is divided only by the optical element and current control transistor. This achieves a low voltage and consequently low power consumption driving.

Furthermore, each pixel can operate by using the three transistors, i.e., the current control transistor, current data write control transistor, and current path control transistor. This decreases the number of transistors in one pixel and increases the area occupied by the optical element. Decreasing the number of transistors in one pixel also decreases a reduction in the fabrication yield. Additionally, when an EL element is used as the optical element, the ratio of the light emission area in the pixel can be increased, and the apparent brightness improves accordingly. Therefore, the value of an electric current flowing per unit area can be decreased to a relatively small value. This suppresses deterioration of the EL element caused by an injection current.

Even when a transistor is formed in the current memory circuit as described above, changes in the voltage characteristic caused by deterioration of this transistor have no large influence since the transistor is driven by current control. Consequently, a display current having an accurate current value can be supplied.

A display panel driving method according to another aspect of the present invention comprises:

a current storage step of supplying a memory current having a predetermined current value to a current memory circuit and storing current data corresponding to the current value during a selection period; and

a display step of supplying, to an optical element during a non-selection period, a display current having a current value substantially equal to the memory current in accordance with the current data stored in the current storage step.

In the present invention as described above, unlike in conventional devices, no preset voltage value is written in a transistor, so no electric current having a current value corresponding to the voltage value is supplied to an optical element. As a consequence, a display current having an accurate current value can be supplied.

Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.

BRIEF DESCRIPTION OF DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention, and together with the general description given above and the detailed description of the embodiments given below, serve to explain the principles of the invention.

FIG. 1 is block diagram showing a practical arrangement of a light emitting element display to which the present invention is applied;

FIG. 2 is a plan view schematically showing one pixel of the light emitting element display;

FIG. 3 is a sectional view showing a section taken along a line III-III inFIG. 2;

FIG. 4 is a sectional view showing a transistor surrounded by a line IV inFIG. 3;

FIG. 5A is an equivalent circuit diagram of the pixel of the light emitting element display, showing the driving principle in a selection period, andFIG. 5B is an equivalent circuit diagram of the pixel of the light emitting element display, showing the driving principle in a non-selection period;

FIG. 6 is a graph showing a relationship between an electric current flowing through an n-channel MOSFET connected in series with a light emitting element of the light emitting element display, and a voltage applied to this MOSFET;

FIG. 7 is a timing chart showing an operation of a driving circuit;

FIG. 8A is an equivalent circuit diagram of a pixel of another light emitting element display, showing the driving principle in a selection period of the pixel of this light emitting element display, andFIG. 8B is an equivalent circuit diagram of the pixel of this light emitting element display, showing the driving principle in a non-selection period;

FIG. 9A is an equivalent circuit diagram of a pixel of still another light emitting element display, showing the driving principle in a selection period of the pixel of this light emitting element display, andFIG. 9B is an equivalent circuit diagram of the pixel of this light emitting element display, showing the driving principle in a non-selection period;

FIG. 10A is an equivalent circuit diagram of a pixel of still another light emitting element display, showing the driving principle in a selection period of the pixel of this light emitting element display, andFIG. 10B is an equivalent circuit diagram of the pixel of this light emitting element display, showing the driving principle in a non-selection period; and

FIG. 11 is an equivalent circuit diagram showing the circuit configuration of one pixel of a conventional light emitting element display.

BEST MODE FOR CARRYING OUT OF THE INVENTION

Practical embodiments of the present invention will be described below with reference to the accompanying drawings. However, the scope of the invention is not limited to the illustrated embodiments.

First Embodiment

FIG. 1 is a block diagram showing a practical arrangement of a light emitting element display to which the present invention is applied. As shown inFIG. 1, the light emittingelement display1 includes, as its basic configuration, an active matrix type light emitting panel (driver)2 and acontroller6 for controlling the wholelight emitting display1. The light emittingelement display1 is a so-called active matrix driving type display device. Thelight emitting panel2 includes a transparent substrate30 (shown inFIG. 3) which is made of, e.g., borosilicate glass, silica glass, and another glass which is resistant against temperatures during a transistor fabrication process (to be described later).Light emitting unit7 is formed on thetransparent substrate30, has a plurality of pixels and emits light so as to display an image corresponding to image data from thecontroller6. Aselection scan driver3, emissionvoltage scan driver4, anddata driver5 are formed on thetransparent substrate30 and drive the individual pixels of thelight emitting unit7. Theseselection scan driver3, emissionvoltage scan driver4, anddata driver5 are so connected as to be able to receive control signals φs, φe, and φd, respectively, and data from thecontroller6. Various lines and elements are formed on thetransparent substrate30 to construct thelight emitting panel2.

In thislight emitting panel2, m selection scan lines X₁, X₂, . . . , X_mare formed parallel to each other on thetransparent substrate30. In addition, m emission voltage scan lines Z₁, Z₂, . . . , Z_mare formed on thetransparent substrate30 so as to alternate with the selection scan lines X₁, X₂, . . . , X_m, respectively. These emission voltage scan lines Z₁, Z₂, . . . , Z_mare parallel to and separated from the selection scan lines X₁, X₂, . . . , X_m. Furthermore, current lines Y₁, Y₂, . . . , Y_nare formed on thetransparent substrate30 substantially perpendicularly to the selection scan lines X₁, X₂, . . . , X_mand emission voltage scan lines Z₁, Z₂, . . . , Z_m. The selection scan lines X₁, X₂, . . . , X_m, emission voltage scan lines Z₁, Z₂, . . . , Z_m, and current lines Y₁, Y₂, . . . , Y_nare made of chromium, chromium alloy, aluminum, aluminum alloy, titanium, titanium alloy, or a low-resistance material selected from at least one of these materials. The selection scan lines X₁, X₂, . . . , X_mand emission voltage scan lines Z₁, Z₂, . . . , Z_mcan be formed by patterning the same conductive film. The current lines Y₁, Y₂, . . . , Y_nare formed to cross the selection scan lines X₁, X₂, . . . , X_mand emission voltage scan lines Z₁, Z₂, . . . , Z_m. The selection scan lines X₁, X₂, . . . , X_mand emission voltage scan lines Z₁, Z₂, . . . , Z_mare insulated from the current lines Y₁, Y₂, . . . , Y_nby, e.g., agate insulating film32 or semiconductor layer33 (to be described later).

A plurality of organic EL elements ij are arrayed in a matrix manner on thetransparent substrate30. One organic EL element is formed in each of the regions surrounded by the current lines Y₁, Y₂, . . . , Y_nand selection scan lines X₁, X₂, . . . , X_m. A driving circuit for supplying a predetermined electric current to each organic EL element is formed around each organic EL element. One organic EL element and the driving circuit corresponding to this element form one pixel Pij of thelight emitting unit2. That is, one organic EL element is formed for each of (m33 n) pixels.

Details of thelight emitting unit2 will be explained below.FIG. 2 is a plan view showing the major components of one pixel of thislight emitting unit2.FIG. 3 is a sectional view taken along line III inFIG. 2.FIG. 4 is a sectional view showing a region surrounded by a line IV inFIG. 3 in an enlarged scale.FIGS. 5A and 5B are equivalent circuit diagrams showing driving of two adjacent pixels P_i,jand P_i,j+1. For better understanding ofFIG. 2, agate insulating film32, first impurity dopedlayer34, second impurity dopedlayer35, block insulatingfilm36,cathode electrode43, and the like are at least partially omitted. InFIG. 3, hatching is partially omitted to make the drawing readily understandable.

The organic EL element E_i,jis formed in a region surrounded by the selection scan line X_i, current line Y_j, selection scan line X_i+1(i.e., a selection scan line positioned in the lower stage of the selection scan line X_i, and positioned below the emission voltage scan line Z_i; not shown), and current line Y_j+1(i.e., a signal line to the right of the current line Y_j; not shown). Around this organic EL element E_i,j, acapacitor13 and threetransistors10,11, and12 as n-channel amorphous silicon thin film transistors are formed. A pixel driving circuit D_i,jfor driving the organic EL element E_i,jincludes thetransistors10,11, and12,capacitor13, and the like. Here, i is an integer from 1 to m, and j is an integer from 1 to n. That is, the “selection scan line X_i” means a selection scan line in the ith row, the “emission voltage scan line Z_i” means an emission voltage scan line in the ith row, and the “current line Y_j” means a signal line in the jth column. The “pixel driving circuit D_i,j” means a driving circuit of a pixel P_i,jin the ith row and jth column, and the “organic EL element E_i,j” means an organic EL element of this pixel P_i,jin the ith row and jth column. G, S, and D attached toreference numerals10,11, and12 mean the gate, source, and drain, respectively, of a transistor.

As shown inFIG. 4, thetransistor12 has a gate electrode (control terminal)12G, agate insulating film32 formed on the entire surface of thelight emitting unit7, asemiconductor layer33 for forming a single channel as a current path, a first impurity dopedlayer34, a second impurity dopedlayer35, ablock insulating film36, adrain electrode12D, asource electrode12S, and a protective insulating film39. Thegate electrode12G is formed on thetransparent substrate30. Thegate electrode12G is made of chromium, chromium alloy, aluminum, aluminum alloy, titanium, titanium alloy, or a low-resistance material selected from at least one of these materials.

Thegate insulating film32 is formed on thegate electrode12G andtransparent substrate30 so as to cover thesegate electrode12G andtransparent substrate30. Thegate insulating film32 is made of, e.g., silicon nitride or silicon oxide which transmits light and has insulating properties. Thegate insulating film32 also covers the gate electrodes of other transistors (all transistors formed on the transparent substrate30), the selection scan lines X₁, X₂, . . . , X_m, and the emission voltage scan lines Z₁, Z₂, . . . , Z_m.

Thesemiconductor layer33 opposes thegate electrode12G via the part of the gate insulating film32 (i.e., thesemiconductor layer33 is formed immediately above thegate electrode12G). Thissemiconductor layer33 is made of intrinsic amorphous silicon. On thissemiconductor layer33, theblock insulating film36 made of silicon nitride is formed. The first and second impurity doped layers34 and35 are formed to be separated from each other on one and the other side portions of theblock insulating film36. The first impurity dopedlayer34 covers one side portion of thesemiconductor layer33 and one side portion of theblock insulating film36. The second impurity dopedlayer35 covers the other side portion of thesemiconductor layer33 and the other side portion of theblock insulating film36. These first and seconddoped layers34 and35 are made of amorphous silicon doped with n-type impurity ions.

Thedrain electrode12D is formed on the first impurity dopedlayer34, and thesource electrode12S is formed on the second impurity dopedlayer35. Thesedrain electrode12D andsource electrode12S are made of chromium, chromium alloy, aluminum, aluminum alloy, titanium, titanium alloy, or a low-resistance material selected from at least one of these materials, and have a function of blocking the transmission of visible light. This prevents the incidence of light from the outside or from the organic EL element E_i,jonto thesemiconductor layer33 and first and second impurity doped layers34 and35.

Thesource electrode12S anddrain electrode12D are electrically insulated from each other. Thesource electrode12S is electrically connected to an anode electrode41 (to be described later) of the EL element. The protective insulating film39 covers thetransistors10,11, and12,capacitor13, selection scan lines X₁, X₂, . . . , X_m, current lines Y₁, Y₂, . . . , Y_n, and emission voltage scan lines Z₁, Z₂, . . . , Z_m, and exposes theanode electrode41. That is, the protective insulating film39 is so formed as to cover the surroundings of theanode electrode41 in a matrix manner.

Thetransistor12 constructed as above is an MOS field-effect transistor having thesemiconductor layer33 as a channel region. Since thetransistors10 and11 have substantially the same structure as thetransistor12, a detailed description thereof will be omitted. One electrode of thecapacitor13 is thegate electrode12G of thetransistor12, and the other electrode of thecapacitor13 is thesource electrode12S of thetransistor12. Since thegate insulating film32 formed between the two electrodes of thecapacitor13 is made of a dielectric material, thiscapacitor13 functions as a capacitor in which current data corresponding to the value of an electric current flowing between the source and drain of thetransistor12 is written. That is, thecapacitor13 functions as a parasitic capacitance in the gate-to-source path of thetransistor12 and stores the written current data. Thesource10S of thetransistor10 and thegate12G of thetransistor12 are connected via a plurality ofopenings47 formed in thegate insulating film32. Thedrain12D of thetransistor12 is connected to one of the emission voltage scan lines Z₁, Z₂, . . . , Z_mvia a plurality ofopenings48 formed in thegate insulating film32.

To form thetransistors10,11, and12,capacitor13, selection scan lines X₁, X₂, . . . , X_m, emission voltage scan lines Z₁, Z₂, . . . , Z_m, and current lines Y₁, Y₂, . . . , Y_na metal film deposited on thetransparent substrate30 is first patterned to form the gate electrodes of thetransistors10,11, and12, the selection scan lines X₁, X₂, . . . , X_m, and the emission voltage scan lines Z₁, Z₂, . . . , Z_min the same step. Subsequently, agate insulating film32 of thetransistors10,11, and12 is formed on the entire surface, and asemiconductor layer33, block insulatingfilm36, and impurity doped layers34 and35 are formed in accordance with their respective shapes. After that, a metal film deposited on top of these components is patterned to form asource electrode10S anddrain electrode10D of thetransistor10, asource electrode11S anddrain electrode11D of thetransistor11, asource electrode12S anddrain electrode12D of thetransistor12, and current lines Y₁, Y₂, . . . , Y_nin the same step. At the intersections of the current lines Y₁, Y₂, . . . , Y_nand selection scan lines X₁, X₂, . . . , X_mand the intersections of the current lines Y₁, Y₂, . . . , Y_nand emission voltage scan lines Z₁, Z₂, . . . , Z_m, theblock insulating film36 is interposed in addition to thegate insulating film32. After that, a protective insulating film39 is formed by patterning. In this embodiment, a channel width W or channel length L of thesemiconductor layer33 of each of the threetransistors10,11, and12 is appropriately set in accordance with the transistor characteristics of that transistor.

The protective insulating film39 is covered with an insulatingpartition wall46 made of, e.g., silicon nitride (FIG. 3). Thepartition wall46 has openings in positions corresponding to theanode electrodes41 surrounded by the current lines Y₁, Y₂, . . . , Y_nparallel in the longitudinal direction, and the selection scan lines X₁, X₂, . . . , X_mand emission voltage scan lines Z₁, Z₂, . . . , Z_mparallel in the lateral direction. The organic EL element E_i,jis formed in each of regions partitioned in a matrix manner by thepartition wall46, i.e., in each of regions surrounded by the current lines Y₁, Y₂, . . . , Y_n, selection scan lines X₁, X₂, . . . , X_m, and emission voltage scan lines Z₁, Z₂, . . . , Z_m. Thepartition wall46 is formed after the formation of thetransistors10,11, and12,capacitor13, selection scan lines X₁, X₂, . . . , X_m, current lines Y₁, Y₂, . . . , Y_n, and emission voltage scan lines Z₁, Z₂, . . . , Z_m.

The organic EL element E_i,jwill be described next. As shown inFIG. 3, this organic EL element E_i,jincludes theanode electrode41, anorganic EL layer42, and acathode electrode43. In the organic EL element E_i,j, theorganic EL layer42 andcathode electrode43 are stacked in this order from theanode electrode41. Theanode electrode41 is formed on thegate insulating film32 in each of the regions surrounded by the current lines Y₁, Y₂, . . . , Y_nand selection scan lines X₁, X₂, . . . , X_m. Thisanode electrode41 preferably injects holes efficiently into theorganic EL layer42. Examples of the main component of the material of thisanode electrode41 are tin-doped indium oxide (ITO), zinc-doped indium oxide (IZO), indium oxide (In₂O₃), tin oxide (SnO₂), and zinc oxide (ZnO). Theanode electrode41 is formed before the formation of thesource electrode12S of thetransistor12. After thisanode electrode41 is formed, thesource electrode12S of thetransistor12 is formed, and the protective insulating film39 is formed after that.

Theorganic EL layer42 is formed on theanode electrode41. Thisorganic EL layer42 can have any of a three-layered structure in which a hole transporting layer, light emitting layer, and electron transporting layer are stacked in this order from theanode electrode41, a two-layered structure in which a hole transporting layer and light emitting layer are stacked in this order from theanode electrode41, a single-layered structure having only a light emitting layer, and some other layer arrangement.

Theorganic EL layer42 has a function of injecting holes and electrons, a function of transporting holes and electrons, and a function of emitting light by generating excitons by recombination of holes and electrons. Thisorganic EL layer42 is desirably an electronically neutral organic compound. Theorganic EL layer42 like this achieves well-balanced injection and transportation of holes and electrons.

It is possible to appropriately mix an electron transporting material in the light emitting layer, a hole transporting material in the light emitting layer, or both an electron transporting material and hole transporting material in the light emitting layer.

This light emitting layer of theorganic EL layer42 contains a light emitting material. A high-molecular material is used as this light emitting material. Examples of the high-molecular material are polycarbazole-based, polyparaphenylene-based, polyarylenevinylene-based, polythiophene-based, polyfluorene-based, polysilane-based, polyacetylene-based, polyaniline-based, polypyridine-based, polypyridinevinylene-based, and polypyrrol-based materials. Examples of the high-molecular material are a polymer or copolymer of a monomer or oligomer forming the above-mentioned high-molecular material (polymer), a polymer or copolymer of a derivative of the monomer or oligomer, and a polymer or copolymer obtained by polymerizing a monomer having oxazole (oxandiazole, triazole, or diazole) or a triphenylamine skeleton. Monomers of these polymers include monomers and precursor polymers which form the aforementioned compounds when given heat, pressure, UV, or electron beams. It is also possible to introduce a non-conjugate unit which combines these monomers.

Practical examples of these high-molecular material are polyfluorene, polyvinylcarbazole, polytodecylthiophene (?), polyethylenedioxythiophene, a polystyrenesulfonic acid dispersed modified product, poly9,9-dialkylfluorene, poly(thienylene-9,9-dialkylfluorene), poly(2,5-dialkylparaphenylenethienylene), (dialkyl: R=C1 to C20), polyparaphenylenevinylene, poly(2-methoxy-5-(2′-ethylhexyloxy)-paraphenylenevinylene), poly(2-methoxy-5-(2′-ethyl-pentyloxy)-paraphenylenevinylene), poly(2,5-dimethyl-paraphenylenevinylene), poly(2,5-thienylenevinylene), poly(2,5-dimethoxyparaphenylenevinylene), and poly(1,4-paraphenylenecyanovinylene).

A film of a low-molecular material, instead of the high-molecular material, can also be formed by evaporation. Depending on the properties of a low-molecular material, the low-molecular material can be dissolved in a solvent and used by coating. Furthermore, a low-molecular material can be dispersed as a dopant in a polymer. When a low-molecular material is thus dispersed in a polymer, it is possible to use various types of polymers including well-known, general-purpose polymers.

Examples of the low-molecular light emitting material (light emitting substance or dopant) are anthracene, naphthalene, phenanthrene, pyrene, tethracene, coronene, chrysene, fluoresceine, perylene, phthaloperylene, naphthaloperylene, perinone, phthaloperinone, naphthaloperinone, diphenylbutadiene, tetraphenylbutadiene, coumarin, oxadiazole, aldazine, bisbenzoquizoline (?), bisstyryl, pyrazine, oxine, aminoquinoline, imine, diphenylethylene, vinylanthracene, diaminocarbazole, pyran, thiopyran, polymethine, merocyanine, an imidazole chelated oxynoid compound, 4-dicyanomethylene-4H-pyran, 4-dicyanomethylene-4H-thiopyran, diketone, a chlorine-based compound, and their derivatives. Practical examples of the low-molecular light emitting material are Alq3 and quinacridone.

The light emitting material is not limited to those enumerated above.

Examples of the electron transporting material contained in the light emitting layer or electron transporting layer are a quinoline derivative, e.g., 8-quinolinol such as tris(8-quinolinolato)aluminum(Alq3) or an organic metal complex having a derivative of this 8-quinolinol as a ligand, an oxadiazole derivative, a perylene derivative, a pyridine derivative, a pyrimidine derivative, a quinoxaline derivative, a diphenylquinone derivative, and a nitro-substituted fluorene derivative.

Examples of the hole transporting material contained in the light emitting layer or hole transporting layer are a tetraarylbenzicine (?) compound (triaryldiamine or triphenyldiamine: TPD), aromatic tertiary amine, a hydrazone derivative, an imidazole derivative, an oxadiazole derivative having an amino group, and polythiophene.

Thecathode electrode43 is formed on theorganic EL layer42. Thisorganic EL layer42 is so formed as to extend on thepartition wall46, and thecathode electrode43 is a layer shared by all the organic EL elements E_1,1to E_m,nformed in thelight emitting unit2. Thiscathode electrode43 is made of a material having excellent electron injection properties and a small work function. More specifically, it is preferable to combine at least one metal selected from lithium, indium, magnesium, calcium, barium, and a rare earth element and a low-resistance material such as gold, silver, copper, aluminum, and chromium. More preferably, the low-resistance material is formed on the low-work-function material.

When an electric field is generated between theanode electrode41 andcathode electrode43 in the organic EL element E_i,jhaving the stacked structure as described above, holes are injected from theanode electrode41 into theorganic EL layer42, and electrons are injected from thecathode electrode43 into theorganic EL layer42. These holes and electrons are transported to the light emitting layer of theorganic EL layer42, and recombine in this light emitting layer to generate excitons, thereby emitting light.

In thelight emitting panel2 described above, ashielding layer44 such as silicone oil or an organic insulating material which shields water and oxygen is formed on thecathode electrode43 on the entire panel surface. In addition, asealing layer45 made of a transparent material such as silica glass or some other glass or a transparent material such as resin is formed on theshielding layer44. Theshielding layer44 and sealinglayer45 protect the organic EL elements E_i,j, pixel driving circuits D_i,j, selection scan lines X₁, X₂, . . . , X_m, emission voltage scan lines Z₁, Z₂, . . . , Z_m, and current lines Y₁, Y₂, . . . , Y_n.

The circuit configuration of the pixel driving circuit D_i,jwill be described in detail below. As shownFIGS. 2,5A, and5B, the gate electrode10G of thetransistor10 is connected to the selection scan line X_i. Thedrain electrode10D of thetransistor10 is connected to thedrain electrode12D of thetransistor12 and to the emission voltage scan line Z_i. Thesource electrode10S of thetransistor10 is connected to thegate electrode12G of thetransistor12 and to one terminal of thecapacitor13. Thesource electrode12S of thetransistor12 is connected to the other terminal of thecapacitor13 and thedrain electrode11D of thetransistor11, and to theanode electrode41 of the organic EL element E_i,j. The gate electrode11G of thetransistor11 is connected to the selection scan line X_i. Thesource electrode11S of thetransistor11 is connected to the current line Y_j. A reference potential V_SSis supplied to the cathode electrode of the organic EL element E_i,j. A voltage V_NSEapplied to the emission voltage scan line Z_iduring a non-selection period (to be described in detail later) is equal to or higher than the reference potential V_SS. A voltage V_SEapplied to the emission voltage scan line Z_iduring a selection period (to be described in detail later) is equal to or lower than the reference potential V_SS. For example, this reference potential V_SSis the ground potential.

As shown inFIG. 1, theselection scan driver3 is connected to the selection scan lines X₁to X_mof thelight emitting unit2. Thisselection scan driver3 is a so-called shift register. In accordance with the control signals φs output from thecontroller6, theselection scan driver3 sequentially outputs scan signals to the selection scan lines in turn from the selection scan line X₁to the selection scan line X_m(after this selection scan line X_m, to the selection scan line X₁), thereby sequentially selecting thetransistors10 and11 connected to these selection scan lines X₁to X_m. More specifically, when thetransistors10 and11 are n-channel transistors, theselection scan driver3 selectively applies a selection scan signal at a high-level ON voltage V_ON(much higher than the reference potential V_SS) or low-level OFF voltage V_OFF(equal to or lower than the reference potential V_SS) to the selection scan lines X₁to X_m. That is, in a selection period during which one selection scan line X_iof the selection scan lines X₁to X_mis selected, theselection scan driver3 outputs a pulse of the ON voltage V_ONto this selection scan line X_i, thereby turning on thetransistors11 and12 (thetransistors11 and12 of all of the pixel driving circuits D_i,1to D_i,n) connected to the selection scan line X_i. In a non-selection period other than this selection period, theselection scan driver3 applies the OFF voltage V_OFFto the selection scan line X_ito turn off thesetransistors11 and12. Desirably, the selection periods of the selection scan lines X₁to X_mdo not overlap each other. However, when a plurality of pixels P connected to the current line Y_jin the same column are to emit the same tone, it is also possible to synchronize selection periods of the selection scan lines X₁to X_mand synchronize selection periods of the emission voltage scan lines Z₁to Z_m.

The emissionvoltage scan driver4 is connected to the emission voltage scan lines Z₁to Z_mof thelight emitting unit2. This emissionvoltage scan driver4 is a so-called shift register. That is, in accordance with the control signals φe output from thecontroller6, the emissionvoltage scan driver4 sequentially outputs pulse signals to the emission voltage scan lines in turn from the emission voltage scan line Z₁to the emission voltage scan line Z_m(after this emission voltage scan line Z_m, to the emission voltage scan line Z₁). More specifically, the emissionvoltage scan driver4 applies a selection voltage (e.g., 0 [V] if the reference potential is the ground potential) equal to or lower than the reference potential V_SSto the emission voltage scan lines Z₁to Z_mat a predetermined cycle. That is, in the selection period during which one selection scan line X_iof the selection scan lines X₁to X_mis selected, the emissionvoltage scan driver4 applies a low-level selection voltage to the emission voltage scan line Z₁. In the non-selection period, on the other hand, the emissionvoltage scan driver4 applies the high-level, non-selection voltage V_NSEhigher than the reference potential V_SSto the emission voltage scan line Z_i. This non-selection voltage V_NSEcan be a negative voltage as long as it is higher than the reference potential V_SS, but has a sufficiently large value by which a source-drain voltage V_DSof thetransistor12 reaches a saturated region. Details of the saturated voltage will be explained later.

In accordance with input image data, thecontroller6 outputs the control signals φs, φe, and φd to theselection driver3,emission scan driver4, anddata driver5, respectively.

Thedata driver5 is a current sink type driver which receives the control signals from thecontroller6 and draws, from the current lines Y₁to Y_n, memory currents flowing to thedata driver5. That is, thisdata driver5 has a current sink circuit and, as indicated by the arrows shown inFIG. 5A, gives rise to memory currents in the current lines Y₁to Y_n. The current value of a display current flowing when the organic EL elements E_1,1to E_m,nemit light in the non-selection period is equal to the current value of the memory current. During the selection period, thedata driver5 stores electric charge, as current data, which has a magnitude corresponding to the current value of this memory current, in eachcapacitor13.

The operation principle of the pixels P_1,1to P_m,nwhen thedata driver5 supplies storage current having a predetermined current value to the current lines Y₁to Y_nwill be explained below.

FIG. 6 is a graph showing the current-voltage characteristics of thetransistor12 as an n-channel MOSFET. Referring toFIG. 6, the abscissa indicates the drain-source voltage value, and the ordinate indicates the drain-source current value. In an unsaturated region of this FET, i.e., in a region in which a source-drain voltage value V_DSis less than a drain saturated threshold voltage V_THcorresponding to a gate-source voltage value V_GS, if the gate-source voltage value V_GSis constant, a source-drain current value I_DSincreases as the source-drain voltage value V_DSincreases. In a saturated region inFIG. 6, i.e., in a region in which the source-drain voltage value V_DSis equal to or larger than the drain saturated threshold voltage V_THcorresponding to the gate-source voltage value V_GS, if the gate-source voltage value V_GSis constant, the source-drain current value I_DSis substantially constant.

In the saturated region, the gate-source current value I_DSis represented by

$\begin{array}{cc}{I}_{\mathrm{DS}}=\frac{\mu C_0\mathrm{<figure-callout\; label="Z"\; filenames="US07317429-20080108-D00001.png"\; state="\{\{state\}\}">Z</figure-callout>}}{2L}{\left(V_{\mathrm{GS}}-V_{\mathrm{TH}}\right)}^2& \left(1\right)\end{array}$
where μ is the mobility of carriers (electrons), C₀is a capacitance having an MOS structure gate insulating film as a dielectric, Z is a channel width, and L is a channel length.

Referring toFIG. 6, gate-source voltage values V_GS0to V_GSMAXhave a relationship of V_GS0=0<V_GS1<V_GS2<V_GS3<V_GS4<V_GSMAX. That is, as is evident fromFIG. 6, if the drain-source voltage value V_DSis constant, the drain-source current value I_DSincreases as the gate-source voltage value V_GSincreases in both the unsaturated and saturated regions. In addition, as the gate-source voltage value V_GSincreases, the drain saturated threshold voltage V_THincreases.

From the foregoing, in the unsaturated region, the source-drain current value I_DSchanges when the source-drain voltage value V_DSslightly changes. In the saturated region, however, the drain-source current value I_DSis unconditionally determined if the gate-source voltage value V_GSis determined. When thetransistor12 is at the gate-source voltage level V_GSMAX, the drain-source current level I_DSis set at the level of a current flowing between theanode electrode41 andcathode electrode43 of the organic EL element E_i,jwhich emits light at the maximum luminance.

The operation of the pixel driving circuit D_i,jconfigured as above, a method of driving this pixel driving circuit D_i,j, and the operation of the light emittingelement display1 will be described below with reference to a timing chart shown inFIG. 7. Referring toFIG. 7, a period of T_SEis the selection period, a period of T_NSEis a non-selection period, and a period of T_SCis one scanning period. Note that T_SC=T_SE+T_NSE.

In accordance with the control signals φs output from thecontroller6, theselection scan driver3 sequentially outputs high-level (ON-level) pulses to the selection scan lines in turn from the selection scan line X₁in the first row to the selection scan line X_min the mth row. Also, in accordance with the control signals φe output from thecontroller6, the emissionvoltage scan driver4 sequentially outputs low-level pulses to the emission voltage scan lines in turn from the emission voltage scan line Z₁in the first row to the emission voltage scan line Z_min the mth row.

As shown inFIG. 7, in each row the high-level voltage output timing of the selection scan line X_iis substantially the same as the low-level pulse output timing of the emission voltage scan line Z_i. The duration of the high-level voltage of the selection scan line X_iis substantially the same as that of the low-level voltage of the emission voltage scan line Z_i. A period during which the high-level pulse and low-level pulse are output is the selection period T_SEof that row. Also, during this selection period T_SEof each row, thedata driver5 generates memory currents (i.e., electric currents flowing toward the data driver5) in the current lines Y₁to Y_nin all columns in accordance with the control signals φd output from thecontroller6. That is, thedata driver5 supplies a memory current to the current line Y_jin each column by a current value corresponding to the image data received by thecontroller6.

The flow of an electric current and the application of a voltage to the pixel P_i,jwill be described in detail below.

At start time t₁of the selection period T_SEin the first row, theselection scan driver3 outputs an ON-level (high-level) voltage to the selection scan line X_iin the ith row. During this selection period T_SEfrom time t₁to time t₂, a scan signal voltage V_ONat a level by which thetransistors10 and11 are turned on is applied to the selection scan line X_i. Also, in this selection period T_SEof the first row, a selection voltage V_SEequal to or lower than the reference voltage V_SSis applied to the emission voltage scan line Z_i. Furthermore, in the selection period T_SEthedata driver5 supplies a memory current having a predetermined current value in accordance with the image data received by thecontroller6.

In this selection period T_SE, therefore, thetransistor10 is turned on to allow an electric current to flow from the drain to the source, and a voltage is applied to the gate of thetransistor12 and one terminal of thecapacitor13, thereby turning on thetransistor12. In addition, in the selection period T_SE, thetransistor11 is turned on, and thedata driver5 supplies memory currents corresponding to the image data to the current lines Y₁, Y₂, . . . , Y_j, Y_j+1, . . . , Y_n. To supply the memory currents to these current lines Y₁, Y₂, . . . , Y_j, Y_j+1, . . . , Y_n, thedata driver5 sets the current lines Y₁, Y₂, . . . , Y_j, Y_j+1, . . . , Y_nat a voltage equal to or lower than the selection voltage V_SEand equal to or lower than the reference voltage V_SS, thereby making the potential of thesource12S of thetransistor12 lower than that of the drain.

Furthermore, since a potential difference is produced between the gate and source of thetransistor12, memory currents I₁, I₂, . . . , I_j, I_j+1, . . . , I_nhaving current values (i.e., current values corresponding to the image data) designated by thedata driver5 flow through the current lines Y₁, Y₂, . . . , Y_j, Y_j+1, . . . , Y_nin directions indicated by arrows a. In this selection period T_SE, the selection voltage V_SEof the emission voltage scan line Z_iis equal to or lower than the reference voltage V_SS, and the anode potential of the organic EL element E_i,jbecomes lower than that of its cathode potential. So, a reverse bias voltage is applied to this organic EL element E_i,j. Consequently, no electric current from the emission voltage scan line Z_iflows through the organic EL element E_i,j.

The potential of the other terminal (connected to thesource electrode12S of the transistor12) of thecapacitor13 of each of the pixels P_i,1to P_i,ncorresponds to the current value (designated) controlled by thedata driver5, and is lower than the gate potential of thetransistor12. That is, electric charge which produces potential differences between the gates and sources of thetransistors12, by which the electric currents I₁to I_nflow through thesetransistors12 of the pixels P_i,1to P_i,n, is charged in thecapacitors13 of these pixels P_i,1to P_i,n.

The potential at a given point on, e.g., a line from thetransistor12 to the current line Y_jchanges in accordance with, e.g., those internal resistances of thetransistors11 and12, which change with time. However, an electric current which flows under the current control of thedata driver5 exhibits a predetermined current value. Hence, even when the resistances of thetransistors11 and12 rise to change the gate-source potential of thetransistor12, the predetermined current value of the electric current flowing in the arrow a direction remains unchanged.

At end time t₂of this selection period T_SE, the high-level pulse output from theselection scan driver3 to the selection scan line X_iis terminated, and the low-level pulse output from the emissionvoltage scan driver4 to the emission voltage scan line Z_iis terminated. That is, in a non-selection period T_NSEfrom this end time t₂to start time T₁of the next selection period T_SE, an OFF-level (low-potential) scan signal voltage V_OFFis applied to the gates of thetransistors10 and11 of the selection scan line X_i. In addition, a non-selection voltage V_NSEmuch higher than the reference potential V_SSis applied to the emission voltage scan line Z_i. Accordingly, as shown inFIG. 5B, in this non-selection period T_NSEthetransistor11 is turned off and no electric current flows through the current lines Y₁to Y_n. Furthermore, thetransistor10 is turned off in the non-selection period T_NSE.

The organic EL element E_i,jinevitably deteriorates with time, i.e., its resistance gradually rises for long time periods, and this gradually raises the divided voltage in this organic EL element E_i,j. When a constant voltage is applied, therefore, a voltage applied to a transistor connected in series with the organic EL element E_i,jmay lower relative to the transistor. Letting V_Edenote the maximum internal voltage of the organic EL element E_i,j, which is required to allow this organic EL element E_i,jto emit light at the maximum luminance during its emission life period. During the non-selection period T_NSEafter the selection period T_SE, as shown inFIG. 6, equation (2) below is met so that the source and drain of thetransistor12 maintain the saturated region, i.e., the source-drain current I_DSof thetransistor12 is controlled only by the gate-source voltage V_GSof thetransistor12, independently of the source-drain voltage V_DSof thetransistor12, even when the gate-source voltage V_GSof thetransistor12 is V_GSMAX
V_NSE−V_E−V_SS≧V_THMAX  (2)
where V_THMAXis a source-drain saturated threshold voltage of thetransistor12 when V_GSis V_GSMAX. This voltage V_THMAXis set at a voltage which is expected to be the highest within the range over which thetransistor12 normally operates when V_GSMAXis supplied to the gate of thistransistor12, by taking account of this displacement of the saturated threshold value when thetransistor12 deteriorates with time and of variations in the characteristics of a plurality oftransistors12 of thelight emitting panel2.

The two terminals of thecapacitor13 maintain the electric charge charged during the selection period T_SE, and thetransistor12 keeps being ON. That is, the gate-source voltage value V_GSof thetransistor12 in the non-selection period T_NSEis equal to that in the selection period T_SEbefore this non-selection period T_SE. Therefore, thetransistor12 keeps allowing the display current, which is equal to the memory current having the current value corresponding to the image data during the selection period T_SE, to flow even in the non-selection period T_NSE. However, thetransistor11 is OFF. As indicated by equation (2) above, therefore, by flowing toward the low reference potential V_SSvia the organic EL element E_i,j, a display current flows through theorganic EL layer42 between theanode41 andcathode43 of the organic EL element E_i,j, i.e., the source-drain current I_DSof thetransistor12 flows. So, the organic EL element E_i,jemits light.

As described above, in the selection period T_SE, thedata driver5 forcedly supplies the memory current between the source and drain of thetransistor12 through the current line Y_jin accordance with the image data. In the non-selection period T_NSE, thedata driver5 supplies the display current equal to the extracted memory current to the organic EL element E_i,j. Accordingly, even when the characteristics of thetransistor12 vary or the characteristics change by deterioration with time, thistransistor12 can supply a desired electric current corresponding to the image data. In addition, a desired electric current flows in the organic EL element E_i,jeven when the resistance of this organic EL element E_i,jrises with time, so stable luminance tone display can be performed. In one pixel, thetransistor12 as a current controlling transistor is the only transistor connected in series with the organic EL element E_i,j. Therefore, the voltage applied to the emission voltage scan line Z_iis divided only by the organic EL element E_i,jandtransistor12. This achieves a low voltage, and as a consequence, low consumption driving. This can also decrease the number of transistors in one pixel to increase the area occupied by an optical element.

When the selection period T_SEof the selection scan line X_iis completed, the selection period T_SEof the selection scan line X_i+1is started subsequently. Theselection scan driver3, emissionvoltage scan driver4,data driver5, andcontroller6 operate in the same manner as for the selection scan line X_i. In this way, the organic EL elements E_1,1to E_1,n, E_2,1to E_2,n, . . . , E_m,1to E_m,nare linearly selected in turn. After the selection periods of the selection scan lines X₁to X_mare sequentially completed, the selection period T_SEof the selection scan line X₁is started again. As described above, an emission time T_EMduring which each pixel emits light in one scan period T_SCis substantially equivalent to the non-selection period T_NSE. As the number of selection scan lines increases, the emission period T_EMcan be extended.

Also, the active matrix driving type light emittingelement display1 using current control can be implemented by using the threetransistors10,11, and12 for one pixel P_i,j. This improves the image characteristics of this light emittingelement display1. That is, in the active matrix driving type light emittingelement display1 in which the current values are controlled, the present invention can increase the ratio of the light emission area of the pixel P_i,jand hence can increase the other design margin. When the ratio of the light emission area increases, the apparent brightness of the display screen of the light emittingelement display1 can be increased. In addition, when an image is displayed with desired apparent brightness, the value of an electric current which flows per unit area of theorganic EL layer42 can be decreased. This can extend the light emission life of the organic EL element E_i,j.

Furthermore, a reverse bias voltage is applied to the organic EL element E_i,jin the selection period T_SE, and this extends the life of this organic EL element E_i,j. In the above embodiment, each of thetransistors10,11, and12 of each pixel driving circuit D_i,jis a single-channel type FET with only an n-channel in which a semiconductor layer is formed by amorphous silicon. Accordingly, thesetransistors10,11, and12 can be simultaneously formed on thetransparent substrate30 in the same step. This can suppress an increase in the time or cost for the fabrication of thelight emitting panel2, light emittingelement display1, and pixel driving circuit D_i,j. The same effects as described in the above embodiment can also be obtained by using p-channel FETs as thetransistors10,11, and12. In this case, the individual signals shown inFIG. 7 have opposite phases.

Second Embodiment

The second embodiment will be described next. This second embodiment is the same as the first embodiment except for the arrangement of each pixel P_i,j. That is, in this second embodiment as shown inFIGS. 8A and 8B, each pixel P_i,j(a pixel driving circuit D_i,jof each pixel P_i,j) has aswitch circuit51 instead oftransistors10 and11, and acurrent memory circuit52 instead of atransistor12 andcapacitor13. The same reference numerals as in the above first embodiment denote the same parts, so a detailed explanation thereof will be omitted.

A power supply signal Sb output to an emission voltage scan line Z_ihas a voltage value Vb during a selection period T_SEand a voltage value Vb′ during a non-selection period T_NSE. These voltage values Vb and Vb′ correspond to the non-selection voltage V_NSEand reference voltage V_SS, respectively, shown inFIG. 7.

A scan signal Sa output to a selection scan line X_ihas a voltage value Va which turns on theswitch circuit51 during the selection period T_SE, and a voltage value Va′ which turns off theswitch circuit51 during the selection period T_SE. This scan signal Sa corresponds to the scan signal (scan signal voltage) shown inFIG. 7.

As shown inFIG. 8A, during the selection period T_SE, theswitch circuit51 outputs the power supply signal Sb from the emission voltage scan line Z_ito thecurrent memory circuit52 in accordance with the scan signal Sa, and supplies an electric current Ib flowing from thecurrent memory circuit52 to a current line Y through a line Q. The current value of this electric current Ib is controlled by a current sink type data driver5 (i.e., thisdata driver5 has a current sink) connected to the current line Y_j. Also, as shown inFIG. 8B, during the non-selection period T_NSE, theswitch circuit51 stops the supply of a display current from thecurrent memory circuit52 to the current line Y_jin accordance with the scan signal Sa, and supplies this display current to an organic EL element E_i,jthrough a line R. Accordingly, this organic EL element E_i,jemits light in the non-selection period T_NSE.

As shown inFIG. 8A, thecurrent memory circuit52 includes a storage means which, during the selection period T_SE, allows the electric current Ib controlled by the currentsink data driver5 to flow from the emission voltage scan line Z_ito the line Q in accordance with the signal voltage Vb of the power supply signal Sb from theswitch circuit51, thereby storing the current value of this electric current Ib. As shown inFIG. 8B, during the non-selection period T_NSE, thiscurrent memory circuit52 allows the electric current Ib corresponding to the current value stored by the storage means to flow from the emission voltage scan line Z_ito the line R in accordance with the signal voltage Vb′ from theswitch circuit51. Accordingly, the current value of the electric current Ib during the non-selection period T_NSEis equal to or has a linear relationship with the current value of the electric current Ib during the selection period T_SE.

Third Embodiment

The third embodiment will be described below. This third embodiment is the same as the first embodiment except for the arrangement of each pixel P_i,j. That is, as shown inFIGS. 9A and 9B, each pixel P_i,jof the third embodiment has atransistor14 instead of atransistor10. The same reference numerals as in the above first embodiment denote the same parts, so a detailed explanation thereof will be omitted.

Unlike thetransistor10, a drain electrode14D and gate electrode14G of thetransistor14 are connected to a selection scan line X_i, and a source electrode14S of thistransistor14 is connected to agate electrode12S of atransistor12. Similar to atransistor11 and thetransistor12, thetransistor14 is an n-channel amorphous silicon thin film transistor.

Thistransistor14 operates by the application of a voltage such as that shown in the waveform chart shown inFIG. 7. During a selection period T_SE, thetransistor14 is turned on by an ON-level (high-level) scan signal from the selection scan line X_ito apply a voltage from this selection scan line X_ito the gate of thetransistor12. Thistransistor12 is turned on by the gate voltage applied by thetransistor14 in the selection period T_SE, and supplies an electric current I_DS(memory current), which is extracted by adata driver5 having a current sink, via thetransistor11 which is ON and a current line Y_j. In acapacitor13 connected between the gate and source of thetransistor12, electric charge corresponding to the current value of the electric current which thetransistor12 supplies to the current line Y_jis charged.

During a non-selection period T_NSE, thetransistors11 and14 are turned off by an OFF-level scan signal supplied to the selection scan line X_i. In thetransistor12, a predetermined voltage is applied between the source and drain by the voltage value corresponding to the electric charge charged in thecapacitor13. Accordingly, thistransistor12 supplies a display current corresponding to the voltage value between the source and drain (i.e., corresponding to the electric charge charged in the capacitor13) to an organic EL element E_i,j, thereby causing this organic EL element E_i,jto emit light. The electric current flowing in the organic EL element E_i,jin this case has a current value corresponding to control signals φs, φd, and φe from acontroller6, i.e., has the current value of the memory current. Therefore, the organic EL element E_i,jemits light with luminance corresponding to image data.

Fourth Embodiment

The fourth embodiment will be described below. This fourth embodiment is the same as the second embodiment except for the arrangement of each pixel P_i,j. That is, as shown inFIGS. 10A and 10B, each pixel P_i,j(a pixel driving circuit D_i,jof each pixel P_i,j) of this fourth embodiment has aswitch53 instead of aswitch circuit51. The same reference numerals as in the above second embodiment denote the same parts, so a detailed explanation thereof will be omitted.

As shown inFIG. 10A, during a selection period T_SE, theswitch53 outputs an ON-level signal (voltage value Va) to acurrent memory circuit52 in accordance with a scan signal Sa, and supplies an electric current Ib flowing from thiscurrent memory circuit52 to a current line Y_jthrough a line Q. This electric current Ib is controlled by a current sink type data driver5 (i.e., thisdata driver5 has a current sink) connected to the current line Y_j. During a non-selection period T_NSE, theswitch53 stops the supply of the electric current Ib from thecurrent memory circuit52 to the current line Y_jin accordance with an OFF-level scan signal (voltage value Va′), and supplies a display current to an organic EL element E_i,jthrough a line R. Accordingly, this organic EL element E_i,jemits light in the non-selection period T_NSE.

The present invention is not limited to the above embodiments. That is, various improvements and design changes can be made without departing from the gist of the present invention.

For example, an organic EL element is used as a light emitting element in each of the above embodiments. However, it is also possible to use a light emitting element in which no electric current flows when a reverse bias voltage is applied and an electric current flows when a positive bias voltage is applied, and which emits light with luminance corresponding to the magnitude of the flowing current. An example is an LED (Light Emitting Diode).

Also, thetransistors10,11,12, and14 in the above embodiments are thin film transistors having amorphous silicon as a semiconductor layer (i.e., a channel layer). However, a thin film transistor using a polysilicon semiconductor layer can also be used.

In each of the above embodiments, acapacitor13 formed by agate insulating film32 in which agate electrode12G andsource electrode12S are stacked is formed between the gate and source of atransistor12. However, a capacitor formed by a member not containing at least one of or any of thegate electrode12G,source electrode12S, andgate insulating film32 can also be formed between the gate and source of thetransistor12.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

Claims (34)

1. A display panel comprising:

at least one optical element which has a pair of electrodes and exhibits an optical operation corresponding to an electric current flowing between the pair of electrodes;

at least one current line;

at least one switch circuit which supplies a memory current having a predetermined current value to the current line during a selection period, and which stops supply of the current to the current line during a non-selection period; and

at least one current memory circuit which stores current data corresponding to the current value of the memory current flowing through the current line during the selection period and, in accordance with the current data stored during the selection period, supplies a display current having a current value substantially equal to the current value of the memory current to the optical element during the non-selection period;

wherein the current memory circuit comprises a current control transistor connected in series with the optical element.

2. A display panel according toclaim 1, wherein the current memory circuit comprises a capacitor, in which electric charges are written as the current data, between a gate and a source of the current control transistor.

3. A display panel according toclaim 1, wherein the switch circuit comprises a current path control transistor which has a current path having one end connected to the current line, and which supplies the memory current to the current line during the selection period and stops the supply of the memory current to the current line during the non-selection period.

4. A display panel according toclaim 1, wherein the switch circuit comprises a current data write control transistor which controls writing of the current data to the current memory circuit.

5. A display panel according toclaim 1, wherein the display panel comprises a plurality of said optical elements, a plurality of said current memory circuits, and a plurality of said switch circuits; and

wherein a plurality of pixels, each including one said optical element, one said current memory circuit, and one said switch circuit, are arrayed in a matrix.

6. A display panel according toclaim 1, further comprising a data driver which allows the memory current to flow from the current memory circuit to the current line during the selection period.

7. A display panel according toclaim 1, further comprising a display voltage scan line which is connected to the current memory circuit, and to which a voltage for supplying the display current to the optical element is output.

8. A display panel according toclaim 7, wherein a first end of a current path of the current memory circuit is connected to the optical element, and a second end of the current path is connected to the display voltage scan line.

9. A display panel according toclaim 1, further comprising a selection scan line to which a selection scan signal for selecting the switch circuit is output.

10. A display panel according toclaim 9, wherein the switch circuit comprises a current path control transistor which has a current path having a first end connected to the current line and a second end connected to the current memory circuit, and the current path control transistor of the switch circuit has a control terminal connected to the selection scan line.

11. A display panel according toclaim 9, wherein the switch circuit comprises a current data write control transistor having a control terminal connected to the selection scan line.

12. A display panel according toclaim 9, further comprising a selection scan driver which outputs the selection scan signal to the selection scan line.

13. A display panel according toclaim 1, wherein a first one of the pair of electrodes of the optical element is connected to the current memory circuit, and a second one of the pair of electrodes of the optical element is connected to a constant-voltage power supply.

14. A display panel according toclaim 1, wherein the optical element comprises a light emitting element.

15. A display panel according toclaim 14, wherein the light emitting element comprises an EL element.

16. A display panel comprising:

at least one optical element which has a pair of electrodes and exhibits an optical operation corresponding to an electric current flowing between the pair of electrodes;

at least one current line;

at least one switch circuit which supplies a memory current having a predetermined current value to the current line during a selection period, and which stops supply of the current to the current line during a non-selection period; and

at least one current memory circuit which stores current data corresponding to the current value of the memory current flowing through the current line during the selection period and, in accordance with the current data stored during the selection period, supplies a display current having a current value substantially equal to the current value of the memory current to the optical element during the non-selection period;

wherein the current memory circuit comprises a current control transistor connected in series with the optical element, and

wherein the switch circuit comprises a current path control transistor which supplies the memory current to the current line during the selection period, and a current data write control transistor which writes the current value of the memory current flowing through the current line during the selection period as the current data between the gate and source of the current control transistor.

17. A display panel comprising:

at least one optical element which has a pair of electrodes and exhibits an optical operation corresponding to an electric current flowing between the pair of electrodes;

at least one current line;

at least one switch circuit which supplies a memory current having a predetermined current value to the current line during a selection period, and which stops supply of the current to the current line during a non-selection period;

at least one current memory circuit which stores current data corresponding to the current value of the memory current flowing through the current line during the selection period and, in accordance with the current data stored during the selection period, supplies a display current having a current value substantially equal to the current value of the memory current to the optical element during the non-selection period; and

a display voltage scan line which is connected to the current memory circuit, and to which a voltage for supplying the display current to the optical element is output;

wherein a first end of a current path of the current memory circuit is connected to the optical element, and a second end of the current path is connected to the display voltage scan line; and

wherein the display panel further comprises a display voltage scan driver which applies a voltage to the current memory circuit through the display voltage scan line during the selection period so that the memory current may flow in the current memory circuit during the selection period, and which applies a voltage to the current memory circuit through the display voltage scan line during the non-selection period so that the display current in accordance with the current data may flow in the current memory circuit during the non-selection period, wherein the current value of the display current is substantially equal to the current value of the memory current flowing in the current memory circuit during the selection period.

18. A display panel according toclaim 17, wherein a first one of the pair of electrodes of the optical element is connected to the current memory circuit, and a second one of the pair of electrodes of the optical element is connected to a constant-voltage power supply; and

wherein the voltage output by the display voltage scan driver during the selection period is not more than a potential of the constant-voltage power supply, and the voltage output by the display voltage scan driver during the non-selection period is not less than the voltage output during the selection period and higher than the potential of the constant-voltage power supply.

19. A display panel comprising:

at least one optical element which has a pair of electrodes and exhibits an optical operation corresponding to an electric current flowing between the pair of electrodes;

at least one current line;

at least one switch circuit which supplies a memory current having a predetermined current value to the current line during a selection period, and which stops supply of the current to the current line during a non-selection period;

at least one current memory circuit which stores current data corresponding to the current value of the memory current flowing through the current line during the selection period and, in accordance with the current data stored during the selection period, supplies a display current having a current value substantially equal to the current value of the memory current to the optical element during the non-selection period;

a display voltage scan line to which a voltage for supplying the display current to the optical element is output; and

a selection scan line to which a selection scan signal for selecting the switch circuit is output,

wherein the current memory circuit comprises a current control transistor which has a current path having a first end connected to the optical element and a second end connected to the display voltage scan line, and

wherein the switch circuit comprises:

a current data write control transistor which has a control terminal connected to the selection scan line, and a current path having a first end connected to the control terminal of the current control transistor and a second end connected to one of the display voltage scan line and the selection scan line; and

a current path control transistor which has a control terminal connected to the selection scan line, and a current path having a first end connected to the current line and a second end connected to the first end of the current control transistor.

20. A display panel according toclaim 19, further comprising:

a selection scan driver which outputs the selection scan signal to the selection scan line;

a data driver which supplies the memory current to the current line and the current memory circuit during the selection period; and

a display voltage scan driver which applies a voltage to the current memory circuit through the display voltage scan line during the selection period so that the memory current may flow in the current memory circuit during the selection period, and applies the voltage to the current memory circuit through the display voltage scan line during the non-selection period so that the display current in accordance with the current data may flow in the current memory circuit during the non-selection period, wherein the current value of the display current is substantially equal to the current value of the memory current flowing in the current memory circuit during the selection period.

21. A display panel according to theclaim 19, wherein the display voltage scan driver outputs a saturated current path voltage to the display voltage scan line so that a voltage between the first end and the second end of the current path of the current control transistor may be saturated and the display current in accordance with a voltage between the control terminal and the first end of the current path of the current control transistor may flow through the current path of the current control transistor during the non-selection period.

22. A display panel according toclaim 19, wherein the current control transistor, the current data write control transistor, and the current path control transistor are single-channel transistors having the same channel.

23. A display panel driving method for driving a display panel, comprising:

supplying a memory current having a predetermined current value to a current memory circuit of the display panel and storing current data corresponding to the current value to the current memory circuit during a selection period; and

supplying, to an optical element of the display panel during a non-selection period, a display current having a current value substantially equal to the current value of the memory current in accordance with the current data stored in the current memory circuit;

wherein the memory current supplied to the current memory circuit is not supplied not through the optical element.

24. A display panel driving method according toclaim 23, wherein the memory current is supplied to the current memory circuit through a current line, and the display current supplied to the optical element is not supplied through the current line.

25. A display panel driving method for driving a display panel, comprising:

supplying a memory current having a predetermined current value to a current memory circuit of the display panel and storing current data corresponding to the current value to the current memory circuit during a selection period; and

supplying, to an optical element of the display panel during a non-selection period, a display current having a current value substantially equal to the current value of the memory current in accordance with the current data stored in the current memory circuit;

wherein the current memory circuit comprises: (i) a current control transistor which has a current path having a first end connected to a first end of the optical element and a second end connected to a display voltage scan line, and (ii) a capacitor which is connected between a gate and a source of the current control transistor and which stores the current data.

26. A display panel driving method according toclaim 25, wherein a voltage for supplying the memory current is output to the display voltage scan line during the selection period, and a voltage for supplying the display current is output to the display voltage scan line during the non-selection period.

27. A display panel driving method according toclaim 25, wherein electric charge corresponding to the memory current flowing through the current path of the current control transistor during the selection period is written as the current data in the capacitor under the control of a current data write control transistor in accordance with a selection scan signal from a selection scan line.

28. A display panel driving method according toclaim 27, wherein the electric charge written in the capacitor during the selection period is held under the control of the current data write control transistor during the non-selection period.

29. A display panel driving method according toclaim 25, wherein the memory current flowing through the current path of the current control transistor during the selection period flows through a current line under the control of a current path control transistor driven in accordance with a selection scan signal from a selection scan line.

30. A display panel driving method according toclaim 25, wherein the display current flowing through the current path of the current control transistor during the non-selection period flows through the optical element under the control of a current path control transistor driven in accordance with a selection scan signal from a selection scan line.

31. A display panel driving method according toclaim 25, wherein the display panel further comprises:

a selection scan line to which a selection scan signal is output;

a current line through which the memory current flows;

a current data write control transistor which has a control terminal connected to the selection scan line, and a current path having a first end connected to a gate of the current control transistor and a second end connected to one of the display voltage scan line and the selection scan line, and which controls writing of the current data of the memory current in accordance with the selection scan signal; and

a current path control transistor which has a control terminal connected to the selection scan line, and a current path having a first end connected to the current line and a second end connected to the first end of the current path of the current control transistor, and which supplies the memory current to the current line via the current control transistor in accordance with the selection scan signal.

32. A display panel driving method according toclaim 31, wherein the supplying of the memory current and storing the current data corresponding to the current value of the memory current comprises, during the selection period, supplying the memory current to the current path of the current control transistor by selecting the current data write control transistor and the current path control transistor in accordance with the selection scan signal from the selection scan line, and storing electric charge as the current data corresponding to the current value of the memory current in the capacitor, and

wherein the supplying of the display current to the optical element comprises, during the non-selection period, causing the current data write control transistor to hold the current data and causing the current path control transistor to stop supply of an electric current to the current line in accordance with the selection scan signal from the selection scan line, and applying a voltage different from a potential at a second end of the optical element to the display voltage scan line, whereby the display current corresponding to the current data flows through the path of the current control transistor and the optical element.

33. A display panel driving method according toclaim 31, wherein the display panel further comprises:

a selection scan driver which outputs the selection scan signal to the selection scan line;

a data driver which draws the memory current from current control transistor to the current line during the selection period; and

a display voltage scan driver which applies a voltage to the current memory circuit through the display voltage scan line during the selection period so that the memory current may flow in the current control transistor during the selection period, and which applies the voltage to the current control transistor through the display voltage scan line during the non-selection period so that the display current in accordance with the current data may flow in the optical element during the non-selection period.

34. A display panel driving method according to theclaim 33, wherein the display voltage scan driver outputs a saturated current path voltage to the display voltage scan line so that a voltage between the first end and the second end of the current path of the current control transistor may be saturated and the display current in accordance with a voltage between the gate and the first end of the current path of the current control transistor may flow through the current path of the current control transistor during the non-selection period.

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