US7209397B2 - Memory device with clock multiplier circuit - Google Patents

Abstract

A memory device having a clock multiplier circuit. The memory device includes a clock generating circuit to receive a first clock signal having a first frequency and to generate a second clock signal having a second frequency that is a multiple of the first frequency. The memory device includes a data receive circuit to receive data at the frequency of the second clock signal and may also include a data transmit circuit to transmit data at the frequency of the second clock signal. Further, the clock generating circuit may additionally generate a third clock signal having a third frequency that is also a multiple of the first frequency, the third clock signal being supplied to a control circuit of the memory device to time the reception of control and/or address signals therein. In a particular embodiment the second frequency is a four-times or eight-times multiple of the first frequency, and the third frequency is a two-times multiple of the first frequency.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent application is a continuation of U.S. patent application Ser. No. 10/732,533, filed Dec. 11, 2003, which is a continuation of U.S. patent application Ser. No. 09/841,911, filed Apr. 24, 2001 now U.S. Pat. No 6,675,272, each of which is hereby incorporated by reference herein in its entirety.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to information storage and retrieval and, more specifically, to coordinating memory components.

BACKGROUND OF THE DISCLOSURE

As computers and data processing equipment have grown in capability, users have developed applications that place increasing demands on the equipment. Thus, there is a continually increasing need to process more information in a given amount of time. One way to process more information in a given amount of time is to process each element of information in a shorter amount of time. As that amount of time is shortened, it approaches the physical speed limits that govern the communication of electronic signals. While it would be ideal to be able to move electronic representations of information with no delay, such delay is unavoidable. In fact, not only is the delay unavoidable, but, since the amount of delay is a function of distance, the delay varies according to the relative locations of the devices in communication.

Since there are limits to the capabilities of a single electronic device, it is often desirable to combine many devices, such as memory components, to function together to increase the overall capacity of a system. However, since the devices cannot all exist at the same point in space simultaneously, consideration must be given to operation of the system with the devices located diversely over some area.

Traditionally, the timing of the devices' operation was not accelerated to the point where the variation of the location of the devices was problematic to their operation. However, as performance demands have increased, traditional timing paradigms have imposed barriers to progress.

One example of an existing memory system uses DDR (double data rate) memory components. The memory system includes a memory controller and a memory module. A propagation delay occurs along an address bus between the memory controller and the memory module. Another propagation delay occurs along the data bus between the memory controller and the memory module.

The distribution of the control signals and a control clock signal in the memory module is subject to strict constraints. Typically, the control wires are routed so there is an equal length to each memory component. A “star” or “binary tree” topology is typically used, where each spoke of the star or each branch of the binary tree is of equal length. The intent is to eliminate any variation of the timing of the control signals and the control clock signal between different memory components of a memory module, but the balancing of the length of the wires to each memory component compromises system performance (some paths are longer than they need to be). Moreover, the need to route wires to provide equal lengths limits the number of memory components and complicates their connections.

In such DDR systems, a data strobe signal is used to control timing of both data read and data write operations. The data strobe signal is not a periodic timing signal, but is instead only asserted when data is being transferred. The timing signal for the control signals is a periodic clock. The data strobe signal for the write data is aligned to the clock for the control signals. The strobe for the read data is delayed by delay relative to the control clock equal to the propagation delay along the address bus plus the propagation delay along the data bus. A pause in signaling must be provided when a read transfer is followed by a write transfer to prevent interference along various signal lines used. Such a pause reduces system performance.

Such a system is constrained in several ways. First, because the control wires have a star topology or a binary tree routing, reflections occur at the stubs (at the ends of the spokes or branches). The reflections increase the settling time of the signals and limit the transfer bandwidth of the control wires. Consequently, the time interval during which a piece of information is driven on a control wire will be longer than the time it takes a signal wavefront to propagate from one end of the control wire to the other. Additionally, as more modules are added to the system, more wire stubs are added to each conductor of the data bus, thereby adding reflections from the stubs. This increases the settling time of the signals and further limits the transfer bandwidth of the data bus.

Also, because there is a constraint on the relationship between the propagation delays along the address bus and the data bus in this system, it is hard to increase the operating frequency without violating a timing parameter of the memory component. If a clock signal is independent of another clock signal, those clock signals and components to which they relate are considered to be in different clock domains. Within a memory component, the write data receiver is operating in a different clock domain from the rest of the logic of the memory component, and the domain crossing circuitry will only accommodate a limited amount of skew between these two domains. Increasing the signaling rate of data will reduce this skew parameter (when measured in time units) and increase the chance that a routing mismatch between data and control wires on the board will create a timing violation.

Also, most DDR systems have strict limits on how large the address bus and data bus propagation delays may be (in time units). These are limits imposed by the memory controller and the logic that is typically included for crossing from the controller's read data receiver clock domain into the clock domain used by the rest of the controller. There is also usually a limit (expressed in clock cycles) on how large the sum of these propagation delays can be. If the motherboard layout makes this sum too large (when measured in time units), the signal rate of the system may have to be lowered, thereby decreasing performance.

In another example of an existing memory system, the control wires and data bus are connected to a memory controller and are routed together past memory components on each memory module. One clock is used to control the timing of write data and control signals, while another clock is used to control the timing of read data. The two clocks are aligned at the memory controller. Unlike the previous prior art example, these two timing signals are carried on separate wires.

In such an alternate system, several sets of control wires and a data bus may be used to intercouple the memory controller to one or more of the memory components. The need for separate sets of control wires introduces additional cost and complexity, which is undesireable. Also, if a large capacity memory system is needed, the number of memory components on each data bus will be relatively large. This will tend to limit the maximum signal rate on the data bus, thereby limiting performance.

Thus, a technique is needed to coordinate memory operations among diversely-located memory components.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a memory system having a single rank of memory components with which an embodiment of the present disclosure may be implemented.

FIG. 2 is a block diagram illustrating clocking details for one slice of a rank of memory components of a memory system such as that illustrated inFIG. 1 in accordance with an embodiment of the present disclosure.

FIG. 3 is a timing diagram illustrating address and control timing notations used in timing diagrams of other Figures.

FIG. 4 is a timing diagram illustrating data timing notations used in timing diagrams of other Figures.

FIG. 5 is a timing diagram illustrating timing of signals communicated over the address and control bus (Addr/Ctrl or AC_S,M) in accordance with an embodiment of the present disclosure.

FIG. 6 is a timing diagram illustrating timing of signals communicated over the data bus (DQ_S,M) in accordance with an embodiment of the present disclosure.

FIG. 7 is a timing diagram illustrating system timing at a memory controller component in accordance with an embodiment of the present disclosure.

FIG. 8 is a timing diagram illustrating alignment of clocks AClk_S1,M1, WClk_S1,M1, and RClk_S1,M1at the memory component inslice1 ofrank1 in accordance with an embodiment of the present disclosure.

FIG. 9 is a timing diagram illustrating alignment of clocks AClk_SNs,M1, WClk_SNs,M1, and RClk_SNs,M1at the memory component in slice N_Sofrank1 in accordance with an embodiment of the present disclosure.

FIG. 10 is a block diagram illustrating further details for one slice of a rank of memory components of a memory system such as that illustrated inFIG. 1 in accordance with an embodiment of the present disclosure.

FIG. 11 is a block diagram illustrating the clocking elements of one slice of a rank of the memory components of a memory system such as that illustrated inFIG. 1 in accordance with an embodiment of the present disclosure.

FIG. 12 is a block diagram illustrating details for the memory controller component of a memory system such as that illustrated inFIG. 1 in accordance with an embodiment of the present disclosure.

FIG. 13 is a block diagram illustrating the clocking elements of a memory controller component of a memory system such as that illustrated inFIG. 1 in accordance with an embodiment of the present disclosure.

FIG. 14 is a logic diagram illustrating details of the ClkC8 block of the memory controller component such as that illustrated inFIG. 12 in accordance with an embodiment of the present disclosure.

FIG. 15 is a block diagram illustrating how the ClkC8[N:1] signals are used in the transmit and receive blocks of the memory controller component such as that illustrated inFIG. 12 in accordance with an embodiment of the present disclosure.

FIG. 16 is a block diagram illustrating a circuit for producing a ClkC8B clock and a ClkC1B clock based on the ClkC8A clock in accordance with an embodiment of the present disclosure.

FIG. 17 is a block diagram illustrating details of the PhShC block in accordance with an embodiment of the present disclosure.

FIG. 18 is a block diagram illustrating the logic details of the skip logic in a controller slice of the receive block of a memory controller component in accordance with an embodiment of the present disclosure.

FIG. 19 is a timing diagram illustrating the timing details of the skip logic in a controller slice of the receive block of a memory controller component in accordance with an embodiment of the present disclosure.

FIG. 20 is a block diagram illustrating the logic details of the skip logic in a controller slice of the transmit block of a memory controller component in accordance with an embodiment of the present disclosure.

FIG. 21 is a timing diagram illustrating the timing details of the skip logic in a controller slice of the transmit block of a memory controller component in accordance with an embodiment of the present disclosure.

FIG. 22 is a timing diagram illustrating an example of a data clocking arrangement in accordance with an embodiment of the present disclosure.

FIG. 23 is a timing diagram illustrating an example of a data clocking arrangement in accordance with an embodiment of the present disclosure.

FIG. 24 is a timing diagram illustrating timing at the memory controller component for the example of the data clocking arrangement illustrated inFIG. 23 in accordance with an embodiment of the present disclosure.

FIG. 25 is a timing diagram illustrating timing at a first slice of a rank of memory components for the example of the data clocking arrangement illustrated inFIG. 23 in accordance with an embodiment of the present disclosure.

FIG. 26 is a timing diagram illustrating timing a last slice of a rank of memory components for the example of the data clocking arrangement illustrated inFIG. 23 in accordance with an embodiment of the present disclosure.

FIG. 27 is a block diagram illustrating a memory system that may comprise multiple ranks of memory components and multiple memory modules in accordance with an embodiment of the present disclosure.

FIG. 28 is a block diagram illustrating a memory system that may comprise multiple ranks of memory components and multiple memory modules in accordance with an embodiment of the present disclosure.

FIG. 29 is a block diagram illustrating a memory system that comprises multiple ranks of memory components and multiple memory modules in accordance with an embodiment of the present disclosure.

FIG. 30 is a block diagram illustrating a memory system that comprises multiple ranks of memory components and multiple memory modules with a dedicated control/address bus per memory module in accordance with an embodiment of the present disclosure.

FIG. 31 is a block diagram illustrating a memory system that comprises multiple ranks of memory components and multiple memory modules with a single control/address bus that is shared among the memory modules in accordance with an embodiment of the present disclosure.

FIG. 32 is a block diagram illustrating a memory system that comprises multiple ranks of memory components and multiple memory modules with a single control/address bus that is shared by all the memory modules in accordance with an embodiment of the present disclosure.

FIG. 33 is a block diagram illustrating a memory system that comprises multiple ranks of memory components and multiple memory modules with a dedicated, sliced control/address bus per memory module in accordance with an embodiment of the present disclosure.

FIG. 34 is a block diagram illustrating a memory system that comprises multiple ranks of memory components and multiple memory modules with a single control/address bus that is shared by all the memory modules in accordance with an embodiment of the present disclosure.

FIG. 35 is a block diagram illustrating a memory system that comprises multiple ranks of memory components and multiple memory modules with a single control/address bus that is shared by all the memory modules in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the present disclosure, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations. The address bus propagation delay, or common address bus propagation delay, refers to the delay for a signal to travel along an address bus between the memory controller component and a memory component. The data bus propagation delay refers to the delay for a signal to travel along a data bus between the memory controller component and a memory component.

According to one embodiment of the present disclosure, a memory system includes multiple memory modules providing multiple ranks and multiple slices of memory components. Such a system can be understood with reference toFIG. 27. The memory system ofFIG. 27 includesmemory module2703 andmemory module2730.Memory module2703 includes a rank that includesmemory components2716–2618 and another rank that includesmemory components2744–2746.

The memory system is organized into slices across the memory controller component and the memory modules. The memory system ofFIG. 27 includes aslice2713 that includes a portion ofmemory controller2702, a portion ofmemory module2703 includingmemory components2716 and2744, and a portion ofmemory module2730 includingmemory components2731 and2734. The memory system ofFIG. 27 includes anotherslice2714 that includes another portion ofmemory controller2702, another portion ofmemory module2703 includingmemory components2717 and2745, and another portion ofmemory module2730 includingmemory components2732 and2735. The memory system ofFIG. 27 further includes yet anotherslice2715 that includes yet another portion ofmemory controller2702, yet another portion ofmemory module2703 includingmemory components2718 and2746, and yet another portion ofmemory module2730 includingmemory components2733 and2736.

The use of multiple slices and ranks, which may be implemented using multiple modules, allows efficient interconnection of a memory controller and several memory components while avoiding degradation of performance that can occur when a data bus or address bus has a large number of connections to it. With a separate data bus provided for each slice, the number of connections to each data bus can be kept to a reasonable number. The separate data buses can carry different signals independently of each other. A slice can include one or more memory components per module. For example, a slice can include one memory component of each rank. Note that the term slice may be used to refer to the portion of a slice excluding the memory controller. In this manner, the memory controller can be viewed as being coupled to the slices. The use of multiple modules allows memory components to be organized according to their path lengths to a memory controller. Even slight differences in such path lengths can be managed according to the organization of the memory components into ranks. The organization of memory components according to ranks and modules allows address and control signals to be distributed efficiently, for example through the sharing of an address bus within a rank or module.

In one embodiment, a slice can be understood to include several elements coupled to a data bus. As one example, these elements can include a portion of a memory controller component, one or more memory components on one module, and, optionally, one or more memory components on another module. In one embodiment, a rank can be understood to include several memory components coupled by a common address bus. The common address bus may optionally be coupled to multiple ranks on the module or to multiple modules. The common address bus can connect a memory controller component to each of the slices of a rank in succession, thereby allowing the common address bus to be routed from a first slice of the rank to a second slice of the rank and from the second slice of the rank to a third slice of the rank. Such a configuration can simplify the routing of the common address bus.

For discussion purposes, a simplified form of a memory system is first discussed in order to illustrate certain concepts, whereas a more complex memory system that includes a plurality of modules and ranks is discussed later in the specification.

FIG. 1 is a block diagram illustrating a memory system having a single rank of memory components with which an embodiment of the present disclosure may be implemented.Memory system101 comprisesmemory controller component102 andmemory module103.Address clock104 provides an address clock signal that serves as a timing signal associated with the address and control signals that propagate alongaddress bus107.Address clock104 provides its address clock signal alongaddress clock conductor109, which is coupled tomemory controller component102 and tomemory module103. The address and control signals are sometimes referred to as simply the address signals or the address bus. However, since control signals may routed according to a topology common to address signals, these terms, when used, should be understood to include address signals and/or control signals.

Writeclock105 provides a write clock signal that serves as a timing signal associated with the data signals that propagate alongdata bus108 during write operations. Writeclock105 provides its write clock signal alongwrite clock conductor110, which is coupled tomemory controller component102 andmemory module103. Readclock106 provides a read clock signal that serves as a timing signal associated with the data signals that propagate alongdata bus108 during read operations. Readclock106 provides its read clock signal along readclock conductor111, which is coupled tomemory controller component102 andmemory module103.

Termination component120 is coupled todata bus108 nearmemory controller component102. As one example,termination component120 may be incorporated intomemory controller component102.Termination component121 is coupled todata bus108 nearmemory module103.Termination component121 is preferably incorporated intomemory module103.Termination component123 is coupled to writeclock conductor110 nearmemory component116 ofmemory module103.Termination component123 is preferably incorporated intomemory module103.Termination component124 is coupled to readclock conductor111 nearmemory controller component102. As an example,termination component124 may be incorporated intomemory controller component102.Termination component125 is coupled to readclock conductor111 nearmemory component116 ofmemory module103.Termination component125 is preferably incorporated intomemory module103. The termination components may utilize active devices (e.g., transistors or other semiconductor devices) or passive devices (e.g. resistors, capacitors, or inductors). The termination components may utilize an open connection. The termination components may be incorporated in one or more memory controller components or in one or more memory components, or they may be separate components on a module or on a main circuit board.

Memory module103 includes arank112 ofmemory components116,117, and118. Thememory module103 is organized so that each memory component corresponds to one slice.Memory component116 corresponds to slice113,memory component117 corresponds to slice114, andmemory component118 corresponds to slice115. Although not shown inFIG. 1, the specific circuitry associated with the data bus, write clock and associated conductors, and read clock and associated conductors that are illustrated forslice113 is replicated for each of theother slices114 and115. Thus, although such circuitry has not been illustrated inFIG. 1 for simplicity, it is understood that such dedicated circuitry on a slice-by-slice basis is preferably included in the memory system shown.

Withinmemory module103,address bus107 is coupled to each ofmemory components116,117, and118.Address clock conductor109 is coupled to each ofmemory components116,117, and118. At the terminus ofaddress bus107 withinmemory module103,termination component119 is coupled to addressbus107. At the terminus ofaddress clock conductor109,termination component122 is coupled to addressclock conductor109.

In the memory system ofFIG. 1, each data signal conductor connects one controller data bus node to one memory device data bus node. However, it is possible for each control and address signal conductor to connect one controller address/control bus node to an address/control bus node on each memory component of the memory rank. This is possible for several reasons. First, the control and address signal conductors pass unidirectional signals (the signal wavefront propagates from the controller to the memory devices). It is easier to maintain good signal integrity on a unidirectional signal conductor than on a bidirectional signal conductor (like a data signal conductor). Second, the address and control signals contain the same information for all memory devices. The data signals will be different for all memory devices. Note that there might be some control signals (such as write enable signals) which are different for each memory device—these are treated as unidirectional data signals, and are considered to be part of the data bus for the purposes of this distinction. For example, in some instances, the data bus may include data lines corresponding to a large number of bits, whereas in some applications only a portion of the bits carried by the data bus may be written into the memory for a particular memory operation. For example, a 16-bit data bus may include two bytes of data where during a particular memory operation only one of the two bytes is to be written to a particular memory device. In such an example, additional control signals may be provided along a similar path as that taken by the data signals such that these control signals, which control whether or not the data on the data bit lines is written, traverse the system along a path with a delay generally matched to that of the data such that the control signals use in controlling the writing of the data is aptly timed. Third, routing the address and control signals to all the memory devices saves pins on the controller and memory module interface.

As a result, the control and address signals will be propagated on wires that will be longer than the wires used to propagate the data signals. This enables the data signals to use a higher signaling rate than the control and address signals in some cases.

To avoid impairment of the performance of the memory system, the address and control signals may be wave-pipelined in accordance with an embodiment of the present disclosure. The memory system is configured to meet several conditions conducive to wave-pipelining. First, two or more memory components are organized as a rank. Second, some or all address and control signals are common to all memory components of the rank. Third, the common address and control signals propagate with low distortion (e.g. controlled impedance). Fourth, the common address and control signals propagate with low intersymbol-interference (e.g. single or double termination).

Wave-pipelining occurs when Tbit<Twire, where the timing parameter Twire is defined to be the time delay for a wavefront produced at the controller to propagate to the termination component at the end of the wire carrying the signal, and the timing parameter Tbit is defined to be the time interval between successive pieces (bits) of information on the wire. Such pieces of information may represent individual bits or multiple bits encoded for simultaneous transmission. Wave-pipelined signals on wires are incident-wave sampled by receivers attached to the wire. This means that sampling will generally take place before the wavefront has reflected from the end of the transmission line (e.g., the wire).

It is possible to extend the applicability of the present disclosure from a single rank to multiple ranks of memory components in several ways. First, multiple ranks of memory components may be implemented on a memory module. Second, multiple memory modules may be implemented in a memory system. Third, data signal conductors may be dedicated, shared, or “chained” to each module. Chaining involves allowing a bus to pass through one module, connecting with the appropriate circuits on that module, whereas when it exits that particular module it may then enter another module or reach termination. Examples of such chaining of conductors are provided and described in additional detail inFIGS. 29,32, and35 below. Fourth, common control and address signal conductors may be dedicated, shared, or chained to each module. Fifth, data signal conductors may be terminated transmission lines or terminated stubs on each module. For this discussion, transmission lines are understood to represent signal lines that have sufficient lengths such that reflections and other transmission line characteristics must be considered and accounted for in order to assure proper signal transmission over the transmission lines. In contrast, terminated stubs are understood to be of such limited length that the parasitic reflections and other transmission line characteristics associated with such stubs can generally be ignored. Sixth, common control and address signal conductors may be terminated transmission lines or terminated stubs on each module. Permitting the shared address and control signals to be wave-pipelined allows their signaling rate to be increased, thereby increasing the performance of the memory system.

FIG. 2 is a block diagram illustrating clocking details for one slice of a rank of memory components of a memory system such as that illustrated inFIG. 1 in accordance with an embodiment of the present disclosure. Thememory controller component102 includes address transmitblock201, which is coupled to addressbus107 andaddress clock conductor109. Thememory controller component102 also includes, on a per-slice basis, data transmitblock202 and data receiveblock203, which are coupled todata bus108. Data transmitblock202 is coupled to writeclock conductor110, and data receiveblock203 is coupled to readclock conductor111.

Within each memory component, such asmemory component116, an address receiveblock204, a data receiveblock205, and a data transmitblock206 are provided. The address receiveblock204 is coupled to addressbus107 andaddress clock conductor109. The data receiveblock205 is coupled todata bus108 and writeclock conductor110. The data transmitblock206 is coupled todata bus108 and readclock conductor111.

Apropagation delay207, denoted t_PD0, exists alongaddress bus107 betweenmemory controller component102 andmemory module103. Apropagation delay208, denoted t_PD1, exists alongaddress bus107 withinmemory module103.

The basic topology represented inFIG. 2 has several attributes. It includes a memory controller. It includes a single memory module. It includes a single rank of memory components. It includes a sliced data bus (DQ), with each slice of wires connecting the controller to a memory component. It includes a common address and control bus (Addr/Ctrl or AC) connecting the controller to all the memory components. Source synchronous clock signals flow with data, control, and address signals. Control and address signals are unidirectional and flow from controller to memory components. Data signals are bi-directional and may flow from controller to memory components (write operation) or may flow from memory components to controller (read operation). There may be some control signals with the same topology as data signals, but which flow only from controller to memory components. Such signals may be used for masking write data in write operations, for example. These may be treated as unidirectional data signals for the purpose of this discussion. The data, address, control, and clock wires propagate with low distortion (e.g., along controlled impedance conductors). The data, address, control, and clock wires propagate with low inter-symbol interference (e.g., there is a single termination on unidirectional signals and double termination on bi-directional signals). These attributes are listed to maintain clarity. It should be understood that the present disclosure is not constrained to be practiced with these attributes and may be practiced so as to include other system topologies.

InFIG. 2, there is a two dimensional coordinate system based on the slice number of the data buses and the memory components (S={0,1, . . . N_S}) and the module number (M={0,1}). Here a slice number of “0” and a module number of ‘0’ refer to the controller. This coordinate system allows signals to be named at different positions on a wire. This coordinate system will also allow expansion to topologies with more than one memory rank or memory module.

FIG. 2 also shows the three clock sources (address clock104, which generates the AClk signal, writeclock105, which generates the WClk signal, and readclock106, which generates the RClk signal) which generate the clocking reference signals for the three types of information transfer. These clock sources each drive a clock wire that is parallel to the signal bus with which it is associated. Preferably, the positioning of the clock sources within the system is such that the physical position on the clock line at which the clock source drives the corresponding clock signal is proximal to the related driving point for the bus line such that the propagation of the clock for a particular bus generally tracks the propagation of the related information on the associated bus. For example, the positioning of the address clock (AClk clock104) is preferably close to the physical position where the address signals are driven onto theaddress bus107. In such a configuration, the address clock will experience similar delays as it propagates throughout the circuit as those delays experienced by the address signals propagating along a bus that follows generally the same route as the address clock signal line.

The clock signal for each bus is related to the maximum bit rate on the signals of the associated bus. This relationship is typically an integer or integer ratio. For example, the maximum data rate may be twice the frequency of the data clock signals. It is also possible that one or two of the clock sources may be “virtual” clock sources; the three clock sources will be in an integral-fraction-ratio (N/M) relationship with respect to one another, and any of them may be synthesized from either of the other two using phase-locked-loop (PLL) techniques to set the frequency and phase. Virtual clock sources represent a means by which the number of actual clock sources within the circuit can be minimized. For example, a WClk clock might be derived from an address clock (AClk) that is received by a memory device such that the memory device is not required to actually receive a WClk clock from an external source. Thus, although the memory device does not actually receive a unique, individually-generated WClk clock, the WClk clock generated from the AClk clock is functionally equivalent. The phase of a synthesized clock signal will be adjusted so it is the same as if it were generated by a clock source in the positions shown.

Any of the clock signals shown may alternatively be a non-periodic signal (a strobe control signal, for example) which is asserted only when information is present on the associated bus. As was described above with respect to clock sources, the non-periodic signal sources are preferably positioned, in a physical sense, proximal to the appropriate buses to which they correspond such that propagation delays associated with the non-periodic signals generally match those propagation delays of the signals on the buses to which they correspond.

FIG. 3 is a timing diagram illustrating address and control timing notations used in timing diagrams of other Figures. InFIG. 3, a risingedge302 of theAClk signal301 occurs at atime307 during transmission ofaddress information ACa305. A risingedge303 of the AClk signal occurs at atime308 during transmission ofaddress information ACb306.Time308 occurs at a time t_CCbefore thetime309 of the next risingedge304 ofAClk signal301. The time tCC represents a cycle time of a clock circuit of a memory controller component. Dashed lines in the timing diagrams are used to depict temporal portions of a signal coincident with address information or datum information. For example, theAClk signal301 includes a temporal portion corresponding to the presence ofaddress information ACa305 and another temporal portion corresponding to the presence ofaddress information ACb306. Address information can be transmitted over an address bus as an address signal.

If one bit per wire occurs per t_CC,address bit311 is transmitted duringcycle310. If two bits per wire occur per t_CC, addressbits313 and314 are transmitted duringcycle312. If four bits per wire occur per t_CC, addressbits316,317,318, and319 are transmitted duringcycle315. If eight bits per wire occur per t_CC, addressbits321,322,323,324,325,326,327, and328 are transmitted duringcycle320. Note that the drive and sample points for each bit window may be delayed or advanced by an offset (up to one bit time, which is t_CC/N_AC), depending upon the driver and sampler circuit techniques used. The parameters N_ACand N_DQrepresent the number of bits per t_CCfor the address/control and data wires, respectively. In one embodiment, a fixed offset is used. An offset between the drive/sample points and the bit windows should be consistent between the driving component and the sampling component. It is preferable that in a particular system, any offset associated with the drive point for a bus is consistent throughout the entire system. Similarly, any understood sampling offset with respect to the bus should also be consistent. For example, if data is expected to be driven at a point generally corresponding to a rising edge of a related clock signal for one data bus line, that understood offset (or lack thereof) is preferably consistently used for all data lines. Note that the offset associated with driving data onto the bus may be completely different than that associated with sampling data carried by the bus. Thus, continuing with the example above, the sample point for data driven generally coincident with a rising edge may be 180 degrees out of phase with respect to the rising edge such that the valid window of the data is better targeted by the sample point.

FIG. 4 is a timing diagram illustrating data timing notations used in timing diagrams of other Figures. InFIG. 4, a risingedge402 of theWClk signal401 occurs at atime407 during transmission of writedatum information Da405. A risingedge403 of theWClk signal401 occurs at atime408. A risingedge404 of theWClk signal401 occurs at atime409 during transmission of readdatum information Qb406.Time407 is separated fromtime408 by a time t_CC, andtime408 is separated fromtime409 by a time t_CC. The time t_CCrepresents the duration of a clock cycle.RClk signal410 includes risingedge411 and risingedge412. These rising edges may be used as references to clock cycles ofRClk signal410. For example, transmission of writedatum information Da405 occurs during a clock cycle ofRClk signal410 that includes risingedge411, and transmission of readdatum information Qb406 occurs during a clock cycle ofRClk signal410 that includes risingedge412. As is apparent to one of ordinary skill in the art, the clock cycle time associated with the address clock may differ from the clock cycle time associated with the read and/or write clocks.

Write datum information is an element of information being written and can be transmitted over a data bus as a write data signal. Read datum information is an element of information being read and can be transmitted over a data bus as a read data signal. As can be seen, the notation Dx is used to represent write datum information x, while the notation Qy is used to represent read datum information y. Signals, whether address signals, write data signals, read data signals, or other signals can be applied to conductor or bus for a period of time referred to as an element time interval. Such an element time interval can be associated with an event occurring on a conductor or bus that carries a timing signal, where such an event may be referred to as a timing signal event. Examples of such a timing signal include a clock signal, a timing signal derived from another signal or element of information, and any other signal from which timing may be derived. In a memory access operation, the time from-when an address signal begins to be applied to an address bus to when a data signal corresponding to that address signal begins to be applied to a data bus can be referred to as an access time interval.

If one bit per wire occurs per t_CC,datum bit415 is transmitted duringcycle414. If two bits per wire occur per t_CC,data bits417 and418 are transmitted duringcycle416. If four bits per wire occur per t_CC,data bits420,421,422, and423 are transmitted duringcycle419. If eight bits per wire occur per t_CC,data bits425,426,427,428,429,430,431, and432 are transmitted duringcycle424. Note that the drive and sample points for each bit window may be delayed or advanced by an offset (up to one bit time, which is t_CC/N_DQ), depending upon the driver and sampler circuit techniques used. In one embodiment, a fixed offset is used. An offset between the drive/sample points and the bit windows should be consistent between the driving component and the sampling component. For example, if the data window is assumed to be positioned such that data will be sampled on the rising edge of the appropriate clock signal at the controller, a similar convention should be used at the memory device such that valid data is assumed to be present at the rising edge of the corresponding clock at that position within the circuit as well.

If one bit per wire occurs per t_CC,datum bit434 is transmitted duringcycle433. If two bits per wire occur per t_CC,data bits436 and437 are transmitted during cycle435. If four bits per wire occur per t_CC,data bits439,440,441, and442 are transmitted duringcycle438. If eight bits per wire occur per t_CC,data bits444,445,446,447,448,449,450, and451 are transmitted duringcycle443. Note that the drive and sample points for each bit window may be delayed or advanced by an offset (up to one bit time, which is t_CC/N_DQ), depending upon the driver and sampler circuit techniques used. In one embodiment, a fixed offset is used. An offset between the drive/sample points and the bit windows should be consistent between the driving component and the sampling component. As stated above, it is preferable that in a particular system, any offset associated with the drive point or sampling point for a bus is consistent throughout the entire system.

The column cycle time of the memory component represents the time interval required to perform successive column access operations (reads or writes). In the example shown, the AClk, RClk, and WClk clock signals are shown with a cycle time equal to the column cycle time. As is apparent to one of ordinary skill in the art, the cycle time of the clock signals used in the system may be different from the column cycle time in other embodiments.

Alternatively, any of the clocks could have a cycle time that is different than the column cycle time. The appropriate-speed clock for transmitting or receiving signals on a bus can always be synthesized from the clock that is distributed with the bus as long as there is an integer or integral-fraction-ratio between the distributed clock and the synthesized clock. As mentioned earlier, any of the required clocks can be synthesized from any of the distributed clocks from the other buses.

This discussion will assume a single bit is sampled or driven on each wire during each t_CCinterval in order to keep the timing diagrams as simple as possible. However, the number of bits that are transmitted on each signal wire during each t_CCinterval can be varied. The parameters N_ACand N_DQrepresent the number of bits per t_CCfor the address/control and data wires, respectively. The distributed or synthesized clock is multiplied up to create the appropriate clock edges for driving and sampling the multiple bits per t_CC. Note that the drive and sample points for each bit window may be delayed or advanced by an offset (up to one bit time, which is t_CC/N_ACor t_CC/N_DQ), depending upon the driver and sampler circuit techniques used. In one embodiment, a fixed offset is used. An offset between the drive/sample points and the bit windows should be consistent between the driving component and the sampling component. Once again, as stated above, it is preferable that in a particular system, any offset associated with the drive point or sampling point for a bus is consistent throughout the entire system.

FIG. 5 is a timing diagram illustrating timing of signals communicated over the address and control bus (Addr/Ctrl or AC_S,M) in accordance with an embodiment of the present disclosure. This bus is accompanied by a clock signal AClk_S,Mwhich sees essentially the same wire path as the bus. The subscripts (S,M) indicate the bus or clock signal at a particular module M or a particular slice S. The controller is defined to be slice zero.

The waveform for AClk clock signal501 depicts the timing of the AClk clock signal at the memory controller component. A risingedge502 of AClk clock signal501 occurs attime510 and is associated with the transmission ofaddress information ACa518. A risingedge503 of AClk clock signal501 occurs attime511 and is associated with the transmission ofaddress information ACb519.

The waveform forAClk clock signal520 depicts the timing of the AClk clock signal at a memory component located at slice one. TheAClk signal520 is delayed a delay of by t_PD0from signal501. For example, the risingedge523 ofsignal520 is delayed by a delay of t_PD0fromedge502 of signal501. Theaddress information ACa537 is associated with the risingedge523 ofsignal520. Theaddress information ACb538 is associated with the risingedge525 ofsignal520.

The waveform forAClk clock signal539 depicts the timing of the AClk clock signal at the memory component located at slice N_S.The AClk signal539 is delayed by a delay of t_PD1fromsignal520. For example, the risingedge541 ofsignal539 is delayed by a delay of t_PD1fromedge523 ofsignal520. Theaddress information ACa548 is associated with the risingedge541 ofsignal539. Theaddress information ACb549 is associated with the risingedge542 ofsignal539.

The clock signal AClk is shown with a cycle time that corresponds to the column cycle time. As previously mentioned, it could also have a shorter cycle time as long as the frequency and phase are constrained to allow the controller and memory components to generate the necessary timing points for sampling and driving the information on the bus. Likewise, the bus is shown with a single bit per wire transmitted per t_CCinterval. As previously mentioned, more than one bit could be transferred in each t_CCinterval since the controller and memory components are able to generate the necessary timing points for sampling and driving the information on the bus. Note that the actual drive point for the bus (the point at which data signals, address signals, and/or control signals are applied to the bus) may have an offset from what is shown (relative to the rising and falling edges of the clock)—this will depend upon the design of the transmit and receive circuits in the controller and memory components. In one embodiment, a fixed offset is used. An offset between the drive/sample points and the bit windows should be consistent between the driving component and-the sampling component. As reiterated above, it is preferable that in a particular system, any offset associated with the drive point or sampling point for a bus is consistent throughout the entire system.

It should be noted inFIG. 5 is that there is a delay t_PD0in the clock AClk_S,Mand bus AC_S,Mas they propagate from the controller to the first slice. As indicated,AClk signal520 is shifted in time and space from AClk signal501. Also note that there is a second delay t_PD1in the clock AClk_S,Mand bus AC_S,Mas they propagate from the first slice to the last slice N_S. There will be a delay of t_PD1/(N_S−1) as the clock and bus travel between each slice. Note that this calculation assumes generally equal spacing between the slices, and, if such physical characteristics are not present in the system, the delay will not conform to this formula. Thus, as indicated,AClk signal539 is shifted in time and space fromAClk signal520. As a result, the N_Smemory components will each be sampling the address and control bus at slightly different points in time.

FIG. 6 is a timing diagram illustrating timing of signals communicated over the data bus (DQ_S,M) in accordance with an embodiment of the present disclosure. This bus is accompanied by two clock signals RClk_S,Mand WClk_S,Mwhich see essentially the same wire path as the bus. The subscripts (S,M) indicate the bus or clock signal at a particular module M and a particular slice S. The controller is defined to be module zero. The two clocks travel in opposite directions. WClk_S,Maccompanies the write data which is transmitted by the controller and received by the memory components. RClk_S,Maccompanies the read data which is transmitted by the memory components and received by the controller. In the example described, read data (denoted by “Q”) and write data (denoted by “D”) do not simultaneously occupy the data bus. Note that in other embodiments, this may not be the case where additional circuitry is provided to allow for additive signaling such that multiple waveforms carried over the same conductor can be distinguished and resolved.

The waveform ofWClk clock signal601 depicts the timing of the WClk clock signal at the memory controller component. Risingedge602 occurs attime610 and is associated with writedatum information Da618, which is present at slice one of module zero. Risingedge607 occurs attime615, and is associated with writedatum information Dd621, which is present at slice one of module zero. Risingedge608 occurs attime616, and is associated withwrite datum De622, which is present at slice one of module zero.

The waveform ofRClk clock signal623 depicts the timing of the RClk clock signal at the memory controller component (at module zero). Risingedge626 is associated with readdatum information Qb619, which is present at the memory controller component (at slice one of module zero). Rising edge is associated with readdatum information Qc620, which is present at the memory controller component (at slice one of module zero).

The waveform ofWClk clock signal632 depicts the timing of the WClk clock signal at the memory component at slice one of module one. Risingedge635 is associated with writedatum information Da649, which is present at slice one of module one. Risingedge645 is associated with writedatum information Dd652, which is present at slice one of module one. Risingedge647 is associated with writedatum information De653, which is present at slice one of module one.

The waveform ofRClk clock signal654 depicts the timing of the RClk clock signal at the memory component of slice one of module one. Risingedge658 is associated with readdatum information Qb650, which is present at slice one of module one. Risingedge660 is associated with readdatum information Qd651, which is present at slice one of module one.

The clock signals are shown with a cycle time that corresponds to t_CC. As previously mentioned, they could also have a shorter cycle time as long as the frequency and phase are constrained to allow the controller and memory components to generate the necessary timing points for sampling and driving the information on the bus. Likewise, the bus is shown with a single bit per wire. As previously mentioned, more than one bit could be transferred in each t_CCinterval since the controller and memory components are able to generate the necessary timing points for sampling and driving the information on the bus. Note that the actual drive point for the bus may have an offset from what is shown (relative to the rising and falling edges of the clock)—this will depend upon the design of the transmit and receive circuits in the controller and memory components. In one embodiment, a fixed offset is used. An offset between the drive/sample points and the bit windows should be consistent between the driving component and the sampling component.

It should be noted inFIG. 6 is that there is a delay t_PD2in the clock WClk_S,Mand bus DQ_S,M(with the write data) as they propagate from the controller to the slices of the first module. Thus,WClk clock signal632 is shifted in time and space fromWClk clock signal601. Also note that there is an approximately equal delay t_PD2in the clock RClk_S,Mand bus DQ_S,M(with the read data) as they propagate from the slices of the first module to the controller. Thus,RClk clock signal623 is shifted in time and space fromRClk clock signal654.

As a result, the controller and the memory components must have their transmit logic coordinated so that they do not attempt to drive write data and read data at the same time. The example inFIG. 6 shows a sequence in which there are write-read-read-write-write transfers. It can be seen that read-read and write-write transfers may be made in successive t_CCintervals, since the data in both intervals is traveling in the same direction. However, gaps (bubbles) are inserted at the write-read and read-write transitions so that a driver only turns on when the data driven in the previous interval is no longer on the bus (it has been absorbed by the termination components at either end of the bus wires).

InFIG. 6, the read clock RClk_S,Mand the write clock WClk_S,Mare in phase at each memory component (however the relative phase of these clocks at each memory component will be different from the other memory components—this will be shown later when the overall system timing is discussed). Note that this choice of phase matching is one of several possible alternatives that could have been used. Some of the other alternatives will be described later.

As a result of matching the read and write clocks at each memory component (slice), the t_CCintervals withread data Qb650 will appear to immediately follow the t_CCintervals withwrite data Da649 at the memory components (bottom ofFIG. 6), but there will be a gap of 2*t_PD2between the readdata interval Qb619 and writedata interval Da618 at the controller (top ofFIG. 6). There will be a second gap of (2*t_CC−2*t_PD2) between the readdata Qc620 and thewrite data Dd621 at the controller. There will be a gap of (2*t_CC) between the readdata Qc651 and thewrite data Dd621. Note that the sum of the gaps at the memory components and the controller will be 2*t_CC.

The overall system timing will be described next. The example system phase aligns the AClk_S,M, RClk_S,M, and WClk_S,Mclocks at each memory component (the slice number varies from one through N_S, and the module number is fixed at one). This has the benefit of allowing each memory component to operate in a single clock domain, avoiding any domain crossing issues. Because the address and control clock AClk_S,Mflows past each memory component, the clock domain of each memory slice will be offset slightly from the adjacent slices. The cost of this phasing decision is that the controller must adjust the read and write clocks for each slice to different phase values—this means there will be 1+(2*N_S) clock domains in the controller, and crossing between these domains efficiently becomes very important. Other phase constraints are possible and will be discussed later.

FIG. 7 is a timing diagram illustrating system timing at a memory controller component in accordance with an embodiment of the present disclosure. As before, the controller sends a write-read-read-write sequence of operations on the control and address bus AClk_S0,M1. The Da write datum information is sent on the WClk_S1,M0and WClk_SNs,M0buses so that it will preferably arrive at the memory component of each slice one cycle after the address and control information ACa. This is done by making the phase of the WClk_S1,M0clock generally equivalent to (t_PD0−t_PD2) relative to the phase of the AClk_S0,M1clock (positive means later, negative means earlier). This will cause them to be in phase at the memory component of the first slice of the first module. Likewise, the phase of the WClk_SNs,M0clock is adjusted to be generally equivalent to (t_PD0+t_PD1−t_PD2) relative to the phase of the AClk_S0,M1clock. Note that some tolerance is preferably built into the system such that the phase adjustment of the clock to approximate the propagation delays can vary slightly from the desired adjustment while still allowing for successful system operation.

In a similar fashion, the phase of the RClk_S1,M0clock is adjusted to be generally equivalent to (t_PD0+t_PD2) relative to the phase of the AClk_S0,M1clock. This will cause them to be in phase at the memory component of the last slice of the first module. Likewise, the phase of the RClk_SNs,M0clock is adjusted according to the expression (t_PD0+t_PD1+t_PD2) relative to the phase of the AClk_S0,M1clock to cause the RClk_SNs,M0clock and the AClk_S0,M1clock to be in phase at the memory component of the last slice of the first module.

The waveform ofAClk clock signal701 depicts the AClk clock signal at the memory controller component, which is denoted as being at slice zero. Risingedge702 occurs attime710 and is associated withaddress information ACa718, which is present at slice zero. Risingedge703 occurs attime711 and is associated withaddress information ACb719, which is present at slice zero. Rising edge704 occurs attime712 and is associated withaddress information ACc720, which is present at slice zero. Risingedge707 occurs attime715 and is associated withaddress information ACd721, which is present at slice zero.

The waveform ofWClk clock signal722 depicts the WClk clock signal for the memory component at slice one when that WClk clock signal is present at the memory controller component at module zero. Risingedge724 occurs attime711 and is associated with writedatum information Da730, which is present. Risingedge729 occurs attime716 and is associated with writedatum information Dd733, which is present.

The waveform ofRClk clock signal734 depicts the RClk clock signal for the memory component of slice one when that RClk clock signal is present at the memory controller component at module zero. Risingedge737 is associated with readdatum information Qb731, which is present. Risingedge738 is associated with readdatum information Qc732, which is present.

The waveform ofWClk clock signal741 depicts the WClk clock signal for the memory component at slice N_Swhen that WClk clock signal is present at the memory controller component at module zero. Writedatum information Da756 is associated withedge744 ofsignal741. Writedatum information Dd759 is associated withedge754 ofsignal741.

The waveform ofRClk clock signal760 depicts the RClk clock signal for the memory component at slice N_Swhen that RClk clock signal is present at the memory controller component at module zero. Readdatum information Qb757 is associated withedge764 ofsignal760. Readdatum information Qc758 is associated withedge766 ofsignal760.

FIG. 8 is a timing diagram illustrating alignment of clocks AClk_S1,M1, WClk_S1,M1, and RClk_S1,M1at the memory component inslice1 ofrank1 in accordance with an embodiment of the present disclosure. All three clocks are delayed by t_PD0relative to the AClk_S0,M1clock produced at the controller.

The waveform of AClk clock signal801 depicts the AClk clock signal for the memory component at slice one of module one.Address information ACa822 is associated withedge802 of signal801.Address information ACb823 is associated withedge804 of signal801.Address information ACc824 is associated withedge806 of signal801.Address information ACd825 associated withedge812 of signal801.

The waveform ofWClk clock signal826 depicts the WClk clock signal for the memory component at slice one of module one. Writedatum information Da841 is associated withedge829 ofsignal826. Writedatum information Dd844 is associated withedge839 ofsignal826.

The waveform ofRClk clock signal845 depicts the RClk clock signal for the memory component at slice one of module one. Readdatum information Qb842 is associated withedge850 ofsignal845. Readdatum information Qc843 is associated withedge852 ofsignal845.

FIG. 9 is a timing diagram illustrating alignment of clocks AClk_SNs,M1, WClk_SNs,M1, and RClk_SNs,M1at the memory component in slice N_Sof rank one of module one in accordance with an embodiment of the present disclosure. All three clocks are delayed by (t_PD0+t_PD1) relative to the AClk_S0,M1clock produced at the controller.

The waveform ofAClk clock signal901 depicts the AClk clock signal for the memory component at slice N_Sat module one. Risingedge902 ofsignal901 is associated withaddress information ACa917. Risingedge903 ofsignal901 is associated with address information ACb. Risingedge904 ofsignal901 is associated withaddress information ACc919. Risingedge907 ofsignal901 is associated withaddress information ACd920.

The waveform ofWClk clock signal921 depicts the WClk clock signal for the memory component at slice N_Sat module one. Risingedge923 ofsignal921 is associated with writedatum information Da937. Risingedge928 ofsignal921 is associated with writedatum information Dd940.

The waveformRClk clock signal929 depicts the RClk clock signal for the memory component at slice N_Sat module one. Risingedge932 ofsignal929 is associated with readdatum information Qb938. Risingedge933 ofsignal929 is associated with readdatum information Qc939.

Note that in bothFIGS. 8 and 9 there is a one t_CCcycle delay between the address/control information (ACa917 ofFIG. 9, for example) and the read or write information that accompanies it (Da937 ofFIG. 9 in this example) when viewed at each memory component. This may be different for other technologies; i.e. there may be a longer access delay. In general, the access delay for the write operation at the memory component should be equal or approximately equal to the access delay for the read operation in order to maximize the utilization of the data bus.

FIGS. 10 through 18 illustrate the details of an exemplary system which uses address and data timing relationships which are nearly identical to what has been described inFIGS. 5 through 9. In particular, all three clocks are in-phase on each memory component. This example system has several differences relative to this earlier description, however. First, two bits per wire are applied per t_CCinterval on the AC bus (address/control bus, or simply address bus). Second, eight bits per wire are applied per t_CCinterval on the DQ bus. Third, a clock signal accompanies the AC bus, but the read and write clocks for the DQ bus are synthesized from the clock for the AC bus.

FIG. 10 is a block diagram illustrating further details for one memory rank (one or more slices of memory components) of a memory system such as that illustrated inFIG. 1 in accordance with an embodiment of the present disclosure. The internal blocks of the memory components making up this rank are connected to the external AC or DQ buses. The serialized data on these external buses is converted to or from parallel form on internal buses which connect to the memory core (the arrays of storage cells used to hold information for the system). Note thatFIG. 10 shows all 32 bits of the DQ bus connecting to the memory rank—these 32 bits are divided up into multiple, equal-sized slices and each slice of the bus is routed to one memory component. Thus, slices are defined based on portions of the DQ bus routed to separate memory components. The example shown inFIG. 10 illustrates a memory component, or device, that supports the entire set of 32 data bits for a particular example system. In other embodiments, such a system may include two memory devices, where each memory device supports half of the 32 data bits. Thus, each of these memory devices would include the appropriate data transmit blocks, data receive blocks, and apportionment of memory core such that they can individually support the portion of the overall data bus for which they are responsible. Note that the number of data bits need not be 32, but may be varied.

The AClk signal is the clock which accompanies the AC bus. It is received and is used as a frequency and phase reference for all the clock signals generated by the memory component. The other clocks are ClkM2, ClkM8, and ClkM. These are, respectively, 2×, 8×, and 1× the frequency of AClk. The rising edges of all clocks are aligned (no phase offset). The frequency and phase adjustment is typically done with some type of phase-locked-loop (PLL) circuit, although other techniques are also possible. A variety of different suitable PLL circuits are well known in the art. The feedback loop includes the skew of the clock drivers needed to distribute the various clocks to the receive and transmit blocks as well as the memory core. The memory core is assumed to operate in the ClkM domain.

Memory component116 comprisesmemory core1001,PLL1002,PLL1003, andPLL1004.AClk clock signal109 is received bybuffer1015, which providesclock signal1019 toPLLs1002,1003, and1004. Various PLL designs are well known in the art, however some PLLs implemented in the example embodiments described herein require minor customization to allow for the specific functionality desired. Therefore, in some embodiments described herein, the particular operation of the various blocks within the PLL are described in additional detail. Thus, although some of the PLL constructs included in the example embodiments described herein are not described in extreme detail, it is apparent to one of ordinary skill in the art that the general objectives to be achieved by such PLLs are readily recognizable through a variety of circuits well known to those skilled in the art.PLL1002 includes phase comparator and voltage controlled oscillator (VCO)1005.PLL1002 providesclock signal ClkM1024 tomemory core1001, address/control receiveblock204, data receiveblock205, and data transmitblock206.

PLL1003 comprisesprescaler1009, phase comparator andVCO1010, anddivider1011.Prescaler1009 may be implemented as a frequency divider (such as that used to implement divider1011) and provides a compensating delay with no frequency division necessary.Prescaler1009 provides asignal1021 to phase comparator andVCO1010. The phase comparator inVCO1010 is represented as a triangle having two inputs and an output. The functionality of thephase comparator1010 is preferably configured such that it produces an output signal that ensures that the phase of thefeedback signal1023, which is one of its inputs, is generally phase aligned with areference signal1021. This convention is preferably applicable to similar structures included in other PLLs described herein.Divider1011 provides afeedback signal1023 to phase comparator andVCO1010.PLL1003 providesclock signal ClkM21025 to address/control receiveblock204.

PLL1004 comprisesprescaler1006, phase comparator andVCO1007, anddivider1008.Prescaler1006 may be implemented as a frequency divider (such as that used to implement divider1011) and provides a compensating delay with no frequency division necessary.Prescaler1006 provides asignal1020 to phase comparator andVCO1007.Divider1008 provides afeedback signal1022 to phase comparator andVCO1007.PLL1004 providesclock signal ClkM81026 to data receiveblock205 and data transmitblock206.

Theaddress bus107 is coupled viabuffers1012 to address/control receiveblock204 viacoupling1016. The data outputs1018 of data transmitblock206 are coupled todata bus108 viabuffers1014. Thedata bus108 is coupled todata inputs1017 of data receiveblock205 viabuffers1013.

Address/control receiveblock204 provides address information to thememory core1001 viainternal address bus1027. Data receiveblocks205 provides write data tomemory core1001 via internalwrite data bus1028.Memory core1001 provides read data to data transmitblocks206 via internalread data bus1029.

FIG. 11 is a block diagram illustrating logic used in the receive and transmit blocks ofFIG. 10 in accordance with an embodiment of the present disclosure. In this Figure, for clarity, the elements for only one bit of each bus are illustrated. It is understood that such elements may be replicated for each bit of the bus.

Address/control receiveblock204 comprisesregisters1101,1102, and1103.Address bus conductor1016 is coupled toregisters1101 and1102, which together form a shift register, and which are clocked byClkM2 clock signal1025 and coupled to register1103 viacouplings1104 and1105, respectively.Register1103 is clocked byClkM clock signal1024 and provides address/control information tointernal address bus1027. The representation ofregisters1101 and1102 inFIG. 11 is preferably understood to imply that they form a shift register such thatdata entering register1101 during one cycle is transferred intoregister1102 during the subsequent cycle as new data entersregister1101. In the particular embodiment shown inFIG. 11, the movement of data is controlled by theclock signal ClkM21025. Thus, ifclock ClkM21025 operates at twice the frequency ofclock ClkM1024, the receiveblock204 generally operates as a serial-to-parallel shift register, where two consecutive serial bits are grouped together in a two-bit parallel format before being output ontosignal lines RAC1027. Thus, other similar representations in the figures where a number of registers are grouped together in a similar configuration preferably are understood to include the interconnections required to allow data to be serially shifted along the path formed by the registers. Examples include theregisters1123–1130 included in transmitblock206 and theregisters1106–1113 included in receiveblock205. As a result, the serial information on theinput1016 is converted to parallel form on theoutput1027.

Data receiveblock205 comprisesregisters1106,1107,1108,1109,1110,1111,1112,1113, and1114.Data input1017 is coupled toregisters1106,1107,1108,1109,1110,1111,1112, and1113, which are clocked byClkM8 clock signal1026 and coupled to register1114 viacouplings1115,1116,1117,1118,1119,1120,1121, and1122, respectively.Register1114 is clocked byClkM clock signal1024 and provides write data to internalwrite data bus1028. As a result, the serial information on theinput1017 is converted to parallel form on theoutput1028.

Data transmitblock206 comprisesregisters1123,1124,1125,1126,1127,1128,1129,1130, and1131. Read data from internalread data bus1029 is provided to register1131, which is clocked byClkM clock1024 and coupled toregisters1123,1124,1125,1126,1127,1128,1129, and1130 viacouplings1132,1133,1134,1135,1136,1137,1138, and1139.Registers1123,1124,1125,1126,1127,1128,1129, and1130 are clocked byClkM8 clock1026 and providedata output1018. As a result, the parallel information on theinput1029 is converted to serial form on theoutput1018.

Shown are the register elements needed to sample the address/control and write data, and to drive the read data. It is assumed in this example that two bits are transferred per address/control (AC[i]) wire in each t_CCinterval, and that eight bits are transferred per read data (Q[i]) wire or write data (D[i]) wire in each t_CCinterval. In addition to the primary clock ClkM (with a cycle time of t_CC), there are two other aligned clocks that are generated. There is ClkM2 (with a cycle time of t_CC/2) and ClkM8 (with a cycle time of t_CC/8). These higher frequency clocks shift information in to or out from the memory component. Once in each t_CCinterval the serial data is transferred to or from a parallel register clocked by ClkM.

Note that ClkM2 and ClkM8 clocks are frequency locked and phase locked to the ClkM clock. The exact phase alignment of the two higher frequency clocks will depend upon the circuit implementation of the driver and sampler logic. There may be small offsets to account for driver or sampler delay. There may also be small offsets to account for the exact position of the bit valid windows on the AC and DQ buses relative to the ClkM clock.

Note also that in the memory component, the ClkM2 or ClkM8 clocks could be replaced by two or eight clocks each with a cycle time of t_CC, but offset in phase in equal increments across the entire t_CCinterval. The serial register, which in transmitblock204 includesregisters1101–1102, in transmitblock206 includes-registers1123–1130, and in data receiveblock205 includesregisters1106–1113, would be replaced by a block of two or eight registers, each register loaded with a different clock signal so that the bit windows on the AC and DQ buses are properly sampled or driven. For example, in the transmitblock204, two individual registers would be included, where one register is clocked by a first clock signal having a particular phase and the second register is clocked by a different clock signal having a different phase, where the phase relationship between these two clock signals is understood such that the equivalent serial-to-parallel conversion can be achieved as that described in detail above. Another possibility is to use level-sensitive storage elements (latches) instead of edge sensitive storage elements (registers) so that the rising and falling edges of a clock signal cause different storage elements to be loaded.

Regardless of how the serialization is implemented, there are multiple bit windows per t_CCinterval on each wire, and multiple clock edges per t_CCinterval are created in the memory component in order to properly drive and sample these bit windows.

FIG. 12 is a block diagram illustrating details for the memory controller component of a memory system such as that illustrated inFIG. 1 in accordance with an embodiment of the present disclosure. Thememory controller component102 comprisesPLLs1202,1203,1204, and1205, address/control transmitblocks201, data transmitblocks202, data receiveblocks203, andcontroller logic core1234.PLL1202 comprises phase comparator andVCO1206.PLL1202 receivesClkIn clock signal1201 and providesClkC clock signal1215 tocontroller logic core1234 and to buffer1224, which outputsAClk clock signal109.

PLL1203 comprisesprescaler1207, phase comparator andVCO1208, anddivider1209.Prescaler1207 may be implemented as a frequency divider and provides a compensating delay with no frequency division necessary.Prescaler1207 receivesClkIn clock signal1201 and providessignal1216 to phase comparator andVCO1208.Divider1209 providesfeedback signal1218 to phase comparator andVCO1208, which providesClkC2 clock output1217 to address/control transmitblocks201.

PLL1204 comprises phase comparator andVCO1210, dummy phase offsetselector1212, anddivider1211. Dummy phase offsetselector1212 inserts an amount of delay to mimic the delay inherent in a phase offset selector and providessignal1220 todivider1211, which providesfeedback signal1221 to phase comparator andVCO1210. Phase comparator andVCO1210 receivesClkIn clock input1201 and providesClkC8 clock output1219 to data transmitblocks202 and data receive blocks203.

PLL1205 comprisesphase shifting circuit1214 and phase comparator andVCO1213.Phase shifting circuit1214 providesfeedback signal1223 to phase comparator andVCO1213. Phase comparator andVCO1213 receivesClkIn clock signal1201 and providesClkCD clock signal1222 to data transmitblocks202 and data receive blocks203.

Controller logic core1234 provides TPhShB signals1235 andTPhShA signals1236 to data transmit blocks202.Controller logic core1234 provides RPhShB signals1237 andRPhShA signals1238 to data receive blocks203.Controller logic core1234 providesLoadSkip signal1239 to data transmitblocks202 and data receive blocks203.Controller logic core1234 comprisesPhShC block1240. Functionality of thecontroller logic1234 is discussed in additional detail with respect toFIG. 17 below.

Controller logic core1234 provides address/control information to address/control transmitblocks201 viainternal address bus1231.Controller logic core1234 provides write data to data transmitblocks1232 via internalwrite data bus1232.Controller logic core1234 receives read data from data receiveblocks203 via internalread data bus1233.

Address/control transmitblocks201 are coupled viaoutput1228 tobuffers1225, which driveAC bus107. Data transmitblocks202 provideoutputs1229 tobuffers1226, which driveDQ bus108.Buffers1227couple DQ bus108 toinputs1230 of data receive blocks203.

Each of address/control transmitblocks201 is connected to the AC bus, and each ofblocks202 and203 is connected to the DQ bus. The serialized data on these external buses is converted to or from parallel from internal buses which connect to the rest of the controller logic. The rest of the controller is assumed to operate in the ClkC clock domain.

In the embodiment shown, the ClkIn signal is the master clock for the whole memory subsystem. It is received and used as a frequency and phase reference for all the clock signals used by the controller. The other clocks are ClkC2, ClkC8, ClkC, and ClkCD. These are, respectively, 2×, 8×, 1×, and 1× the frequency of ClkIn. ClkC will have no phase offset relative to ClkIn, and ClkCD will be delayed by 90 degrees. ClkC2 has every other rising edge aligned with a rising edge of ClkIn.

Every eighth ClkC8 rising edge is aligned with a rising edge of ClkIn except for25 an offset which compensates for the delay of a frequency divider and phase offset selector in the transmit and receive blocks. There are “N” additional ClkC8 signals (ClkC8[N:1]) which are phase-shifted relative to the ClkC8 signal. These other ClkC8 phases are used to synthesize the transmit and receive clock domains needed to communicate with the memory components.

The frequency and phase adjustment is typically done with some type of phase-locked-loop (PLL) circuit, although other techniques are also possible. The feedback loop of the PLL circuit includes the skew of the clock drivers needed to distribute the various clocks to the receive and transmit blocks as well as the rest of the controller logic.

FIG. 13 is a block diagram illustrating the logic used in the receive and transmit blocks ofFIG. 12 in accordance with an embodiment of the present disclosure.Memory controller component102 comprises address/control transmitblocks201, data transmitblocks202, and data receive blocks203. For clarity, the elements for only one bit are illustrated. It is understood that such elements may be replicated for each bit of the buses.

Address/control transmitblocks201comprise register1301 andregisters1302 and1303.Internal address bus1231 is coupled to register1301, which is clocked byClkC clock1215 and provides outputs toregisters1302 and1303 viacouplings1304 and1305, respectively.Registers1302 and1303 are clocked byClkC2 clock1217 and provideoutput1328 to the AC bus. As a result, the parallel information on theinternal address bus1231 is converted to serial form on theoutput1228. Additional functional description of the address/control transmitblocks201 is provided with respect toFIG. 13 below.

Generally, the data transmitblocks202 and data receiveblocks203 shown inFIG. 13 serve the function of performing serial-to-parallel or parallel-to-serial conversion of data (the type of conversion depending upon the direction of the data flow). Such blocks are similar to those present within the memory devices, however in the case of the transmit and receive blocks included in the controller in this particular system, additional circuitry is required in order to obtain the appropriate clocking signals required to perform these serial-to-parallel and parallel-to-serial conversions. In the memory devices of this example, such clock adjustment circuitry is not required, as the clocks are understood to be phase aligned within the memory devices. However, within the controller such phase alignment cannot be guaranteed due to the assumption within the system that phase alignment within the memory devices will possibly cause phase mismatching in other portions of the system due to the physical positioning of the memory devices with respect to the controller. Thus, a memory device positioned a first distance from the controller will have a different set of characteristic delays with respect to signals communicated with the controller than a second memory device positioned at a second position. As such, individual clock adjustment circuitry would be required for such memory devices within the controller such that the controller is assured of properly capturing read data provided by each of the memory devices and to allow for the controller to properly drive write data intended to be received by each of the memory devices.

Within the transmitblock202, data for transmission is received over theTD bus1232 in parallel format. This data is loaded into theregister1310 based on theclock ClkC signal1215. Once loaded in theregister1310, the data is either directly passed through themultiplexer1312 to theregister1313 or caused to be delayed by a half clock cycle by traversing the path through themultiplexer1312 that includes theregister1311 which is clocked by the falling edge of the ClkC signal. Such circuitry enables the data on the TD bus, which is in the ClkC clock domain, to be successfully transferred into the clock domain needed for its transmission. This clock domain is the TClkC1B clock domain, which has the same frequency as the ClkC clock, but is not necessarily phase aligned to the ClkC clock signal. Similar circuitry is included within the receiveblock203 such that data received in the RClkC1B clock domain can be successfully transferred onto the RQ bus that operates in the ClkC clock domain.

Data transmitblocks202 comprisePhShA block1306,clock divider circuit1307, registers1308,1309,1310,1311, and1313,multiplexer1312, andshift register1314. TPhShA signals1236 and ClkC8 clock signals1219 are provided toPhShA block1306. Additional detail regarding thePhShA block1306 are provided with respect toFIG. 15 below.Clock divider circuit1307 comprises 1/1divider circuit1324 and 1/8divider circuit1325. TPhShB signals1235 are provided to 1/8divider circuit1325. An output ofPhShA block1306 is provided to inputs of 1/1divider circuit1324 and 1/8divider circuit1325. An output of 1/1divider circuit1324 is provided toclock shift register1314. An output of 1/8divider circuit1325 is provided toclock register1313 and as an input to register1308.

Register1308 is clocked byClkCD clock signal1222 and provides an output to register1309.Register1309 is clocked byClkC clock signal1215 and receivesLoadSkip signal1238 to provide an output tomultiplexer1312 and an output toclock registers1310 and1311.Register1310 receives write data fromwrite data bus1232 and provides an output to register1311 andmultiplexer1312.Register1311 provides an output tomultiplexer1312. Multiplexer1312 provides an output to register1313.Register1313 provides parallel outputs to shiftregister1314.Shift register1314 providesoutput1229. As a result, the parallel information on theinput1232 is converted to serial form on theoutput1229.

Data receiveblocks203 comprisePhShA block1315,clock dividing circuit1316, registers1317,1318,1320,1321, and1323,shift register1319, andmultiplexer1322.Clock dividing circuit1316 comprises 1/1divider circuit1326 and 1/8divider circuit1327. RPhShA signals1238 andClkC8 clock signal1219 are provided toPhShA block1315, which provides an output to 1/1divider circuit1326 and 1/8divider circuit1327.RPhShB signal1237 is provided to an input of 1/8divider circuit1327. The 1/1divider circuit1326 provides an output used toclock shift register1319. The 1/8divider circuit1327 provides an output used toclock register1320 and used as an input to register1317.Register1317 is clocked byClkCD clock signal1222 and provides an output to register1318.Register1318 receivesLoadSkip signal1238 and is clocked byClkC clock signal1215, providing an output tomultiplexer1322 and an output used toclock registers1321 and1323.

Shift register1319 receivesinput1230 and provides parallel outputs to register1320.Register1320 provides an output to register1321 and tomultiplexer1322.Register1321 provides an output tomultiplexer1322. Multiplexer1322 provides an output to register1323.Register1323 provides an output to internalread data bus1233. As a result, the serial information on theinput1230 is converted to parallel form on theoutput1233.

Shown are the register and gating elements needed to drive address/control and write data, and to sample the read data. It is assumed in this example that two bits are transferred per address/control (AC[i]) wire in each t_CCinterval, and that eight bits are transferred per read data (Q[i]) wire or write data (D[i]) wire in each t_CCinterval. In addition to the primary clock ClkC (with a cycle time of t_CC), there are two other aligned clocks that are generated. There is ClkC2 (with a cycle time of t_CC/2) and ClkC8 (with a cycle time of t_CC/8). These higher frequency clocks shift information in to or out from the controller. Once in every t_CCinterval the serial data is transferred to or from a parallel register clocked by ClkC.

Note that in the controller, the ClkC2 or ClkC8 clocks can be replaced by two or eight clocks each with a cycle time of t_CC, but offset in phase in equal increments across the entire t_CCinterval. In such embodiments, the serial register is replaced by blocks of two or eight registers, where each register is loaded with a different clock signal so that the bit windows on the AC and DQ buses are properly sampled or driven. Another possibility is to use level-sensitive storage elements (latches) instead of edge sensitive storage elements (registers) so that the rising and falling edges of a clock signal cause different storage elements to be loaded.

Regardless of how the serialization is implemented, there will be multiple bit windows per t_CCinterval on each wire, and many embodiments utilize multiple clock edges per t_CCinterval in the controller in order to properly drive and sample these bit windows.

FIG. 13 also shows how the controller deals with the fact that the read and write data that is received and transmitted for each slice is in a different clock domain. Since a slice may be as narrow as a single bit, there can be 32 read clock domains and 32 write clock domains simultaneously present in the controller (this example assumes a DQ bus width of 32 bits). Remember that in this example no clocks are transferred with the read and write data, and such clocks are preferably synthesized from a frequency source. The problem of multiple clock domains would still be present even if a clock was transferred with the read and write data. This is because the memory component is the point in the system where all local clocks are preferably in-phase. Other system clocking topologies are described later in this description.

The transmit block for address/control bus (AC) inFIG. 13 uses the ClkC2 and ClkC clocks to perform two-to-one serialization. The ClkC2 clock shifts theserial register1302,1304 onto theAC wires1328. Note the exact phase alignment of the ClkC2 clock depends upon the circuit implementation of the driver logic; there may be a small offset to account for driver delay. There may also be small offsets to account for the exact position of the bit drive window on the AC bus relative to the ClkC clock. For example, if the output drivers have a known delay, the phase of the ClkC2 clock signal may be adjusted such that a portion of the output circuitry begins providing data to the output drivers slightly earlier than the time at which the data is to actually be driven onto an external signal line. The shifting of the phase of the ClkC2 clock signal can thus be used to account for the inherent delay in the output driver such that data is actually presented on the external data line at the desired time. Similarly, adjustments to the phase of the ClkC2 clock signal may also be used to ensure that the positioning of the valid data window for data driven based on the ClkC2 clock signal is optimally placed.

In a similar fashion, the transmit block for write data bus (D) inFIG. 13 uses a phase-delayed ClkC8 clock to perform eight-to-one serialization. The phase-delayed ClkC8 clock shifts theserial register1314 onto the DQ wires. Note the exact alignment of the phase-delayed ClkC8 clock will depend upon the circuit implementation of the driver logic; there may be a small offset to-account for driver delay. There may also be small offsets to account for the exact position of the bit drive window on the DQ bus.

The TphShA[i][n:0]control signals1236 select the appropriate phase offset relative to the input reference vectors ClkC8[N:1]. A phase offset selector may be implemented using a simple multiplexer, a more elaborate phase interpolator, or other phase offset selection techniques. In one example of a phase interpolator, a first reference vector of less-than-desired phase offset and a second reference vector of greater-than-desired phase offset are selected. A weighting value is applied to combine a portion of the first reference vector with a portion of the second reference vector to yield the desired output phase offset of the TClkC8A clock. Thus, the desired output phase offset of the TClkC8A clock is effectively interpolated from the first and second reference vectors. In one example of a phase multiplexer, the TphShA[i][n:0]control signals1236 are used to select one of the ClkC8[N:1] clock signals1219 to pass through to the TClkC8A clock (note that 2ⁿ⁺¹=N). The phase that is used is, in general, different for each transmit slice on the controller. The phase for each slice on the controller is preferably selected during a calibration process during initialization. This process is described in detail later in this description.

The TClkC8A clock passes through 1/81325 and 1/11324 frequency dividers before clocking the parallel1313 and serial1314 registers. Note that the ClkC8[N:1] signals that are distributed have a small phase offset to compensate for the delay of the phase offset selection block (PhShA)1306 and the frequency divider blocks1324 and1325. This offset is generated by a phase-locked-loop circuit and will track out supply voltage and temperature variations.

Even with the transmit phase shift value set correctly (so that the bit windows on theD bus1229 are driven properly), the phase of the TClkC1B clock used for theparallel register1313 could be misaligned (there are eight possible combinations of phase). There are several ways of dealing with the problem. The scheme that is used in the embodiment illustrated provides aninput TPhShB1235, such that when this input is pulsed, the phase of the TClkC1B clock will shift by ⅛^thof a cycle (45 degrees). The initialization software adjusts the phase of this clock until the parallel register loads the serial register at the proper time. This initialization process is described in detail later in this description.

Alternatively, it is also possible to perform the phase adjustment in the ClkC domain when preparing theTD bus1232 for loading into the transmitblock202. To do so, multiplexers and registers may be used to rotate the write data across ClkC cycle boundaries. A calibration process may be provided at initialization to accommodate the phase of the TClkC1B clock during which the transmitblock202 is powered up.

After the phase shift controls are properly adjusted, the write data can be transmitted onto the D bus from theparallel register1313. However, the write data still needs to be transferred from theTD bus1232 in theClkC1215 domain into theparallel register1313 in the TClkC1B domain. This is accomplished with theskip multiplexer1312. The multiplexer selects between registers that are clocked on the rising1310 and falling1311 edges of ClkC. The SkipT value determines which of the multiplexer paths is selected. The SkipT value is determined by sampling the TClkC1B clock by theClkCD clock1222. The resulting value is loaded into aregister1309 by theLoadSkip signal1238 during the initialization routine. This circuitry is described in detail later in this description.

The receiveblock203 for the read data Q is shown at the bottom ofFIG. 13. The receive block has essentially the same elements as the transmit block that was just discussed, except that the flow of data is reversed. However, the clock domain crossing issues are fundamentally similar.

The RPhShA[i][n:0]control signals1238 select one of the ClkC8[N:1] clock signals1219 to pass through to the RClkC8 clock. The phase that is used is, in general, different for each receive slice on the controller. The phase is selected during a calibration process during initialization. This process is described in detail later in this description.

The RClkC8A clock passes through 1/81327 and 1/11326 frequency dividers before clocking the parallel1320 and serial1319 registers. Note that the ClkC8[N:1] signals1219 that are distributed have a small phase offset to compensate for the delay of the phase offset selection block (PhShA)1315 and the frequency divider blocks1326 and1327. This offset is generated by a phase-locked-loop circuit and will track out supply voltage and temperature variations.

Even with the receive phase shift value set correctly (so that the bit windows on the Q bus are sampled properly), the phase of the RClkC1B clock used for theparallel register1320 could be mismatched (there are eight possible combinations of phase). There are several ways of dealing with the problem. The scheme that is used in the embodiment illustrated provides aninput RPhShB1237, such that when this input is pulsed, the phase of the RClkC1B clock will shift by 1/8^thof a cycle (45 degrees). The initialization software adjusts the phase of this clock until theparallel register1320 loads theserial register1319 at the proper time. This initialization process is described in detail later in this description.

A skip multiplexer similar to that described for the transmit circuit is used to move between the RClkC1B clock domain and the ClkC clock domain. After the phase shift controls are properly adjusted, the read data can be received from theQ bus1230 and loaded into theparallel register1320. However, the read data still needs to be transferred from theparallel register1320 in the RClkC1B domain into theregister1323 in theClkC1215 domain. This is accomplished with theskip multiplexer1322. The multiplexer can insert or not insert aregister1321 that is clocked on the negative edge of ClkC in between registers that are clocked on the rising edges ofRClkC1B1320 andClkC1323. The SkipR value determines which of the multiplexer paths is selected. The SkipR value is determined by sampling the RClkC1B clock by theClkCD clock1222. The resulting value is loaded into aregister1318 by theLoadSkip signal1238 during the initialization routine. This circuitry is described in detail later in this description.

FIG. 14 is a logic diagram illustrating details of the PLL used to generate the ClkC8 signal as illustrated inFIG. 12 in accordance with an embodiment of the present disclosure.PLL1204 comprisesPLL circuit1401, adjustable matcheddelays1402, matchedbuffers1403, andphase comparator1404.PLL circuit1401 comprisesVCO1405, dummy phase offsetselector1406,frequency divider1407, andphase comparator1408.ClkIn clock signal1201 is provided toVCO1405 andphase comparator1408.VCO1405 provides an output to adjustable matcheddelays1402 and matchedbuffers1403. Adjustable matcheddelays1402 provide a plurality of incrementally delayed outputs to matchedbuffers1403.

ThePLL circuit1401 generates a clock signal that is 8 times the frequency of the inputclock signal ClkIn1201, and the generated signal is also phase-shifted to account for delay expected to exist in the paths of the clock signals produced by the circuit inFIG. 14. As such, expected delays are compensated for during the clock generation process such that the clock signals that appear at the point of actual use are correctly phase adjusted. The remaining portion of theblock1204 outside of thePLL circuit1401 is used to generate equally phase-spaced versions of the clock produced by thePLL circuit1401. This is accomplished through well-known delay locked loop techniques where the delay locked loop provides the mechanism for generating the equally spaced clock signals. The clock signals produced as a result of theblock1204 inFIG. 14 are provided to the phase shifting logic described below with respect toFIG. 15. The results of the clock generation performed by the circuits ofFIGS. 14 and 15 are used to perform the serial-to-parallel or parallel-to-serial conversion as described inFIG. 13 above.

Output1409 of matchedbuffers1403, which is not delayed by adjustable matcheddelays1402, is provided to an input of dummy phase offsetselector1406 and an input ofphase comparator1404 and provides the ClkC8 clock signal.Delayed output1410 provides the ClkC8₁clock signal.Delayed output1411 provides the ClkC8₂clock signal.Delayed output1412 provides the ClkC8₃clock signal.Delayed output1413 provides the ClkC8_N−1clock signal.Delayed output1414 provides the ClkC8_Nclock signal, which is provided to an input ofphase comparator1404.Phase comparator1404 provides a feedback signal to adjustable matcheddelays1402, thereby providing a delay-locked loop (DLL). Each of the matchedbuffers1403 has a substantially similar propagation delay, thereby providing a buffered output without introducing unintended timing skew amongoutput1409 and delayedoutputs1410–1414.

TheClkIn reference clock1201 is received and is frequency-multiplied by 8× by thePLL1204. Several delays are included with the PLL feedback loop ofPLL1204, including a buffer delay introduced by matchedbuffers1403, a dummy phase offset selection delay introduced by dummy phase offsetselector1406, and a frequency divider delay introduced byfrequency divider1407. By including these delays in the feedback loop, the clock that is used for sampling and driving bits on the DQ will be matched to the ClkIn reference, and any delay variations caused by slow drift of temperature and supply voltage will be tracked out.

The output of thePLL circuit1401 is then passed through adelay line1402 with N taps. The delay of each element is identical, and can be adjusted over an appropriate range so that the total delay of N elements can equal one ClkC8 cycle (t_CC/8). There is afeedback loop1404 that compares the phase of the undelayed ClkC8 to the clock with maximum delay ClkC8[N]. The delay elements are adjusted until their signals are phase aligned, meaning there is t_CC/8 of delay across the entire delay line.

The ClkC8[N:1] signals pass throughidentical buffers1403 and see identical loads from the transmit and receive slices to which they connect. TheClkC8 reference signal1409 also has a buffer and a matched dummy load to mimic the delay.

FIG. 15 is a block diagram illustrating how the ClkC8[N:1] signals are used in the transmit and receive blocks of the memory controller component such as that illustrated inFIG. 13 in accordance with an embodiment of the present disclosure.PhShA logic block1501 comprises phase offsetselection circuit1502, which comprises phase offsetselector1503. Phase offsetselector1503 receives ClkC8₁clock signal1410, ClkC8₂clock signal1411, ClkC8₃clock signal1412, ClkC8_N−1clock signal1413, and ClkC8_Nclock signal1414 (i.e., N variants of the ClkC8 clock signal) and selects and providesClkC8A clock signal1504. This is accomplished using the N-to-1multiplexer1503 which selects one of the signals depending upon the setting of the control signals PhShA[i][n:0], where N=2ⁿ⁺¹. This allows the phase of the ClkC8A output clock for slice [i] to be varied across one ClkC8 cycle (t_CC/8) in increments of t_CC/8N.

At initialization, a calibration procedure is performed with software and/or hardware in which test bits are sampled and driven under each combination of the control signals PhShA[i][n:0]. The combination which yields the best margin is selected for each slice. This static value compensates for the flight time of the DQ and AC signals between the controller and the memory components. This flight time is mainly a factor of trace length and propagation velocity on printed wiring boards, and does not vary much during system operation. Other delay variations due to supply voltage and temperature are automatically tracked out by the feedback loops of the PLLs in the system.

FIG. 16 is a block diagram illustrating thePhShB circuit1307 and1316 ofFIG. 13.Clock conversion circuit1601 ofFIG. 16 preferably corresponds to 1/1divider circuit1324 and 1/1divider circuit1326 ofFIG. 13. Similarly,clock conversion circuit1602 ofFIG. 16 preferably corresponds to 1/8divider circuit1325 and 1/8divider circuit1327 ofFIG. 13. It produces a ClkC8B clock and a ClkC1B clock based on the ClkC8A clock in accordance with an embodiment of the present disclosure.Clock conversion circuit1601 comprises amultiplexer1603, which receivesClkC8A signal1504 and providesClkC8B signal1604.Clock conversion circuit1602 comprisesregisters1605,1606,1607, and1612,logic gate1608,multiplexer1611, and incrementingcircuits1609 and1610.PhShB signal1614 is applied to register1605, andClkC8A clock signal1504 is used toclock register1605. Outputs ofregister1605 are applied as an input and a clock input to register1606. An output ofregister1606 is applied as an input to register1607 andlogic gate1608. An output ofregister1606 is used toclock register1607. An output ofregister1607 is applied tologic gate1608. An output ofregister1607 is used toclock register1612. An output oflogic gate1608 is applied tomultiplexer1611.

Incrementing circuit1609 increments an incoming three-bit value by two.Incrementing circuit1610 increments the incoming three-bit value by one in a binary manner such that it wraps from 111 to 000. Multiplexer1611 selects among the three-bit outputs of incrementingcircuits1609 and1610 and provides a three-bit output to register1612.Register1612 provides a three-bit output to be used as the incoming three-bit value for incrementingcircuits1609 and1610. The most significant bit (MSB) of the three-bit output is used to provideClkC1B clock signal1613.

InFIG. 16, the ClkC8A clock that is produced by the PhShA (1306 and1315 ofFIG. 13) block is then used to produce a ClkC8B clock at the same frequency and to produce a ClkC1B clock at ⅛^ththe frequency. These two clocks are phase aligned with one another (each rising edge of ClkC1B is aligned with a rising edge of ClkC8B.

ClkC1B1613 is produced by passing it through a divide-by-eightcounter1602. ClkC8A clocks a threebit register1612 which increments on each clock edge. The most-significant bit will be ClkC1B, which is ⅛^ththe frequency of ClkC8A. TheClkC8B1604 clock is produced by a multiplexer which mimics the clock-to-output delay of the three bit register, so that ClkC1B and ClkC8B are aligned. As is apparent to one of ordinary skill in the art, other delaying means can be used in place of the multiplexer shown inblock1601 to accomplish the task of matching the delay through the divide-by-8 counter.

As described with respect toFIG. 13, it is necessary to adjust the phase ofClkC1B1613 so that the parallel register is loaded from/to the serial register in the transmit and receive blocks at the proper time. At initialization, a calibration procedure will transmit and receive test bits to determine the proper phasing of the ClkC1B clock. This procedure will use thePhShB control input1614. When this input has a rising edge, the three bit counter will increment by +2 instead of +1 on one of the following ClkC8A edges (after synchronization). The phase of the ClkC1B clock will shift ⅛^thof a cycle earlier. The calibration procedure will continue to advance the phase of the ClkC1B clock and check the position of test bits on the TD[i][7:0] and RQ[i][7:0] buses. When the test bits are in the proper position, the ClkC1B phase will be frozen.

FIG. 17 is a block diagram illustrating details of the PhShC block (1240 inFIG. 12) in accordance with an embodiment of the present disclosure.PhShC block1240 includesblocks1701–1704.Block1701 comprisesregister1705 andmultiplexer1706. Writedata input1714 is provided to register1705 andmultiplexer1706.Register1705 is clocked byClkC clock signal1215 and provides an output tomultiplexer1706. Multiplexer1706 receives TPhShC[0]selection input1713 and provideswrite data output1715.Block1702 comprisesregister1707 andmultiplexer1708. Readdata input1717 is provided to register1707 andmultiplexer1708.Register1707 is clocked byClkC clock signal1215 and provides an output tomultiplexer1708. Multiplexer1708 receives RPhShC[0]selection input1716 and provides readdata output1718.Block1703 comprisesregister1709 andmultiplexer1710. Writedata input1720 is provided to register1709 andmultiplexer1710.Register1709 is clocked byClkC clock signal1215 and provides an output tomultiplexer1710. Multiplexer1710 receives TPhShC[31]selection input1719 and provideswrite data output1721.Block1704 comprisesregister1711 andmultiplexer1712. Readdata input1723 is provided to register1711 andmultiplexer1712.Register1711 is clocked byClkC clock signal1215 and provides an output tomultiplexer1712. Multiplexer1712 receives RPhShC[31] selection input1722 and provides readdata output1724. While only two instances of the blocks for the write data and only two instances of the blocks for the read data are illustrated, it is understood that the blocks may be replicated for each bit of write data and each bit of read data.

ThePhShC block1240 is the final logic block that is used to adjust the delay of the 32×8 read data bits and the 32×8 write data bits so that all are driven or sampled from/to the same ClkC clock edge in the controller logic block. This is accomplished with an eight bit register which can be inserted into the path of the read and write data for each slice. The insertion of the delay is determined by the two control buses TPhShC[31:0] and RPhShC[31:0]. There is one control bit for each slice, since the propagation delay of the read and write data may cross a ClkC boundary at any memory slice position. Some systems with larger skews in the read and write data across the memory slices may need more than one ClkC of adjustment. The PhShC cells shown can be easily extended to provide additional delay by adding more registers and more multiplexer inputs.

The two control buses TPhShC[31:0] and RPhShC[31:0] are configured during initialization with a calibration procedure. As with the other phase-adjusting steps, test bits are read and written to each memory slice, and the control bits are set to the values that, in the example embodiment, allow all 256 read data bits to be sampled in one ClkC cycle and all 256 write data bits to be driven in one ClkC cycle by the controller logic.

FIG. 18 is a block diagram illustrating the logic details of the skip logic from the transmit block203 (inFIG. 13) of a memory controller component in accordance with an embodiment of the present disclosure. The skip logic comprisesregisters1801,1802,1803,1804, and1806, andmultiplexer1805.RClkC1B clock input1807 is provided to register1801 and is used toclock register1803.ClkCD clock input1222 is used toclock register1801, which provides an output to register1802.Register1802 receivesLoadSkip signal1238 and is clocked byClkC clock signal1215, providing an output tomultiplexer1805 and an output used toclock registers1804 and1806.Register1803 receives data in domain RClkC1B atinput1808 and provides an output to register1804 andmultiplexer1805.Register1804 provides an output tomultiplexer1805. Multiplexer1805 provides an output to register1806.Register1806 provides data in domain ClkC atoutput1809.

The circuit transfers the data in the RClkC1B clock domain to the ClkC domain. These two clocks have the same frequency, but may have any phase alignment. The solution is to sample RClkC1B with a delayed version of ClkC called ClkCD (the limits on the amount of delay can be determined by the system, but in one embodiment, the nominal delay is ¼ of a ClkC cycle). This sampled value is called SkipR, and it determines whether the data in an RClkC1B register may be transferred directly to a ClkC register, or whether the data must first pass through a negative-edge-triggered ClkC register.

RegardingFIG. 18, the following worst case setup constraints can be assumed:

• Case B0
  T_D,MAX+t_H1,MIN+t_CL,MIN+t_V,MAX+t_M,MAX+t_S,MIN<=t_CYCLE
  or
  t_D,MAX<=t_CH,MIN−t_H1,MIN−t_V,MAX−t_M,MAX−t_S,MIN  **constraint S**
• Case D1
  t_D,MAX+t_H1,MIN+t_CYCLE+t_V,MAX+t_S,MIN<=t_CYCLE+t_CL,MIN
  or
  t_D,MAX<=t_CL,MIN−t_H1,MIN−t_V,MAX−t_S,MIN

The following worst case hold constraints can be assumed:

• Case A1
  t_D,MIN−t_S1,MIN+t_V,,MIN>=t_H,MIN
  or
  t_D,MIN>=t_H,MIN+t_S1,MIN−t_V,,MIN  **constraint H**
• Case C0
  t_D,MIN−t_S1,MIN+t_V,,MIN+t_M,,MIN>=t_H,MIN
  or
  t_D,MIN>=t_H,MIN+t_S1,MIN−t_V,,MIN−t_M,,MIN

The timing parameters used above are defined as follow:

• t_S1—Setup time for clock sampler
• t_H1—Hold time for clock sampler
• t_S—Setup time for data registers
• t_H—Hold time for data registers
• t_V—Valid delay (clock-to-output) of data registers
• t_M—Propagation delay of data multiplexer
• t_CYCLE—Clock cycle time (RClkC1B, ClkC, ClkCD)
• t_CH—Clock high time (RClkC1B, ClkC, ClkCD)
• t_CL—Clock low time (RClkC1B, ClkC, ClkCD)
• t_D—Offset between ClkC and ClkCD (ClkCD is later)

Note:

• t_D,NOM˜t_CYCLE/4
• t_CH.NOM˜t_CYCLE/2
• t_CL.NOM˜t_CYCLE/2

FIG. 19 is a timing diagram illustrating the timing details of the skip logic of the receive block203 (illustrated inFIG. 13) in accordance with an embodiment of the present disclosure.FIG. 19 illustrates waveforms ofClkCD clock signal1901,ClkC clock signal1902, RClkC1B (case A0)clock signal1903, RClkC1B (case A1)clock signal1904, RClkC1B (case B0)clock signal1905, RClkC1B (case B1)clock signal1906, RClkC1B (case C0)clock signal1907, RClkC1B (case C1)clock signal1908, RClkC1B (case D0)clock signal1909, and RClkC1B (case D1)clock signal1910.Times1911,1912,1913,1914,1915,1916,1917, and1918, at intervals of one clock cycle, are illustrated to indicate the timing differences between the clock signals.

FIG. 19 generally summarizes the possible phase alignments of RClkC1B and ClkC as eight cases labeled A0 through D1. These cases are distinguished by the position of the RClkC1B rising and falling edge relative to the set/hold window of the rising edge of ClkCD which samples RClkC1B to determine the SkipR value. Clearly, if the RClkC1B rising or falling edge is outside of this window, it will be correctly sampled. If it is at the edge of the window or inside the window, then it can be sampled as either a zero or one (i.e., the validity of the sample cannot be ensured). The skip logic has been designed such that it functions properly in either case, and this then determines the limits on the delay of the ClkCD clock t_D.

For the receive block,case B01905 has the worst case setup constraint, andcase A11904 has the worst case hold constraint:
t_D,MAX<=T_CH,MIN−t_H1,MIN−t_V,MAX−t_M,MAX−t_S,MIN  **constraint S**
t_D,MIN>=t_H,MIN+t_S1,MIN−t_V,,MIN  **constraint H**

As mentioned earlier, the nominal value of t_D(the delay of ClkCD relative to ClkC) is expected to be ¼ of a ClkC cycle. The value of t_Dcan vary up to the t_D,MAXvalue shown above, or down to the t_D,MINvalue, also shown above. If the setup (e.g., t_S1, t_S), hold (e.g., t_H1, t_H), multiplexer propagation delay (e.g., t_M), and valid (e.g., t_V) times all went to zero, then the t_Dvalue could vary up to t_CH,MIN(the minimum high time of ClkC) and down to zero. However, the finite set/hold window of registers, and the finite clock-to-output (valid time) delay and multiplexer delay combine to reduce the permissible variation of the t_Dvalue.

Note that it would be possible to change some of the elements of the skip logic without changing its basic function. For example, a sampling clock ClkCD may be used that is earlier rather than later (the constraint equations are changed, but there is a similar dependency of the timing skew range of ClkC to ClkCD upon the various set, hold, and valid timing parameters). In other embodiments, a negative-edge-triggered RClkC1B register is used instead of a ClkC register into the domain-crossing path (again, the constraint equations are changed, but a similar dependency of the timing skew range of ClkC to ClkCD upon the various set, hold, and valid timing parameters remains).

Finally, it should be noted that the skip value that is used is preferably generated once during initialization and then loaded (with the LoadSkip control signal) into a register. Such a static value is preferable to rather than one that is sampled on every ClkCD edge because if the alignment of RClkC1B is such that it has a transition in the set/hold window of the ClkCD sampling register, it may generate different skip values each time it-is sampled. This would not affect the reliability of the clock domain crossing (the RClkC1B date would be correctly transferred to the ClkC register), but it would affect the apparent latency of the read data as measured in ClkC cycles in the controller. That is, sometimes the read data would take a ClkC cycle longer than at other times. Sampling the skip value and using it for all domain crossings solves this problem. Also note that during calibration, every time the RClkC1B phase is adjusted, the LoadSkip control is pulsed in case the skip value changes.

FIG. 20 is a block diagram illustrating the logic details of the skip logic of the transmitblock202 ofFIG. 13 in accordance with an embodiment of the present disclosure. The skip logic comprisesregisters2001,2002,2003,2004, and2006, andmultiplexer2005.TClkC1B clock input2007 is provided to register2001 and is used toclock register2006.ClkCD clock input1222 is used toclock register2001, which provides an output to register2002.Register2002 receivesLoadSkip signal1238 and is clocked byClkC clock signal1215, providing an output tomultiplexer2005 and an output used toclock registers2003 and2004.Register2003 receives data in domain ClkC atinput2008 and provides an output to register2004 andmultiplexer2005.Register2004 provides an output tomultiplexer2005. Multiplexer2005 provides an output to register2006.Register2006 provides data in domain TClkC1B atoutput2009.

The circuit ofFIG. 20 is used in the transfer of data in the ClkC clock domain to the TClkC1B domain. The two clocks ClkC and TClkC1B have the same frequency, but may be phase mismatched. One technique that can be used in the clock domain crossing is to sample TClkC1B with a delayed version of ClkC called ClkCD (the limits on the amount of delay can vary, but in one embodiment, the delay selected is ¼ of a ClkC cycle). The sampled value, SkipT, determines whether the data in a ClkC register is transferred directly to a TClkC1B register, or whether the data first passes through a negative-edge-triggered ClkC register.

RegardingFIG. 20, the following worst case setup constraints can be assumed:

• Case C0
  t_D,MIN−t_S1,MIN>=t_V,MAX+t_M,MAX+t_S,MIN
  or
  t_D,MIN>=t_S1,MIN+t_V,MAX+t_M,MAX+t_S,MIN  **constraint S**
• Case A1
  t_D,MIN−t_S1,MIN>=t_V,MAX+t_S,MIN
  or
  t_D,MIN>=t_S1,MIN+t_V,MAX+t_S,MIN

The following worst case hold constraints can be assumed:

• Case D1
  t_H,MIN<=t_CH,MIN−t_D,MAX−t_H1,MIN−T_V,,MIN
  or
  t_D,MAX<=t_CH,MIN−t_H1,MIN−t_V,MIN−t_H,MIN
  or
  t_D,MAX<=t_CL,MIN−t_H1,MIN−t_V,MIN−t_M,,MIN−t_H,MIN
• Case B0
  t_H,MIN<=t_CL,MIN−t_D,MAX−t_H1,MIN−t_V,,MIN−t_M,,MIN
  or
  t_D,MAX<=t_CL,MIN−t_H1,MIN−t_V,MIN−t_M,,MIN−t_H,MIN  **constraint H**
  Definitions for the timing parameters used above may be found in the discussion ofFIG. 18 above.

FIG. 21 is a timing diagram illustrating the timing details of the skip logic of the transmitblock202 ofFIG. 13 in accordance with an embodiment of the present disclosure.FIG. 21 illustrates waveforms ofClkCD clock signal2101,ClkC clock signal2102, TClkC1B (case A0)clock signal2103, TClkC1B (case A1) clock signal2104, TClkC1B (case B0)clock signal2105, TClkC1B (case B1)clock signal2106, TClkC1B (case C0)clock signal2107, TClkC1B (case C1)clock signal2108, TClkC1B (case D0)clock signal2109, and TClkC1B (case D1)clock signal2110.Times2111,2112,2113,2114,2115,2116,2117, and2118, at intervals of one clock cycle, are illustrated to indicate the timing differences between the clock signals.

FIG. 21 generally summarizes the possible phase alignments of TClkC1B and ClkC as eight cases labeled A0 through D1. These cases are distinguished by the position of the TClkC1B rising and falling edge relative to the set/hold window of the rising edge of ClkCD which samples TClkC1B to determine the SkipR value. Clearly, if the TClkC1B rising or falling edge is outside of this window, it will be correctly sampled. If it is at the edge of the window or inside the window, then it can be sampled as either a zero or one (i.e., the validity of the sample cannot be ensured). The skip logic has been designed such that it functions properly in either case, and this then determines the limits on the delay of the ClkCD clock t_D.

For the transmit block,case CO2107 has the worst case setup constraint, andcase B02105 has the worst case hold constraint:
t_D,MIN>=t_S1,MIN+t_V,MAX+t_M,MAX+t_S,MIN  **constraint S**
t_D,MAX<=t_CL,MIN−t_H1,MIN−t_V,MIN−t_M,,MIN−t_H,MIN  **constraint H**

As mentioned earlier, the nominal value of t_D(the delay of ClkCD relative to Clkc) will by ¼ of a ClkC cycle. This can vary up to the t_D,MAXvalue shown above, or down to the t_D,MINvalue. If the set, hold, mux (i.e., multiplexer), and valid times all went to zero, then the t_Dvalue could vary up to t_CH,MIN(the minimum high time of ClkC) and down to zero. However, the finite set/hold window of registers, and the finite clock-to-output (valid time) delay and multiplexer delay combine to reduce the permissible variation of the t_Dvalue.

As described with respect toFIG. 19 above, some elements of the skip logic can be changed for different embodiments while preserving its general functionality. Similarly, as described with respect to the skip logic ofFIG. 19, the skip value that is used is preferably generated during initialization and then loaded (with the LoadSkip control signal) into a register.

FIG. 22 is a timing diagram illustrating an example of a data clocking arrangement in accordance with an embodiment of the present disclosure. However, in this example, the clock phases in the memory controller and memory components have been adjusted to a different set of values than in the example illustrated inFIGS. 5 though21. The waveforms of WClk_S1,M0clock signal2201 and RClk_S1,M0clock signal2202 are illustrated to show the data timing forslice1 from the perspective of the memory controller component atslice0. The rising edges of sequential cycles of WClk_S1,M0clock signal2201 occur attimes2205,2206,2207,2208,2209,2210,2211, and2212, respectively. Writedatum information Da2213 is present on the data lines at the controller attime2205. Readdatum information Qb2204 is present attime2208. Readdatum information Qc2215 is present attime2209. Writedatum information Dd2216 is present attime2210. Writedatum information De2217 is present attime2211.

The waveforms of WClk_S1,M1clock signal2203 and RClk_S1,M1clock signal2204 are illustrated to show the data timing forslice1 from the perspective of the memory component atslice1. Writedatum information Da2218 is present on the data lines at the memory component attime2206. Readdatum information Qb2219 is present attime2207. Readdatum information Qc2220 is present attime2208. Writedatum information Dd2221 is present attime2211. Writedatum information De2222 is present attime2212.

The exemplary system illustrated inFIGS. 5 through 21 assumed that the clock for the read and write data were in phase at each memory component.FIG. 22 assumes that for each slice the read clock at each memory component is in phase with the write clock at the controller (RClk_Si,M0=WClk_Si,M1), and because the propagation delay t_PD2is the same in each direction, the write clock at each memory component is in phase with the read clock at the controller (WClk_Si,M0=RClk_Si,M1). This phase relationship shifts the timing slots for the read and write data relative toFIG. 6, but does not change the fact that two idle cycles are inserted during a write-read-read-write sequence. The phase relationship alters the positions within the system where domain crossings occur (some domain crossing logic moves from the controller into the memory components).

FIGS. 23 through 26 are timing diagrams illustrating an example of a data clocking arrangement in accordance with an embodiment of the present disclosure. However, in this example the clock phases in the memory controller and memory components have been adjusted to a different set of values than those in the example illustrated inFIGS. 5 though21. The example inFIGS. 23 through 26 also uses a different set of clock phase values than the example inFIG. 22.

FIG. 23 is a timing diagram illustrating an example of a data clocking arrangement in accordance with an embodiment of the present disclosure. The waveforms of WClk_S1,M0clock signal2301 and RClk_S1,M0clock signal2302 are illustrated to show the data timing forslice1 from the perspective of the memory controller component atslice0. Rising edges of sequential cycles of WClk_S1,M0clock signal2301 occur attimes2305,2306,2307, and2308, respectively. Writedatum information Da2309 is present on the data bus at the controller during a first cycle of WClk_S1,M0clock signal2301. Readdatum information Qb2310 is present at a fourth cycle of WClk_S1,M0clock signal2301. Readdatum information Qc2311 is present attime2305. Writedatum information Dd2312 is present attime2306. Writedatum information De2313 is present attime2307.

The waveforms of WClk_S1,M1clock signal2303 and RClk_S1,M1clock signal2304 are illustrated to show the data timing forslice1 from the perspective of the memory component atslice1. Writedatum information Da2314 is advanced one clock cycle relative to its position from the perspective of the memory controller component atslice0. In other words, the write data appears on the data bus at the memory device approximately one clock cycle later than when it appears on the data bus at the controller. Readdatum information Qb2315 is delayed one clock cycle relative to its position from the perspective of the memory controller component atslice0. Readdatum information Qc2316 is also delayed one clock cycle relative to its position from the perspective of the memory controller component atslice0. Writedatum information Dd2317 is present attime2317. Writedatum information De2318 is present attime2308.

The example system assumes that the clock for the read and write data are in phase at each memory component.FIG. 23 assumes that for each slice the read clock and write clock are in phase at the controller (RClk_Si,M0=WClk_Si,M0), and also that each slice is in phase with every other slice at the controller (WClk_Si,M0=WClk_Sj,M0). This shifts the timing slots for the read and write data relative toFIG. 6 andFIG. 22, but it does not change the fact that two idle cycles are used during a write-read-read-write sequence. The phase relationship alters the positions within the system where domain crossings occur (all the domain crossing logic moves from the controller into the memory components).

FIG. 6 represents the case in which all three clock phases (address, read data, and write data) are made the same at each memory component,FIG. 23 represents the case in which all three clock phases (address, read data, and write data) are made the same at the memory controller, andFIG. 22 represents one possible intermediate case. This range of cases is shown to emphasize that various embodiments of the present disclosure may be implemented with various phasing. The memory controller and memory components can be readily configured to support any combination of clock phasing.

The one extreme case in which all three clock phases (address, read data, and write data) are made the same at each memory component (illustrated inFIGS. 5 through 21) is important because there is a single clock domain within each memory component. The other extreme case in which all three clock phases (address, read data, and write data) are made the same at the memory controller (FIG. 23) is also important because there is a single clock domain within the controller.FIGS. 24 through 26 further illustrate this case.

FIG. 24 is a timing diagram illustrating timing at the memory controller component for the example of the data clocking arrangement illustrated inFIG. 23 in, accordance with an embodiment of the present disclosure. The waveforms of AClk_S0,M1clock signal2401 are illustrated to show the address/control timing for memory module one from the perspective of the memory controller component atslice0. The rising edges of sequential cycles of AClk_S0,M1clock signal2401 occur attimes2406,2407,2408,2409,2410,2411,2412, and2413, respectively.Address information ACa2414 is present on the address signal lines at the controller attime2406.Address information ACb2415 is present attime2407.Address information ACc2416 is present attime2408.Address information ACd2417 is present attime2412.

The waveforms of WClk_S1,M0clock signal2402 and RClk_S1,M0clock signal2403 are illustrated to show the data timing forslice1 from the perspective of the memory controller component atmodule0. Writedatum information Da2418 is present on the data lines at the controller attime2407. Readdatum information Qb2419 is present attime2411. Readdatum information Qc2420 is present attime2412. Writedatum information Dd2421 is present attime2413.

The waveforms of WClk_SNs,M0clock signal2404 and RClk_SNs,M0clock signal2405 are illustrated to show the data timing for slice N_Sfrom the perspective of the memory controller component atmodule0. Writedatum information Da2422 is present on the data lines at the controller attime2407. Readdatum information Qb2423 is present attime2411. Readdatum information Qc2424 is present attime2412. Writedatum information Dd2425 is present attime2413.

FIGS. 24 through 26 show the overall system timing for the case in which all clock phases are aligned at the controller.FIG. 24 is the timing at the controller, and is analogous toFIG. 7, except for the fact that the clocks are all common at the controller instead of at each memory slice. As a result, the clocks are all aligned inFIG. 24, and the two-cycle gap that the controller inserts into the write-read-read-write sequence is apparent between address packets ACc and ACd.

FIG. 25 is a timing diagram illustrating timing at a first slice of a rank of memory components for the example of the data clocking arrangement illustrated inFIG. 23 in accordance with an embodiment of the present disclosure. The waveforms of AClk_S1,M1clock signal2501 is illustrated to show the address/control timing for memory module one from the perspective of the memory component atslice1.Times2504,2505,2506,2507,2508,2509,2510, and2511 correspond totimes2406,2407,2408,2409,2410,2411,2412, and2413, respectively, ofFIG. 24.Signal AClk_S1,M12501 is delayed by a delay of t_PD0relative to signalAClk_S0,M12401 inFIG. 24. In other words, the AClk signal takes a time period t_PD0to propagate from the controller to the memory component.Address information ACa2512 is associated withedge2530 ofsignal2501.Address information ACb2513 is associated withedge2531 ofsignal2501.Address information ACc2514 is associated withedge2532 ofsignal2501.Address information ACd2515 is associated withedge2533 ofsignal2501.

The waveforms of WClk_S1,M1clock signal2502 and RClk_S1,M1clock signal2503 are illustrated to show the data timing forslice1 from the perspective of the memory component atmodule1.FIG. 25 shows the timing at the first memory component (slice1), and the clocks have become misaligned because of the propagation delays t_PD2and t_PD0.Signal WClk_S1,M12502 is delayed by a delay of t_PD2relative to signalWClk_S1,M02402 ofFIG. 24. Writedatum information Da2516 is associated withedge2534 ofsignal2502. Writedatum information Dd2519 is associated withedge2537 ofsignal2502.Signal RClk_S1,M12503 precedes by t_PD2signal RClk_S1,M02403 ofFIG. 24. Readdatum information Qb2517 is associated withedge2535 ofsignal2503. Readdatum information Qc2518 is associated withedge2536 ofsignal2503.

FIG. 26 is a timing diagram illustrating timing a last slice of a rank of memory components for the example of the data clocking arrangement illustrated inFIG. 23 in accordance with an embodiment of the present disclosure. The waveforms of AClk_SNs,M1clock signal2601 are illustrated to show the address/control timing for memory module one from the perspective of the memory component at slice N_S. Times2604,2605,2606,2607,2608,2609,2610, and2611 correspond totimes2406,2407,2408,2409,2410,2411,2412, and2413, respectively, ofFIG. 24.Signal AClk_SNs,M12601 is delayed by a delay of t_PD0+t_PD1relative to signalAClk_S0,M12401 ofFIG. 24. In other words, addressinformation ACa2612 is associated withedge2630 ofsignal2601.Address information ACb2613 is associated withedge2631 ofsignal2601.Address information ACc2614 is associated withedge2632 ofsignal2601.Address information ACd2615 is associated withedge2633 ofsignal2601.

The waveforms of WClk_SNs,M1clock signal2602 and RClk_SNs,M1clock signal2603 are illustrated to show the data timing for slice N_Sfrom the perspective of the memory component atmodule1.Signal WClk_SNs,M12602 is delayed by a delay of t_PD2relative to signalWClk_S1,M02402 ofFIG. 24. Writedatum information Da2616 is associated withedge2634 of signal2602 (e.g., the writedatum information Da2616 is present on the data bus at the memory component whenedge2634 ofsignal2602 is present on the AClk clock conductor at the memory component). Writedatum information Dd2619 is associated withedge2637 ofsignal2602.Signal RClk_SNs,M12603 precedes by t_PD2signal RClk_S1,M02603 ofFIG. 24. Readdatum information Qb2617 is associated withedge2635 ofsignal2603. Readdatum information Qc2618 is associated withedge2636 ofsignal2603.

FIG. 26 shows the timing at the last memory component (slice N_S), and the clocks have become further misaligned because of the propagation delays t_PD1. As a result, each memory component will have domain crossing hardware similar to that which is in the controller, as described with respect toFIGS. 12–21.

As a reminder, the example system described inFIG. 2 included single memory module, a single rank of memory components on that module, a common address and control bus (so that each controller pin connects to a pin on each of two or more memory components), and a sliced data bus (wherein each controller pin connects to a pin on exactly one memory component). These characteristics were chosen for the example embodiment in order to simplify the discussion of the details and because this configuration is an illustrative special case. However, the clocking methods that have been discussed can be extended to a wider range of system topologies. Thus, it should be understood that embodiments of the present disclosure may be practiced with systems having features that differ from the features of the example system ofFIG. 2.

The rest of this discussion focuses on systems with multiple memory modules or multiple memory ranks per module (or both). In these systems, each data bus wire connects to one controller pin and to one pin on each of two or more memory components. Since the t_PD2propagation delay between the controller and each of the memory components will be different, the clock domain crossing issue in the controller becomes more complicated. If the choice is made to align all clocks in each memory component, then the controller will need a set of domain crossing hardware for each rank or module of memory components in a slice. This suffers from a drawback in that it requires a large amount of controller area and that it adversely affects critical timing paths. As such, in a multiple module or multiple rank system, it may be preferable to keep all of the clocks aligned in the controller, and to place the domain crossing logic in the memory components.

FIG. 27 is a block diagram illustrating a memory system that includes multiple ranks of memory components and multiple memory modules in accordance with an embodiment of the present disclosure. The memory system comprisesmemory controller component2702,memory module2703,memory module2730, writeclock2705, readclock2706, writeclock2726, readclock2727,splitting component2742,splitting component2743,termination component2720,termination component2724,termination component2737, andtermination component2740. It should be understood that there is at least one write clock per slice in the example system shown.

Within each memory module, memory components are organized in ranks. A first rank ofmemory module2703 includesmemory components2716,2717, and2718. A second rank ofmemory module2703 includesmemory components2744,2745, and2746. A first rank ofmemory module2730 includesmemory components2731,2732, and2733. A second rank ofmemory module2730 includesmemory components2734,2735, and2736.

The memory system is organized into slices across the memory controller component and the memory modules. Examples of these slices includeslice2713,slice2714, andslice2715. Each slice comprises one memory component of each rank. In this embodiment, each slice within each memory module is provided with itsown data bus2708, writeclock conductor2710, and readclock conductor2711.Data bus2708 is coupled tomemory controller component2702,memory component2716, andmemory component2744. Atermination component2720 is coupled todata bus2708 nearmemory controller component2702, and may, for example, be incorporated intomemory controller component2702. Atermination component2721 is coupled near an opposite terminus ofdata bus2708, and is preferably provided withinmemory module2703. Writeclock2705 is coupled to writeclock conductor2710, which is coupled tomemory controller component2702 and tomemory components2716 and2744. Atermination component2723 is coupled near a terminus ofwrite clock conductor2710 nearmemory components2716 and2744, preferably withinmemory module2703. Readclock2706 is coupled to readclock conductor2711, which is coupled throughsplitting component2742 tomemory controller component2702 andmemory components2716 and2744. Splitting components are described in additional detail below. Atermination component2724 is coupled nearmemory controller component2702, and may, for example, be incorporated intomemory controller component2702. Atermination component2725 is coupled near a terminus of readclock conductor2711 nearmemory components2716 and2744, preferably withinmemory module2703.

Slice2713 ofmemory module2730 is provided withdata bus2747, writeclock conductor2728, readclock conductor2729.Data bus2747 is coupled tomemory controller component2702,memory component2731, andmemory component2734. Atermination component2737 is coupled todata bus2747 nearmemory controller component2702, and may, for example, be incorporated intomemory controller component2702. Atermination component2738 is coupled near an opposite terminus ofdata bus2747, and is preferably provided withinmemory module2730. Writeclock2726 is coupled to writeclock conductor2728, which is coupled tomemory controller component2702 and tomemory components2731 and2734. Atermination component2739 is coupled near a terminus ofwrite clock conductor2728 nearmemory components2731 and2734, preferably withinmemory module2730. Readclock2727 is coupled to readclock conductor2729, which is coupled throughsplitting component2743 tomemory controller component2702 andmemory components2731 and2734. Atermination component2740 is coupled nearmemory controller component2702, and may, for example, be incorporated intomemory controller component2702. Atermination component2741 is coupled near a terminus of readclock conductor2729 nearmemory components2731 and2734, preferably withinmemory module2730.

The sliced data bus can be extended to multiple ranks of memory component and multiple memory components in a memory system. In this example, there is a dedicated data bus for each slice of each module. Each data bus is shared by the ranks of memory devices on each module. It is preferable to match the impedances of the wires as they transition from the main printed wiring board onto the modules so that they do not differ to an extent that impairs performance. In some embodiments, the termination components are on each module. A dedicated read and write clock that travels with the data is shown for each data bus, although these could be regarded as virtual clocks; i.e. the read and write clocks could be synthesized from the address/control clock as in the example system that has already been described.

FIG. 28 is a block diagram illustrating a memory system that includes multiple ranks of memory components and multiple memory modules in accordance with an embodiment of the present disclosure. The memory system comprisesmemory controller component2802,memory module2803,memory module2830, writeclock2805, readclock2806,splitting component2842,splitting component2843,splitting component2848,splitting component2849,splitting component2850,splitting component2851,termination component2820,termination component2824,termination component2880, andtermination component2881.

Within each memory module, memory components are organized in ranks. A first rank ofmemory module2803 includesmemory components2816,2817, and2818. A second rank ofmemory module2803 includesmemory components2844,2845, and2846. A first rank ofmemory module2830 includesmemory components2831,2832, and2833. A second rank ofmemory module2830 includesmemory components2834,2835, and2836.

The memory system is organized into slices across the memory controller component and the memory modules. Examples of these slices include slice2813,slice2814, andslice2815. Each slice comprises one memory component of each rank. In this embodiment, each slice across multiple memory modules is provided with adata bus2808, writeclock conductor2810, and readclock conductor2811.Data bus2808 is coupled tomemory controller component2802, viasplitter2848 tomemory components2816 and2844, and viasplitter2849 tomemory components2831 and2834. Atermination component2820 is coupled todata bus2808 nearmemory controller component2802, and may, for example, be incorporated intomemory controller component2802. Atermination component2880 is coupled near an opposite terminus ofdata bus2808, nearsplitter2849. Atermination component2821 is coupled nearmemory components2816 and2844 and is preferably provided withinmemory module2803. Atermination component2838 is coupled nearmemory components2831 and2834 and is preferably provided withinmemory module2830.

Writeclock2805 is coupled to writeclock conductor2810, which is coupled tomemory controller component2802, viasplitter2850 tomemory components2816 and2844, and viasplitter2851 tomemory components2831 and2834. Atermination component2881 is coupled near a terminus ofwrite clock conductor2810, nearsplitter2851. Atermination component2823 is coupled nearmemory components2816 and2844, preferably withinmemory module2803. A termination component2839 is coupled nearmemory components2831 and2834, preferably withinmemory module2830.

Readclock2806 is coupled to readclock conductor2811, which is coupled throughsplitting component2843 tomemory components2831 and2834 and throughsplitting component2842 tomemory controller component2802 andmemory components2816 and2844. Atermination component2824 is coupled nearmemory controller component2802, and may, for example, be incorporated intomemory controller component2802. Atermination component2825 is coupled near a terminus of readclock conductor2811 nearmemory components2816 and2844, preferably withinmemory module2803. Atermination component2841 is coupled near a terminus of readclock conductor2811 nearmemory components2831 and2834, preferably withinmemory module2830.

As illustrated, this example utilizes a single data bus per data slice that is shared by all the memory modules, as inFIG. 28. In this example, each data wire is tapped using some form of splitting component S. This splitter could be a passive impedance matcher (three resistors in a delta- or y-configuration) or some form of active buffer or switch element. In either case, the electrical impedance of each wire is maintained down its length (within manufacturing limits) so that signal integrity is kept high. As in the previous configuration, each split-off data bus is routed onto a memory module, past all the memory components in the slice, and into a termination component.

FIG. 29 is a block diagram illustrating a memory system that comprises multiple ranks of memory components and multiple memory modules in accordance with an embodiment of the present disclosure. The memory system comprisesmemory controller component2902,memory module2903,memory module2930, writeclock2905, read clock2906,termination component2920,termination component2921,termination component2923, andtermination component2924.

Within each memory module, memory components are organized in ranks. A first rank ofmemory module2903 includesmemory components2916,2917, and2918. A second rank ofmemory module2903 includesmemory components2944,2945, and2946. A first rank ofmemory module2930 includesmemory components2931,2932, and2933. A second rank ofmemory module2930 includesmemory components2934,2935, and2936.

The memory system is organized into slices across the memory controller component and the memory modules. Examples of these slices includeslice2913,slice2914, andslice2915. Each slice comprises one memory component of each rank. In this embodiment, each slice across memory modules shares a common daisy-chaineddata bus2908, a common daisy-chainedwrite clock conductor2910, and a common daisy-chainedread clock conductor2911.Data bus2908 is coupled tomemory controller component2902,memory component2916,memory component2944,memory component2931, andmemory component2934. Atermination component2920 is coupled todata bus2908 nearmemory controller component2902, and may, for example, be incorporated intomemory controller component2902. Atermination component2921 is coupled near an opposite terminus ofdata bus2908.

Writeclock2905 is coupled to writeclock conductor2910, which is coupled tomemory controller component2902 and tomemory components2916,2944,2931, and2934. Atermination component2923 is coupled near a terminus ofwrite clock conductor2910. Read clock2906 is coupled to readclock conductor2911, which is coupled tomemory controller component2902 andmemory components2916,2944,2931, and2934. Atermination component2924 is coupled nearmemory controller component2902, and may, for example, be incorporated intomemory controller component2902.

In this embodiment, there is a single data bus per data slice, but instead of using splitting components, each data wire is routed onto a memory module, past all the memory components of the slice, and back off the module and onto the main board to “chain” through another memory module or to pass into a termination component. The same three configuration alternatives described above with respect to the data bus are also applicable to a common control/address bus in a multi-module, multi-rank memory system.

FIG. 30 is a block diagram illustrating a memory system that comprises multiple ranks of memory components and multiple memory modules with a dedicated control/address bus per memory module in accordance with an embodiment of the present disclosure. The memory system comprisesmemory controller component3002,memory module3003,memory module3030, address/control clock3004, address/control clock3053,termination component3052, andtermination component3056.

Within each memory module, memory components are organized in ranks. A first rank ofmemory module3003 includesmemory components3016,3017, and3018. A second rank ofmemory module3003 includesmemory components3044,3045, and3046. A first rank ofmemory module3030 includesmemory components3031,3032, and3033. A second rank ofmemory module3030 includesmemory components3034,3035, and3036.

The memory system is organized into slices across the memory controller component and the memory modules. Examples of these slices includeslice3013,slice3014, andslice3015. Each slice comprises one memory component of each rank. In this embodiment, each memory module is provided with itsown address bus3007 and address/control clock conductor3010.Address bus3007 is coupled tomemory controller component3002 andmemory components3016,3017,3018,3044,3045, and3046. Atermination component3052 is coupled to addressbus3007 nearmemory controller component3002, and may, for example, be incorporated intomemory controller component3002. Atermination component3019 is coupled near an opposite terminus ofaddress bus3007, and is preferably provided withinmemory module3003. Address/control clock3004 is coupled to address/control clock conductor3009, which is coupled tomemory controller component3002 and tomemory components3016,3017,3018,3044,3045, and3046. Atermination component3022 is coupled near a terminus of address/control clock conductor3009, preferably withinmemory module3003.

Memory module3030 is provided withaddress bus3054 and address/control clock conductor3055.Address bus3054 is coupled to memory controller component is3002 and to memory components,3031,3032,3033,3034,3035, and3036. Atermination component3056 is coupled to addressbus3054 nearmemory controller component3002, and may, for example, be incorporated intomemory controller component3002. Atermination component3057 is coupled near an opposite terminus ofaddress bus3054 and is preferably provided withinmemory module3030. Address/control clock3053 is coupled to address/control clock conductor3055, which is coupled tomemory controller component3002 and tomemory components3031,3032,3033,3034,3035, and3036. Atermination component3058 is coupled near a terminus of address/control clock conductor3055, preferably withinmemory module3030.

Each control/address wire is routed onto a memory module, past all the memory components, and into a termination component. The wire routing is shown in the direction of the ranks on the module, but it could also be routed in the direction of slices.

FIG. 31 is a block diagram illustrating a memory system that comprises multiple ranks of memory components and multiple memory modules with a single control/address bus that is shared among the memory modules in accordance with an embodiment of the present disclosure. The memory system comprisesmemory controller component3102,memory module3103,memory module3130, address/control clock3104,splitting component3159,splitting component3160,splitting component3161,splitting component3162,termination component3163, andtermination component3164.

Within each memory module, memory components are organized in ranks. A first rank ofmemory module3103 includesmemory components3116,3117, and3118. A second rank ofmemory module3103 includesmemory components3144,3145, and3146. A first rank ofmemory module3130 includesmemory components3131,3132, and3133. A second rank ofmemory module3130 includesmemory components3134,3135, and3136.

The memory system is organized into slices across the memory controller component and the memory modules. Examples of these slices includeslice3113,slice3114, andslice3115. Each slice comprises one memory component of each rank. In this embodiment, anaddress bus3107 and an address/control clock conductor3109 are coupled to each memory component among multiple memory modules.Address bus3107 is coupled tomemory controller component3102, viasplitter3159 tomemory components3116,3117,3118,3144,3145, and3146, and viasplitter3161 tomemory components3131,3132,3133,3134,3135, and3136. Atermination component3152 is coupled to addressbus3107 nearmemory controller component3102, and may, for example, be incorporated intomemory controller component3102. Atermination component3163 is coupled near an opposite terminus ofaddress bus3107, nearsplitter3161. Atermination component3119 is coupled to addressbus3107, preferably withinmemory module3103. Atermination component3157 is coupled to addressbus3107, preferably withinmemory module3130.

Address/control clock3104 is coupled to address/control clock conductor3109, which is coupled tomemory controller component3102, viasplitter3160 tomemory components3116,3117,3118,3144,3145, and3146, and viasplitter3162 tomemory components3131,3132,3133,3134,3135, and3136. Atermination component3164 is coupled near a terminus of address/control clock conductor3109, nearsplitter3162. Atermination component3122 is coupled to the address/control clock conductor3109, preferably withinmemory module3103. Atermination component3158 is coupled to the address/control clock conductor3109, preferably withinmemory module3130.

In this example, each control/address wire is tapped using some form of splitting component S. This splitter could be a passive impedance matcher (three resistors in a delta- or y-configuration) or some form of active buffer or switch element. In either case, the electrical impedance of each wire is maintained down its length (within manufacturing limits) so that signal integrity is kept high. As in the previous configuration, each split-off control/address bus is routed onto a memory module, past all the memory components, and into a termination component.

FIG. 32 is a block diagram illustrating a memory system that comprises multiple ranks of memory components and multiple memory modules with a single control/address bus that is shared by all the memory modules in accordance with an embodiment of the present disclosure. The memory system comprisesmemory controller component3202,memory module3203,memory module3230, address/control clock3204,termination component3219, andtermination component3222.

Within each memory module, memory components are organized in ranks. A first rank ofmemory module3203 includesmemory components3216,3217, and3218. A second rank ofmemory module3203 includesmemory components3244,3245, and3246. A first rank ofmemory module3230 includesmemory components3231,3232, and3233. A second rank ofmemory module3230 includesmemory components3234,3235, and3236.

The memory system is organized into slices across the memory controller component and the memory modules. Examples of these slices includeslice3213,slice3214, andslice3215. Each slice comprises one memory component of each rank. In this embodiment, the memory components of the memory modules share a common daisy-chainedaddress bus3207 and a common daisy-chained address/control clock conductor3209.Address bus3207 is coupled tomemory controller component3202 andmemory components3216,3217,3218,3244,3245,3246,3231,3232,3233,3234,3235, and3236. Atermination component3252 is coupled to addressbus3207 nearmemory controller component3202, and may, for example, be incorporated intomemory controller component3202. Atermination component3219 is coupled near an opposite terminus ofaddress bus3207.

Address/control clock3204 is coupled to address/control clock conductor3209, which is coupled tomemory controller component3202 and tomemory components3216,3217,3218,3244,3245,3246,3231,3232,3233,3234,3235, and3236. Atermination component3222 is coupled near a terminus of address/control clock conductor3209.

Unlike the memory system ofFIG. 31, instead of using some kind of splitting component, each control/address wire is routed onto a memory module, past all the memory components, and back off the module and onto the main board to chain through another memory module or to pass into a termination component.

The same three configuration alternatives are possible for a sliced control/address bus in a multi-module, multi-rank memory system. This represents a departure from the systems that have been discussed up to this point—the previous systems all had a control/address bus that was common across the memory slices. It is also possible to instead provide an address/control bus per slice. Each bus is preferably routed along with the data bus for each slice, and preferably has the same topological characteristics as a data bus which only performs write operations.

FIG. 33 is a block diagram illustrating a memory system that comprises multiple ranks of memory components and multiple memory modules with a dedicated, sliced control/address bus per memory module in accordance with an embodiment of the present disclosure. The memory system comprises memory controller component3302,memory module3303,memory module3330, address/control clock3304, address/control clock3353,termination component3352, andtermination component3356.

Within each memory module, memory components are organized in ranks. A first rank ofmemory module3303 includesmemory components3316,3317, and3318. A second rank ofmemory module3303 includesmemory components3344,3345, and3346. A first rank ofmemory module3330 includesmemory components3331,3332, and3333. A second rank ofmemory module3330 includesmemory components3334,3335, and3336.

The memory system is organized into slices across the memory controller component and the memory modules. Examples of these slices includeslice3313,slice3314, andslice3315. Each slice comprises one memory component of each rank. In this embodiment, each slice within each memory module is provided with itsown address bus3307 and address/control clock conductor3310.Address bus3307 is coupled to memory controller component3302 andmemory components3316 and3344. Atermination component3352 is coupled to addressbus3307 near memory controller component3302, and may, for example, be incorporated into memory controller component3302. Atermination component3319 is coupled near an opposite terminus ofaddress bus3307, and is preferably provided withinmemory module3303. Address/control clock3304 is coupled to address/control clock conductor3309, which is coupled to memory controller component3302 and tomemory components3316 and3344. Atermination component3322 is coupled near a terminus of address/control clock conductor3309, preferably withinmemory module3303.

Memory module3330 is provided withaddress bus3354 and address/control clock conductor3355.Address bus3354 is coupled to memory controller component3302 and to memory components,3331 and3334. Atermination component3356 is coupled to addressbus3354 near memory controller component3302, and may, for example, be incorporated into memory controller component3302. Atermination component3357 is coupled near an opposite terminus ofaddress bus3354 and is preferably provided withinmemory module3330. Address/control clock3353 is coupled to address/control clock conductor3355, which is coupled to memory controller component3302 and tomemory components3331 and3334. Atermination component3358 is coupled near a terminus of address/control clock conductor3355, preferably withinmemory module3330. Each control/address wire is routed onto a memory module, past all the memory components in the slice, and into a termination component.

FIG. 34 is a block diagram illustrating a memory system that comprises multiple ranks of memory components and multiple memory modules with a single control/address bus that is shared by all the memory modules in accordance with an embodiment of the present disclosure. The memory system comprisesmemory controller component3402,memory module3403,memory module3430, address/control clock3404,splitting component3459,splitting component3460,splitting component3461,splitting component3462,termination component3463, andtermination component3464.

Within each memory module, memory components are organized in ranks. A first rank ofmemory module3403 includesmemory components3416,3417, and3418. A second rank ofmemory module3403 includesmemory components3444,3445, and3446. A first rank ofmemory module3130 includesmemory components3431,3432, and3433. A second rank ofmemory module3430 includesmemory components3434,3435, and3436.

The memory system is organized into slices across the memory controller component and the memory modules. Examples of these slices includeslice3413,slice3414, andslice3415. Each slice comprises one memory component of each rank. In this embodiment, anaddress bus3407 and an address/control clock conductor3409 are coupled to each memory component-in a slice among multiple memory modules.Address bus3407 is coupled tomemory controller component3402, viasplitter3459 tomemory components3416 and3444, and viasplitter3461 tomemory components3431 and3434. Atermination component3452 is coupled to addressbus3407 nearmemory controller component3402, and may, for example, be incorporated intomemory controller component3402. Atermination component3463 is coupled near an opposite terminus ofaddress bus3407, nearsplitter3461. Atermination component3419 is coupled to addressbus3407, preferably withinmemory module3403. Atermination component3457 is coupled to addressbus3407, preferably withinmemory module3430.

Address/control clock3404 is coupled to address/control clock conductor3409, which is coupled tomemory controller component3402, viasplitter3460 tomemory components3416 and3444, and viasplitter3462 tomemory components3431 and3434. Atermination component3464 is coupled near a terminus of address/control clock conductor3409, nearsplitter3462. Atermination component3422 is coupled to the address/control clock conductor3409, preferably withinmemory module3403. Atermination component3458 is coupled to the address/control clock conductor3409, preferably withinmemory module3430.

In this example, each control/address wire is tapped using some form of splitting component S. This splitter could be a passive impedance matcher (three resistors in a delta- or y-configuration) or some form of active buffer or switch element. In either case, the electrical impedance of each wire is maintained down its length (within manufacturing limits) so that signal integrity is kept high. As in the previous configuration, each split-off control/address bus is routed onto a memory module, past all the memory components, and into a termination component.

FIG. 35 is a block diagram illustrating a memory system that comprises multiple ranks of memory components and multiple memory modules with a single control/address bus that is shared by all the memory modules in accordance with an embodiment of the present disclosure. The memory system comprisesmemory controller component3502,memory module3503,memory module3530, address/control clock3504,termination component3519, andtermination component3522.

Within each memory module, memory components are organized in ranks. A first rank ofmemory module3503 includesmemory components3516,3517, and3518. A second rank ofmemory module2903 includesmemory components3544,3545, and3546. A first rank ofmemory module3530 includesmemory components3531,3532, and3533. A second rank ofmemory module3530 includesmemory components3534,3535, and3536.

The memory system is organized into slices across the memory controller component and the memory modules. Examples of these slices includeslice3513,slice3514, andslice3515. Each slice comprises one memory component of each rank. In this embodiment, each slice across memory modules shares a common daisy-chainedaddress bus3507 and a common daisy-chained address/control clock conductor3509.Address bus3507 is coupled tomemory controller component3502 andmemory components3516,3544,3531, and3534. Atermination component3552 is coupled to addressbus3507 nearmemory controller component3502, and may, for example, be incorporated intomemory controller component3502. Atermination component3519 is coupled near an opposite terminus ofaddress bus3507.

Address/control clock3504 is coupled to address/control clock conductor3509, which is coupled tomemory controller component3502 and tomemory components3516,3544,3531, and3534. Atermination component3522 is coupled near a terminus of address/control clock conductor3509.

Unlike the memory system ofFIG. 34, instead of using some kind of splitting component, each control/address wire is routed onto a memory module, past all the memory components, and back off the module and onto the main board to chain through another memory module or to pass into a termination component.

As can be seen with reference to the Figures described above, embodiments of the present disclosure allow implementation of a memory system, a memory component, and/or a memory controller component. Within these embodiments skew may be measured according to bit time and/or according to a timing signal. In some embodiments, logic in the memory controller component accommodates skew, while in other embodiments, logic in a memory component accommodates skew. The skew may be greater than a bit time or greater than a cycle time.

One embodiment of the present disclosure provides a memory module with a first wire carrying a first signal. The first wire is connected to a first module contact pin. The first wire is connected to a first pin of a first memory component. The first wire is connected to a first termination device. The first wire maintains an approximately constant first impedance value along its full length on the memory module. The termination component approximately matches this first impedance value. Optionally, there is a second memory component to which the first wire does not connect. Optionally, the first signal carries principally information selected from control information, address information, and data information during normal operation. Optionally, the termination device is a component separate from the first memory component on the memory module. Optionally, the termination device is integrated into first memory component on the memory module. Such a memory module may be connected to a memory controller component and may be used in a memory system.

One embodiment of the present disclosure provides a memory module with a first wire carrying a first signal and a second wire carrying a second signal. The first wire connects to a first module contact pin. The second wire connects to a second module contact pin. The first wire connects to a first pin of a first memory component. The second wire connects to a second pin of the first memory component. The first wire connects to a third pin of a second memory component. The second wire does not connect to a pin of the second memory component. The first wire connects to a first termination device. The second wire connects to a second termination device. The first wire maintains an approximately constant first impedance value along its full length on the memory module. The second wire maintains an approximately constant second impedance value along its full length on the memory module. The first termination component approximately matches the first impedance value. The second termination component approximately matches the second impedance, value. Optionally, the first and/or second termination device is a component separate from the first memory component on the memory module. Optionally, the first and/or second termination device is a integrated into the first memory component on the memory module. Optionally, the first signal carries address information and the second signal carries data information. Such a memory module may be connected to a memory controller component and may be used in a memory system.

One embodiment of the present disclosure provides a method for conducting memory operations in a memory system. The memory system includes a memory controller component and a rank of memory components. The memory components include slices. The slices include a first slice and a second slice. The memory controller component is coupled to conductors, including a common address bus connecting the memory controller component to the first slice and the second slice, a first data bus connecting the memory controller component to the first slice, and a second data bus connecting the memory controller component to the second slice. The first data bus is separate from the second data bus The method includes the step of providing a signal to one of the conductors. The signal may be an address signal, a write data signal, or a read data signal. The propagation delay of the one of the conductors is longer than an amount of time that an element of information represented by the signal is applied to that conductor. Optionally, the method may include the step of providing a first data signal to the first data bus and a second data signal to the second data bus. The first data signal relates specifically to the first slice and the second data signal relates specifically to the second slice. In one example, the first data signal carries data to or from the first slice, while the second data signal carries data to or from the second slice.

One embodiment of the present disclosure provides a method for coordinating memory operations among a first memory component and a second memory component. The method includes the step of applying a first address signal relating to the first memory component to a common address bus over a first time interval. The common address bus is coupled to the first memory component and the second memory component. The method also includes the step of applying a second address signal relating to the second memory component to the common address bus over a second time interval. The first time interval is shorter than-a propagation delay of the common address bus, and the second time interval is shorter than a common address bus propagation delay of the common address bus. The method also includes the step of controlling a first memory operation of the first memory component using a first memory component timing signal. The first memory component timing signal is dependent upon a first relationship between the common address bus propagation delay and a first data bus propagation delay of a first data bus coupled to the first memory component. The method also includes the step of controlling a second memory operation of the second memory component using a second memory component timing signal. The second memory component timing signal is dependent upon a second relationship between the common address bus propagation delay and a second data bus propagation delay of a second data bus coupled to the second memory component.

One embodiment of the present disclosure (referred to as description B) provides a memory system with a memory controller component, a single rank of memory components on a single memory module, a common address bus connecting controller to all memory components of the rank in succession, separate data buses connecting controller to each memory component (slice) of the rank, an address bus carrying control and address signals from controller past each memory component in succession, data buses carrying read data signals from each memory component (slice) of the rank to the controller, data buses carrying write data signals from controller to each memory component (slice) of the rank, data buses carrying write mask signals from controller to each memory component (slice) of the rank, the read data and write data signals of each slice sharing the same data bus wires (bidirectional), the buses designed so that successive pieces of information transmitted on a wire do not interfere, a periodic clock signal accompanying the control and address signals and used by the controller to transmit information and by the memory components to receive information, a periodic clock signal accompanying each slice of write data signals and optional write mask signals and which is used by the controller to transmit information and by a memory component to receive information, and a periodic clock signal accompanying each slice of read data signals and which is used by a memory component to transmit information and by the controller to receive information.

One embodiment of the present disclosure (referred to as description A) provides a memory system with features taken from the above description (description B) and also a timing signal associated with control and-address signals which duplicates the propagation delay of these signals and which is used by the controller to transmit information and by the memory components to receive information, a timing signal associated with each slice of write data signals and optional write mask signals which duplicates the propagation delay of these signals and which is used by the controller to transmit information and by a memory component to receive information, a timing signal associated with each slice of read data signals which duplicates the propagation delay of these signals and which is used by a memory component to transmit information and by the controller to receive information, wherein a propagation delay of a wire carrying control and address signals from the controller to the last memory component is longer than the length of time that a piece of information is transmitted on the wire by the controller.

One embodiment of the present disclosure provides a memory system with features taken from the above description (description A) wherein a propagation delay of a wire carrying write data signals and optional write mask signals from the controller to a memory component is longer than the length of time that a piece of information is transmitted on the wire by the controller.

One embodiment of the present disclosure provides a memory system with features taken from the above description (description A) wherein a propagation delay of a wire carrying read data signals from a memory component to the controller is longer than the length of time that a piece of information is transmitted on the wire by the memory component.

One embodiment of the present disclosure provides a memory system with features taken from the above description (description A) wherein the alignments of the timing signals of the write data transmitter slices of the controller are adjusted to be approximately the same regardless of the number of slices in the rank, wherein the alignments of timing signals of the read data receiver slices of the controller are adjusted to be approximately the same regardless of the number of slices in the rank, and the alignments of timing signals of the read data receiver slices of the controller are adjusted to be approximately the same as the timing signals of the write data transmitter slices.

One embodiment of the present disclosure provides a memory system with features taken from the above description (description A) wherein the alignments of the timing signals of the write data transmitter slices of the controller are adjusted to be mostly different from one another.

One embodiment of the present disclosure provides a memory system with features taken from the above description (description A) wherein the alignments of timing signals of the read data receiver slices of the controller are adjusted to be mostly different from one another.

One embodiment of the present disclosure provides a memory system with features taken from the above description (description A) wherein the alignments of the timing signals of the read data transmitter of each memory component is adjusted to be the approximately the same as the timing signals of the write data receiver in the same memory component and wherein the alignments of the timing signals will be different for each memory component slice in the rank.

One embodiment of the present disclosure provides a memory system with features taken from the above description (description A) wherein the alignments of the timing signals of the write data transmitter of each memory component is adjusted to be different from the timing signals of the read data receiver in the same memory component.

Numerous variations to the embodiments described herein are possible without deviating from the scope of the claims set forth herein. Examples of these variations are described below. These examples may be applied to control and address signals, read data signals, write data signals, and optional write mask signals. For example, a timing signal associated with the such signals may be generated by an external clock component or by a controller component. That timing signal may travel on wires that have essentially the same topology as the wires carrying such signals. That timing signal may be generated from the information contained on the wires carrying such signals or from a timing signal associated with any of such signals. That timing signal may be asserted an integral number of times during the interval that each piece of information is present on a wire carrying such signals. As another variation, an integral number of pieces of information may be asserted on a wire carrying such signals each time the timing signal associated with such signals is asserted. As yet another variation, an integral number of pieces of information may be asserted on a wire carrying such signals each time the timing signal associated with such signals is asserted an integral number of times. The point when a timing signal associated with such signals is asserted may have an offset relative to the time interval that each piece of information is present on a wire carrying such signals.

As examples of other variations, the termination components for some of the signals may be on any of a main printed wiring board, a memory module board, a memory component, or a controller component. Also, two or more ranks of memory components may be present on the memory module and with some control and address signals connecting to all memory components and with some control and address signals connecting to some of the memory components. It is also possible for two or more modules of memory components to be present in the memory system, with some control and address signals connecting to all memory components and with some control and address signals connecting to some of the memory components.

Accordingly, a method and apparatus for coordinating memory operations among diversely-located memory components has been described. It should be understood that the implementation of other variations and modifications of the present disclosure in its various aspects will be apparent to those of ordinary skill in the art, and that the present disclosure is not limited by the specific embodiments described. It is therefore contemplated to cover by the present disclosure, any and all modifications, variations, or equivalents that fall within the spirit and scope of the basic underlying principles disclosed and claimed herein.

Claims (22)

The invention claimed is:

1. A memory device comprising:

clock generation circuitry to receive a first clock signal having a first frequency and to generate a second clock signal having a second frequency that is a multiple of, and higher than, the first frequency; and

a data receive circuit to receive data from an external signal path at the second frequency of the second clock signal.

2. The memory device ofclaim 1 wherein the clock generation circuitry comprises a first phase locked loop circuit to generate the second clock signal, and wherein the second frequency is an eight-times multiple of the first frequency.

3. The memory device ofclaim 2 wherein the data receive circuit comprises a serial-input register that is loaded with data at the second frequency and a parallel-input register coupled to receive data from the serial-input register, and wherein the clock generation circuitry further comprises a second phase locked loop circuit to generate a third clock signal having the first frequency, the third clock signal being provided to the parallel-input register to transfer data from the serial-input register to the parallel-input register at the first frequency.

4. The memory device ofclaim 1 wherein the clock generation circuitry comprises a first phase locked loop circuit to generate the second clock signal, and wherein the second frequency is a four-times multiple of the first frequency.

5. The memory device ofclaim 1 further comprising a data transmit circuit to transmit data at the second frequency of the second clock signal.

6. The memory device ofclaim 5 wherein the clock generation circuitry comprises a first phase locked loop circuit to generate the second clock signal, and wherein the second frequency is a eight-times multiple of the first frequency.

7. The memory device ofclaim 6 wherein the data transmit circuit comprises a serial-output register to output data at the second frequency, and a parallel-output register to provide data to the serial-output register, and wherein the clock generation circuitry further comprises a second phase locked loop circuit to generate a third clock signal having the first frequency, the third clock signal being provided to the parallel-output register to load data into the parallel-output register at the first frequency.

8. The memory device ofclaim 1 further comprising a circuit to receive control information at the frequency of a third clock signal, and wherein the clock generation circuitry comprises a first phase locked loop circuit to generate the third clock signal at a third frequency that is a two-times multiple of the first frequency.

9. The memory device ofclaim 8 wherein the control information includes address information.

10. The memory device ofclaim 8 wherein the circuit to receive control information comprises a serial-input register that is loaded with data at the third frequency and a parallel-input register coupled to receive data from the serial-input register, and wherein the clock generation circuitry further comprises a second phase locked loop circuit to generate a fourth clock signal having the first frequency, the fourth clock signal being provided to parallel-input register to transfer data from the serial-input register to the parallel-input register at the first frequency.

11. The memory device ofclaim 1, further comprising a memory core circuit to receive/transmit memory signals at the first frequency.

12. The memory device ofclaim 11, wherein the clock generation circuitry comprises a phase locked loop circuit to generate a third clock signal having the first frequency and wherein the memory core circuit is to receive/transmit memory signals in response to the third clock signal.

13. A memory device comprising:

clock generation circuitry to receive a first clock signal having a first frequency and to generate a second clock signal having a second frequency that is a multiple of, and higher than, the first frequency; and

a data transmit circuit to transmit data on an external signal path at the second frequency of the second clock signal.

14. The memory device ofclaim 13, wherein the clock generation circuitry comprises a first phase locked loop circuit to generate the second clock signal, and wherein the second frequency is an eight-times multiple of the first frequency.

15. The memory device ofclaim 14, wherein the wherein the data transmit circuit comprises a serial-output register to output data at the second frequency, and a parallel-output register to provide data to the serial-output register, and wherein the clock generation circuitry further comprises a second phase locked loop circuit to generate a third clock signal having the first frequency, the third clock signal being provided to the parallel-output register to load data into the parallel-output register at the first frequency.

16. The memory device ofclaim 13, wherein the clock generation circuitry comprises a first phase locked loop circuit to generate the second clock signal, and wherein the second frequency is a four-times multiple of the first frequency.

17. The memory device ofclaim 13 further comprising an control circuit to receive control information at the frequency of a third clock signal, wherein the clock generation circuitry comprises a first phase locked loop circuit to generate the third clock signal at a third frequency that is a two-times multiple of the first frequency.

18. The memory device ofclaim 17 wherein the control information includes address information.

19. The memory device ofclaim 17 wherein the circuit to receive control information comprises a serial-input register that is loaded with data at the third frequency and a parallel-input register coupled to receive data from the serial-input register, and wherein the clock generation circuitry further comprises a second phase locked loop circuit to generate a fourth clock signal having the first frequency, the fourth clock signal being provided to the parallel-input register to transfer data from the serial-input register to the parallel-input register at the first frequency.

20. The memory device ofclaim 13 further comprising a memory core circuit to receive/transmit memory signals at the first frequency.

21. The memory device ofclaim 20 wherein the clock generation circuitry comprises a phase locked loop circuit to generate a third clock signal having the first frequency and wherein the memory core circuit is to receive/transmit memory signals in response to the third clock signal.

22. A memory device comprising:

clock generation circuitry to receive a first clock signal having a first frequency and to generate a second clock signal having a frequency that is an eight-times multiple of the first frequency and a third clock signal having a frequency that is a two-times multiple of the first frequency;

a data receive circuit to receive data at the frequency of the second clock signal;

a data transmit circuit to transmit data at the frequency of the second clock signal; and

a circuit to receive control information at the frequency of the third clock signal.

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