US7200041B2 - Sensing scheme for low-voltage flash memory - Google Patents

Abstract

Single-ended sensing devices for sensing a programmed state of a floating-gate memory cell are adapted for use in low-voltage memory devices. The sensing device has an input node selectively coupled to the memory cell. The sensing device includes a precharging path for applying a precharge potential to the input node of the sensing device for precharging bit lines prior to sensing the programmed state of the memory cell, and a reference current path for applying a reference current to the input node of the sensing device. The sensing device still further includes a sense inverter having an input coupled to the input node of the sensing device and an output for providing an output signal indicative of the programmed state of the memory cell. The reference current is applied to the input node of the sensing device during sensing of the programmed state of the memory cell.

Description

STATEMENT OF RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 10/717,147, filed Nov. 19, 2003, now U.S. Pat. No. 6,813,190, issued Nov. 2, 2004, and titled “METHODS OF SENSING A PROGRAMMED STATE OF A FLOATING-GATE MEMORY CELL,” which is a divisional of U.S. patent application Ser. No. 10/036,751, filed Dec. 21, 2001, now U.S. Pat. No. 6,687,161, issued Feb. 3, 2004, and titled, “SENSING SCHEME FOR LOW-VOLTAGE FLASH MEMORY,” which are commonly assigned and incorporated by reference in its entirety herein, and which claim priority to Italian Patent Application Serial No. RM2001A000001 filed Jan. 3, 2001, which is commonly assigned.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to semiconductor memory devices, and in particular, the present invention relates to sensing schemes in a low-voltage semiconductor flash memory device.

BACKGROUND OF THE INVENTION

Semiconductor memory devices are rapidly-accessible memory devices. In a semiconductor memory device, the time required for storing and retrieving information generally is independent of the physical location of the information within the memory device. Semiconductor memory devices typically store information in a large array of cells. A group of cells are electrically connected together by a bit line, or data line. An electrical signal is used to program a cell or cells.

Computer, communication and industrial applications are driving the demand for memory devices in a variety of electronic systems. One important form of semiconductor memory device includes a non-volatile memory made up of floating-gate memory cells called flash memory. Computer applications use flash memory to store BIOS firmware. Peripheral devices such as printers store fonts and forms on flash memory. Digital cellular and wireless applications consume large quantities of flash memory and are continually pushing for lower voltages and power demands. Portable applications such as digital cameras, audio recorders, personal digital assistants (PDAs) and test equipment also use flash memory as a medium to store data.

To achieve lower operating voltages and lower power demands, operation of the memory device must generally come under tighter constraints. Lower operating margins increase the demands on sensing circuits and related circuits for accessing a memory cell and sensing the data contained therein. For example, sensing devices in flash memory devices often rely on a voltage differential to determine the programmed state of a memory cell, such as a voltage differential between a target bit line and a reference voltage. As operating voltages are reduced, such differential sensing devices often must be capable of distinguishing between smaller voltage differentials. At lower voltages, differential sensing becomes slower and, at very low voltages, may even become unreliable.

Read Only Memory (ROM) devices often utilize a single-ended sensing scheme as opposed to differential sensing. A single-ended sensing device has a single input coupled to a target bit line and provides an output signal indicative of a potential level of the target bit line. In operation, the target bit line is precharged to some precharge potential. During or after precharging, the word line of the target memory cell is driven. Upon release from the precharge potential, the logic state of the target memory cell is sensed. If the potential level of the target bit line remains unchanged, it is indicative of no current flow through the target memory cell, thus corresponding to a first logic state. If the potential level of the target bit line falls, it is indicative of current flow through the target memory cell, thus corresponding to a second logic state.

The single-ended sensing device often contains an inverter providing the output signal indicative of the logic state and having a threshold point close to the precharge potential. Choosing a threshold point close to the precharge potential improves the speed of the sensing device by reducing the time necessary to detect the second logic state. Choosing a threshold point close to the precharge potential also improves the power usage of the sensing device by reducing the amount of current necessary to precharge the bit line for the next read cycle. However, choosing a threshold point close to the precharge potential risks erroneous indications of the second logic state if undesired, or residual, current flow is experienced. Such risks have hindered use of single-ended sensing in high-performance flash memory devices, which often experience some residual current due to depletion, leakage, insufficient programming or other phenomena, yet must often perform at lower operating voltages and lower power requirements.

For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative sensing devices for integrated-circuit memory devices, memory devices containing such sensing devices, and methods of their operation.

SUMMARY OF THE INVENTION

The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.

Single-ended sensing devices for sensing a programmed state of a floating-gate memory cell are described herein for use in low-voltage memory devices. Sensing devices in accordance with the various embodiments include an input node selectively coupled to a floating-gate memory cell. Such sensing devices include a precharging path for applying a precharge potential to the input node of the sensing device. The precharge potential is used for precharging bit lines prior to sensing the programmed state of the floating-gate memory cell. Such sensing devices further include a reference current path for applying a reference current to the input node of the sensing device. Such sensing devices still further include a sense inverter having an input coupled to the input node of the sensing device and an output for providing an output signal indicative of the programmed state of the floating-gate memory cell. The reference current is applied to the input node of the sensing device during sensing of the programmed state of the floating-gate memory cell, thus compensating for residual current and improving immunity to erroneous indications of an erased floating-gate memory cell.

For one embodiment, the invention provides a single-ended sensing device for sensing a programmed state of a floating-gate memory cell. The sensing device has an input node selectively coupled to the floating-gate memory cell. The sensing device includes a precharging path coupled between a first potential node and the input node of the sensing device, wherein the first potential node is coupled to receive a precharge potential. The sensing device further includes a reference current path coupled between a second potential node and the input node of the sensing device, wherein the second potential node is coupled to receive a second potential for providing a reference current to the input node of the sensing device. The sensing device still further includes a sense inverter having an input coupled to the input node of the sensing device and an output for providing an output signal responsive to a potential level of the input node of the sensing device relative to a threshold point, wherein the output signal is indicative of the programmed state of the floating-gate memory cell. For a further embodiment, the sensing device further includes a reference current control signal generator having an output node coupled to the gate of a p-channel field-effect transistor of the reference current path for providing a reference current control signal for applying the reference current. The reference current control signal generator includes a diode coupled between a potential node and the output node of the reference current control signal generator and a resistive component coupled between another potential node and the output node of the reference current control signal generator.

For another embodiment, the invention provides a method of sensing a programmed state of a floating-gate memory cell. The method includes coupling a bit line to an input node of a single-ended sensing device, wherein the bit line is coupled to a source/drain region of the floating-gate memory cell, coupling the bit line and the input node to a first potential node to receive a precharge potential, applying a reference current to the input node, driving a word line coupled to a control gate of the floating-gate memory cell, and isolating the bit line and the input node from the first potential node. The method further includes sensing a potential level at the input node while applying the reference current, wherein the potential level at the input node is indicative of the programmed state of the floating-gate memory cell. For a further embodiment, applying a reference current to the input node includes generating a reference current and applying the reference current to the input node, wherein the reference current varies inversely with changes in ambient temperature.

The invention further provides memory devices and electronic systems making use of such sensing devices. The invention still further provides methods and apparatus of varying scope.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a block diagram of a basic flash memory device coupled to a processor as part of an electronic system.

FIG. 1B is a schematic of a portion of a typical non-volatile memory main block as a portion of a memory array of a memory device of the type shown inFIG. 1A.

FIG. 2 is a schematic of a portion of a memory device showing a single-ended sensing device coupled to receive a reference current.

FIG. 3 is a schematic of a reference current control signal generator for use with a sensing device of the type shown inFIG. 2.

FIG. 4 is a schematic of a driver circuit for use with a pass circuit and sensing device of the types shown inFIG. 2.

FIG. 5 is a schematic of a timing circuit for use with a sensing device of the type shown inFIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of the present embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that process, electrical or mechanical changes may be made without departing from the scope of the present invention. The term substrate used in the following description includes any base semiconductor structure. Examples include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and the term substrate includes the underlying layers containing such regions/junctions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof.

Sensing devices in accordance with the various embodiments are adaptable for a variety of memory devices, including flash memory devices.FIG. 1A is a functional block diagram of a basicflash memory device101 that is coupled to aprocessor103. Thememory device101 and theprocessor103 may form part of anelectronic system100. Thememory device101 has been simplified to focus on features of the memory that are helpful in understanding the present invention. Thememory device101 includes an array ofmemory cells105. The memory cells are preferably non-volatile floating-gate memory cells and generally have their control gates coupled to word lines, drain regions coupled to local bit lines, and source regions commonly coupled to a ground potential. Thememory array105 is arranged in rows and columns, with the rows arranged in blocks. The memory cells generally can be erased in blocks. Data, however, may be stored in thememory array105 separate from the block structure.

Arow decoder109 and acolumn decoder111 are provided to decode address signals provided on address lines A0-Ax 113. Anaddress buffer circuit115 is provided to latch the address signals. Address signals are received and decoded to access thememory array105. A columnselect circuit119 is provided to select a column of thememory array105 in response to control signals from thecolumn decoder111.Sensing circuitry121 is used to sense and amplify data stored in the memory cells.Sensing circuitry121 includes a sensing device in accordance with the various embodiments of the invention.Data input123 andoutput125 buffer circuits are included for bi-directional data communication over a plurality of data (DQ)lines127 with theprocessor103. Adata latch129 is typically provided between datainput buffer circuit123 and theDQ lines127 for storing data values (to be written to a memory cell) received from the DQ lines127. Data amplified by thesensing circuitry121 is provided to the dataoutput buffer circuit125 for output on the DQ lines127.

Command control circuit131 decodes signals provided oncontrol lines135 from theprocessor103. These signals are used to control the operations on thememory array105, including data read, data write, and erase operations. Input/output control circuit133 is used to control the datainput buffer circuit123 and the dataoutput buffer circuit125 in response to some of the control signals. As stated above, theflash memory device101 has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of flash memories is known to those skilled in the art.

Arrays of flash memory cells are often configured as floating-gate transistors placed at the intersection of word lines and local bit lines. The word lines are coupled to the control gates of the floating-gate transistors.FIG. 1B is a schematic of a portion of a typical non-volatile memorymain block130 as a portion of thememory array105.

The detail ofmain block130 is provided to better understand the various embodiments of the invention. However, the invention is not limited to the specific floating-gate memory cell and layout described with reference toFIG. 1B.

As shown inFIG. 1B, themain block130 includesword lines132 and intersecting local bit lines134. For ease of addressing in the digital environment, the number ofword lines132 and the number oflocal bit lines134 are each some power of two, e.g., 256word lines132 by 4,096 local bit lines134.

Floating-gate transistors136 are located at each intersection of aword line132 and alocal bit line134. Thefloating-gate transistors136 represent the non-volatile memory cells for storage of data. Typical construction of suchfloating-gate transistors136 include asource region138 and adrain region140 constructed from an N⁺-type material of high impurity concentration formed in a P-type semiconductor substrate of low impurity concentration, a channel region formed between the source and drain, a floatinggate142, and acontrol gate144. Floatinggate142 is isolated from the channel region by a tunneling dielectric and from thecontrol gate144 by an intergate dielectric. The materials of construction are not critical to the invention, but commonly include doped polysilicon for the gate materials, and silicon oxides, nitrides or oxynitrides for the dielectric materials.Floating-gate transistors136 having theircontrol gates144 coupled to aword line132 typically share acommon source region138 depicted asarray source146. To reduce resistance to eachsource region138, eacharray source146 is often coupled to a metal line to ground, such asarray ground148. As shown inFIG. 1B,floating-gate transistors136 coupled toadjacent word lines132 may share thesame array source146.Floating-gate transistors136 have theirdrain regions140 coupled to alocal bit line134. A column of thefloating-gate transistors136 are those transistors having theirdrain regions140 commonly coupled to a givenlocal bit line134. A row of thefloating-gate transistors136 are those transistors having theircontrol gates144 commonly coupled to a givenword line132.

FIG. 2 is a schematic of a portion of amemory device101 having at least onesensing device205 in accordance with the invention. As shown inFIG. 2, atarget memory cell136 is selectively coupled to asensing device205 through its associatedlocal bit line134 andglobal bit line215. As noted previously, there are generally manylocal bit lines134 associated with a singleglobal bit line215 and manyglobal bit lines215 associated with asingle sensing device205 in typical high-density memory devices. Thesensing device205 is generally one ofmany sensing devices205 contained in thesensing circuitry121 as depicted inFIG. 1A.

Theglobal bit line215 associated with thetarget memory cell136 is coupled to its associatedsensing device205 usingpass circuit210.Pass circuit210 is depicted as containing a single selective coupling device orpass transistor225 providing the selective coupling between theglobal bit line215 and thesensing device205. Thepass transistor225 has a gate coupled to receive a control signal fromnode235. Those skilled in the art of memory devices will recognize thatpass circuit210 would contain additional pass transistors associated with other global bit lines. Furthermore, additional pass transistors may be interposed between theglobal bit line215 and thesensing device205.

Thelocal bit line134 associated with thetarget memory cell136 is coupled to its associatedglobal bit line215 usingpass circuit220.Pass circuit220 is depicted as containing a single selective coupling device orpass transistor230 providing the selective coupling between thelocal bit line134 and theglobal bit line215. Thepass transistor230 has a gate coupled to receive a control signal fromnode240. Those skilled in the art of memory devices will recognize thatpass circuit220 would contain additional pass transistors associated with other local bit lines. Furthermore, additional pass transistors may be interposed between thelocal bit line134 and theglobal bit line215. Passcircuits210 and220 may represent a portion of the columnselect circuit119 ofFIG. 1A.

Thesensing device205 includes a precharging path for selectively applying the precharge potential to charge thelocal bit line134, theglobal bit line215, and theinput node262. The precharging path is shown inFIG. 2 as the p-channel field-effect transistor (pFET)256 coupled between a potential node250 and theinput node262. The potential node250 is coupled to receive the precharge potential. The precharge potential may be a supply potential, such as Vcc. ThepFET256 selectively couples the potential node250 to theinput node262 in response to a control signal received atnode254.

Thesensing device205 further includes a reference current path for selectively applying a reference current to theinput node262. Ideally, atarget memory cell136 and its path to thesensing device205 would exhibit a zero current draw if the floating-gate transistor of thetarget memory cell136 were programmed, i.e., in a first programmed state, such that theinput node262 would remain at the precharge potential during sensing. However, some residual current may be expected, whether such residual current is due to leakage, depletion, or some other phenomena. This residual current could result in an erroneous indication that the target memory cell is erased, i.e., in a second programmed state. The reference current path provides a reference current to theinput node262 to compensate for such residual currents and to avoid erroneous indications of the second programmed state.

The reference current path is shown inFIG. 2 as thepFET258 coupled between thepotential node252 and theinput node262. Thepotential node252 is coupled to receive a supply potential, such as Vcc. The reference current should be less than a current flow through thetarget memory cell136 if thetarget memory cell136 is erased or in the second programmed state, yet more than the expected residual current. For one embodiment, the reference current is controlled to be less than half of the expected current of an erased memory cell in the second programmed state. For a further embodiment, the reference current is controlled to be approximately one order of magnitude less than the expected current of an erased memory cell in the second programmed state. For one embodiment, the reference current is controlled through the application of a reference current control signal to the gate of thepFET258 fromnode260. Varying the potential level of the reference current control signal will vary the conductance of thepFET258, resulting in control of the current flow through the reference current path.

Thesensing device205 still further includes asense inverter264 having a threshold point. The sense inverter generates an output signal atoutput node278 in response to a potential level at theinput node262 relative to the threshold point. The potential level of theinput node262 is indicative of the state of thelocal bit line134.

Thesense inverter264 includes a p-channel stage having apFET268 coupled between apotential node266 and theoutput node278. Thepotential node266 is coupled to receive a supply potential, such as Vcc. The supply potential represents a first logic level, such as a logic high level. Thesense inverter264 further includes an n-channel stage having at least one n-channel field-effect transistor (nFET) coupled between theoutput node278 and apotential node276. Thepotential node276 is coupled to receive a ground potential, such as Vss. The ground potential represents a second logic level, such as a logic low level. For the embodiment ofFIG. 2, thesense inverter264 includesnFET270,nFET272 andnFET274 coupled in series between theoutput node278 and thepotential node276. ThepFET268,nFET270,nFET272 andnFET274 each have a gate coupled to theinput node262. The multiple nFET devices in thesense inverter264 are used to move the threshold point closer to the precharge potential. The combination of a low voltage p-channel stage and a weak n-channel stage in thesense inverter264 can maintain the threshold point near the precharge potential. Other methods of altering the threshold point of thesense inverter264 may be used, such as varying the sizing of the FET devices.

During sensing, if the target memory cell is in the second programmed state, the bit lines will be expected to drop to a potential below the precharge potential. The expected bit line potential is approximately the precharge potential minus the threshold voltage of the transistors minus some delta for ohmic drop across the bit lines. The threshold point of thesense inverter264 must be some potential level higher than this expected bit line potential in order to reliably detect and amplify the data value of the target memory cell. For one embodiment, the expected minimum bit line potential is approximately 0.94V and the threshold point of thesense inverter264 is approximately 1.1V using a supply potential and precharge potential of approximately 1.8V.

Operation of thememory device101 proceeds generally as follows. The bit lines134 and215 are decoded and coupled to theinput node262 of asensing device205. The decoded bit lines may be thought of as a single bit line coupled to the target memory cell. The bit line and theinput node262 are precharged to the precharge potential from the potential node250 and theword line132 of thetarget memory cell136 is driven. In addition, a reference current is applied to theinput node262 of thesensing device205 through the reference current path. The bit line is then isolated from the precharge potential while maintaining application of the reference current. The programmed state of thetarget memory cell136 is sensed and amplified by thesensing device205. The data value at theoutput node278 is latched and the memory device is returned to a low power mode.

For one embodiment, a reference current control signal generator is used to control the reference current to mimic the expected residual current of the target memory cell. For a further embodiment, the memory device includes one such reference current control signal generator for each sensing device. For another embodiment, the memory device includes one such reference current control signal generator for some number of sensing devices. For a further embodiment, the memory device includes one such reference current control signal generator for each word of output or every 16 sensing devices.

To best mimic the expected residual current of a floating-gate memory cell, it may be desirable to utilize a similar floating-gate memory cell in controlling the reference current. However, use of a dummy floating-gate memory cell requires a trimming operation and leads to undesirable testing during fabrication. As described herein, a resistive component may be used in the reference current control signal generator in place of the floating-gate memory cell to avoid the unnecessary trimming and testing of a dummy floating-gate memory cell.

FIG. 3 is a schematic of a reference currentcontrol signal generator300 in accordance with an embodiment of the invention. The reference currentcontrol signal generator300 provides the reference current control signal as an output signal. For one embodiment, the reference current control signal has a potential level that varies proportionately with changes in ambient temperature. As ambient temperature increases, the reference current control signal increases. In turn, thepFET258 is pushed closer to deactivation with a resultant decrease in the value of the reference current such that the reference current varies inversely with changes in ambient temperature. This will tend to track changes in current flow through a target memory cell in the erased state, as this current also tends to decrease in response to increasing ambient temperatures. The reference current is preferably proportional to the current flow through a target memory cell in the erased state to maintain consistent sensing conditions.

The reference currentcontrol signal generator300 includes a diode302 having an input coupled to receive a supply potential from apotential node304 and an output coupled to anoutput node306. Thepotential node304 is preferably coupled to receive the same supply potential received at thepotential node266 of thesense inverter264, e.g., the supply potential Vcc. Theoutput node306 is coupled to thenode260 to provide the control signal to the gate of thepFET258 of asensing device205. For the embodiment depicted inFIG. 3, the diode302 contains an array of one or more diode-connected field-effect transistors such as pFETs358. The pFETs358 are coupled in parallel between the input and output of the diode302. Each pFET358 has a gate coupled to the output of the diode302, a first source/drain region coupled to the input of the diode302, and a second source/drain region coupled to the output of the diode302. For one embodiment, each pFET358 is preferably sized to be substantially identical to thepFET258 of thesensing device205. For a further embodiment, the diode302 includes 12 pFETs358 coupled in parallel, each sized to be substantially identical to thepFET258 of thesensing device205. For a still further embodiment, theoutput node306 is concurrently coupled to 16sensing devices205.

The reference currentcontrol signal generator300 may optionally be selectively enabled or disabled. An enable signal received atnode310 may be used to enable or disable the reference currentcontrol signal generator300 by providing an FET of a first type, such aspFET308, coupled between thepotential node304 and the input of the diode302 and having its gate coupled to receive the enable signal. The reference currentcontrol signal generator300 is enabled when the input of the diode302 is actively coupled to receive the supply potential from thepotential node304. The enable signal received atnode310 may also be used to pull theoutput node306 to a ground potential when the reference currentcontrol signal generator300 is disabled by providing an FET of an opposite type, such asnFET312, coupled between theoutput node306 and a groundpotential node314 and having its gate coupled to receive the enable signal.

The reference currentcontrol signal generator300 further includes aresistive component316 coupled between theoutput node306 and apotential node318. Thepotential node318 is coupled to receive a ground potential. Thepotential node318 is preferably coupled to receive the same ground potential received at thepotential node276 of thesense inverter264, e.g., the ground potential Vss. Theresistive component316 includes at least one resistive element, such as resistive element320. Additional resistive elements, such asresistive elements322,324 and326, may be coupled in parallel with the resistive element320. As shown inFIG. 3, each resistive element may selectively present an open path to allow post-fabrication adjustment of resistance of theresistive component316. This will allow finer adjustment and control of the reference current generated in response to the reference current control signal.

The first resistive element320 has a first resistance value, the secondresistive element322 has a second resistance value, the thirdresistive element324 has a third resistance value and the fourthresistive element326 has a fourth resistance value. For one embodiment, the second resistance value is substantially equal to the first resistance value, the third resistance value is approximately one-half the first resistance value and the fourth resistance value is approximately one-fourth the first resistance value. For a further embodiment, the first resistance value is approximately 16 kΩ. As shown,resistive element322 selectively presents an openpath using nFET340 in response to a control signal received atnode348,resistive element324 selectively presents an openpath using nFET342 in response to a control signal received atnode350, andresistive element326 selectively presents an openpath using nFET344 in response to a control signal received atnode352. Each control signal is distinct, allowing selection of the combined resistance value of theresistive component316 after fabrication.

The reference currentcontrol signal generator300 may further include one or more field-effect transistors coupled between theoutput node306 and theresistive component316. For the embodiment depicted inFIG. 3, the reference currentcontrol signal generator300 includes afirst nFET325 and asecond nFET330 coupled in series between theoutput node306 and theresistive component316. For one embodiment, thenFET325 is preferably sized to be substantially identical to thepass transistor225 of thepass circuit210 and thenFET330 is preferably sized to be substantially identical to thepass transistor230 of thepass circuit220.

ThenFET325 andnFET330 each have their gate coupled to receive a control signal onnode346. ThenFET338 coupled between the resistive element320 and the secondpotential node318 further has its gate coupled to receive the control signal onnode346. Thenode346 may be coupled to receive a supply potential as the control signal, thereby activating thenFETs325,330 and338. Alternatively, thenode346 may be coupled to receive the output of a voltage divider. As such, the control signal may be a reduced potential level, such as Vcc/2, and may result in at least a partial activation of thenFETs325,330 and338.

It is noted that thepass transistor225 of thepass circuit210 acts as a cascode amplifier having a high input capacitance and a low output capacitance; the capacitance of theglobal bit line215 is typically orders of magnitude larger than the capacitance of theinput node262 of thesensing device205. While this will lead to fast reaction times at theinput node262 to a current sink through the target memory cell, it also reduces the immunity of thesensing device205 to noise in the control signal to the gate of thepass transistor225. For improved reliability, it is preferred that signal noise be suppressed for the control signal received atnode235 at least during sensing of the programmed state of the target memory cell. U.S. patent application Ser. No. 10/032,375 claiming priority to Italian Patent Application RM2000A000698) entitled “Supply Noise Reduction in Memory Device Column Selection,” which is commonly assigned, describes methods and circuits for suppressing noise for such control signals. An example of one such circuit and method for suppressing noise will be described with reference toFIG. 4.

Thesensing device205 has three phases of operation, i.e., a first sensing phase for precharging and address decoding, a second sensing phase for sensing the programmed state of the target memory cell, and a non-sensing phase for isolation of the sensing device from the memory cells. Thedriver circuit400 ofFIG. 4 has three states corresponding to these three phases of operation. In the first and second sensing phases, thepass transistor225 is activated to permit coupling of thetarget memory cell136 to its associatedsensing device205. During the first sensing phase, thepass transistor225 receives its activating control signal using an unfiltered path. During the first sensing phase, thesensing device205 is tolerant of noise. To improve transition speeds of thepass transistor225, the control signal onnode235 is preferably unfiltered. During the second sensing phase, thepass transistor225 receives its activating control signal through a filtered path and is isolated from the unfiltered path. As the programmed state of the target memory cell is being sensed during the second sensing phase, it is desirable to suppress noise atnode235. Thepass transistor225 is simply being maintained in the activated state during the second sensing phase such that transition speed is inconsequential. In the non-sensing phase, thepass transistor225 is deactivated to isolate thetarget memory cell136 from its associatedsensing device205.

As shown inFIG. 4, a first control signal is applied to a first input ofNAND gate440 fromnode450. The first control signal, herein referred to as FILTER_ON, is indicative of whether thepass transistor225 should be isolated from the unfiltered supply potential. Using the logic circuits as shown inFIG. 4, a logic low level of FILTER_ON indicates that thepass transistor225 is to be isolated from thepotential node410 while a logic high level indicates that thepass transistor225 may be coupled to thepotential node410. Thepotential node410 is coupled to receive a supply potential such as Vcc. A second control signal is applied to a second input ofNAND gate440 and to aninverter445 fromnode455. The second control signal, herein referred to as YPASS, is indicative of whether thepass transistor225 should be activated or deactivated. Using the logic circuits as shown inFIG. 4, a logic low level of YPASS indicates that thepass transistor225 is to be coupled topotential node420 for deactivation while a logic high level indicates that thepass transistor225 is to be coupled to at least one ofpotential nodes410 and415 for activation. Thepotential node420 is coupled to receive a ground potential such as Vss. Thepotential node415, likepotential node410, is coupled to receive the supply potential.

In operation, thememory device101 initially may be in the non-sensing phase of operation, at least as it relates to thetarget memory cell136. The YPASS control signal, for the logic circuits as depicted inFIG. 4, has a logic low level during the non-sensing phase. The output of theinverter445 applied to the gate ofpFET430, now a logic high level, will deactivatepFET430 and isolate the gate of thepass transistor225 frompotential node415. Because thenFET435 is of a type opposite thepFET430, its response to the same control signal will be opposite. As such, the output of theinverter445 applied to the gate of thenFET435 will activatenFET435, thus coupling the gate of thepass transistor225 topotential node420. The output of theNAND gate440 will also have a logic high level, thus deactivatingpFET425 and isolating the gate of thepass transistor225 frompotential node410. Isolating the gate of thepass transistor225 from the supply potentials and coupling it to the ground potential will thus provide a control signal having a logic low level, resulting in deactivation of the n-channel pass transistor225 and isolation of thetarget memory cell136 from thesensing device205.

Using the logic circuits as depicted inFIG. 4, the YPASS control signal and the FILTER_ON control signal each have a logic high level during the first sensing phase. In this manner, the gate of thepass transistor225 is coupled to thepotential node410 to receive an unfiltered supply potential. The gate of thepass transistor225 is concurrently isolated from thepotential node420. In this configuration, the gate of thepass transistor225 is also coupled to thepotential node415 through a filtered path. The filtered path of thedriver circuit400 includes the path from thepotential node415 to thenode235 through thefilter455 and the selectivecoupling device pFET430.Filter455 serves to reduce noise, or undesirable fluctuations, in the supply potential received atpotential node415.Filter455 may be a lowpass RC filter, having aresistive component460 and acapacitive component465, to reduce high-frequency noise. While it is not necessary to concurrently couple the gate of thepass transistor225 to bothpotential nodes410 and415 during the first sensing phase, there are advantages to doing so. By concurrently coupling the gate of thepass transistor225 to bothpotential nodes410 and415 during the first sensing phase, thecapacitive component465 in the filtered path is quickly charged. Subsequent transition to the second sensing phase, as described below, will not risk loss of the activating gate bias onpass transistor225 due to the RC time constant of an uncharged filter.

During the second sensing phase, thememory device101 senses the programmed state of thetarget memory cell136 and thus its data value. To improve operating margins of thesensing device205, especially in low-voltage applications, it is desirable to reduce noise in the supply potential provided to the gate of thepass transistor225. Accordingly, the gate of thepass transistor225 should be coupled to thepotential node415 through the filtered path and isolated from thepotential node410.

Using the logic circuits as depicted inFIG. 4, the YPASS control signal remains at the logic high level and the FILTER_ON control signal transitions to a logic low level during the second sensing phase. In this manner, the gate of thepass transistor225 is isolated from thepotential nodes410 and420, but is coupled to thepotential node415 through the filtered path. The gate of thepass transistor225 thus receives a filtered supply potential as its control signal, resulting in improved noise immunity of the sensing operation. As shown inFIG. 4, the outputs of theNAND gate440 and theinverter445 may be buffered, such as by the pairs ofinverters460/465 and470/475, respectively.

After latching the detected data value, the memory device may return to the non-sensing phase of operation. Timing of the various phases of operation is controlled by the command control circuit of the memory device. The various control signals, such as FILTER_ON and YPASS, are generated by the command control circuit for control of access to the memory array as described herein.

For improved performance of thesensing device205, it is important that the timing of the bit line precharging be controlled tightly. The precharging should be sufficient to completely charge the parasitics of the bit lines to provide consistent sensing operations. An insufficient precharge may lead to an erroneous indication of an erased state of the target memory cell. However, for improved access speed, this precharging should not be any longer than necessary to charge these parasitics. Timing of an operation phase such as the precharging phase is generally controlled by a timing signal or pulse. Pulse generators for generating a timing pulse often provide compensation for changes in supply voltage, but may exhibit unacceptable variation as a result of changes in ambient temperature. U.S. patent application Ser. No. 10/032,277 claiming priority to Italian Patent Application RM2000A000700) entitled “Voltage and Temperature Compensated Pulse Generator,” which is commonly assigned, describes methods and circuits for generating a timing pulse including compensation for supply voltage and ambient temperature. An example of one such circuit and method for generating such a timing pulse will be described with reference toFIG. 5.

FIG. 5 is a schematic of apulse generator500 having acomparator510, aramp signal generator550 and an adaptivethreshold signal generator570. Theramp signal generator550 is often an RC circuit. Thecomparator510 provides an output signal in response to a difference between a potential level of a threshold signal generated by thethreshold signal generator570 and a potential level of a ramp signal generated by theramp signal generator550.

The adaptivethreshold signal generator570 ofFIG. 5 includes an upperresistive component576 coupled between a firstpotential node572 and anoutput node580. The upperresistive component576 ofFIG. 5 includes aresistive element582. As is well known in the art, resistive elements or resistors may be configured in a variety of parallel configurations, series configuration, or combination parallel/series configurations to produce equivalent resistive elements. Accordingly, for additional embodiments, theresistive element582 may represent two or more resistive elements in a variety of parallel, series, or parallel/series configurations. For one embodiment, theresistive element582 contains one or more semiconductor resistors and the upperresistive component576 has a positive temperature coefficient of resistivity.

The upperresistive component576 has an effective temperature coefficient of resistivity that is the composite of the temperature coefficients of resistivity of all of its resistive elements. For the embodiment depicted inFIG. 5, the effective temperature coefficient of resistivity of the upperresistive component576 equals the temperature coefficient of resistivity of theresistive element582.

The adaptivethreshold signal generator570 ofFIG. 5 further includes a lowerresistive component578 coupled between a secondpotential node574 and theoutput node580. The firstpotential node572 is coupled to receive a first potential and the secondpotential node574 is coupled to receive a second potential, with the first potential higher than the second potential. For one embodiment, the firstpotential node572 is coupled to receive a supply potential, such as Vcc, and the secondpotential node574 is coupled to receive a ground potential, such as Vss.

The lowerresistive component578 has an effective temperature coefficient of resistivity that is lower than the effective temperature coefficient of resistivity of the upperresistive component576. To accomplish this, the lowerresistive component578 includes at least one resistive element having a temperature coefficient of resistivity lower than the effective temperature coefficient of resistivity of the upperresistive component576. For one embodiment, the lowerresistive component578 includes at least one resistive element having a temperature coefficient of resistivity lower than the lowest temperature coefficient of resistivity of any resistive element of the upperresistive component576. For another embodiment, the lowerresistive component578 includes at least one resistive element having a negative temperature coefficient of resistivity.

For the embodiment depicted inFIG. 5, the lowerresistive component578 includes, as a resistive element, a bipolar junction transistor (BJT)586 having its base coupled to its collector. TheBJT586 has a negative temperature coefficient of resistivity. As an example, the base-emitter bias, Vbe, of an npn BJT may change by −0.2 mV/° C. in this configuration. Additional resistive elements, such asresistive elements584 and588 can be used to adjust the nominal resistance level of the lowerresistive component578 to produce a desired resistance ratio between the upperresistive component576 and the lowerresistive component578, and thus to produce a desired threshold signal for a given set of first and second potentials. For the embodiment depicted inFIG. 5,resistive element584 is coupled in parallel withBJT586 whileresistive element588 is coupled in series withBJT586. For one embodiment, theresistive elements584 and588 each contain semiconductor resistors, each having a positive temperature coefficient of resistivity. As with theresistive element582,resistive elements584 and588 may each represent one or more resistive elements in a variety of parallel configurations, series configurations, or combination parallel/series configurations.

Increasing resistance levels in the RC circuit of the ramp generator will lead to a decreasing slope of the ramp signal. If the threshold signal remains substantially constant, a decreasing slope of the ramp signal will lead to a larger pulse width from the comparator as it will take longer for the ramp signal to equal or exceed the threshold signal. To compensate for this undesirable temperature variation in the ramp signal generator, thethreshold signal generator570 includes a lowerresistive component578 having an effective temperature coefficient of resistivity that is lower than an effective temperature coefficient of the upperresistive component576. In the voltage divider configuration, this difference in effective temperature coefficients of resistivity results in a decreasing threshold signal in response to increasing ambient temperatures, thus compensating for the decreasing slope of the ramp signal and leading to a more consistent timing pulse over a range of operating conditions.

CONCLUSION

Single-ended sensing devices for sensing a programmed state of a floating-gate memory cell have been described for use in low-voltage memory devices. Sensing devices in accordance with the various embodiments include an input node selectively coupled to the floating-gate memory cell. Such sensing devices include a precharging path for applying a precharge potential to the input node of the sensing device for precharging bit lines prior to sensing the programmed state of the floating-gate memory cell. Such sensing devices further include a reference current path for applying a reference current to the input node of the sensing device. Such sensing devices still further include a sense inverter having an input coupled to the input node of the sensing device and an output for providing an output signal indicative of the programmed state of the floating-gate memory cell. The reference current is applied to the input node of the sensing device during sensing of the programmed state of the floating-gate memory cell, thus compensating for residual current and improving immunity to erroneous indications of an erased floating-gate memory cell.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.

Claims (28)

1. A sensing device for sensing a programmed state of a non-volatile memory cell, wherein the sensing device has an input node selectively coupled to the non-volatile memory cell, the sensing device comprising:

means for precharging the input node of the sensing device to a precharge potential while the input node is coupled to the non-volatile memory cell;

means for applying a reference current to the input node of the sensing device while sensing the programmed state of the non-volatile memory cell; and

means for sensing a current flow through the non-volatile memory cell.

2. The sensing device ofclaim 1, further comprising:

means for generating a control signal that varies proportionately with changes in ambient temperature, wherein the means for applying the reference current is responsive to the control signal.

3. The sensing device ofclaim 2, wherein the means for applying the reference current responds inversely proportional to the control signal.

4. The sensing device ofclaim 2, wherein the means for applying the reference current is adapted to generate a reference current that is greater than an expected current flow through the non-volatile memory cell in a first programmed state and less than an expected current flow through the non-volatile memory cell in a second programmed state.

5. The sensing device ofclaim 4, wherein the means for applying the reference current is adapted to generate a reference current that is less than one-half the expected current flow through the non-volatile memory cell in the second programmed state.

6. The sensing device ofclaim 2, wherein the means for applying the reference current is adapted to generate a reference current that is greater than an expected current flow through the non-volatile memory cell in a first programmed state and approximately one order of magnitude less than an expected current flow through the non-volatile memory cell in a second programmed state.

7. The sensing device ofclaim 1, wherein the means for applying the reference current is fabricated without trimming a dummy memory cell.

8. A memory device, comprising:

an array of non-volatile memory cells; and

a single-ended sensing device for sensing a programmed state of a non-volatile memory cell of the array of non-volatile memory cells, wherein the sensing device has an input node selectively coupled to a non-volatile memory cell of the array of non-volatile memory cells, the sensing device further comprising:

a precharging path coupled between a first potential node and the input node of the sensing device, wherein the first potential node is coupled to receive a precharge potential;

a reference current path coupled between a second potential node and the input node of the sensing device, wherein the second potential node is coupled to receive a second potential for providing a reference current that varies inversely to changes to ambient temperature to the input node of the sensing device; and

a sense inverter having an input coupled to the input node of the sensing device and an output for providing an output signal responsive to a potential level of the input node of the sensing device relative to a threshold point, wherein the output signal is indicative of the programmed state of the non-volatile memory cell.

9. The memory device ofclaim 8, wherein the precharging path further comprises a field-effect transistor coupled between the first potential node and the input node of the sensing device.

10. The memory device ofclaim 8, wherein the reference current path further comprises a field-effect transistor coupled between the second potential node and the input node of the sensing device and having a gate coupled to receive a reference current control signal.

11. The memory device ofclaim 10, wherein the field-effect transistor of the reference current path is a p-channel field-effect transistor.

12. The memory device ofclaim 11, further comprising a reference current control signal generator having an output node coupled to the gate of the p-channel field-effect transistor of the reference current path for providing the reference current control signal, the reference current control signal generator comprising:

a diode coupled between a third potential node and the output node of the reference current control signal generator, wherein the third potential node is coupled to receive a third potential; and

a resistive component coupled between a fourth potential node and the output node of the reference current control signal generator, wherein the fourth potential node is coupled to receive a fourth potential.

13. The memory device ofclaim 12, wherein the diode further comprises a plurality of diode-connected field-effect transistors coupled in parallel between the fourth potential node and the output node of the reference current control signal generator.

14. The memory device ofclaim 13, wherein each field-effect transistor of the plurality of diode-connected field-effect transistors is a p-channel field-effect transistor sized to be substantially identical to the p-channel field-effect transistor of the reference current path.

15. The memory device ofclaim 12, wherein the reference current control signal generator further comprises:

at least one field-effect transistor coupled between the resistive component and the output node of the reference current control signal generator.

16. The memory device ofclaim 12, wherein the resistive component further comprises:

a first resistive element coupled between the fourth potential node and the output node of the reference current control signal generator;

a first field-effect transistor coupled between the first resistive element and the fourth potential node and responsive to a first control signal;

a second resistive element coupled in parallel with the first resistive element between the fourth potential node and the output node of the reference current control signal generator; and

a second field-effect transistor coupled between the second resistive element and the fourth potential node and responsive to a second control signal different from the first control signal.

17. The memory device ofclaim 16, wherein the resistive component further comprises:

at least one additional resistive element coupled in parallel with the first resistive element between the fourth potential node and the output node of the reference current control signal generator; and

at least one additional field-effect transistor, each additional field-effect transistor coupled between one of the additional resistive elements and the fourth potential node and each additional field-effect transistor responsive to an additional control signal different from the first control signal.

18. The memory device ofclaim 12, wherein the resistive component comprises a plurality of resistive elements selectively coupled in parallel between the fourth potential node and the output node of the reference current control signal generator.

19. An electronic system, comprising:

a processor; and

a memory device coupled to the processor, wherein the memory device has an array of non-volatile memory cells and a single-ended sensing device for sensing a programmed state of a non-volatile memory cell of the array of non-volatile memory cells, wherein the sensing device has an input node selectively coupled to a non-volatile memory cell of the array of non-volatile memory cells and further comprises:

a precharging path coupled between a first potential node and the input node of the sensing device, wherein the first potential node is coupled to receive a precharge potential;

a reference current path coupled between a second potential node and the input node of the sensing device, wherein the second potential node is coupled to receive a second potential for providing a reference current that varies inversely to changes in ambient temperature to the input node of the sensing device; and

a sense inverter having an input coupled to the input node of the sensing device and an output for providing an output signal responsive to a potential level of the input node of the sensing device relative to a threshold point, wherein the output signal is indicative of the programmed state of the non-volatile memory cell.

20. The electronic system ofclaim 19, wherein the precharging path of the sensing device further comprises a field-effect transistor coupled between the first potential node and the input node of the sensing device.

21. The electronic system ofclaim 19, wherein the reference current path of the sensing device further comprises a p-channel field-effect transistor coupled between the second potential node and the input node of the sensing device and having a gate coupled to receive a reference current control signal.

22. The electronic system ofclaim 21, wherein the sensing device further comprises a reference current control signal generator having an output node coupled to the gate of the field-effect transistor of the reference current path for providing the reference current control signal, wherein the reference current control signal generator comprises:

a diode coupled between a third potential node and the output node of the reference current control signal generator, wherein the third potential node is coupled to receive a third potential; and

a resistive component coupled between a fourth potential node and the output node of the reference current control signal generator, wherein the fourth potential node is coupled to receive a fourth potential.

23. The electronic system ofclaim 22, wherein the diode of the reference current control signal generator further comprises a plurality of diode-connected field-effect transistors coupled in parallel between the fourth potential node and the output node of the reference current control signal generator.

24. The electronic system ofclaim 23, wherein each field-effect transistor of the plurality of diode-connected field-effect transistors is a p-channel field-effect transistor sized to be substantially identical to the p-channel field-effect transistor of the reference current path.

25. The electronic system ofclaim 22, wherein the reference current control signal generator further comprises:

at least one field-effect transistor coupled between the resistive component and the output node of the reference current control signal generator.

26. The electronic system ofclaim 22, wherein the resistive component of the reference current control signal generator further comprises:

a first resistive element coupled between the fourth potential node and the output node of the reference current control signal generator;

a first field-effect transistor coupled between the first resistive element and the fourth potential node and responsive to a first control signal;

a second resistive element coupled in parallel with the first resistive element between the fourth potential node and the output node of the reference current control signal generator; and

a second field-effect transistor coupled between the second resistive element and the fourth potential node and responsive to a second control signal different from the first control signal.

27. The electronic system ofclaim 26, wherein the resistive component of the reference current control signal generator further comprises:

at least one additional resistive element coupled in parallel with the first resistive element between the fourth potential node and the output node of the reference current control signal generator; and

at least one additional field-effect transistor, each additional field-effect transistor coupled between one of the additional resistive elements and the fourth potential node and each additional field-effect transistor responsive to an additional control signal different from the first control signal.

28. The electronic system ofclaim 22, wherein the resistive component of the reference current control signal generator comprises a plurality of resistive elements selectively coupled in parallel between the fourth potential node and the output node of the reference current control signal generator.

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