US7091124B2 - Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices - Google Patents

Abstract

Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes forming a bond-pad on a die having an integrated circuit, the bond-pad being electrically coupled to the integrated circuit. A conductive line is then formed on the die, the conductive line having a first end portion attached to the bond-pad and a second end portion spaced apart from the bond-pad. The method can further include forming a via or passage through the die, the bond-pad, and the first end portion of the conductive line, and depositing an electrically conductive material in at least a portion of the passage to form a conductive interconnect extending at least generally through the microelectronic device.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application is related to U.S. patent application Ser. No. 10/733,226 entitled MICROELECTRONIC DEVICES AND METHODS FOR FILLING VIAS IN MICROELECTRONIC DEVICES, filed concurrently herewith and incorporated herein in its entirety by reference.

TECHNICAL FIELD

The following disclosure relates generally to microelectronic devices and methods for packaging microelectronic devices and, more particularly, to methods for forming vias in microelectronic workpieces.

BACKGROUND

Conventional die-level packaged microelectronic devices can include a microelectronic die, an interposer substrate or lead frame attached to the die, and a moulded casing around the die. The die generally includes an integrated circuit and a plurality of bond-pads coupled to the integrated circuit. The bond-pads are typically coupled to terminals on the interposer substrate or lead frame and serve as external electrical contacts on the die through which supply voltage, signals, etc., are transmitted to and from the integrated circuit. In addition to the terminals, the interposer substrate can also include ball-pads coupled to the terminals by conductive traces supported in a dielectric material. Solder balls can be attached to the ball-pads in one-to-one correspondence to define a “ball-grid array.” Packaged microelectronic devices with ball-grid arrays are generally higher grade packages having lower profiles and higher pin counts than conventional packages using lead frames.

One process for packaging a die with a ball-grid array at the die level includes (a) forming a plurality of dies on a semiconductor wafer, (b) cutting the wafer to separate or singulate the dies, (c) attaching individual dies to an interposer substrate, (d) wire-bonding the bond-pads of the dies to the terminals of the interposer substrate, and (e) encapsulating the dies with a suitable moulding compound. Mounting individual dies to interposer substrates or lead frames in the foregoing manner can be a time-consuming and expensive process. In addition, forming robust wire-bonds that can withstand the forces involved in moulding processes becomes more difficult as the demand for higher pin counts and smaller packages increases. Moreover, the process of attaching individual dies to interposer substrates or lead frames may damage the bare dies. These difficulties have made the packaging process a significant factor in the production of microelectronic devices.

Another process for packaging microelectronic devices is wafer-level packaging. In this process, a plurality of microelectronic dies are formed on a wafer, and then a redistribution layer is formed over the dies. The redistribution layer can include a dielectric layer and a plurality of exposed ball-pads forming arrays on the dielectric layer. Each ball-pad array is typically arranged over a corresponding die, and the ball-pads in each array are coupled to corresponding bond-pads of the die by conductive traces extending through the dielectric layer. After forming the redistribution layer on the wafer, discrete masses of solder paste are deposited onto the individual ball-pads. The solder paste is then reflowed to form small solder balls or “solder bumps” on the ball-pads. After forming the solder balls, the wafer is singulated to separate the individual microelectronic devices from each other.

Wafer-level packaging is a promising development for increasing efficiency and reducing the cost of microelectronic devices. By “pre-packaging” individual dies with a redistribution layer before cutting the wafers to singulate the dies, sophisticated semiconductor processing techniques can be used to form smaller arrays of solder balls. Additionally, wafer-level packaging is an efficient process that simultaneously packages a plurality of dies, thereby reducing costs and increasing throughput.

Packaged microelectronic devices such as those described above are used in cellphones, pagers, personal digital assistants, computers, and many other electronic products. To meet the demand for smaller electronic products, there is a continuing drive to increase the performance of packaged microelectronic devices, while at the same time reducing the height and the surface area or “footprint” of such devices on printed circuit boards. Reducing the size of microelectronic devices, however, becomes more difficult as the performance increases because higher performance typically means more integrated circuitry and bond-pads. This results in larger ball-grid arrays and thus larger footprints. One technique for increasing the component density of microelectronic devices within a given footprint is to stack one device on top of another.

FIG. 1 schematically illustrates a firstmicroelectronic device10 attached to a secondmicroelectronic device20 in a wire-bonded, stacked-die arrangement. The firstmicroelectronic device10 includes a die12 having an integratedcircuit14 electrically coupled to a series of bond-pads16. Aredistribution layer18 electrically couples a plurality offirst solder balls11 to corresponding bond-pads16. The secondmicroelectronic device20 similarly includes a die22 having an integratedcircuit24 electrically coupled to a series of bond-pads26. Aredistribution layer28 electrically couples a plurality ofsecond solder balls21 to corresponding bond-pads26. Wire-bonds13 extending from thefirst solder balls11 to thesecond solder balls21 electrically couple the firstmicroelectronic device10 to the secondmicroelectronic device20.

Thesecond solder balls21 on the secondmicroelectronic device20 are positioned outboard of the firstmicroelectronic device10 to facilitate installation of the wire-bonds13. As mentioned above, such installation can be a complex and/or expensive process. Forming the wire-bonds13, for example, is not only difficult because it requires individual wires between each pair of solder balls, but it may not be feasible to form wire-bonds for the high-density, fine-pitch arrays of some high performance devices. In addition, positioning thesecond solder balls21 outboard of the firstmicroelectronic device10 to accommodate the wire-bonds13 undesirably increases the footprint of the stacked-die arrangement.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates a first microelectronic device attached to a second microelectronic device in a stacked-die arrangement in accordance with the prior art.

FIG. 2 is a cut-away isometric view of a microfeature workpiece configured in accordance with an embodiment of the invention.

FIGS. 3A–3G are schematic cross-sectional views illustrating various stages in a method of forming a conductive interconnect in a microelectronic device in accordance with an embodiment of the invention.

FIG. 4 is a schematic cross-sectional view illustrating a stage in a method of forming a conductive interconnect in a microelectronic device in accordance with another embodiment of the invention.

FIGS. 5A–5C are schematic cross-sectional views illustrating various stages in a method of forming a conductive interconnect in a microelectronic device in accordance with a further embodiment of the invention.

FIG. 6 is a schematic side cross-sectional view of a microelectronic device set configured in accordance with an embodiment of the invention.

FIG. 7 is a schematic side cross-sectional view of a microelectronic device set configured in accordance with another embodiment of the invention.

DETAILED DESCRIPTION

A. Overview

The following disclosure describes several embodiments of microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias in dies and other substrates. One aspect of the invention is directed toward a method of manufacturing a microelectronic device having a die with an integrated circuit. In one embodiment, the method includes forming a bond-pad on the die electrically coupled to the integrated circuit, and forming a redistribution layer on the die. The redistribution layer can include a conductive line having a first end portion attached to the bond-pad and a second end portion spaced apart from the bond-pad. The method can further include forming a via or passage through the die, the bond-pad, and the first end portion of the conductive line. An electrically conductive material can then be deposited into at least a portion of the passage to provide a conductive interconnect extending through the die that is electrically coupled to the bond-pad and the conductive line.

In one aspect of this embodiment, the method can further include cleaning the passage and applying a passivation layer to at least a portion of the passage before depositing the electrically conductive material into the passage. In one embodiment, the passivation layer can at least generally insulate the die from the electrically conductive material filling the passage. In another aspect of this embodiment, the method can further include applying a TiCL₄TiN layer to at least a portion of the passage, and applying a Ni layer over at least a portion of the TiCL₄TiN layer before depositing the electrically conductive material into the passage.

Another aspect of the invention is directed toward a set of microelectronic devices. In one embodiment, the microelectronic device set includes a first microelectronic device stacked on a second microelectronic device in a stacked-die arrangement. The first microelectronic device can include a first die with a first integrated circuit, a first bond-pad electrically coupled to the first integrated circuit, and a passage through the first die and the first bond-pad. The first die also includes a metal interconnect in the passage and coupled to the first bond-pad to form a conductive link extending at least partially through the first microelectronic device. The second microelectronic device can include a second die with a second integrated circuit and a second bond-pad electrically coupled to the second integrated circuit. The second bond-pad can be electrically coupled to the conductive link of the first microelectronic device.

Many specific details of the present invention are described below with reference to semiconductor devices. The term “microfeature workpiece,” however, as used throughout this disclosure includes substrates upon which and/or in which microelectronic devices, micromechanical devices, data storage elements, read/write components, and other features are fabricated. For example, such microelectronic workpieces can include semiconductor wafers (e.g., silicon or gallium arsenide wafers), glass substrates, insulated substrates, and many other types of substrates. The feature signs in microfeature workpieces can include very small features of 0.11 μm or less, but larger features are also included on microfeature workpieces.

Specific details of several embodiments of the invention are described below with reference to microelectronic dies and other microelectronic devices in order to provide a thorough understanding of such embodiments. Other details describing well-known structures often associated with microelectronic devices are not set forth in the following description to avoid unnecessarily obscuring the description of the various embodiments. Persons of ordinary skill in the art will understand, however, that the invention may have other embodiments with additional elements or without several of the elements shown and described below with reference toFIGS. 2–7.

In the Figures, identical reference numbers identify identical or at least generally similar elements. To facilitate the discussion of any particular element, the most significant digit or digits of any reference number refer to the Figure in which that element is first introduced. For example, element210 is first introduced and discussed with reference toFIG. 2.

B. Embodiments of Microfeature Workpieces

FIG. 2 is a cut-away isometric view of a wafer ormicrofeature workpiece200 in accordance with an embodiment of the invention. In one aspect of this embodiment, themicrofeature workpiece200 includes afront side201, aback side202, and a plurality of microelectronic devices210 (identified individually asmicroelectronic devices210a–f). Each microelectronic device210 can include amicroelectronic die212 and a redistribution layer218 (RDL218) formed on thedie212. Each die212 can include an integrated circuit214 (shown schematically), afirst surface241, asecond surface242, and a plurality of metallic and/or conductive bond-pads216 electrically coupled to theintegrated circuit214. TheRDL218 can include a plurality of metallic and/orconductive lines230 that each have afirst end portion231 electrically coupled to a corresponding bond-pad216, asecond end portion232 spaced outwardly from thefirst end portion231, and a trace between the first andsecond end portions231 and232. As described in greater detail below, thesecond end portions232 in one embodiment can have ball-pads configured to receive solder balls for electrically connecting the microelectronic devices210 to other devices.

In the embodiment illustrated inFIG. 2, the processing of the microelectronic devices210 has not been completed. As described below with reference toFIGS. 3A–6, additional processing can be carried out on themicrofeature workpiece200 to configure or package the individual microelectronic devices210 for use in an electronic device or product. After this additional processing is complete, themicrofeature workpiece200 is cut along lines A₁—A₁to singulate the microelectronic devices210.

FIGS. 3A–3G illustrate various stages in a method of forming a conductive interconnect in themicroelectronic device210bin accordance with an embodiment of the invention.FIG. 3A, more specifically, is a schematic side cross-sectional view of themicrofeature workpiece200 taken substantially alongline3A—3A inFIG. 2. In one aspect of this embodiment, theRDL218 includes afirst passivation layer350 applied to thesecond surface242 of thedie212, and a firstdielectric layer351 applied over thefirst passivation layer350. Thefirst dielectric layer351 can be removed around the bond-pad216 by etching or another known process to expose the bond-pad216. Exposing the bond-pad216 in this manner allows thefist end portion231 of theconductive line230 to contact the bond-pad216 when theconductive line230 is formed over thefirst dielectric layer351.

After forming theconductive line230, afirst hole360 is formed through thefirst end portion231 of theconductive line230 and the bond-pad216. In one embodiment, thefirst hole360 can be formed by an etching process. In other embodiments, thefirst hole360 can be formed using other suitable methods. Additionally, asecond dielectric layer352 is applied over themicrofeature workpiece200 to cover theconductive line230 and fill thefirst hole360.

In one embodiment, the first and seconddielectric layers351,352 include a polyimide material. In other embodiments, the first and seconddielectric layers351,352 include other nonconductive and/or insulative materials. Thefirst passivation layer350 and/or one or more subsequent passivation layers can include a low temperature chemical vapor deposition (low temperature CVD) material, such as tetraethylorthosilicate (TEOS). In other embodiments, one or more of the passivation layers on themicrofeature workpiece200 can include parylene and/or other suitable materials, such as silicon oxide (SiO_x) or silicon nitride (Si₃N₄). The foregoing list of passivation and dielectric material options is not exhaustive. Accordingly, in other embodiments, it is expected that other suitable materials and processes can be used to form one or more of the layers discussed herein. In addition, it is further expected that, in yet other embodiments, one or more of the layers described above with reference toFIG. 3A, or described below with reference to subsequent Figures, may be omitted.

FIG. 3A illustrates one method for providing an RDL on a die in accordance with the present invention. In other embodiments, other methods resulting in other RDL/die configurations can be used. Accordingly, as those of ordinary skill in the art will recognize, the methods described in detail below for forming vias in microelectronic devices are not limited to the particular RDL/die configuration illustrated inFIG. 3A.

FIGS. 3B–3G are schematic side cross-sectional views similar toFIG. 3A showing themicrofeature workpiece200 in subsequent stages of forming the interconnect.FIG. 3B, for example, is a schematic side cross-sectional view of themicrofeature workpiece200 after asecond hole361 and athird hole362 have been formed through thesecond dielectric layer352. In one aspect of this embodiment, forming thesecond hole361 includes removing thesecond dielectric layer352 from thefirst hole360, thereby exposing the bond-pad216 and thefirst end portion231 of theconductive line230. Thethird hole362 is formed through thesecond dielectric layer352 to expose part of thesecond end portion232 of theconductive line230. In one aspect of this embodiment, the second andthird holes361,362 can be formed by dry-etching or by other suitable methods known to those of skill in the semiconductor processing art.

FIG. 3C illustrates themicrofeature workpiece200 ofFIG. 3B after application of asecond passivation layer354 and athird passivation layer356. Thesecond passivation layer354 is applied over thesecond dielectric layer352 such that it is deposited into thefirst hole360, thesecond hole361, and thethird hole362. Thethird passivation layer356 is applied to thefirst surface241 of thedie212. In one aspect of this embodiment, the second and third passivation layers354,356 can include parylene. In other embodiments, thesecond passivation layer354 can include other materials, such as an oxide.

Referring next toFIG. 3D, after application of the second and third passivation layers354,356, a laser363 (shown schematically) cuts a passage or through-hole364 through themicroelectronic device210b.In one aspect of this embodiment, the through-hole364 extends at least through thedie212, the bond-pad216, and thefirst end portion231 of theconductive line230. For example, in the illustrated embodiment, the through-hole364 extends entirely through thethird passivation layer356, thedie212, and thesecond passivation layer354. Thelaser363 generally cuts from theback side202 of themicrofeature workpiece200 toward thefront side201, but it can conceivably cut from thefront side201 toward theback side202. Further, thelaser363 can be aligned with respect to the bond-pad216 using a pattern recognition system or other known alignment system. In other embodiments, the through-hole364 can be formed using other suitable methods known to those of skill in the art. For example, in another embodiment, it is expected that the through-hole364 can be formed by a suitable etching or drilling process.

After forming the through-hole364, it is cleaned to remove ablation (i.e., slag) and/or other undesirable byproducts resulting from the laser cut. In one embodiment, the through-hole364 is cleaned using a wet-etch process. In this embodiment, the portion of thesecond passivation layer354 remaining in thefirst hole360 protects the bond-pad216 and thefirst end portion231 of theconductive line230 from the wet-etch chemistry used to clean the slag from the die area of through-hole364. This feature allows a single cleaning process/chemistry to clean the slag from the via for the interconnect without having to use a second cleaning process to clean residue on the bond-pad216 andfirst end portion231. In other embodiments, the through-hole364 can be cleaned using other methods. For example, in some embodiments (one of which is described in greater detail below), cleaning agents that do not attack the metal of the bond-pad216 can be used to clean the through-hole364 so that thesecond passivation layer354 is not needed to protect the bond-pad216. One such cleaning agent may include 6% TMAH: propylene glycol for removing laser ablation. Alternatively, in certain other embodiments, the through-hole364 can remain uncleaned after formation.

Referring toFIG. 3E, after cleaning the through-hole364, afourth passivation layer358 is applied to themicrofeature workpiece200 to at least cover the portion of the die212 exposed by the through-hole364. Thefourth passivation layer358 can be applied in a number of different ways. For example, in the illustrated embodiment, the second and third passivation layers354,356 (FIG. 3D) are removed from themicrofeature workpiece200, and thefourth passivation layer358 is then applied to the entire workpiece so that it covers the exposed portions of thedie212, the bond-pad216, theconductive line230, and thesecond dielectric layer352. In one aspect of this embodiment, thefourth passivation layer358 can include a low temperature CVD oxide. In other embodiments, thefourth passivation layer358 can include other suitable materials. Thefourth passivation layer358 can insulate the die212 from electrical leakage after the through-hole364 has been filled with conductive metal (not shown) as described in greater detail below.

After application of thefourth passivation layer358, afirst metal layer371 is applied to themicrofeature workpiece200. In the illustrated embodiment, thefirst metal layer371 covers the entirefourth passivation layer358. In one aspect of this embodiment, thefirst metal layer371 can include TiCL₄TiN. In other embodiments, thefirst metal layer371 can include other suitable materials known to those of skill in the art. For ease of reference, the passage formed by the through-hole364, thefirst hole360, and thesecond hole361 is referred to herein as a via orpassage374 extending through themicrofeature workpiece200.

Referring next toFIG. 3F, thefirst metal layer371 is removed from the horizontal and diagonal surfaces of themicrofeature workpiece200. Thefourth passivation layer358 is similarly removed from these surfaces, except that it is left on thefirst surface241 of thedie212. In one embodiment, thefirst metal layer371 and thefourth passivation layer358 can be removed from these surfaces by a suitable etching process, such as a “dry etch” or “spacer etch” process that only removes material from horizontal surfaces and surfaces having horizontal components. In other embodiments, other processes can be used to remove these layers from the designated surfaces.

After thefirst metal layer371 and thefourth passivation layer358 have been removed from the horizontal and diagonal surfaces of themicrofeature workpiece200 as described above, asecond metal layer372 is applied to thefirst metal layer371. Thesecond metal layer372 can act as a wetting agent to facilitate flowing and/or adhesion of subsequent metals in thepassage374. In one embodiment, for example, thesecond metal layer372 can include Ni that is applied over the TiCL₄TiN of thefirst metal layer371 in an electroless plating operation. In this embodiment, when the TiCL₄TiN is activated by an HF:Pd wet dip, it provides nucleation for the Ni during the plating process. In other embodiments, thepassage374 can be coated with other suitable materials using other methods or, alternatively, one or more of the first and second metal layers371,372 may be omitted.

Referring next toFIG. 3G, thepassage374 receives ametal fill376 to form aconductive interconnect377 extending through themicroelectronic device210b.In one aspect of this embodiment, the metal fill376 can include solder or electroplating material. In other embodiments, other electrically conductive materials can be used to fill thepassage374. After filling thepassage374, afirst cap381 can be formed before depositing thefill376 in thepassage374, or in another embodiment thecap381 can be applied to theinterconnect377 so that it makes intimate contact with thefirst end portion231 of theconductive line230. Asecond cap382 can be applied to thesecond end portion232 of theconductive line230. In one embodiment, the first andsecond caps381,382 can include Ni applied in an electroless plating process. In other embodiments, the first andsecond caps381,382 can include other wetting agents and/or other materials. Alternatively, thefirst cap381 and thesecond cap382 can be omitted. In another aspect of this embodiment, asolder ball384 is attached to thesecond cap382 to provide an external connection to other electronic devices in a subsequent assembly operation.

In addition to requiring only a single cleaning process for the through-hole364, another feature of aspects of the embodiments described above with reference toFIGS. 3A–3G is that thepassage374 extends through theentire microfeature workpiece200. One advantage of this feature is that it makes thepassage374 easier to clean and fill than would otherwise be the case if the passage were “blind” (i.e., a passage that extends only partially through the workpiece). For example, in certain applications where thepassage374 has an aspect ratio of 25–30:1 or greater, a blind passage is difficult to fill with metallic materials using known physical vapor deposition (PVD), atomic level deposition (ALD), or plating processes. Thepassage374 mitigates this problem.

FIG. 4 illustrates a stage in a method of forming a conductive interconnect in amicroelectronic device410 in accordance with another embodiment of the invention. In one aspect of this embodiment, the first part of this method is at least generally similar to the steps described above with reference toFIGS. 3A–3B, and results in the workpiece configuration illustrated inFIG. 3B. The second part of this method, however, differs from that described above with reference toFIGS. 3C–3G in that no passivation is deposited into thefirst hole360 before thelaser363 cuts a through-hole464 through thedie212. Instead, the through-hole464 is cut and cleaned in the absence of any protection over the exposed metal of the bond-pad216 and theconductive line230. In the absence of such protection, the cleaning agents may be limited to those chemistries that do not attack or otherwise degrade the metal of the bond-pad216 or theconductive line230. For example, in one embodiment, such cleaning agents can include tetramethylammonium hydroxide (TMAH). In other embodiments, other cleaning agents can be used to clean the through-hole464. After the through-hole464 has been suitably cleaned, themicroelectronic device410 can undergo additional packaging steps that are at least generally similar to those described above with reference toFIGS. 3E–3G to arrive at the configuration illustrated inFIG. 3G.

FIGS. 5A–5C illustrate various stages in a method of forming a conductive interconnect in amicroelectronic device510 in accordance with another embodiment of the invention. Referring first toFIG. 5A, the first part of this method can be at least generally similar to the steps described above with reference toFIGS. 3A–3D to arrive at the workpiece configuration illustrated inFIG. 3D. In a further aspect of this embodiment, however, anadditional passivation layer558 is applied to the portion of thedie212 left exposed by the through-hole364. In addition, after thepassivation layer558 has been applied, afirst metal layer571 is applied to the through-hole364 and to theback side202 of themicrofeature workpiece200. In one embodiment, thefirst metal layer571 can include TiCL₄TiN. In other embodiments, thefirst metal layer571 can include other suitable materials.

Referring next toFIG. 5B, thefirst metal layer571 is removed from theback side202 of themicrofeature workpiece200, leaving thepassivation layer558 covering this surface. Additionally, thefirst metal layer571 and the second passivation layer354 (FIG. 3D) are removed from thefront side201 of themicrofeature workpiece200 to expose thefirst hole360, thesecond hole361, and thethird hole362. The portions of thepassivation layer558 and thefirst metal layer571 in the through-hole364 remain after the other layers have been removed to insulate the die212 from electrical leakage during use. For ease of reference, the passage formed by the through-hole364, thefirst hole360, and thesecond hole361 is referred to herein as a via orpassage574 extending through themicrofeature workpiece200.

Referring next toFIG. 5C, thepassage574 receives ametal fill576 to form aconductive interconnect577 extending through themicroelectronic device510. In one aspect of this embodiment, theinterconnect577 can include solder or electroplating material. In other embodiments, other electrically conductive materials can be used to fill thepassage574. After filling thepassage574, thefirst cap381 can be applied to theinterconnect577, and thesecond cap382 can be applied to thesecond end portion232 of theconductive line230 to receive thesolder ball384.

The embodiments described above with reference toFIGS. 3A–5C include three methods forming and/or filling through-holes in microfeature workpieces that extend through bond-pads and/or associated RDLs. In other embodiments, other methods can be used to form and/or fill such through-holes. Accordingly, the present invention is not limited to the particular filling methods described above, but extends to other methods for providing a conductive material in a through-hole formed in accordance with the present invention.

FIG. 6 is a schematic side cross-sectional view of a microelectronic device set605 configured in accordance with an embodiment of the invention. In one aspect of this embodiment, the microelectronic device set605 includes a plurality of microelectronic devices610 (individually identified as a firstmicroelectronic device610a,a secondmicroelectronic device610b,and a thirdmicroelectronic device610c) interconnected in a stacked-die arrangement. The firstmicroelectronic device610acan be at least generally similar to the packagedmicroelectronic devices210band510 discussed above and illustrated inFIGS. 3G and 5C, respectively. Accordingly, the firstmicroelectronic device610acan include a plurality ofinterconnects677aextending through a die612a,corresponding bond-pads616a,and correspondingfirst end portions631 ofconductive lines630. In addition, the firstmicroelectronic device610acan further includesolder balls684 deposited onsecond end portions632 of theconductive lines630 for electrically connecting the microelectronic device set605 to other electronic devices. The second and thirdmicroelectronic devices610b–ccan similarly includeinterconnects677b–cextending through dies612b–cand bond-pads616b–c,respectively.

In another aspect of this embodiment, first solder balls686acan be used to electrically connect the firstmicroelectronic device610ato the secondmicroelectronic device610b,andsecond solder balls686bcan in turn be used to electrically connect the secondmicroelectronic device610bto the thirdmicroelectronic device610c.Asuitable adhesive690 or other compound can also be used to structurally attach the microelectronic devices610 together in the illustrated stacked-die configuration.

FIG. 7 is a schematic side cross-sectional view of a microelectronic device set705 configured in accordance with an embodiment of the invention. In one aspect of this embodiment, the microelectronic device set705 includes a plurality of microelectronic devices710 (individually identified as a first microelectronic device710aand a second microelectronic device710b) interconnected in a stacked-die arrangement. Aspects of the first microelectronic device710acan be at least generally similar to corresponding aspects of themicroelectronic devices210band510 discussed above and illustrated inFIGS. 3G and 5C, respectively. For example, the first microelectronic device710acan include a top orfirst RDL718adisposed on a first surface of a die712a,and a bottom orsecond RDL718bdisposed on a second surface of the die712a.A plurality of interconnects777aextend through the die712ainterconnecting thefirst RDL718ato thesecond RDL718b.The second microelectronic device710bsimilarly includes athird RDL718cdisposed on a surface of asecond die712b.

In another aspect of this embodiment,solder balls786 can be used to electrically connect thesecond RDL718bof the first microelectronic device710ato thethird RDL718cof the second microelectronic device710b.Additionally, asuitable adhesive790 or other compound can also be used to structurally attach the microelectronic devices710 together in the illustrated stacked-die configuration.

One feature of aspects of the embodiments illustrated inFIGS. 6 and 7 is that the respective microelectronic devices610,710 are electrically connected without the need for wire-bonds. One advantage of this feature is that the added cost and complexity of wire-bonds is avoided. A further advantage of this feature is that the footprint of the microelectronic device sets605,705 can be reduced over comparable device sets having wire-bond interconnections.

From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.

Claims (26)

1. A method of manufacturing a microelectronic device having a die with an integrated circuit, the method comprising:

forming a bond-pad on the die, wherein the bond-pad is electrically coupled to the integrated circuit;

forming a redistribution layer on the die, the redistribution layer including a conductive line having a first end portion attached to the bond-pad and a second end portion spaced apart from the bond-pad;

forming a passage through the die, the bond-pad, and the first end portion of the conductive line; and

depositing an electrically conductive material into at least a portion of the passage, wherein the electrically conductive material extends through the bond pad and contacts the bond-pad.

2. The method ofclaim 1, further comprising applying a passivation layer to at least a portion of the passage before depositing an electrically conductive material into at least a portion of the passage.

3. The method ofclaim 1, further comprising:

cleaning the passage after forming the passage through the die, the bond-pad, and the first end portion of the redistribution layer; and

applying a passivation layer to at least a portion of the passage before depositing an electrically conductive material into at least a portion of the passage.

4. The method ofclaim 1, further comprising applying a TiCL₄TiN layer to at least a portion of the passage before depositing an electrically conductive material into at least a portion of the passage.

5. The method ofclaim 1, further comprising applying a wetting agent to at least a portion of the passage before depositing an electrically conductive material into at least a portion of the passage.

6. The method ofclaim 1, further comprising applying a Ni layer to at least a portion of the passage before depositing an electrically conductive material into at least a portion of the passage.

7. The method ofclaim 1, further comprising:

applying a TiCL₄TiN layer to at least a portion of the passage; and

applying a Ni layer over at least a portion of the TiCL₄TiN layer before depositing an electrically conductive material into at least a portion of the passage.

8. The method ofclaim 1, further comprising:

applying a passivation layer to at least a portion of the passage;

applying a TiCL₄TiN layer over at least a portion of the passivation layer; and

applying a Ni layer over at least a portion of the TiCL₄TiN layer before depositing an electrically conductive material into at least a portion of the passage.

9. The method ofclaim 1 wherein forming the passage includes laser-cutting a through-hole completely through the die.

10. The method ofclaim 1 wherein the bond-pad includes a hole filled with a passivation material, and wherein forming the passage includes laser-cutting a through-hole completely through the die and the passivation material.

11. The method ofclaim 1, further comprising:

forming a hole through the first end portion of the conductive line and the bond-pad; and

filling the hole with a passivation material, wherein forming the passage through the die, the bond-pad, and the first end portion of the conductive line includes cutting a through-hole completely through the die and the passivation material.

12. The method ofclaim 1, further comprising:

etching a hole through the first end portion of the conductive line and the bond-pad; and

filling the hole with a passivation material, wherein forming the passage through the die, the bond-pad, and the first end portion of the conductive line includes laser-cutting a through-hole completely through the die and the passivation material.

13. The method ofclaim 1, further comprising forming a hole in the bond-pad before forming the passage through the die, the bond-pad, and the first end portion of the conductive line.

14. The method ofclaim 1, further comprising:

forming a hole in the bond-pad before forming the passage through the die, the bond-pad, and the first end portion of the conductive line; and

at least generally filling the first hole with a dielectric material, wherein forming the passage through the die, the bond-pad, and the first end portion of the conductive line includes forming the passage through the dielectric material.

15. A method of manufacturing a microelectronic device having a die with an integrated circuit, the method comprising:

forming a bond-pad on the die, wherein the bond-pad is electrically coupled to the integrated circuit;

forming a redistribution layer on the die, the redistribution layer including a conductive line having a first end portion attached to the bond-pad and a second end portion spaced apart from the bond-pad;

forming a passage through the die, the bond-pad, and the first end portion of the conductive line;

depositing an electrically conductive material into at least a portion of the passage, wherein the electrically conductive material extends through the bond pad;

forming a ball-pad on the second end portion of the conductive line; and

depositing a solder ball on the ball-pad.

16. A method of manufacturing a microelectronic device having a die with an integrated circuit and a bond-pad electrically coupled to the integrated circuit, the method comprising:

etching a hole through the bond-pad;

filling the hole with a passivation material;

forming a passage completely through the die and the bond-pad, wherein forming the passage through the die and the bond-pad includes laser-cutting a through-hole through the die and the passivation material; and

depositing an electrically conductive material into at least a portion of the passage, wherein the electrically conductive material contacts at least a portion of the bond-pad.

17. The method ofclaim 16 wherein the die includes a first surface and a second surface opposite to the first surface, wherein forming a bond-pad on the die includes forming a bond-pad at least proximate to the second surface, and wherein forming a passage through the die and the bond-pad includes applying a laser from the first surface of the die toward the second surface of the die to laser-cut a through-hole through the die.

18. The method ofclaim 16, further comprising applying a passivation layer to at least a portion of the passage before depositing an electrically conductive material into at least a portion of the passage.

19. The method ofclaim 16, further comprising applying a TiCL₄TiN layer to at least a portion of the passage before depositing an electrically conductive material into at least a portion of the passage.

20. The method ofclaim 16, further comprising:

applying a TiCL₄TiN layer to at least a portion of the passage; and

applying a Ni layer over at least a portion of the TiCL₄TIN layer before depositing an electrically conductive material into at least a portion of the passage.

21. A method of forming a conductive interconnect in a microfeature workpiece having a die, the die having an integrated circuit and a bond-pad coupled to the integrated circuit, the method comprising:

forming a conductive line electrically coupled to the bond-pad;

forming a hole in the bond-pad;

forming a via completely through the die in alignment with the hole in the bond-pad, wherein the via and the hole define a passage extending completely through the die, the bond-pad, and a portion of the conductive line; and

depositing an electrically conductive material into at least a portion of the passage, wherein the electrically conductive material contacts at least a portion of the bond-pad.

22. The method ofclaim 21 further comprising insulating the die from the electrically conductive material in the passage.

23. The method ofclaim 21, further comprising applying an insulating layer to the die proximate to the passage to insulate the die from the electrically conductive material in the passage.

24. The method ofclaim 21, further comprising filling the hole in the bond-pad with a material, wherein forming a passage through the die and the bond-pad includes forming a passage through the die and the material filling the hole in the bond-pad.

25. The method ofclaim 21, further comprising filling the hole in the bond-pad with a passivation material, wherein forming a passage through the die and the bond-pad includes forming a passage through the die and the passivation material filling the hole in the bond-pad.

26. The method ofclaim 21 wherein forming a hole in the bond-pad includes forming a first hole having a first diameter, and wherein forming the passage includes laser-cutting a through-hole having a second diameter, the second diameter being less than the first diameter.

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