US6707715B2 - Reference generator circuit and method for nonvolatile memory devices - Google Patents

Abstract

Reference generator circuitry for providing a reference to sense amplifiers in a flash memory device. The circuitry includes a reference current generator for generating a reference current for use by the sense amplifier circuits. A current buffer circuit in the flash memory device mirrors the reference current and applies a plurality of mirrored reference currents to the reference inputs of the sense amplifiers. A startup circuit is utilized in order to provide a fast settling time of the reference node appearing at the input of the sense amplifiers. The startup circuit includes first and second discharge current stages, with the first discharge current stage discharging the charge appearing at the reference node input of the sense amplifiers based upon a bandgap reference current. The second discharge current stage discharging the charge appearing at the reference node input of the sense amplifiers based upon the reference current. Each discharge current stage utilizes feedback to gradually decrease the rate of discharge by the discharge current stage so that the discharge current stages are disabled by the time the voltage appearing at the reference node input of the sense amplifiers reaches the desired voltage level.

Description

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

The present invention relates to a reference current generator for memory devices, and particularly to circuitry for more effectively generating a reference current in nonvolatile memory devices.

2. Description of the Related Art

The first nonvolatile memories were electrically programmable read-only memories (EPROMs). In these memories, the memory cells include a floating-gate transistor that is programmable using the hot carrier effect. Programming of an EPROM memory cell includes applying a potential difference between the drain and the source of the floating gate transistor in the presence of a high potential difference (of about 20 volts, this value varying according to the desired programming speed) between the control gate and the source. The application of the first of these potential differences generates an electrical field that gives rise to a flow of electrons in the channel. These electrons collide with atoms of the channel, causing the appearance of new free electrons. These electrons have very high energy (hence the term “hot carriers”). The high difference in potential between the control gate and the source of the floating gate transistor gives rise to a strong electrical field between the floating gate and the substrate, the effect of which is that certain of these electrons are injected into the floating gate, thus putting the memory cell in a state known as a “programmed” state.

The fact that the programming of a memory cell requires the application of voltages both to the control gate and to the drain of the floating-gate transistor eliminates the need for the use of a selection transistor to program one particular memory cell without programming the others. This results in a relatively small silicon area and the effectuation of large scale integration. By contrast, the erasure of all the memory cells of the memory is done substantially simultaneously by exposing the memory cells to ultraviolet radiation.

In addressing the need to individually erase EPROM memory cells, electrically erasable programmable read only memories (EEPROMs) were created. These memories are electrically programmable and erasable by tunnel effect (i.e., the Fowler Nordheim effect). The memory cells have a floating-gate transistor whose drain is connected to the bit line by a selection transistor. The gate of the selection transistor is connected to the word line. The gate of the floating-gate transistor is controlled by a bias transistor. Generally, the source of the floating gate transistor is connected to a reference potential, such as ground. These floating-gate transistors have an oxide layer between the substrate and the floating gate that is very thin to enable the transfer of charges by tunnel effect. The advantage of EEPROMs as compared with EPROMs lies in the fact that each memory cell is programmable and erasable independently of the other EEPROM cells. The tradeoff here is that a larger surface area of silicon is required and therefore a smaller scale of integration is achieved.

A third type of memory has more recently gained popularity. This type of memory, flash EPROMs, combines the relatively high integration of EPROMs with the ease of programming and erasure of EEPROMs. Flash memory cells can be individually programmed utilizing the hot carrier effect in the same way as EPROM cells are programmed. Flash memory cells are also electrically erasable by the tunnel effect. The memory cells of a flash EPROM memory includes a floating-gate transistor that has an oxide layer whose thickness is greater than the oxide layer thickness of an EEPROM floating gate transistor but smaller than the oxide layer thickness of an EPROM floating gate transistor. Consequently, the flash memory cell is capable of erasure by the tunnel effect. For erasure, a highly negative potential difference is created between the control gate and the source of the floating gate transistor, the drain being left in the high impedance state or connected to the ground potential so that a high electrical field is created which tends to remove the electrons from the floating gate.

Flash EPROM devices, hereinafter referred to as flash memory devices, typically include at least one array of flash memory cells organized into rows and columns of flash memory cells. The array is typically partitioned into blocks, each of which is further divided into sectors. A row decoder and column decoder are used to select a single row and at least one column of memory cells based upon the value of an externally generated address applied to the flash memory device. Sense amplifiers are coupled to the column lines corresponding to the columns of memory cells to amplify the voltage levels on the addressed column lines based upon the data values stored in the addressed flash memory cells. The particular implementations of the array and the row and column decoders are known in the art and will not be described further for reasons of simplicity.

A conventional sense amplifier circuit includes a differential amplifier circuit that generally senses a voltage differential between the voltage appearing on a column line connected to a reference cell and the voltage appearing on a reference node and the voltage appearing on a column line connected to an addressed memory cell, and drives a sense output signal (that is coupled to the data output pins of the flash memory device) based upon the sensed voltage differential.

Conventional flash memory devices include a reference current generator for generating a reference current for use by the sense amplifier circuits. A current mirror circuit in the flash memory device mirrors the reference current and applies a single mirrored reference current to all of the sense amplifiers. A startup circuit is utilized in some existing flash memory devices in order to provide a fast settling time of the reference node appearing at the input of the sense amplifiers. An existing startup circuit includes first and second discharge current stages, with each discharge current stage discharging the charge appearing at the reference node input of the sense amplifiers based upon a bandgap reference current. Each discharge current stage utilizes feedback to gradually decrease the rate of discharge by the discharge current stage so that the discharge current stages are disabled by the time the voltage appearing at the reference node input of the sense amplifiers reaches the desired voltage level.

The known reference current generator and startup circuits, however, have shortcomings. For instance, the use of the reference current generator and corresponding current mirror circuit limits the number of sense amplifiers that may be utilized at one time. There is a relatively slow settling time of the reference voltage due to the large capacitive loading on the reference current generator/mirror circuit when a large number of sense amplifiers are used. In addition, the limitation exists due to the amount of noise introduced within each sense amplifier that may affect data integrity. As a result, certain flash memory device features, such as burst mode and page mode features, cannot be effectively executed in conventional flash memory devices.

Based upon the foregoing, there is a need to more effectively and accurately provide reference current levels to sense amplifiers in a nonvolatile memory device, such as a flash memory device.

SUMMARY OF THE INVENTION

Embodiments of the present invention overcome shortcomings in prior flash memory devices and satisfy a significant need for a nonvolatile memory device, such as a flash memory device, that quickly and efficiently provides a reference current to sense amplifiers in the nonvolatile memory device.

In an exemplary embodiment of the present invention, the nonvolatile memory device includes a reference generator circuit for generating a reference current for application to the reference input of the sense amplifiers in the nonvolatile memory device. A bandgap reference circuit generates a bandgap voltage reference. At least one startup circuit initially sets the reference input of the sense amplifiers to a predetermined voltage level. The startup circuit allows for a relatively quick settling of the reference input to the desired predetermined voltage level.

The startup circuit includes a first circuit stage coupled to the bandgap reference circuit for receiving a bandgap current generated from the bandgap voltage reference. The first circuit stage discharges a charge appearing on the reference input of the sense amplifiers from an initial voltage level, such as the supply voltage Vdd, to a voltage level greater than the predetermined voltage level, a rate of discharge being based upon the received bandgap current. The startup circuit further includes a second circuit stage coupled to the reference generator circuit and including a second discharge circuit for discharging a charge appearing on the reference input of the sense amplifiers from the initial voltage level towards the predetermined voltage level, a rate of discharge being based upon the reference current. By basing the rate of discharge of the second discharge circuit upon the reference current, the startup circuit is better matched to the reference generator circuit across process and operational corners.

For flash memory devices having a relatively large number of sense amplifiers, a current buffer circuit may be disposed between the output of the reference generator circuit and the reference inputs of the sense amplifiers. In this case, the current buffer circuit may be implemented as current mirror circuitry having a first circuit leg and a plurality of second circuit legs. The reference current provided by the reference current generator passes through the first circuit leg. The reference current is thereby mirrored in each second circuit leg. Each second circuit leg provides the mirrored reference current to a distinct set of sense amplifiers. In this way, the reference current generated by the reference current generator has lower capacitive load so as to provide a faster settling time. The reference current generator is also isolated from coupling noise associated with the sense amplifiers, which may approach nontrivial levels for a nonvolatile memory device having many sense amplifiers.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the system and method of the present invention may be obtained by reference to the following Detailed Description when taken in conjunction with the accompanying Drawings wherein:

FIG. 1 is a block diagram of a nonvolatile memory device according to the exemplary embodiment of the present invention;

FIG. 2 is a diagram of reference current circuitry of the nonvolatile memory device of FIG. 1;

FIG. 3 is a diagram of a cascode current buffer circuit of the reference current circuitry of FIG. 2;

FIG. 4 is a diagram of startup circuit of the reference current circuitry of FIG. 2;

FIG. 5 is a block diagram of an electronics system/device in which the nonvolatile memory device of FIG. 1 is disposed; and

FIG. 6 is a flow chart illustrating an operation of the nonvolatile memory device of FIG.1.

DETAILED DESCRIPTION OF THE PREFERRED EXEMPLARY EMBODIMENTS

The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which an exemplary embodiment of the invention is shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiment set forth herein. Rather, the embodiment is provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

Referring to FIGS. 1-4, there is disclosed anonvolatile memory device1 according to an exemplary embodiment of the present invention. It is understood thatmemory device1 may be any type of nonvolatile memory device, such as a flash memory device.Memory device1 will be described below as a flash memory device for reasons of simplicity.

Flash memory device1 includes one or more arrays orbanks2 ofmemory cells20. Eacharray2 ofmemory cells20 may be arranged into rows and columns ofmemory cells20. Eacharray2 may be partitioned into blocks ofmemory cells20, with each block being further partitioned into one or more sectors of memory cells20 (not shown). Althoughflash memory device1 is illustrated in FIG. 1 as having only one array/bank2 ofmemory cells20, it is understood thatflash memory device1 may include two ormore arrays2 ofmemory cells20.

Array2 is shown in FIG. 1 as being relatively sparsely populated withmemory cells20 for reasons of clarity. It is understood thatarray2 is substantially entirely populated withmemory cells20 arranged in rows and columns ofmemory cells20 as described above. Althoughmemory cells20 are described herein as flash memory cells, it is understood thatmemory cells20 may be other types of non-volatile memory cells, such as EPROM memory cells.

Thememory cells20 in each column may be connected to adistinct column line5, and thememory cells20 in each row ofmemory cells20 in a block may be connected to a distinct row line.Column lines5 may be local column lines that are coupled to main column lines (not shown in FIG. 1) for providing the selected local column lines to the periphery ofarray2. The use of local and main column lines in flash memories are known in the art and will not be described in greater detail for reasons of simplicity.

Flash memory device1 may further includerow decode circuitry7 which receives an externally generated input address or portion thereof and selects and/or activates a row ofmemory cells20 based upon the input address. In particular, thememory cells20 are selected by connecting thememory cells20 in the addressed row to the column lines5. Rowdecode circuitry7 may include logic that, for example, in response to receiving an externally generated address, drives a single row line corresponding to the externally generating address to a first voltage level to activate eachmemory cell20 in the row, while driving the remaining row lines to another voltage level to deactivate thememory cells20 in the remaining rows. Rowdecode circuitry7 may be implemented with boolean logic gates as is known in the art.

Further,flash memory device1 may includecolumn decode circuitry8 which receives an externally generated input address or portion thereof and selects one or more column lines corresponding to the externally generated address.Column decode circuitry8 may, for example, be implemented as multiplexing circuitry connected to eachcolumn line5 inarray2 ofmemory cells20.Column decode circuitry8 is connected to eachcolumn line5 ofmemory cells20.

Flash memory device1 may includesense amplifiers9 that sense the voltage levels appearing on the selectedcolumn lines5 corresponding to the data stored in the addressedmemory cells20, and drive sense amplifier output signals to voltage levels that are more easily interpreted or otherwise handled by circuitry external toarray2.

Flash memory device1 may include a precharge circuit (not shown) that prechargescolumn lines5 to a certain voltage level during the initial portion of a memory access operation.

Flash memory device1 may include a data input/output (I/O)circuit13 that generally couples addressedmemory cells20 to external I/O data pins14 offlash memory device1. As shown in FIG. 1, data I/O circuit13 is connected to the output ofsense amplifiers9.Flash memory device1 may also includecontrol circuitry15 for receiving externally generated, input control signals and controlling the various components offlash memory device1 to perform memory access operations. For instance,control circuit15 may generate timing/control signals for controllingrow decode circuitry7,column decode circuitry8, data I/O circuit13 andsense amplifiers9 during a memory access operation.

Eachmemory cell20 offlash memory device1 is adapted to provide one of at least two distinct current levels that correspond to the data value stored in thememory cell20. In order to be able to read the data value stored in amemory cell20,memory device1 may further include referencecurrent circuitry10.Reference circuitry10 is adapted to provide a reference current to senseamplifiers9 along a plurality of reference lines RN_O-RN₃. Referring to FIG. 2,reference circuitry10 may include areference generator circuit30 which provides a predetermined current level that is between the two current levels capable of being provided bymemory cell20.Reference generator circuit30 generates reference current Iref on a reference node N, as shown in FIG.2.Reference generator circuit30 includes a flash memory transistor and/orcell30a,enablecircuitry30band apullup device30c(FIG.4). When enabled by enablecircuitry30b,the reference current Iref passes throughflash memory transistor30a.Because reference generators are known in the art,reference generator30 will not be described in detail for reasons of simplicity.

In conventional flash memory devices, a single current mirror duplicates the reference current and applies a single duplicated reference current to all of the sense amplifiers. In part because the number ofsense amplifiers9 appearing in flash memory device may be substantially greater than the number of sense amplifiers in conventional flash memory devices,flash memory device1 includescurrent buffer circuitry32 having an input connected to reference node N and a plurality of output signals RN. Each output signal RN ofcurrent buffer circuitry32 is connected to a distinct group or set ofsense amplifiers9. By dividingsense amplifiers9 into a plurality of groups, the capacitive loading on each output ofcurrent buffer circuitry32 is lowered which thereby improves the settling time ofreference generator circuit30.

Although FIG. 2 showssense amplifiers9 being divided into four groups, it is understood thatsense amplifiers9 may be divided into any number of groups, with each group being driven by a separate circuit.

An implementation ofcurrent buffer32 is shown in FIG.3. As can be seen in FIG. 3,current buffer circuitry32 is implemented as a current mirror having afirst circuit leg33 which is connected to reference node N and passes a first current throughfirst circuit leg33 based upon the voltage appearing on reference node N.First circuit leg33 may include afirst transistor34 having a control terminal connected to reference node N and a source terminal coupled to supply voltage Vdd.First transistor34 passes a current that is based upon the voltage appearing on reference node N. Asecond transistor35 is coupled tofirst transistor34 so as to receive the current passing throughfirst transistor34.

Current buffer circuitry32 further includes a plurality ofsecond circuit legs36, each of which includes afirst transistor37 having a source terminal coupled to supply voltage Vdd, a drain terminal and a control terminal coupled together. Eachsecond circuit leg36 further includes asecond transistor38 having a drain terminal coupled to the drain terminal offirst transistor37, a source terminal connected to the ground reference and a control terminal connected to the control terminal ofsecond transistor35 offirst circuit leg33. As can be seen, the current passing throughsecond transistor35 offirst circuit leg33 is mirrored insecond transistor38 of eachsecond circuit leg36. The output of eachsecond circuit leg36 may be taken at the drain terminal offirst transistor37. The output of each second circuit leg is connected to the reference input of a distinct group ofsense amplifiers9, as discussed above and shown in FIG.2.

Current buffer circuit32 advantageously reduces the capacitive loading at the output of referencecurrent generator30, which thereby reduces settling time. In addition,current buffer circuit32 isolates referencecurrent generator30 from coupling noise generated bysense amplifiers9.

Although the transistors offirst circuit leg33 andsecond circuit legs36 are illustrated in FIG. 3 as n-channel MOS transistors, it is understood that the transistors may be other types of transistors, such as p-channel MOS transistors. In addition, althoughcurrent buffer circuitry32 is shown in FIG. 3 as including foursecond circuit legs36, it is understood thatcurrent buffer circuitry32 may include any number ofsecond circuit legs36.

In order to ensure that the current passing throughsecond transistor35 offirst circuit leg33 is accurately mirrored insecond transistor38 of eachsecond circuit leg36, the layout ofsecond transistor38 of eachsecond circuit leg36 substantially matches the layout ofsecond transistor35 offirst circuit leg33.

The reference input ofsense amplifiers9 are initially set to the power supply voltage Vdd.Flash memory device1 further includes one ormore startup circuits40 for relatively quickly bringing the voltage appearing at the reference input ofsense amplifiers9 to a desired voltage level. In this way, a memory read operation may be performed sooner than in prior flash memory devices. In the exemplary embodiment of the present invention,flash memory device1 includes astartup circuit40 for each group ofsense amplifiers9. FIG. 4 illustrates an implementation of astartup circuit40 andreference generator circuit30.

Startup circuit40 may include abandgap reference circuit41 that generates a bandgap reference voltage Vbgref. In addition,startup circuit40 may includereference duplicating circuit42 which generates a current that, to some extent, duplicates the reference current Iref generated byreference generator circuit30.Reference duplicating circuit42 includes afirst transistor43 having a source terminal coupled to the ground reference and a gate terminal connected to bandgap reference voltage Vbgref so that a bandgap current Ibg passes throughfirst transistor43 that somewhat resembles the reference current Iref.Reference duplicating circuit42 further includes asecond transistor44 connected betweenfirst transistor43 and supply voltage Vdd and sources bandgap current Ibg tofirst transistor43.

Startup circuits40 are adapted to initially discharge the voltage appearing at the reference input ofsense amplifiers9. Eachstartup circuit40 includes a first discharge circuit orstage46 that discharges the voltage appearing on the reference input ofsense amplifiers9 associated with the startup circuit40 (hereinafter referred to as the “reference input node RN”).First discharge circuit46 discharges the voltage appearing on the reference input node RN associated therewith until the voltage reaches an intermediate voltage level greater than the desired predetermined voltage level.First discharge circuit46 includes afirst transistor47 having a source terminal connected to the supply voltage Vdd and a control terminal connected to the control terminal ofsecond transistor44 ofreference duplicating circuit42. In this way, the current passing throughsecond transistor44, bandgap current Ibg, is mirrored infirst transistor47.First discharge circuit46 further includes asecond terminal48 having a drain terminal coupled to the drain terminal offirst transistor47 and a control terminal connected to the drain terminal offirst transistor48. Athird transistor49 has a drain terminal connected to the corresponding reference input node RN and a control terminal connected to the control terminal ofsecond transistor48 so as to form a current mirror therewith.Third transistor49 is sized larger than the size ofsecond transistor48 according to a desired discharge speed and settling time. In this way, the reference input node RN is discharged by a current passing throughthird transistor49 that is based upon the bandgap current Ibg.

First discharge circuit46 further includescontrol circuitry52 for gradually decreasing the amount of the bandgap current Ibg sunk bysecond transistor48 so that current sunk bythird transistor49 is stopped when the voltage appearing on the reference input voltage reaches the intermediate voltage level. Thecontrol circuitry52 relies upon feedback to gradually decrease the bandgap current sunk bysecond transistor48.Control circuitry52 includes afourth transistor53 having a source terminal connected to supply voltage Vdd and a control terminal connected to the reference input node RN. Afifth transistor54 ofcontrol circuitry52 includes a drain terminal and a control terminal coupled to the drain terminal offourth transistor53 and a source terminal connected to the ground reference. As can be seen, the current passing throughfourth transistor53 andfifth transistor54 is based upon the voltage level appearing on the corresponding reference input node RN. With the corresponding reference input node RN initially charged to the supply voltage Vdd, the current passing throughfourth transistor53 andfifth transistor54 is relatively small. The current passing throughfourth transistor53 andfifth transistor54 gradually increases as the voltage appearing on the corresponding reference input node RN gradually decreases. The voltage appearing at the drain terminals offourth transistor53 andfifth transistor54 is at a low voltage level when the current passing throughfourth transistor53 andfifth transistor54 is relatively small, and gradually increases as the current passing throughfourth transistor53 andfifth transistor54 gradually increases.

Control circuitry52 further includes asixth transistor55 having a drain terminal connected to the drain terminal ofsecond transistor48, a source terminal connected to the ground reference and a control terminal connected to the drain terminal offourth transistor53 andfifth transistor54.Sixth transistor55 gradually sinks an increasing amount of the bandgap current Ibg until substantially the entire amount of the bandgap current Ibg is sunk throughsixth transistor55, which effectively stops discharging of the corresponding reference input node RN bythird transistor49. The point at which thethird transistor49 no longer discharges the corresponding reference input node RN is when the reference input node RN reaches the intermediate voltage level, which is a voltage level between the supply voltage Vdd and the desired predetermined voltage. For example,third transistor49 no longer sinks current from the corresponding reference input node RN when the voltage drop appearing on the reference input node RN reaches 75% of the total amount of the desired voltage drop (from the supply voltage Vdd to the desired predetermined voltage level).

Eachstartup circuit40 includes a second discharge circuit orstage56 that discharges the voltage appearing on the reference input node RN ofsense amplifiers9 associated with thestartup circuit40.Second discharge circuit56 discharges the voltage appearing on the reference input node RN associated therewith until the voltage reaches the desired predetermined voltage level.Second discharge circuit56 includes afirst transistor57 having a source transistor connected to the supply voltage Vdd and a control terminal connected to the output ofreference generating circuit30. In this way, the reference current Iref is mirrored infirst transistor57.Second discharge circuit56 further includes asecond transistor58 having a drain terminal coupled to the drain terminal offirst transistor57 and a control terminal connected to the drain terminal ofsecond transistor58. A third transistor59 has a drain terminal connected to the corresponding reference input node RN and a control terminal connected to the control terminal ofsecond transistor58 so as to form a current mirror therewith. Third transistor59 is sized according to the desired discharge speed and settling time. In this way, the corresponding reference input node RN is discharged by a current passing through third transistor59 that is based upon the reference current Iref.

Second discharge circuit56 further includescontrol circuitry62 for gradually decreasing the amount of the mirrored reference current Imref sunk bysecond transistor58 so that voltage discharged by third transistor59 is stopped when the voltage appearing on the reference input node RN reaches the desired predetermined voltage level. Thecontrol circuitry62 relies upon feedback to gradually decrease the mirrored reference current Imref sunk bysecond transistor58.Control circuitry62 includes afourth transistor63 having a source terminal connected to supply voltage Vdd and a control terminal connected to the reference input node RN. Afifth transistor64 ofcontrol circuitry62 includes a drain terminal and a control terminal coupled to the drain terminal offourth transistor63 and a source terminal connected to the ground reference. As can be seen, the current passing throughfourth transistor63 andfifth transistor64 is based upon the voltage level appearing on the corresponding reference input node RN. With the corresponding reference input node RN initially charged to the supply voltage Vdd, the current passing throughfourth transistor63 andfifth transistor64 is relatively small. The current passing throughfourth transistor63 andfifth transistor64 gradually increases as the voltage appearing on the corresponding reference input node RN gradually decreases. The voltage appearing at the drain terminals offourth transistor63 andfifth transistor64 is at a low voltage level when the current passing throughfourth transistor63 andfifth transistor64 is relatively small, and gradually increases as the current passing throughfourth transistor63 andfifth transistor64 gradually increases.

Control circuitry62 further includes asixth transistor65 having a drain terminal connected to the drain terminal ofsecond transistor58, a source terminal connected to the ground reference and a control terminal connected to the drain terminal offourth transistor63 andfifth transistor65.Sixth transistor65 gradually sinks an increasing amount of the mirrored reference current Imref until substantially the entire amount of the current is sunk throughsixth transistor65.

Second transistor58 andfifth transistor64 may have the same transistor structure as the transistors in thesecond circuit legs36 ofcurrent buffer circuitry32 so that the reference current Iref mirrored in thesecond circuit legs36 substantially matches the reference current mirrored insecond transistor58 andfifth transistor64.

Although FIG. 4 shows the transistors inreference generator circuit30,reference duplicating circuit42,first discharge circuit46 andsecond discharge circuit56 as being n-channel and p-channel MOS transistors, it is understood that the transistors could be other types of transistors as well.

An operation of theflash memory device1 will be described with reference to FIG.6. Prior to performing a memory access operation and followingflash memory device1 powering up, the reference input nodes RN are charged to the power supply voltage Vdd. Referencecurrent generator circuit30 generates at500 a reference current Iref to be applied to the reference input node RN ofsense amplifiers9. Thefirst circuit leg33 ofcurrent buffer circuitry32 generates a duplicate of reference current Iref, which is mirrored in eachsecond circuit leg36 at501. Eachsecond circuit leg36 applies at502 its mirrored version of reference current Iref to the reference input of the group ofsense amplifiers9 corresponding to thesecond circuit leg36.

At around the same time reference current Iref is generated,reference duplicating circuit47 of eachstartup circuit40 generates at504 bandgap reference current Ibg.First discharge circuit46 of eachstartup circuit40 begins at505 to discharge current from the reference input nodes RN, due tosecond transistor48 sinking substantially all of the bandgap reference current Ibg. As the voltage appearing on the reference input nodes RN decreases, the amount of the bandgap reference current Ibg passing throughsixth transistor55 gradually increases. When the voltage level appearing on the reference input nodes RN reach the intermediate voltage level, substantially the entire bandgap reference current Ibg is sunk bysixth transistor55 of thefirst discharge circuits46, thereby stopping at507first discharge circuits46 from discharging the reference input nodes RN.

During this time,second discharge circuit56 of eachstartup circuit40 discharges current from the reference input nodes RN. Initially, substantially the entire amount of the mirrored reference current Imref is sunk bysecond transistor58, which causes third transistor59 to discharge current from the corresponding reference input node RN. As the voltage appearing on a reference input node RN gradually decreases at508 due to the discharging, the voltage appearing on the drain terminal offourth transistor63 andfifth transistor64 gradually increases, which causes the current passing through second transistor58 (and hence third transistor59) to gradually decrease. When the voltage level appearing on the reference input nodes RN reach the desired predetermined voltage level, substantially the entire mirrored reference current Imref is sunk bysixth transistor65 of thesecond discharge circuits56, thereby stopping at509second discharge circuits56 from discharging the reference input nodes RN.

It is understood thatflash memory device1 may be utilized in any of a number of devices requiring nonvolatile memory. For instance,flash memory device1 may be located in an electronics system100 (FIG. 5) having aprocessing unit102 that accesses data stored inflash memory device1.System100 may be, for example, a computer and/or data processing device, or a telecommunications device, such as a wireless telephone.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

Claims (42)

What is claimed is:

1. A circuit for providing a reference current in a memory device, comprising:

a reference generator circuit for generating a reference current, the reference generator circuit comprising a reference memory cell having a structure similar to a structure of memory cells in the memory device, the reference current comprises the current flowing through the reference memory cell; and

at least one startup circuit for initially setting the reference node to a predetermined voltage level, the reference node being coupled to the at least one sense amplifier, comprising:

a discharge circuit coupled to the reference generator circuit for discharging a charge appearing on the reference node from an initial voltage level towards the predetermined voltage level, a rate of discharge being based upon the reference current.

2. The circuit ofclaim 1, wherein the discharge circuit comprises:

a first transistor having a control terminal coupled to an output of the reference generator circuit, a first conduction terminal coupled to a supply voltage reference and a second conduction terminal;

a current mirror having a first leg coupled to the second conduction terminal of the first transistor and a second leg coupled to the reference node;

a second transistor having a first conduction terminal coupled to the second conduction terminal of the first transistor, a second conduction terminal coupled to a ground reference and a control terminal; and

a drive circuit for driving the control terminal of the second transistor so that an amount of current from the first transistor passing through the second transistor is gradually increased.

3. The circuit ofclaim 2, wherein the drive circuit comprises:

a third transistor having a control terminal coupled to the reference node, a first conduction terminal coupled to a supply voltage reference and a second conduction terminal, the second conduction terminal being connected to the control terminal of the second transistor; and

a fourth transistor having a first conduction terminal coupled to the second conduction terminal of the third transistor and the control terminal of the second transistor, a second conduction terminal coupled to the ground reference and a control terminal coupled to the first conduction terminal of the fourth transistor.

4. The circuit ofclaim 2, wherein the current mirror comprises:

a third transistor coupled between the second conduction terminal of the first transistor and the ground reference; and

a fourth transistor coupled between the reference node and the ground reference, a control terminal of the fourth transistor being connected to the control terminal of the third transistor.

5. The circuit ofclaim 2, wherein:

the drive circuit has an input connected to the reference node and provides an output signal having a voltage that varies inversely with the voltage appearing on the reference node.

6. The circuit ofclaim 1, further comprising:

a current buffer circuit disposed between the reference generator circuit and the reference node, the current buffer circuit provides a substantial duplicate of the reference current to a plurality of reference nodes.

7. The circuit ofclaim 1, further comprising:

a current buffer circuit disposed between the reference generator circuit and the reference node, the current buffer circuit comprising at least one current mirror having a first leg coupled to the reference generator circuit and a second leg coupled to the reference node.

8. A method setting a reference node in a memory device having memory cells to a first predetermined voltage level, comprising:

generating a reference current, the reference current comprising current of a reference memory cell in the memory device;

applying a current proportional to the reference current to a reference node; and

discharging a charge appearing on the reference node to a predetermined voltage level at a rate that is based upon the reference current.

second discharging the charge appearing on the reference node to a third predetermined level at a rate that is based upon the reference current.

9. The method ofclaim 8, wherein:

the step of applying comprises producing a plurality of currents proportional to the reference current and applying each current proportional to the reference current to a distinct reference node.

10. A nonvolatile memory device, comprising:

an array of memory cells arranged into rows and columns of memory cells and including a plurality of column lines, each column of memory cells being coupled to a distinct column line;

an address decode circuitry having input signals coupled to address input pins of the memory device and adapted to select a row and a plurality of columns of memory cells;

a plurality of sense amplifier circuits, each sense amplifier circuit being coupled to a plurality of column lines, column lines selected by the address decode circuitry being connected to the sense amplifier circuits, the sense amplifiers serving to detect a difference between the selected columns lines and a reference; and

circuitry for providing a reference current to the sense amplifier circuits, comprising:

a reference generator circuit for generating a reference current, comprising a reference memory cell having a structure similar to the structure of the memory cells in the array of memory cells, the reference current comprising current flowing in the reference memory cell;

a current buffer circuit for generating at least one current proportional to the reference current and applying the at least one proportional current to at least one reference node to which at least some of the sense amplifier circuits are coupled; and

at least one startup circuit for initially setting the at least one reference node to a predetermined voltage level, comprising a discharge circuit coupled to the reference generator circuit for discharging a charge appearing on the at least one reference node from an initial voltage level to the predetermined voltage level, a rate of discharge being based upon the reference current.

11. The memory device ofclaim 10, wherein the discharge circuit comprises:

a first transistor having a control terminal coupled to an output of the reference generator circuit, a first conduction terminal coupled to a supply voltage reference and a second conduction terminal;

a current mirror having a first leg coupled to the second conduction terminal of the first transistor and a second leg coupled to the reference node;

a second transistor having a first conduction terminal coupled to the second conduction terminal of the first transistor, a second conduction terminal coupled to a ground reference and a control terminal; and

a drive circuit for driving the control terminal of the second transistor so that an amount of current from the first transistor passing through the second transistor is gradually increased.

12. The memory device ofclaim 11, wherein the drive circuit comprises:

a third transistor having a control terminal coupled to the reference node, a first conduction terminal coupled to a supply voltage reference and a second conduction terminal, the second conduction terminal being connected to the control terminal of the second transistor; and

a fourth transistor having a first conduction terminal coupled to the second conduction terminal of the third transistor and the control terminal of the second transistor, a second conduction terminal coupled to the ground reference and a control terminal coupled to the first conduction terminal of the fourth transistor.

13. The memory device ofclaim 11, wherein the current mirror comprises:

a third transistor coupled between the second conduction terminal of the first transistor and the ground reference; and

a fourth transistor coupled between the reference node and the ground reference, a control terminal of the fourth transistor being connected to a control terminal of the third transistor.

14. The memory device ofclaim 10, wherein the circuitry for providing further comprises a plurality of startup circuits, each startup circuit initially setting a distinct reference node to the predetermined voltage level.

15. The memory device ofclaim 14, wherein:

the current buffer circuit is disposed between the reference generator circuit and each reference node, the current buffer circuit providing to each reference node a current proportional to the reference current.

16. The memory device ofclaim 10, wherein:

the current buffer circuit comprises at least one current mirror having a first leg coupled to the reference generator circuit and a second leg coupled to the reference node.

17. A nonvolatile memory device, comprising:

an array of memory cells arranged into rows and columns of memory cells and including a plurality of column lines, each column of memory cells being coupled to a distinct column line;

address decode circuitry having input signals coupled to address input pins of the memory device and adapted to select a row and a plurality of columns of memory cells;

a plurality of sense amplifier circuits, each sense amplifier circuit being coupled to a plurality of column lines, column lines selected by the address decode circuitry being connected to the sense amplifier circuits, the sense amplifier circuits serving to detect a difference between the selected columns lines and a reference, the sense amplifier circuits being divided into a plurality of groups with each group of sense amplifier circuits being connected to a distinct first reference node; and

circuitry for providing a reference current to the sense amplifier circuits, comprising:

a reference generator circuit for generating a reference current level relative to a second reference node; and

current buffer circuitry having an input connected to the second reference node and having a plurality of outputs, each output providing to a distinct first reference node a current proportional to the reference current level.

18. The nonvolatile memory device ofclaim 17, wherein:

the current buffers comprise current mirror circuitry having a first leg connected to the second reference node and a plurality of second legs, the current in each second leg being based upon the current in the first leg, each second leg being connected to a distinct first reference node.

19. The nonvolatile memory device ofclaim 18, wherein:

the first leg of the current mirror circuitry includes a first transistor; and

each second leg of the current mirror circuitry includes a second transistor, the first transistor and the second transistors are substantially matched to each other.

20. The nonvolatile memory device ofclaim 18, wherein:

the first leg of the current mirror circuitry includes a first transistor; and

each second leg of the current mirror circuitry includes a second transistor, the first transistor and the second transistors are substantially the same size and have the same layout configuration.

21. The nonvolatile memory device ofclaim 17, wherein the circuitry for providing a reference current to the sense amplifier circuits further comprises:

at least one reference memory cell, the reference current comprising the current in the at least one reference memory cell;

a plurality of startup circuits for initially setting each first reference node to a predetermined voltage level, each startup circuit being associated with a distinct first reference node, each startup circuit comprising a discharge circuit coupled to the reference generator circuit for discharging a charge appearing on the first reference node associated therewith from an initial voltage level to the predetermined voltage level, a rate of discharge being based upon the reference current.

22. The nonvolatile memory device ofclaim 17, wherein the nonvolatile memory device comprises a flash memory device.

23. An electronics device, comprising:

a processing element; and

a nonvolatile memory device, comprising:

an array of memory cells arranged into rows and columns of memory cells and including a plurality of column lines, each column of memory cells being coupled to a distinct column line;

address decode circuitry having input signals coupled to address input pins of the memory device and adapted to select a row and a plurality of columns of memory cells;

a plurality of sense amplifier circuits, each sense amplifier circuit being coupled to a plurality of column lines, column lines selected by the address decode circuitry being connected to the sense amplifier circuits, the sense amplifier circuits serving to detect a difference between the selected columns lines and a reference, the sense amplifier circuits being divided into a plurality of groups with each group of sense amplifier circuits being connected to a distinct first reference node; and

circuitry for providing a reference current to the sense amplifier circuits, comprising:

a reference generator circuit for generating a reference current level relative to a second reference node; and

a current buffer circuitry having an input connected to the second reference node and having a plurality of outputs, each output providing to a distinct first reference node a current proportional to the reference current level.

24. The electronics device ofclaim 23, wherein:

the reference generator circuit comprises a reference cell transistor having a structure similar to the structure of a transistor in the memory cells in the array, the reference current comprising current flowing through the reference cell transistor; and

the circuitry for providing a reference current further comprises:

a plurality of startup circuits, each startup circuit being connected to a distinct first reference node and adapted to discharge a voltage appearing thereon at a rate based upon the reference current.

25. The circuit ofclaim 1, further comprising a current buffer circuit disposed between the reference generator circuit and the reference node, the current buffer circuit providing to the reference node a current proportional to the reference current.

26. The circuit ofclaim 25, wherein the current buffer circuit provides to the reference node a substantial duplicate of the reference current.

27. The method ofclaim 8, further comprising:

generating a second reference current; and

discharging the charge appearing on the reference node from a second predetermined voltage level to a third predetermined voltage level, the third predetermined voltage level being a voltage between the predetermined voltage level and the second predetermined voltage level.

28. The method ofclaim 8, further comprising mirroring the reference current to produce a substantial duplicate thereof, the current proportional to the reference current being the substantial duplicate thereof.

29. The nonvolatile memory device ofclaim 10, wherein the startup circuit further comprises:

a second discharge circuit coupled to the voltage reference circuit for receiving a second reference current and for discharging the charge appearing on the at least one reference node substantially from the initial voltage level towards the predetermined voltage level, a rate of discharge being based upon the second reference current.

30. The nonvolatile memory device ofclaim 10, wherein the current proportional to the reference current is substantially the same as the reference current.

31. The nonvolatile memory device ofclaim 17, wherein the current buffer circuitry provides to each first reference node a substantial duplicate of the reference current level.

32. The nonvolatile memory device ofclaim 21, wherein each startup circuit further comprises a second discharge circuit for receiving a second reference current and for discharging the charge appearing on the first reference node corresponding thereto substantially from the initial voltage level towards the predetermined voltage level, a rate of discharge being based upon the received second reference current.

33. The nonvolatile memory device ofclaim 32, wherein each second discharge circuit discharges the charge appearing on the corresponding first reference node until the corresponding first reference node reaches a second predetermined voltage level greater than the first predetermined voltage level.

34. A circuit for providing a reference current in a memory device having at least one sense amplifier, comprising:

a reference generator circuit for generating a reference current;

a second reference generator circuit for generating a second reference current; and

at least one startup circuit for initially setting a reference node to a predetermined voltage level, the reference node being coupled to the at least one sense amplifier, comprising:

a circuit coupled to the reference generator circuit for changing a charge appearing on the reference node from an initial voltage level towards the predetermined voltage level, a rate of change being based upon the reference current; and

a second circuit coupled to the second reference generator circuit for changing a charge appearing on the reference node from an initial voltage level towards the predetermined voltage level, a rate of change being based upon the second reference current.

35. The circuit ofclaim 34, wherein the circuit discharges the charge appearing on the reference node from the initial voltage level to the predetermined voltage level, a rate of change being based upon the reference current.

36. The circuit ofclaim 34, wherein the circuit comprises:

a first transistor having a control terminal coupled to an output of the reference generator circuit, a first conduction terminal coupled to a supply voltage reference and a second conduction terminal;

a current mirror having a first leg coupled to the second conduction terminal of the first transistor and a second leg coupled to the reference node;

a second transistor having a first conduction terminal coupled to the second conduction terminal of the first transistor, a second conduction terminal coupled to a second supply voltage reference and a control terminal; and

a drive circuit for driving the control terminal of the second transistor so that an amount of current from the first transistor passing through the second transistor is gradually increased.

37. The circuit ofclaim 36, wherein the drive circuit comprises:

a third transistor having a control terminal coupled to the reference node, a first conduction terminal coupled to the supply voltage reference and a second conduction terminal, the second conduction terminal being connected to the control terminal of the second transistor; and

a fourth transistor having a first conduction terminal coupled to the second conduction terminal of the third transistor and the control terminal of the second transistor, a second conduction terminal coupled to the second supply voltage reference and a control terminal coupled to the first conduction terminal of the fourth transistor.

38. The circuit ofclaim 36, wherein the current mirror comprises:

a third transistor coupled between the second conduction terminal of the first transistor and the second supply voltage reference; and

a fourth transistor coupled between the reference node and the second supply voltage reference, a control terminal of the fourth transistor being connected to the control terminal of the third transistor.

39. The circuit ofclaim 36, wherein:

the drive circuit has an input connected to the reference node and provides an output signal having a voltage that varies inversely with the voltage appearing on the reference node.

40. The circuit ofclaim 34, further comprising:

a current buffer circuit coupled between the reference generator circuit and the reference node for providing to a plurality of reference nodes a current proportional to the reference current.

41. A nonvolatile memory device, comprising:

an array of memory cells arranged into rows and columns of memory cells and including a plurality of column lines, each column of memory cells being coupled to a distinct column line;

address decode circuitry having input signals coupled to address input pins of the memory device and adapted to select a row and a plurality of columns of memory cells;

a plurality of sense amplifier circuits, each sense amplifier circuit being coupled to a plurality of column lines, column lines selected by the address decode circuitry being connected to the sense amplifier circuits, the sense amplifiers serving to detect a difference between the selected columns lines and a reference; and

circuitry for providing a reference current to the sense amplifier circuits, comprising:

a reference generator circuit for generating a reference current;

a current buffer circuit for generating at least one current proportional to the reference current and applying the at least one proportional current to at least one reference node to which at least some of the sense amplifiers are coupled;

at least one startup circuit for initially setting the at least one reference node to a predetermined voltage level, comprising:

a circuit coupled to the reference generator circuit for changing a charge appearing on the at least one reference node from an initial voltage level to the predetermined voltage level, a rate of change being based upon the reference current; and

a second circuit for changing the charge appearing on the reference node approximately from the initial voltage level towards the predetermined voltage level, a rate of change being based upon a second reference current.

42. The nonvolatile memory device ofclaim 41, wherein the reference generator circuit comprises a transistor having a structure similar to the structure of the memory cells in the array, the reference current comprising the current in the transistor.

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