US6693934B2 - Wavelength division multiplexed vertical cavity surface emitting laser array - Google Patents

Abstract

Vertical cavity surface emitting laser arrays that emit light at different wavelengths and that are suitable for wavelength multiplexed applications. Such arrays are beneficially produced using binary masks that control the thickness elements of a spacer, which in turn controls the wavelengths of light from the individual VCSEL elements. The binary masks can be used to control either deposition (growth) or etching. The binary masks, which are comprised of open areas and closed areas, are selectively applied to an intermediate VCSEL array structure.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

Not applicable.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the field of vertical cavity surface emitting laser arrays. More specifically, it relates to vertical cavity surface emitting laser arrays that emit light at different wavelengths, and to a method of producing such arrays binary masks.

2. Discussion of the Related Art

Vertical cavity surface emitting lasers (VCSELs) represent a relatively new class of semiconductor lasers. In a VCSEL, optical emission occurs normal to the plane of a PN junction. VCSELs have certain advantages over edge-emitting laser diodes, including smaller optical beam divergence and well-defined, highly circular laser beams. Such advantages make VCSELs well suited for optical data storage, data and telecommunication systems, and laser scanning.

VCSELs can be formed from a wide range of material systems to produce specific characteristics. VCSELs typically have active regions, distributed Bragg reflector (DBR) mirrors, current confinement structures, substrates, and contacts. Because of their complicated structure and because of their material requirements, VCSELs are usually grown using metal-organic chemical vapor deposition (MOCVD) or by using molecular beam epitaxy (MBE).

To assist the understanding of VCSELs, FIG. 1 illustrates atypical VCSEL10. As shown, an n-doped gallium arsenide (GaAS)substrate12 is disposed with an n-typeelectrical contact14. An n-doped lower mirror stack16 (a DBR) is on the GaASsubstrate12, and an n-type graded-indexlower spacer18 is disposed over thelower mirror stack16. Anactive region20 having a plurality of quantum wells is formed over thelower spacer18. A p-type graded-indextop spacer22 is disposed over theactive region20, and a p-type top mirror stack24 (another DBR) is disposed over thetop spacer22. Over thetop mirror stack24 is a p-conduction layer9, a p-typeGaAs cap layer8, and a p-typeelectrical contact26.

Still referring to FIG. 1, thelower spacer18 and thetop spacer22 separate thelower mirror stack16 from thetop mirror stack24 such that an optical cavity is formed. As the optical cavity is resonant at specific wavelengths, the mirror separation is controlled to resonant at a predetermined wavelength (or at a multiple thereof). At least part of thetop mirror stack24 includes aninsulating region40 that is formed by implanting protons into thetop mirror stack24 or by forming an oxide layer. In either event, theinsulating region40 has a conductive annular central opening42 that forms an electrically conductive path though theinsulating region40.

In operation, an external bias causes anelectrical current21 to flow from the p-typeelectrical contact26 toward the n-typeelectrical contact14. Theinsulating region40 and its conductive central opening42 confine the current21 flow through theactive region20. Some of the electrons in the current21 are converted into photons in theactive region20. Those photons bounce back and forth (resonate) between thelower mirror stack16 and thetop mirror stack24. While thelower mirror stack16 and thetop mirror stack24 are very good reflectors, some of the photons leak out as light23 that travels along an optical path. Still referring to FIG. 1, the light23 passes through the p-type conduction layer9, through the p-typeGaAs cap layer8, through anaperture30 in the p-typeelectrical contact26, and out of the surface of the vertical cavitysurface emitting laser10.

It should be understood that FIG. 1 illustrates a typical VCSEL, and that numerous variations are possible. For example, the dopings can be changed (say, providing a p-type substrate), different material systems can be used, operational details can be varied, and additional structures, such as tunnel junctions, can be added. Furthermore, FIG. 1 only illustrates one VCSEL.

Producing multiple VCSELs on one substrate can be beneficial. In some applications, such as data and telecommunication systems, it is beneficial to have a VCSEL array that is comprised of multiple individual VCSEL elements that emit light at different wavelengths. Such an array could be used to implement wavelength division multiplexed systems. That is, light of one wavelength could be emitted (and, if required, modulated), then light of another wavelength could be emitted (and, if required, modulated), and so on. Because of the inherent low cost and volume capability of VCSELs, a VCSEL array suitable for wavelength division multiplexing would be highly attractive.

However, despite their many benefits, VCSEL arrays suitable for wavelength division multiplexing are not commercially available. One reason for this has been the unavailability of a low cost method of producing stable wavelength division multiplexed light beams from a single substrate.

In a VCSEL, the wavelength of the light output depends on various factors, one of which (as previously noted) is the separation of the top DBR mirror and the bottom DBR mirror. Thus, the output wavelength can be tuned by controlling the length of the cavity between the top and bottom DBRs. That cavity length is set during the manufacturing process. FIG. 2, which illustrates a side view of asimplified VCSEL element98 of a VCSEL array, is useful for visualizing the cavity length. As shown, theVCSEL element98 includes asubstrate100 having abackside contact102 and abackside DBR mirror104. An active region106 is on thebackside DBR mirror104. A front side DBR110 is on the active region106. Front sideelectrical contacts112 are on the front side DBR110. Thus, the front side and back side DBR separation is controlled by the width of the active region106 (and by the reflection depth of the DBRs). Therefore, the output wavelength is controlled by the processes that form the VCSEL element.

Therefore, a process of producing a VCSEL array that emits light beams of different wavelengths would be beneficial. Even more beneficial would be a new VCSEL array that is suitable for wavelength division multiplexing. Still more beneficial would be a low cost lithographic technique of producing VCSEL arrays that emit light beams having different wavelengths.

SUMMARY OF THE INVENTION

The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention, and is not intended to be a full description. A full appreciation of the various aspects of the invention can be gained by taking the entire specification, claims, drawings, and abstract as a whole.

Accordingly, the principles of the present invention are directed to a method of producing VCSEL arrays, and to VCSEL arrays produced by that method, that are capable of emitting light beams having different wavelengths and that are suitable implementing wavelength division multiplexing in a cost effective manner. According to the principles of the present invention, binary masks are used to control depositions and/or etchings of a spacer that is disposed between top DBR mirrors and an active region. By using the binary masks, the wavelengths of individual VCSEL elements on a common substrate can be controlled.

According to one method that is in accord with the principles of the present invention, a process-controlled spacer is selectively grown on an active region using a sequence of binary masks such that the spacer has multiple thicknesses that are controlled by the binary masks. Then, front side (top) DBR mirrors are disposed over the spacer. Electrical contacts for the individual VCSEL elements are then provided. Additionally, suitable isolation regions are formed, either in the spacer or in the front side DBR mirrors, such that discrete VCSEL elements are formed. Suitable spacers can be formed from regrowth Al_xGa_(1−X)As (or similar materials), a dielectric deposition (such as PECVD SiO₂), or a glass deposition.

According to another method that is in accord with the principles of the present invention, a process-controlled spacer is formed over an active region. Then, that process-controlled spacer is selectively etched using a sequence of binary masks such that the spacer has multiple thicknesses in locations controlled by the binary masks. Beneficially, the spacer includes etch stop layers that accurately control the etch depth, and thus the spacer thicknesses. Then, front side DBR mirrors are disposed over the spacer and electrical contacts for the individual VCSEL elements are provided. Additionally, isolation regions are formed, either in the substrate or in the front side DBR mirrors, such that discrete VCSEL elements are produced. Suitable etch processes include isotropic planar etching, with the particular etchant that is used being dependent on the spacer material.

A VCSEL array according to the principles of the present invention includes a substrate, an active region adjacent the substrate, and a spacer having a plurality of regions with different thicknesses. Beneficially, the difference in thickness between each region is a multiple of a distance L. Front side DBR mirror structures are over the spacer, and electrical contacts for the individual VCSEL elements are over the front side DBR mirror structures.

The novel features of the present invention will become apparent to those of skill in the art upon examination of the following detailed description of the invention or can be learned by practice of the present invention. It should be understood, however, that the detailed description of the invention and the specific examples presented, while indicating certain embodiments of the present invention, are provided for illustration purposes only because various changes and modifications within the spirit and scope of the invention will become apparent to those of skill in the art from the detailed description of the invention and claims that follow.

BRIEF DESCRIPTION OF THE DRAWING

The accompanying figures, in which like reference numerals refer to identical or functionally-similar elements throughout the separate views and which are incorporated in and form part of the specification, further illustrate the present invention and, together with the detailed description of the invention, serve to explain the principles of the present invention.

In the drawings:

FIG. 1 illustrates a typical vertical cavity surface emitting laser;

FIG. 2 illustrates a side section view of a simplified VCSEL element;

FIG. 3 illustrates a top view of a binary mask set according to the principles of the present invention;

FIG. 4 illustrates a side view of a partially fabricated VCSEL array after depositions through the binary mask set illustrated in FIG. 3;

FIG. 5 illustrates a side view of a VCSEL array according to the principles of the present invention;

FIG. 6 illustrates a side view of a partially fabricated VCSEL array after a spacer is formed;

FIG. 7 illustrates a side view of a partially fabricated VCSEL array after etching the spacer of FIG.6 through binary mask set illustrated in FIG. 3; and

FIG. 8 illustrates a top view of another binary mask set that is in accord with the principles of the present invention

Note that in the drawings that like numbers designate like elements. Additionally, for explanatory convenience the descriptions use directional signals such as up and down, top and bottom, and lower and upper. Such signals, which are derived from the relative positions of the elements illustrated in the drawings, are meant to aid the understanding of the present invention, not to limit it.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

The principles of the present invention provide for VCSEL arrays, and for methods of fabricating such VCSEL arrays, that output light at multiple wavelengths. Such VCSEL arrays are particularly useful in wavelength division multiplexed applications.

The principles of the present invention provide for forming spacers using a binary mask set. Binary masks have open and closed regions that can conceptually correspond to binary digits (Os and Is). FIG. 3 illustrates oneset200 of binary masks, with that set being comprised of a first mask202 and of a second mask204. Each mask is comprised of open areas206 (which can correspond to binary 0) and closed areas208 (which can corresponds to binary 1).

A first use of the mask set200 is in producing a special spacer using material depositions. Turn now to FIG. 4 for a partially fabricatedVCSEL structure300. That VCSEL structure is produced by forming anactive region302 on a lower DBR304, which is on a substrate306 having ametallic contact307. Over the active region is an optional top buffer layer308. If used, the top buffer layer308 controls the minimum separation between the lower DBR304 and upper DBRs that will be formed.

The first mask202 is placed over the partially fabricatedVCSEL structure300 active region302 (or over the top buffer layer308).Spacer material310 having a thickness 2L is then grown (deposited) through theopen areas206 of the first mask. Then, the first mask202 is removed and the second mask204 is placed over the partially fabricatedVCSEL structure300.Spacer material312 having a thickness L is then grown through theopen areas206 of the second mask. Then, the second mask204 is removed.Top DBRs316 are then grown on the deposited spacer layers (isolation regions, which are not shown in FIG. 3, are fabricated as required) such that discrete VCSEL elements are produced. The result is fourDBRs316 that are spaced apart from each other, with the thickness of each spacer element being an integer multiple of L.

Still referring to FIG. 4, suitable spacer materials include regrowth Al_XGa_(1−X)As (or similar materials), a dielectric deposition (such as PECVD SiO₂), or a glass deposition. If the deposited spacer material(s) is properly selected, the spacer can be relatively stress-free. Stress can further be reduced by annealing thestructure300 after each deposition to smooth out interface roughness. Additionally, while the foregoing is described as producing DBR separations that are multiples of L, this is not required. The thickness of the various depositions can be varied to achieve design goals.

Referring now to FIG. 5,electrical contacts510 are then formed on theDBRs316. The result is aVCSEL array500 that emits light at different wavelengths from the individual VCSEL elements.

Another use of the mask set200 shown in FIG. 3 is in producing a special spacer by etching. Turn now to FIG. 6 for a partially fabricatedVCSEL structure400. That VCSEL structure is produced by forming anactive region302 on a lower DBR304, which is on a substrate306 having acontact307. Over the active region is an optional top buffer layer308. If used, the top buffer layer308 controls the minimum separation between the lower DBR304 and upper DBRs that will be formed later. Over the active region is amaterial402. That material can be a dielectric deposition or a semiconductor growth. Additionally, to assist accurate etching, etch stop layers412 can be located within thematerial402.

Referring now to FIG. 7, the first mask202 is located over thematerial402. Thematerial402 is then etched a distance 2L through theopen areas206 of the first mask. Anetch stop layer412 can be used to stop the etch at the proper location. Then, the first mask202 is removed and the second mask204 is located over the partially fabricated VCSEL structure. Thematerial402 is then etched a distance L through theopen areas206 of the second mask. Again, an etch stop layer can assist accurate etch depth. Then, the second mask204 is removed.Top DBRs316 are then grown on the etched spacer layers. The result is fourDBRs316 that are spaced apart from each other, with the separation between each of theDBRs316 being an integer multiple of L. Electrical contacts (which are not shown, but reference the contacts550 in FIG. 5) for the individual VCSEL elements are then provided.Isolation regions455 are also formed in suitable locations including a location between thetop DBRs316.

Referring now to FIGS. 6 and 7, the etch process is best performed using an etchant that depends on thematerial402. Isotropic planar etching is beneficial. Furthermore, thematerial402 can include embedded etch stop layers412 to enable accurate control of each step's position.

Wavelength tuned VCSEL arrays produced using binary masks have the advantages of being able to produce a wide range of spacer thicknesses using lithographic techniques and relatively few masks and process steps. Furthermore, VCSEL arrays according to the present invention are relatively easily fabricated using normal fabrication processes. Also, standard processes can be used to fabricated features of the VCSEL array, such as trenches for oxidation and material growths.

The foregoing has described using a binary mask set that is comprised of two individual masks (reference FIG.3). However, the principles of the present invention encompass that use of other mask sets. For example, FIG. 8 illustrates amask set600 that is comprised of four individual masks, themasks602,604,606, and608. Those masks still includeopen areas206 andclosed areas208. Such a mask set with 4 individual masks can produce up to 16 thickness variations. The number of thickness variations is related to a power of 2.

The embodiments and examples set forth herein are presented to best explain the present invention and its practical application and to thereby enable those skilled in the art to make and utilize the invention. Those skilled in the art, however, will recognize that the foregoing description and examples have been presented for the purpose of illustration and example only. Other variations and modifications of the present invention will be apparent to those of skill in the art, and it is the intent of the appended claims that such variations and modifications be covered. The description as set forth is not intended to be exhaustive or to limit the scope of the invention. Many modifications and variations are possible in light of the above teaching without departing from the spirit and scope of the following claims. It is contemplated that the use of the present invention can involve components having different characteristics. It is intended that the scope of the present invention be defined by the claims appended hereto, giving full cognizance to equivalents in all respects.

Claims (29)

The embodiments of an invention in which an exclusive property or right is claimed are defined as follows:

1. A method of fabricating a vertical cavity surface emitting laser array, comprising:

fabricating a structure comprised of a substrate, a first mirror on the substrate, and an active region on the first mirror;

growing at least a first spacer element and a second spacer element over the active region using a first mask, having open spaces and closed spaces, of a binary mask set;

growing at least a third spacer element over the active region and further growing the first spacer element using a second mask, having open spaces and closed spaces, of the binary mask set, and

forming distributed Bragg reflector (DBR) mirrors over the first, second, and third spacer elements;

wherein the first, second, and third spacer elements have different thicknesses.

2. A method of fabricating a vertical cavity surface emitting laser array according toclaim 1, wherein the first, second, and third spacer elements are formed from Al_xGa_(1−x)As.

3. A method of fabricating a vertical cavity surface emitting laser array according toclaim 1, wherein the first, second, and third spacer elements are formed from a dielectric deposition.

4. A method of fabricating a vertical cavity surface emitting laser array according toclaim 1, wherein the dielectric deposition is performed using SiO₂.

5. A method of fabricating a vertical cavity surface emitting laser array according toclaim 1, wherein the first, second, and third spacer elements include glass.

6. A method of fabricating a vertical cavity surface emitting laser array according toclaim 1, wherein the first spacer element and the second spacer element are formed with a thickness difference of L, and wherein the first spacer element and the third spacer element are formed with a thickness difference of 2L.

7. A method of fabricating a vertical cavity surface emitting laser array according toclaim 1, further including forming electrical contacts on the top DBR mirrors.

8. A method of fabricating a vertical cavity surface emitting laser array according toclaim 7, further including forming isolation regions to form discrete VCSEL elements.

9. A method of fabricating a vertical cavity surface emitting laser array, comprising:

fabricating a structure having a substrate, a first mirror on the substrate, an active region on the first mirror, and a spacer on the active region;

etching the spacer through a first mask, having open spaces and closed spaces, of a binary mask set to define at least a first spacer element and a second spacer element;

etching the spacer through a second mask, having open spaces and closed spaces, of the binary mask set to define at least a third spacer element and to further define the first spacer element, and

forming distributed Bragg reflector (DBR) mirrors over at least the first, second, and third spacer elements;

wherein the DBR mirrors are separated by the first, second, and third spacer elements at different distances from a top of the active region.

10. A method of fabricating a vertical cavity surface emitting laser array according toclaim 9, wherein the spacer includes etch stop layers.

11. A method of fabricating a vertical cavity surface emitting laser array according toclaim 9, further including forming electrical contacts on the DBR mirrors.

12. A method of fabricating a vertical cavity surface emitting laser array according toclaim 11, further including forming isolation regions to form discrete VCSEL elements.

13. A method of fabricating a vertical cavity surface emitting laser array according toclaim 9, wherein said etching includes isotropic planar etching.

14. A method of fabricating a vertical cavity surface emitting laser array according toclaim 9, wherein the first spacer element and the second spacer element are formed with a thickness difference of L, and wherein the first spacer element and the third spacer element are formed with a thickness difference of 2L.

15. A VCSEL array, comprising:

a substrate having a first electrical contact;

an active region over the substrate;

a plurality of spacer elements over the active region, each spacer element having a different thickness;

a plurality of front side DBR mirrors, each located on an associated spacer element such that the distance from each front side DBR mirror to the active region depends on the thicknesses of the spacer elements; and

a plurality of electrical contacts, each located on an associated front side DBR mirror,

wherein the plurality of spacer elements, each having a different thickness, are formed by successively applying a binary mask set.

16. A VCSEL array according toclaim 15, wherein said VCSEL array emits a plurality of wavelengths of light, wherein each of the wavelengths is dependent on a distance from an associated front side DBR mirror to the active region.

17. A VCSEL array according toclaim 16, wherein a distance from each front side DBR mirror to a top surface of said active region is an integer multiple of L.

18. A VCSEL array according toclaim 15, further including isolation regions between the front side DBR mirrors.

19. A VCSEL array according toclaim 15, further including a buffer layer between said spacer and said active region.

20. A method of fabricating an array having a plurality of VCSELs, comprising:

fabricating a structure comprised of a substrate, a lower DBR mirror over the substrate, and an active region over the lower DBR mirror;

forming a plurality of spacer elements over the active region by successively growing a spacer material using a set of binary masks; and

forming top DBR mirrors over the spacer elements;

wherein at least two of the spacer elements have different thicknesses and at least two of the VCSELs generate LASER lights with different wavelengths.

21. A method of fabricating an array having a plurality of VCSELs according toclaim 20, wherein the spacer material includes Al_xGa_(1−x)As.

22. A method of fabricating an array having a plurality of VCSELs according toclaim 20, wherein the spacer material includes SiO₂or glass.

23. A method of fabricating an array having a plurality of VCSELs according toclaim 20, wherein the thicknesses of the spacer elements differ by L, where L is a thickness formed by one of the masks in the set of binary masks.

24. A method of fabricating an array having a plurality of VCSELs according toclaim 20, further including forming electrical contacts on the top DBR mirrors.

25. A method of fabricating an array having a plurality of VCSELs, comprising:

fabricating a structure comprised of a substrate, a lower DBR mirror over the substrate, and an active region over the lower DBR mirror;

growing a spacer material over the active region;

forming a plurality of spacer elements by successively etching the spacer material using a set of binary masks; and

forming top DBR mirrors over the spacer elements;

wherein at least two of the spacer elements have different thicknesses and at least two of the VCSELs generate LASER lights with different wavelengths.

26. A method of fabricating an array having a plurality of VCSELs according toclaim 25, wherein the spacer material includes Al_xGa_(1−x)As.

27. A method of fabricating an array having a plurality of VCSELs according toclaim 25, wherein the spacer material includes SiO₂or glass.

28. A method of fabricating an array having a plurality of VCSELs according toclaim 25, wherein the thicknesses of the spacer elements differ by L, where L is a thickness etched by one of the masks in the set of binary masks.

29. A method of fabricating an array having a plurality of VCSELs according toclaim 25, further including forming electrical contacts on the top DBR mirrors.

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