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US6635914B2 - Microelectronic programmable device and methods of forming and programming the same - Google Patents

Microelectronic programmable device and methods of forming and programming the same
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US6635914B2
US6635914B2US09/951,882US95188201AUS6635914B2US 6635914 B2US6635914 B2US 6635914B2US 95188201 AUS95188201 AUS 95188201AUS 6635914 B2US6635914 B2US 6635914B2
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ion conductor
electrode
programmable structure
microelectronic programmable
microelectronic
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US09/951,882
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US20020168820A1 (en
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Michael N. Kozicki
Maria Mitkova
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AXON TECHNOLOGIES CORP
Axon Technologies Corp
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AXON TECHNOLOGIES CORP
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Priority to PCT/US2002/011082prioritypatent/WO2002082452A2/en
Priority to US10/163,059prioritypatent/US6914802B2/en
Priority to US10/268,107prioritypatent/US6985378B2/en
Publication of US20020168820A1publicationCriticalpatent/US20020168820A1/en
Priority to US10/335,705prioritypatent/US6865117B2/en
Priority to US10/390,268prioritypatent/US6927411B2/en
Priority to US10/452,041prioritypatent/US6998312B2/en
Priority to US10/458,551prioritypatent/US20040124407A1/en
Assigned to AXON TECHNOLOGIES CORPORATIONreassignmentAXON TECHNOLOGIES CORPORATIONASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).Assignors: KOZICKI, MICHAEL N., MITKOVA, MARIA
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Publication of US6635914B2publicationCriticalpatent/US6635914B2/en
Priority to US10/796,808prioritypatent/US7101728B2/en
Priority to US11/117,229prioritypatent/US7169635B2/en
Priority to US11/276,097prioritypatent/US7405967B2/en
Priority to US11/744,382prioritypatent/US7385219B2/en
Priority to US11/760,556prioritypatent/US7372065B2/en
Priority to US12/119,393prioritypatent/US7728322B2/en
Priority to US12/136,629prioritypatent/US7560722B2/en
Priority to US12/166,261prioritypatent/US7675766B2/en
Priority to US12/475,271prioritypatent/US8022384B2/en
Priority to US12/701,060prioritypatent/US7929331B2/en
Priority to US12/895,509prioritypatent/US8134140B2/en
Priority to US13/090,193prioritypatent/US8213217B2/en
Priority to US13/229,417prioritypatent/US8218350B2/en
Priority to US13/237,809prioritypatent/US8213218B2/en
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Abstract

A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally include an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying a bias across the electrodes, and thus information may be stored using the structure.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. patent application Ser. No. 09/502,915, entitled PROGRAMMABLE MICROELECTRONIC DEVICES AND METHODS OF FORMING AND PROGRAMMING SAME, filed Apr. 19, 2000; U.S. patent application Ser. No. 09/555,612, entitled PROGRAMMABLE SUBSURFACE AGGREGATING METALLIZATION CELL STRUCTURE AND METHOD OF MAKING SAME, filed Dec. 4, 1998; U.S. patent application Ser. No. 60/231,343, entitled COMMON ELECTRODE CONFIGURATIONS OF THE PROGRAMMABLE METALLIZATION CELL, filed Sep. 8, 2000; U.S. patent application Ser. No. 60/231,345, entitled GLASS COMPOSITION SUITABLE FOR PROGRAMMABLE METALLIZATION CELLS AND METHOD OF FORMING THE SAME, filed Sep. 8, 2000; U.S. patent application Ser. No. 60/231,350, entitled ULTRA LOW ENERGY PROGRAMMABLE METALLIZATION CELL DEVICES AND METHODS OF FORMING THE SAME, filed Sep. 8, 2000; U.S. patent application Ser. No. 60/231,427, entitled ELECTRODES FOR THE PROGRAMMABLE METALLIZATION CELL, filed Sep. 8, 2000; U.S. patent application Ser. No. 60/231,346, entitled SOLID SOLUTION FOR THE PROGRAMMABLE METALLIZATION CELL AND METHOD OF FORMING THE SAME, filed Sep. 8, 2000; U.S. patent application Ser. No. 60/231,432, entitled PROGRAMMABLE METALLIZATION CELL WITH FLOATING ELECTRODE AND METHOD OF PROGRAMMING AND FORMING THE SAME, filed Sep. 8, 2000; U.S. patent application Ser. No. 60/282,045, entitled OPTIMIZED ELECTRODES FOR THE PROGRAMMABLE METALLIZATION CELL, filed Apr. 6, 2001; U.S. patent application Ser. No. 60/283,591, entitled OPTIMIZED GLASS COMPOSITION FOR THE PROGRAMMABLE METALLIZATION CELL, filed Apr. 13, 2001; and U.S. patent application Ser. No. 60/291,886, entitled ELECTRODES FOR THE PROGRAMMABLE METALLIZATION CELL, filed May 18, 2001.
FIELD OF THE INVENTION
The present invention generally relates to microelectronic devices. More particularly, the invention relates to programmable microelectronic structures suitable for use in integrated circuits.
BACKGROUND OF THE INVENTION
Memory devices are often used in electronic systems and computers to store information in the form of binary data. These memory devices may be characterized into various types, each type having associated with it various advantages and disadvantages.
For example, random access memory (“RAM”) which may be found in personal computers is typically volatile semiconductor memory; in other words, the stored data is lost if the power source is disconnected or removed. Dynamic RAM (“DRAM”) is particularly volatile in that it must be “refreshed”(i.e., recharged) every few microseconds in order to maintain the stored data. Static RAM (“SRAM”) will hold the data after one writing so long as the power source is maintained; once the power source is disconnected, however, the data is lost. Thus, in these volatile memory configurations, information is only retained so long as the power to the system is not turned off In general, these RAM devices can take up significant chip area and therefore may be expensive to manufacture and consume relatively large amounts of energy for data storage. Accordingly, improved memory devices suitable for use in personal computers and the like are desirable.
Other storage devices such as magnetic storage devices (e.g., floppy disks, hard disks and magnetic tape) as well as other systems, such as optical disks, CD-RW and DVD-RW are non-volatile, have extremely high capacity, and can be rewritten many times. Unfortunately, these memory devices are physically large, are shock/vibration-sensitive, require expensive mechanical drives, and may consume relatively large amounts of power. These negative aspects make such memory devices non-ideal for low power portable applications such as lap-top and palm-top computers, personal digital assistants (“PDAs”), and the like.
Due, at least in part, to a rapidly growing numbers of compact, low-power portable computer systems in which stored information changes regularly, low energy read/write semiconductor memories have become increasingly desirable and widespread. Furthermore, because these portable systems often require data storage when the power is turned off, non-volatile storage device are desired for use in such systems.
One type of programmable semiconductor non-volatile memory device suitable for use in such systems is a programmable read-only memory (“PROM”) device. One type of PROM, a write-once read-many (“WORM”) device, uses an array of fusible links. Once programmed, the WORM device cannot be reprogrammed.
Other forms of PROM devices include erasable PROM (“EPROM”) and electrically erasable PROM (EEPROM) devices, which are alterable after an initial programming. EPROM devices generally require an erase step involving exposure to ultra violet light prior to programming the device. Thus, such devices are generally not well suited for use in portable electronic devices. EEPROM devices are generally easier to program, but suffer from other deficiencies. In particular, EEPROM devices are relatively complex, are relatively difficult to manufacture, and are relatively large. Furthermore, a circuit including EEPROM devices must withstand the high voltages necessary to program the device. Consequently, EEPROM cost per bit of memory capacity is extremely high compared with other means of data storage. Another disadvantage of EEPROM devices is that, although they can retain data without having the power source connected, they require relatively large amounts of power to program. This power drain can be considerable in a compact portable system powered by a battery.
In view of the various problems associated with conventional data storage devices described above, a relatively non-volatile, programmable device which is relatively simple and inexpensive to produce is desired. Furthermore, this memory technology should meet the requirements of the new generation of portable computer devices by operating at a relatively low voltage while providing high storage density and a low manufacturing cost.
SUMMARY OF THE INVENTION
The present invention provides improved microelectronic devices for use in integrated circuits. More particularly, the invention provides relatively non-volatile, programmable devices suitable for memory and other integrated circuits.
The ways in which the present invention addresses various drawbacks of now-known programmable devices are discussed in greater detail below. However, in general, the present invention provides a programmable device that is relatively easy and inexpensive to manufacture, and which is relatively easy to program.
In accordance with one exemplary embodiment of the present invention, a programmable structure includes an ion conductor and at least two electrodes. The structure is configured such that when a bias is applied across two electrodes, one or more electrical properties of the structure change. In accordance with one aspect of this embodiment, a resistance across the structure changes when a bias is applied across the electrodes. In accordance with other aspects of this embodiment, a capacitance or other electrical property of the structure changes upon application of a bias across the electrodes. One or more of these electrical changes may suitably be detected. Thus, stored information may be retrieved from a circuit including the structure.
In accordance with another exemplary embodiment of the invention, a programmable structure includes an ion conductor, at least two electrodes, and a barrier interposed between at least a portion of one of the electrodes and the ion conductor. In accordance with one aspect of this embodiment the barrier material includes a material configured to reduce diffusion of ions between the ion conductor and at least one electrode. The diffusion barrier may also serve to prevent undesired electrodeposit growth within a portion of the structure. In accordance with another aspect, the barrier material includes an insulating material. Inclusion of an insulating material increases the voltage required to reduce the resistance of the device. In accordance with yet another aspect of this embodiment, the barrier includes material that conducts ions, but which is relatively resistant to the conduction of electrons. Use of such material may reduce undesired plating at an electrode and increase the thermal stability of the device.
In accordance with another exemplary embodiment of the invention, a programmable microelectronic structure is formed on a surface of a substrate by forming a first electrode on the substrate, depositing a layer of ion conductor material over the first electrode, and depositing conductive material onto the ion conductor material. In accordance with one aspect of this embodiment, a solid solution including the ion conductor and excess conductive material is formed by dissolving (e.g., via thermal and/or photodissolution) a portion of the conductive material in the ion conductor. In accordance with a further aspect, only a portion of the conductive material is dissolved, such that a portion of the conductive material remains on a surface of the ion conductor to form an electrode on a surface of the ion conductor material.
In accordance with another embodiment of the present invention, at least a portion of a programmable structure is formed within a through-hole or via in an insulating material. In accordance with one aspect of this embodiment, a first electrode feature is formed on a surface of a substrate, insulating material is deposited onto a surface of the electrode feature, a via is formed within the insulating material, and a portion of the programmable structure is formed within the via. After the via is formed within the insulating material, a portion of the structure within the via is formed by depositing an ion conductive material onto the conductive material, depositing a second electrode material onto the ion conductive material, and, if desired, removing any excess electrode, ion conductor, and/or insulating material. In accordance with another aspect of this embodiment, only the ion conductor is formed within the via. In this case, a first electrode is formed below the insulating material an in contact with the ion conductor and the second electrode is formed above the insulating material and in contact with the ion conductor. The configuration of the via may be changed to alter (e.g., reduce) a contact area between one or more of the electrodes and the ion conductor. Reducing the cross-sectional area of the interface between the ion conductor and the electrode increases the efficiency of the device (change in electrical property per amount of power supplied to the device). In accordance with another aspect of this embodiment, the via may extend through the lower electrode to reduce the interface area between the electrode and the ion conductor. In accordance with yet another aspect of this embodiment, a portion of the ion conductor may be removed from the via or the ion conductor material may be directionally deposited into only a portion of the via to further reduce an interface between an electrode and the ion conductor.
In accordance with another embodiment of the invention, a programmable device may be formed on a surface of a substrate.
In accordance with a further exemplary embodiment of the invention, multiple bits of information are stored in a single programmable structure. In accordance with one aspect of this embodiment, a programmable structure includes a floating electrode interposed between two additional electrodes.
In accordance with yet another embodiment of the invention, multiple programmable devices are coupled together using a common electrode (e.g., a common anode or a common cathode).
In accordance with yet another embodiment of the invention, multiple programmable devices share a common electrode.
In accordance with yet a further exemplary embodiment of the present invention, a capacitance of a programmable structure is altered by causing ions within an ion conductor of the structure to migrate.
BRIEF DESCRIPTION OF THE DRAWINGS
A more complete understanding of the present invention may be derived by referring to the detailed description and claims, considered in connection with the figures, wherein like reference numbers refer to similar elements throughout the figures, and:
FIG. 1 is a cross-sectional illustration of a programmable structure formed on a surface of a substrate in accordance with the present invention;
FIG. 2 is a cross-sectional illustration of a programmable structure in accordance with an alternative embodiment of the present invention;
FIG. 3 is a current-voltage diagram illustrating current and voltage characteristics of the device illustrated in FIG. 2 in an “on” and “off” state;
FIG. 4 is a cross-sectional illustration of a programmable structure in accordance with yet another embodiment of the present invention;
FIG. 5 is a schematic illustration of a portion of a memory device in accordance with an exemplary embodiment of the present invention;
FIG. 6 is a schematic illustration of a portion of a memory device in accordance with an alternative embodiment of the present invention;
FIGS. 7 and 8 are a cross-sectional illustrations of a programmable structure having an ion conductor/electrode contact interface formed about a perimeter of the ion conductor in accordance with another embodiment of the present invention;
FIGS. 9 and 10 are a cross-sectional illustrations of a programmable structure having an ion conductor/electrode contact interface formed about a perimeter of the ion conductor in accordance with yet another embodiment of the present invention;
FIGS. 11 and 12 illustrate a programmable device having a horizontal configuration in accordance with the present invention;
FIGS. 13-19 illustrate programmable device structures with reduced electrode/ion conductor interface surface area in accordance with the present invention;
FIG. 20 illustrates a programmable device with a tapered ion conductor in accordance with the present invention;
FIGS. 21-24 illustrate a programmable device including a floating electrode in accordance with the present invention; and
FIGS. 25-29 illustrate common electrode programmable device structures in accordance with the present invention.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS
The present invention generally relates to microelectronic devices. More particularly, the invention relates to programmable structures or devices suitable for various integrated circuit applications.
FIGS. 1 and 2 illustrate programmablemicroelectronic structures100 and200 formed on a surface of asubstrate110 in accordance with an exemplary embodiment of the present invention.Structures100 and200 includeelectrodes120 and130, anion conductor140, and optionally include buffer orbarrier layers155 and/or255.
Generally,structures100 and200 are configured such that when a bias greater than a threshold voltage (VT), discussed in more detail below, is applied acrosselectrodes120 and130, the electrical properties ofstructure100 change. For example, in accordance with one embodiment of the invention, as a voltage V≧VTis applied acrosselectrodes120 and130, conductive ions withinion conductor140 begin to migrate and form an electrodeposit (e.g., electrodeposit160) at or near the more negative ofelectrodes120 and130; such an electrodeposit, however, is not required to practice the present invention. The term “electrodeposit” as used herein means any area within the ion conductor that has an increased concentration of reduced metal or other conductive material compared to the concentration of such material in the bulk ion conductor material. As the electrodeposit forms, the resistance betweenelectrodes120 and130 decreases, and other electrical properties may also change. In the absence of any insulating barriers, which are discussed in more detail below, the threshold voltage required to grow the electrodeposit from one electrode toward the other and thereby significantly reduce the resistance of the device is approximately the redox potential of the system, typically a few hundred millivolts. If the same voltage is applied in reverse, the electrodeposit will dissolve back into the ion conductor and the device will return to a high resistance state. In accordance with other embodiments of the invention, application of an electric field betweenelectrodes120 and130 may cause ions dissolved withinconductor140 to migrate and thus cause a change in the electrical properties ofdevice100, without the formation of an electrodeposit.Structures100 and200 may be used to store information and thus may be used in memory circuits. For example,structure100 or other programmable structures in accordance with the present invention may suitably be used in memory devices to replace DRAM, SRAM, PROM, EPROM, or EEPROM devices. In addition, programmable structures of the present invention may be used for other applications where programming or changing of electrical properties of a portion of an electrical circuit are desired.
Substrate110 may include any suitable material. For example,substrate110 may include semiconductive, conductive, semiinsulative, insulative material, or any combination of such materials. In accordance with one embodiment of the invention,substrate110 includes an insulatingmaterial112 and aportion114 including microelectronic devices formed on a semiconductor substrate.Layers112 and114 may be separated by additional layers (not shown) such as, for example, layers typically used to form integrated circuits. Because the programmable structures can be formed over insulating or other materials, the programmable structures of the present invention are particularly well suited for applications where substrate (e.g., semiconductor material) space is a premium.
Electrodes120 and130 may be formed of any suitable conductive material. For example,electrodes120 and130 may be formed of doped polysilicon material or metal.
In accordance with one exemplary embodiment of the invention, one ofelectrodes120 and130 is formed of a material including a metal that dissolves inion conductor140 when a sufficient bias (V≧VT) is applied across the electrodes (oxidizable electrode) and the other electrode is relatively inert and does not dissolve during operation of the programmable device (an indifferent electrode). For example,electrode120 may be an anode during a write process and be comprised of a material including silver that dissolves inion conductor140 andelectrode130 may be a cathode during the write process and be comprised of an inert material such as tungsten, nickel, molybdenum, platinum, metal silicides, and the like. Having at least one electrode formed of a material including a metal which dissolves inion conductor140 facilitates maintaining a desired dissolved metal concentration withinion conductor140, which in turn facilitates rapid andstable electrodeposit160 formation withinion conductor140 or other electrical property change during use ofstructure100 and/or200. Furthermore, use of an inert material for the other electrode (cathode during a write operation) facilitates electrodissolution of any electrodeposit that may have formed and/or return of the programmable device to an erased state after application of a sufficient voltage.
During an erase operation, dissolution of any electrodeposit that may have formed preferably begins at or near the oxidizable electrode/electrodeposit interface. Initial dissolution of the electrodeposit at the oxidizable electrode/electrodeposit interface may be facilitated by formingstructure100 such that the resistance of the at the oxidizable electrode/electrodeposit interface is greater than the resistance at any other point along the electrodeposit, particularly, the interface between the electrodeposit and the indifferent electrode.
One way to achieve relatively low resistance at the indifferent electrode is to form the electrode of relatively inert, non-oxidizing material such as platinum. Use of such material reduces formation of oxides at the interface betweenion conductor140 and the indifferent electrode as well as the formation of compounds or mixtures of the electrode material andion conductor140 material, which typically have a higher resistance thanion conductor140 or the electrode material.
Relatively low resistance at the indifferent electrode may also be obtained by forming a barrier layer between the oxidizable electrode (anode during a write operation), wherein the barrier layer is formed of material having a relatively high resistance. Exemplary high resistance materials include layers (e.g.,layer155 and/or layer255) of ion conducting material (e.g., AgxO, AgxS, AgxSe, AgxTe, where x≧2, AgyI, where x≧1, CuI2, CuO, CuS, CuSe, CuTe, GeO2, or SiO2) interposed betweenion conductor140 and a metal layer such as silver. Some of these materials have additional benefits as discussed in more detail below.
Reliable growth and dissolution of an electrodeposit can also be facilitated by providing a roughened indifferent electrode surface (e.g., a root mean square roughness of greater than about 1 nm) at the electrode/ion conductor interface. The roughened surface may be formed by manipulating film deposition parameters and/or by etching a portion of one of the electrode of ion conductor surfaces. During a write operation, relatively high electrical fields form about the spikes or peaks of the roughened surface, and thus the electrodeposits are more likely to form about the spikes or peaks. As a result, more reliable and uniform changes in electrical properties for an applied voltage acrosselectrodes120 and130 may be obtained by providing a roughed interface between the indifferent electrode (cathode during a write operation) andion conductor140.
Oxidizable electrode material may have a tendency to thermally dissolve or diffuse intoion conductor140, particularly during fabrication and/or operation ofstructure100. The thermal diffusion is undesired because it may reduce the resistance ofstructure100 and thus reduce the change of an electrical property during use ofstructure100.
To reduce undesired diffusion of oxidizable electrode material intoion conductor140 and in accordance with another embodiment of the invention, the oxidizable electrode includes a metal intercalated in a transition metal sulfide or selenide material such as Ax(MB2)1−x, where A is Ag or Cu, B is S or Se, M is a transition metal such as Ta, V, and Ti, and x ranges from about 0.1 to about 0.7. The intercalated material mitigates undesired thermal diffusion of the metal (Ag or Cu) into the ion conductor material, while allowing the metal to participate in the electrodeposit growth upon application of a sufficient voltage acrosselectrodes120 and130. For example, when silver in intercalated into a TaS2film, the TaS2film can include up to about 66.8 atomic percent silver. The Ax(MB2)1−xmaterial is preferably amorphous to prevent to prevent undesired diffusion of the metal though the material. The amorphous material may be formed by, for example, physical vapor deposition of a target material comprising Ax(MB2)1−x.
α-AgI is another suitable material for the oxidizable electrode, as well as the indifferent electrode. Similar to the Ax(MB2)1−xmaterial discussed above, α-AgI can serve as a source of Ag during operation ofstructure100—e.g., upon application of a sufficient bias, but the silver in the AgI material does not readily thermally diffuse intoion conductor140. AgI has a relatively low activation energy for conduction of electricity and does not require doping to achieve relatively high conductivity. When the oxidizable electrode is formed of AgI, depletion of silver in the AgI layer may arise during operation ofstructure100, unless excess silver is provided to the electrode. One way to provide the excess silver is to form a silver layer adjacent the AgI layer as discussed above when AgI is used as a buffer layer. The AgI layer (e.g.,layer155 and/or255) reduces thermal diffusion of Ag intoion conductor140, but does not significantly affect conduction of Ag during operation ofstructure100. In addition, use of AgI increases the operational efficiency ofstructure100 because the AgI mitigates non-Faradaic conduction (conduction of electrons that do not participate in the electrochemical reaction).
Other materials suitable forbuffer layers155 and/or255 include GeO2and SiOx. Amorphous GeO2is relatively porous an will “soak up” silver during operation ofdevice100, but will retard the thermal diffusion of silver toion conductor140, compared to structures or devices that do not include a buffer layer. Whenion conductor140 includes germanium, GeO2may be formed by exposingion conductor140 to an oxidizing environment at a temperature of about 300° C. to about 800° C. or by exposingion conductor140 to an oxidizing environment in the presence of radiation having an energy greater than the band gap of the ion conductor material. The GeO2may also be deposited using physical vapor deposition (from a GeO2target) or chemical vapor deposition (from GeH4and an O2).
Buffer layers can also be used to increase a “write voltage” by placing the buffer layer (e.g., GeO2or SiOx) betweenion conductor140 and the indifferent electrode. The buffer material allows metal such as silver to diffuse though the buffer and take part in the electrochemical reaction.
In accordance with one embodiment of the invention, at least oneelectrode120 and130 is formed of material suitable for use as an interconnect metal. For example,electrode130 may form part of an interconnect structure within a semiconductor integrated circuit. In accordance with one aspect of this embodiment,electrode130 is formed of a material that is substantially insoluble in material comprisingion conductor140. Exemplary materials suitable for both interconnect andelectrode130 material include metals and compounds such as tungsten, nickel, molybdenum, platinum, metal silicides, and the like.
Layers155 and/or255 may also include a material that restricts migration of ions betweenconductor140 and the electrodes. In accordance with exemplary embodiments of the invention, a barrier layer includes conducting material such as titanium nitride, titanium tungsten, a combination thereof, or the like. The barrier may be electrically indifferent, i.e., it allows conduction of electrons throughstructure100 or200, but it does not itself contribute ions to conduction throughstructure200. An electrically indifferent barrier may reduce undesired dendrite growth during operation of the programmable device, and thus may facilitate an “erase” or dissolution ofelectrodeposit160 when a bias is applied which is opposite to that used to grow the electrodeposit. In addition, use of a conducting barrier allows for the “indifferent” electrode to be formed of oxidizable material because the barrier prevents diffusion of the electrode material to the ion conductor.
Ion conductor140 is formed of material that conducts ions upon application of a sufficient voltage. Suitable materials forion conductor140 include glasses and semiconductor materials. In one exemplary embodiment of the invention,ion conductor140 is formed of chalcogenide material.
Ion conductor140 may also suitably include dissolved conductive material. For example,ion conductor140 may comprise a solid solution that includes dissolved metals and/or metal ions. In accordance with one exemplary embodiment of the invention,conductor140 includes metal and/or metal ions dissolved in chalcogenide glass. An exemplary chalcogenide glass with dissolved metal in accordance with the present invention includes a solid solution of AsxS1−x—Ag, GexSe1−x—Ag, GexS1−x—Ag, AsxS1−x—Cu, GexSe1−x—Cu, GexS1−x—Cu, where x ranges from about 0.1 to about 0.5 other chalcogenide materials including silver, copper, zinc, combinations of these materials, and the like. In addition,conductor140 may include network modifiers that affects mobility of ions throughconductor140. For example, materials such as metals (e.g., silver), halogens, halides, or hydrogen may be added toconductor140 to enhance ion mobility and thus increase erase/write speeds of the structure.
A solid solution suitable for use asion conductor140 may be formed in a variety of ways. For example, the solid solution may be formed by depositing a layer of conductive material such as metal over an ion conductive material such as chalcogenide glass and exposing the metal and glass to thermal and/or photo dissolution processing. In accordance with one exemplary embodiment of the invention, a solid solution of As2S3—Ag is formed by depositing As2S3onto a substrate, depositing a thin film of Ag onto the As2S3, and exposing the films to light having energy greater than the optical gap of the As2S3,—e.g., light having a wavelength of less than about 500 nanometers. If desired, network modifiers may be added toconductor140 during deposition of conductor140 (e.g., the modifier is in the deposited material or present duringconductor140 material deposition) or afterconductor140 material is deposited (e.g., by exposingconductor140 to an atmosphere including the network modifier).
In accordance with another embodiment of the invention, a solid solution may be formed by depositing one of the constituents onto a substrate or another material layer and reacting the first constituent with a second constituent. For example, germanium (preferably amorphous) may be deposited onto a portion of a substrate and the germanium may be reacted with H2Se to form a Ge—Se glass. Similarly, As can be deposited and reacted with the H2Se gas, or arsenic or germanium can be deposited and reacted with H2S gas. Silver or other metal can then be added to the glass as described above.
In accordance with one aspect of this embodiment, a solidsolution ion conductor140 is formed by depositing sufficient metal onto an ion conductor material such that a portion of the metal can be dissolved within the ion conductor material and a portion of the metal remains on a surface of the ion conductor to form an electrode (e.g., electrode120). In accordance with alternative embodiments of the invention, solid solutions containing dissolved metals may be directly deposited ontosubstrate110 and the electrode then formed overlying the ion conductor.
An amount of conductive material such as metal dissolved in an ion conducting material such as chalcogenide may depend on several factors such as an amount of metal available for dissolution and an amount of energy applied during the dissolution process. However, when a sufficient amount of metal and energy are available for dissolution in chalcogenide material using photodissolution, the dissolution process is thought to be self limiting, substantially halting when the metal cations have been reduced to their lowest oxidation state. In the case of As2S3—Ag, this occurs at Ag4As2S3=2Ag2S+As2S, having a silver concentration of about 44 atomic percent. If, on the other hand, the metal is dissolved in the chalcogenide material using thermal dissolution, a higher atomic percentage of metal in the solid solution may be obtained, provided a sufficient amount of metal is available for dissolution.
In accordance with a further embodiment of the invention, the solid solution is formed by photodissolution to form a macrohomogeneous ternary compound and additional metal is added to the solution using thermal diffusion (e.g., in an inert environment at a temperature of about 85° C. to about 150° C.) to form a solid solution containing, for example, about 30 to about 50, and preferably about 34 atomic percent silver. Ion conductors having a metal concentration above the photodissolution solubility level facilitates formation of electrodeposits that are thermally stable at operating temperatures (typically about 85° C. to about 150° C.) ofdevices100 and200. Alternatively, the solid solution may be formed by thermally dissolving the metal into the ion conductor at the temperature noted above; however, solid solutions formed exclusively from photodissolution are thought to be less homogeneous than films having similar metal concentrations formed using photodissolution and thermal dissolution.
Ion conductor140 may also include a filler material, which fills interstices or voids. Suitable filler materials include non-oxidizable and non-silver based materials such as a non-conducting, immiscible silicon oxide and/or silicon nitride, having a cross-sectional dimension of less than about 1 nm, which do not contribute to the growth of an electrodeposit. In this case, the filler material is present in the ion conductor at a volume percent of up to about 5 percent to reduce a likelihood that an electrodeposit will spontaneously dissolve into the supporting ternary material as the device is exposed to elevated temperature, which leads to more stable device operation without compromising the performance of the device.Ion conductor140 may also include filler material to reduce an effective cross-sectional area of the ion conductor. In this case, the concentration of the filler material, which may be the same filler material described above but having a cross-sectional dimension up to about 50 nm, is present in the ion conductor material at a concentration of up to about 50 percent by volume. The filler material may also include metal such as silver or copper to fill the voids in the ion conductor material.
In accordance with one exemplary embodiment of the invention,ion conductor140 includes a germanium-selenide glass with silver diffused in the glass. Germanium selenide materials are typically formed from selenium and Ge(Se)4/2tetrahedra that may combine in a variety of ways. In a Se-rich region, Ge is 4-fold coordinated and Se is 2-fold coordinated, which means that a glass composition near Ge0.20Se0.80will have a mean coordination number of about 2.4. Glass with this coordination number is considered by constraint counting theory to be optimally constrained and hence very stable with respect to devitrification. The network in such a glass is known to self-organize and become stress-free, making it easy for any additive, e.g., silver, to finely disperse and form a mixed-glass solid solution. Accordingly, in accordance with one embodiment of the invention,ion conductor140 includes a glass having a composition of Ge0.17Se0.83to Ge0.25Se0.75.
The composition and structure ofion conductor140 material often depends on the starting or target material used to form the conductor. Generally, it is desired to form a homogenous material layer forconductor140 to facilitate reliable and repeatable device performance. In accordance with one embodiment of the invention, a target for physical vapor deposition of material suitable forion conductor140 is formed by selecting a proper ampoule, preparing the ampoule, maintaining proper temperatures during formation of the glass, slow rocking the composition, and quenching the composition.
Volume and wall thickness are important factors for consideration in selecting an ampoule for forming glass. The wall thickness must be thick enough to withstand gas pressures that arise during the glass formation process and are preferably thin enough to facilitate heat exchange during the formation process. In accordance with exemplary embodiment of the invention, quartz ampoules with a wall thickness of about 1 mm are used to form Se and Te based chalcogenide glasses, whereas quartz ampoules with a wall thickness of about 1.5 mm are used to form sulfur-based chalcogenide glasses. In addition, the volume of the ampoule is preferably selected such that the volume of the ampoule is about five times greater than the liquid glass precursor material.
Once the ampoule is selected, the ampoule is prepared for glass formation, in accordance with one embodiment of the invention, by cleaning the ampoule with hydrofluoric acid, ethanol and acetone, drying the ampoule for at least 24 hours at about 120° C., evacuating the ampoule and heating the ampoule until the ampoule turns a cherry red color and cooling the ampoule under vacuum, filling ampoule with charge and evacuating the ampoule, heating the ampoule while avoiding melting of the constituents to desorb any remaining oxygen, and sealing the ampoule. This process reduces oxygen contamination, which in turn promotes macrohomogeneous growth of the glass.
The melting temperature of the glass formation process depends on the glass material. In the case of germanium-based glasses, sufficient time for the chalcogen to react at low temperature with all available germanium is desired to avoid explosion at subsequent elevated temperatures (the vapor pressure of Se at 920° C. is 10 ATM. and 20 ATM. for S at 720° C.). To reduce the risk of explosion, the glass formation process begins by ramping the ampoule temperature to about 300° C. for selenium-based glasses (about 200° C. for sulfur-based glasses) over the period of about an hour and maintaining this temperature for about 12 hours. Next, the temperature is elevated slowly (about 0.5° C./min) up to a temperature about 50° C. higher than the liquidus temperature of the material and the ampoule remains at about this temperature for about 12 hours. The temperature is then elevated to about 940° C. to ensure melting of all non-reacted germanium for Se-based glasses or about 700° C. for S-based glasses. The ampoule should remain at this elevated temperature for about 24 hours.
The melted glass composition is preferably slow rocked at a rate of about 20/minute at least about six hours to increase the homogeneity of the glass.
Quenching is preferably performed from a temperature at which the vapors and the liquid are in an equilibrium to produce vitrification of the desired composition. In this case, the quenching temperature is about 50° C. over the liquidus temperature of the glass material. Chalcogenide-rich glasses include a range of concentrations in which under-constrained and over-constrained glasses exist. In cases where the glass composition coordinated number is far from the optimal coordination (e.g., coordination numbers of about 2.4 for Ge—Se systems) the quenching rate has to be fast enough in order to ensure vitrification, e.g., quenching in ice-water or an even stronger coolant such as a mixture of urea and ice-water. In the case of optimally coordinated glasses, quenching can be performed in air at about 25° C.
In accordance with one exemplary embodiment of the invention, at least a portion ofstructure100 is formed within a via of an insulatingmaterial150. Forming a portion ofstructure100 within a via of an insulatingmaterial150 may be desirable because, among other reasons, such formation allows relatively small structures, e.g., on the order of 10 nanometers, to be formed. In addition, insulatingmaterial150 facilitates isolatingvarious structures100 from other electrical components.
Insulatingmaterial150 suitably includes material that prevents undesired diffusion of electrons and/or ions fromstructure100. In accordance with one embodiment of the invention,material150 includes silicon nitride, silicon oxynitride, polymeric materials such as polyimide or parylene, or any combination thereof.
Acontact165 may suitably be electrically coupled to one ormore electrodes120,130 to facilitate forming electrical contact to the respective electrode. Contact165 may be formed of any conductive material and is preferably formed of a metal such as aluminum, aluminum alloys, tungsten, or copper.
In accordance with one embodiment of the invention,structure100 is formed by formingelectrode130 onsubstrate110.Electrode130 may be formed using any suitable method such as, for example, depositing a layer ofelectrode130 material, patterning the electrode material, and etching the material to formelectrode130. Insulatinglayer150 may be formed by depositing insulating material ontoelectrode130 andsubstrate110 and forming vias in the insulating material using appropriate patterning and etching processes.Ion conductor140 andelectrode120 may then be formed within insulatinglayer150 by depositingion conductor140 material andelectrode120 material within the via. Such ion conductor and electrode material deposition may be selective—i.e., the material is substantially deposited only within the via, or the deposition processes may be relatively non-selective. If one or more non-selective deposition methods are used, any excess material remaining on a surface of insulatinglayer150 may be removed using, for example, chemical mechanical polishing and/or etching techniques. Barrier layers155 and/or255 may similarly be formed using any suitable deposition and/or etch processes.
Information may be stored using programmable structures of the present invention by manipulating one or more electrical properties of the structures. For example, a resistance of a structure may be changed from a “0” or off state to a “1” or on state during a suitable write operation. Similarly, the device may be changed from a “1” state to a “0” state during an erase operation. In addition, as discussed in more detail below, the structure may have multiple programmable states such that multiple bits of information are stored in a single structure.
Write Operation
FIG. 3 illustrates current-voltage characteristics of a programmable structure (e.g. structure200) in accordance with the present invention. In the illustrated embodiment, via diameter, D, is about 4 microns,conductor140 is about 35 nanometers thick and formed of Ge3Se7—Ag (near As8Ge3Se7),electrode130 is indifferent and formed of nickel,electrode120 is formed of silver, andbarrier255 is a native nickel oxide. As illustrated in FIG. 3, current throughstructure200 in an off state (curve310) begins to rise upon application of a bias of over about one volt; however, once a write step has been performed (i.e., an electrodeposit has formed), the resistance throughconductor140 drops significantly (i.e., to about 200 ohms), illustrated bycurve320 in FIG.3. As noted above, whenelectrode130 is coupled to a more negative end of a voltage supply, compared toelectrode120, an electrodeposit begins to form nearelectrode130 and grow towardelectrode120. An effective threshold voltage (i.e., voltage required to cause growth of the electrodeposit and to break throughbarrier255, thereby couplingelectrodes320,330 together is relatively high because ofbarrier255. In particular, a voltage V≧VTmust be applied to structure200 sufficient to cause electrons to tunnel through barrier255 (whenbarrier255 comprises an insulating layer) to form the electrodeposit and to overcome the barrier (e.g., by tunneling through or leakage) and conduct throughconductor140 and at least a portion ofbarrier255.
In accordance with alternate embodiments of the invention, where no insolating barrier layer is present, an initial “write” threshold voltage is relatively low because no insulative barrier is formed between, for example,ion conductor140 and either of theelectrodes120,130.
Read Operation
A state of the device (e.g., 1 or 0) may be read, without significantly disturbing the state, by, for example, applying a forward or reverse bias of magnitude less than a voltage threshold (about 1.4 V for a structure illustrated in FIG. 3) for electrodeposition or by using a current limit which is less than or equal to the minimum programming current (the current which will produce the highest of the on resistance values). A current limited (to about 1 milliamp) read operation is shown in FIG.3. In this case, the voltage is swept from 0 to about 2 V and the current rises up to the set limit (from 0 to 0.2 V), indicating a low resistance (ohmic/linear current-voltage) “on” state. Another way of performing a non-disturb read operation is to apply a pulse, with a relatively short duration, which may have a voltage higher than the electrochemical deposition threshold voltage such that no appreciable Faradaic current flows, i.e., nearly all the current goes to polarizing/charging the device and not into the electrodeposition process.
Erase Operation
A programmable structure (e.g., structure200) may suitably be erased by reversing a bias applied during a write operation, wherein a magnitude of the applied bias is equal to or greater than the threshold voltage for electrodeposition in the reverse direction. In accordance with an exemplary embodiment of the invention, a sufficient erase voltage (V≧VT) is applied to structure200 for a period of time which depends on the strength of the initial connection but is typically less than about 1 millisecond to returnstructure200 to its “off” state having a resistance well in excess of a million ohms. In cases where the programmable structure does not include a barrier betweenconductor140 andelectrode120, a threshold voltage for erasing the structure is much lower than a threshold voltage for writing the structure because, unlike the write operation, the erase operation does not require electron tunneling through a barrier or barrier breakdown.
Control of Operational Parameters
The concentration of conductive material in the ion conductor can be controlled by applying a bias across the programmable device. For example, metal such as silver may be taken out of solution by applying a negative voltage in excess of the reduction potential of the conductive material. Conversely, conductive material may be added to the ion conductor (from one of the electrodes) by applying a bias in excess of the oxidation potential of the material. Thus, for example, if the conductive material concentration is above that desired for a particular device application, the concentration can be reduced by reverse biasing the device to reduce the concentration of the conductive material. Similarly, metal may be added to the solution from the oxidizable electrode by applying a sufficient forward bias. Additionally, it is possible to remove excess metal build up at the indifferent electrode by applying a reverse bias for an extended time or an extended bias over that required to erase the device under normal operating conditions. Control of the conductive material may be accomplished automatically using a suitable microprocessor.
This technique may also be used to form one of the electrodes from material within the ion conductor material. For example, silver from the ion conductor may be plated out to form the oxidizable electrode. This allows the oxidizable electrode to be formed after the device is fully formed and thus mitigates problems associated with conductive material diffusing from the oxidizable electrode during manufacturing of the device.
As noted above, in accordance with yet another embodiment of the invention, multiple bits of data may be stored within a single programmable structure by controlling an amount of electrodeposit which is formed during a write process. An amount of electrodeposit that forms during a write process depends on a number of coulombs or charge supplied to the structure during the write process, and may be controlled by using a current limit power source. In this case, a resistance of a programmable structure is governed by Equation 1, where Ronis the “on” state resistance, VTis the threshold voltage for electrodeposition , and ILIMis the maximum current allowed to flow during the write operation.Ron=VTILIMEquation1
Figure US06635914-20031021-M00001
In practice, the limitation to the amount of information stored in each cell will depend on how stable each of the resistance states is with time. For example, if a structure is with a programmed resistance range of about 3.5 kΩ and a resistance drift over a specified time for each state is about ±250Ω, about 7 equally sized bands of resistance (7 states) could be formed, allowing 3 bits of data to be stored within a single structure. In the limit, for near zero drift in resistance in a specified time limit, information could be stored as a continuum of states, i.e., in analog form.
A portion of anintegrated circuit402, including aprogrammable structure400, configured to provide additional isolation from electronic components is illustrated in FIG.4. In accordance with an exemplary embodiment of the present invention,structure400 includeselectrodes420 and430, anion conductor440, acontact460, and anamorphous silicon diode470, such as a Schottky or p-n junction diode, formed betweencontact460 andelectrode420. Rows and columns ofprogrammable structures400 may be fabricated into a high density configuration to provide extremely large storage densities suitable for memory circuits. In general, the maximum storage density of memory devices is limited by the size and complexity of the column and row decoder circuitry. However, a programmable structure storage stack can be suitably fabricated overlying an integrated circuit with the entire semiconductor chip area dedicated to row/column decode, sense amplifiers, and data management circuitry (not shown) sincestructure400 need not use any substrate real estate. In this manner, storage densities of many gigabits per square centimeter can be attained using programmable structures of the present invention. Utilized in this manner, the programmable structure is essentially an additive technology that adds capability and functionality to existing semiconductor integrated circuit technology.
FIG. 5 schematically illustrates a portion of a memorydevice including structure400 having an isolatingp-n junction470 at an intersection of abit line510 and aword line520 of a memory circuit. FIG. 6 illustrates an alternative isolation scheme employing atransistor610 interposed between an electrode and a contact of a programmable structure located at an intersection of abit line610 and aword line620 of a memory device.
FIGS. 7-10 illustrate programmable devices in accordance with another embodiment of the invention. The devices illustrated in FIGS. 7-10 have an electrode (e.g., the cathode during a write process) with a smaller cross sectional area in contact with the ion conductor compared to the devices illustrated in FIGS. 1-2 and4. The smaller electrode interface area is thought to increase the efficiency and endurance of the device because an increased percentage of ions in the solid solution are able to take part in the electrodeposit formation process. Thus any cathode plating from ions that do not participate in the electrodeposit process is reduced.
FIGS. 7 and 8 illustrate a cross sectional and a top cut-away view of aprogrammable device700 including anindifferent electrode710, anoxidizable electrode720, and anion conductor730 former overlying an insulatinglayer740 such as silicon oxide, silicon nitride, or the like.
Structure700 is formed by depositing an indifferent electrode material layer and an insulatinglayer750 overlying insulatinglayer740. A via is then formed throughlayer750 andelectrode material layer710, using an anisotropic etch process (e.g., reactive ion etching or ion milling) such that the via extends to and/or through a portion oflayer740. The via is then filled with ion conductor material and is suitably doped to form a solid solution as described herein. Any excess ion conductor material is removed from the surface oflayer750 andelectrode730 is formed, for example using a deposition and etch process. In this case, the indifferent electrode (cathode during write process) area in contact withion conductor730 is the surface area ofelectrode710 about the perimeter ofconductor730, rather than the area underlying the ion conductor, as illustrated in FIGS. 1-2 and4.
FIGS. 9 and 10 illustrate aprogrammable device900 having anindifferent electrode910, anoxidizable electrode920, anion conductor930 and insulatinglayers940 and950 in accordance with yet another embodiment of the invention.Structure900 is similar tostructure700, except that once a via is formed throughlayer750, an isotropic etch process (e.g., chemical or plasma) is employed to form the via throughelectrode910, such that a sloped intersection between anion conductor930 andelectrode910 is formed.
FIGS. 11 and 12 illustrate anotherprogrammable device1100, with a reduced electrode/ion conductor interface, in accordance with the present invention.Structure1100 includeselectrodes1110 and1120 and anion conductor1130, formed on a surface of an insulatingmaterial1140, rather than within a via as discussed above. In this case, the programmable structure is formed by defining anion conductor1130 patter on a surface of insulating material1140 (e.g., using deposition and etch techniques) and formingelectrodes1110 and1120, such that the electrodes each contact a portion of the ion conductor. In the case of the illustrated embodiment, the electrodes are formed overlying and in contact with both a portion of the ion conductor and the insulating material. Although the thickness of the layers may be varied in accordance with specific applications of the device, in a preferred embodiment of the invention, the thickness of the ion conductor and electrode films is about 1 nm to about 100 nm. Sub-lithographic lateral dimensions of portions of the device may be obtained by overexposing photoresist used to pattern the portions and/or over etching the film layer.
FIG. 13 illustrates adevice1300 in accordance with yet another embodiment of the invention.Structure1300 is similar to the devices illustrated in FIGS. 7 and 8, except that the cross-sectional area of the ion conductor that is in contact with the electrodes is reduced by filling a portion of a via with non-ion conductor material, rather than etching through an electrode layer.
Structure1300 includeselectrodes1310 and1320 and anion conductor1330 formed within an insulatinglayer1340. In this case,ion conductor1330 is formed by creating a trench within insulatinglayer1340, the trench having a diameter indicated by D2. The trench is then filled using, for example, interference lithography techniques or conformally lining the via with insulating material and using an anisotropic etch process to remove some of the insulating material, leaving a via with a diameter of D3.Structure1300 formed using this technique may have a ion conductor cross sectional area as small as about 10 nm in contact withelectrodes1310 and1320.
FIGS. 14-17 illustrate another embodiment of the invention, where the cross sectional area of the ion conductor/electrode interface is relatively small.Structure1400, illustrated in FIG. 14, includeselectrodes1410 and1420 and anion conductor1430.Structure1400 is formed in a manner similar tostructure700, except that the ion conductor material is deposited conformally, using, for example chemical vapor deposition or physical vapor deposition, into a trench, and the trench is not filled with the ion conductor material.
Structure1500 is similar tostructure1400, except that anion conductor1530 is formed by etching a portion ofion conductor1430, such that a via1540 is formed through toelectrode1410.Structure1600 is similar tostructure1500 and is formed by conformally depositing the ion conductor material as described above and then removing the ion conductor material from a surface of insulatingmaterial1450 prior to depositingelectrode1420 material. Finally,structure1700 may be formed by selectively deposing theion conductor1730 material into only a portion of the trench formed in insulating material1450 (e.g., using angled deposition and/or shadowing techniques), removing any excess ion conductor material on the surface ofinsulator1450, and forming anelectrode1720 overlying the insulator and in contact withion conductor1730.
FIGS. 18 and 19 illustrate yet another embodiment of the invention, where a pillar or wall within a trench is used to reduce a cross-sectional area of the interface between the ion conductor and one or more electrodes.Structure1800, illustrated in FIG. 18, includeselectrodes1810 and1820 and anion conductor1830 formed within an insulatinglayer1840. In addition,structure1800 includes apillar1850 of insulating material (e.g., insulating material used to form layer1840), formed within a trench withinlayer1840.Structure1800 may be formed using the shadowed deposition technique discussed above.Structure1900 is similar tostructure1800, exceptstructure1900 includes apartial pillar1950 and anion conductor1930, which fills the remaining portion of the formed trench.
FIG. 20 illustrates yet anotherstructure2000 in accordance with the present invention.Structure2000 includeselectrodes2010 and2020 and anion conductor2030 formed within an insulatinglayer2040.Structure2000 is formed using an anisotropic or a combination of an anisotropic and an isotropic etch processes to form a tapered via.Ion conductor2030 is then formed within the trench using techniques previously described.
FIGS. 21-24 illustrate programmable devices in accordance with yet another embodiment of the invention. The structures illustrated in FIGS. 21-24 include a floating electrode, which allows multiple bits of information to be stored within a single programmable device.
Structure2100 includes afirst electrode2110, a second, floatingelectrode2120, athird electrode2130,ion conductor portions2140 and2150, which may all be formed on a substrate or wholly or partially formed within a via as described above. Althoughstructure2100 is illustrated in a vertical configuration, the structure may be formed in a horizontal configuration, similar tostructure1100. In accordance with one aspect of this embodiment, the first and third electrodes are formed of an indifferent electrode and the second electrode is formed of an oxidizable electrode material. Alternatively, the first and third electrodes may be formed of oxidizable electrode material and the second, floating electrode may be formed of an indifferent electrode material. In either case, the structure includes two “half cells,” where each half cell functions as a programmable device described above in connection with FIG.1. Each half cell is preferably configured such that the resistance of one half cell differs from the resistance of the other half cell when both cells are in an erased state.
In the case when floatingelectrode2120 is formed of oxidizable electrode material, bits of data may be stored as follows. The overall impedance ofstructure2100 is approximately equal to the resistance ofportions2140 and2150. When no electrodeposit is formed within either portion, this high resistance state may be represent by thestate00. When a voltage is applied tostructure2100, such thatelectrode2130 is positive relative toelectrode2110 and the applied bias is greater that the threshold voltage required to form an electrodeposit inportion2140, anelectrodeposit2160 will form throughconductor portion2140 fromelectrode2110 toward floatingelectrode2120 as illustrated in FIG.22. Under this condition, an electrodeposit will not form withinconductor portion2150 becauseportion2150 is under a reverse bias condition and thus will not support growth of an electrodeposit. The growth of the electrodeposit will change the impedance ofportion2140 from Z1to Z1′, thus changing the overall impedance ofstructure2100, which may be represent by thestate01. The current level used to formelectrodeposit2160 should be selected such that it is sufficiently low, allowing the electrodeposit to be dissolved upon application of a sufficient reverse bias. A third state may be formed by reversing the polarity of the applied bias acrosselectrodes2110 and2130, such that most of the voltage drop occurs across the high resistanceion conductor portion2150 and formation of anelectrodeposit2170 begins, as illustrated in FIG. 23, without causing electrodeposit2160 to dissolve. The impedance ofportion2150 changes from Z2to Z2′, and the overall impedance ofstructure2100 is Z1′ plus Z2′, which may be represented by thestate11. Once both half cells are in the write state,electrodeposit2160 and/or2170 may be dissolved by applying a sufficient bias across one or both of the half cells.Electrodeposit2170 can be erased, for example, by sufficiently negatively biasingelectrode2130 with respect toelectrode2110, which may be represented by astate00. The four possible states, along with the current limit used to form the state, are represented in table 1 below.
TABLE 1
CurrentState/
Seq #PolaritylimitZ half-cell 1Z half-cell 2value
1Sub-thresholdZeroZ1Z200
2Upper + Lower −LowZ1Z201
3Upper − Lower +LowZ1Z211
4Upper − Lower +HighZ1Z210
Structure2100 can be changed to11 fromstate10 by applying a low current limit bias to growelectrodeposit2150 inportion2140. Similarly,structure2100 can be changed fromstate11 tostate01 by dissolvingelectrodeposit2170 by applying a relatively high current limit bias such thatupper electrode2130 is positive with respect tolower electrode2110. Finally,structure2100 can be returned tostate00 using a short current pulse to thermally dissolveelectrodeposit2160, using a current which is high enough to cause localized heating of the electrodeposit. This will increase the metal concentration in the half-cell but this excess metal can be removed electrically from the cell by plating it back onto the floating electrode. This sequence is summarized in table 2 below.
TABLE 2
CurrentState/
Seq #PolaritylimitZ half-cell 1Z half-cell 2value
4Existing stateZ1Z210
5Upper + Lower −LowZ1Z211
6Upper + Lower −HighZ1Z201
7Upper + Lower −ThermalZ1Z200
Other write and erase sequences are also possible (as are other definitions of the various states represented by the half-cell impedances). For example, it is possible to go fromstate00 to eitherstate01 orstate10, depending on the write polarity chosen. Similarly, it is possible to go fromstate11 to eitherstate10 orstate01. It is also possible to go fromstate11 tostate00 by the application of a current pulse (in either direction) which is high and short enough to thermally dissolve the electrodeposits in both half-cells simultaneously.
In addition to storing information in digital form,structure2100 can also be used as a noise-tolerant, low energy anti-fuse element for use in field programmable gate arrays (FPGAs) and field configurable circuits and systems. Most physical anti-fuse technologies require large currents and voltages to make a permanent connection. The need for such high energy state-switching stimuli is generally considered to be somewhat beneficial as this reduces the likelihood of the anti-fuse accidentally forming a connection in electrically noisy situations. However, the use of high voltages and large currents on chip represent a significant problem as all components in the programming circuits are typically sized accordingly and the high energy consumption reduces battery life in portable systems.
FIGS. 25-29 illustrate structures in accordance with another embodiment of the invention in which multiple programmable devices include a common electrode (e.g., the devices share a common anode or cathode. Forming structures in which multiple structures share a common electrode is advantageous because such structures allow a higher density of cells to be formed on a given substrate surface area.
FIGS. 25 and 26 illustrate astructure2500, having a horizontal configuration and a common electrode.Structure2500 includes anelectrical connector2510 coupled to acommon surface electrode2520,electrodes2530 and2540, andion conductor portions2550 and2560 overlying an insulatinglayer2170.Structure2500 may be used to form word and bit lines as described above by forming a row of electrodes (e.g., anodes) coupled toconductor2510, and columns of oppositely bias electrodes (e.g., cathodes) running perpendicular toelectrodes2520. A conductive plug, formed of any suitably conducting material can be used toelectrically couple electrode2520 toconductor2510. Although illustrated with a horizontal configuration, common electrode structures in accordance with this embodiment may be formed using structures having a vertical configuration as described herein.
FIGS. 27 and 28 illustrateadditional structures2700 and2800 having a common electrode shared between two ormore devices Structures2700 and2800 include a common electrode,electrodes2720 and2725,ion conductors2730,2735 and2830,2835 respectively, and insulatinglayers2740 and2750.Structures2700 and2800 may be formed using techniques described above in connection with FIGS.15 and16—e.g., by conformally depositing ion conductor material within a trench of an insulating layer. In accordance with another embodiment of the invention, directional deposition may be used to form a structure similar tostructure1700.Structures2700 and2800 each include two programmable devices includingcommon electrode2710 an ion conductor (e.g., conductor2735) and another electrode (e.g., electrode2725).Dielectric material2750 is an insulating material that does not interfere with surface electrodeposit growth, such as silicon oxides, silicon nitrides, and the like.
FIG. 29 illustrates astructure2900 including multiple programmable devices2902-2916 formed about acommon electrode2920. Each of the devices2902-2916 may be formed using the method described above in connection with FIG.21. In the embodiment illustrated in FIG. 29, each of electrodes2930-2936 and2938-2944 may be coupled together in a direction perpendicular to the direction ofcommon electrode2920, such thatelectrode2920 forms a bit line and electrodes2930-2936 and electrodes2938-2944 form word lines.Structure2900 may operate and be programmed in a manner similar tostructure2100 described above.
In accordance with other embodiments of the present invention, a programmable structure or device stores information by storing a charge as opposed to growing an electrodeposit. A capacitance of a structure or device is altered by applying a bias across electrodes of the device such that positively charged ions migrate toward one of the electrodes. If the applied bias is less that a write threshold voltage, no short will form between the electrodes. Capacitance of the structure changes as a result of the ion migration. When the applied bias is removed, the metal ions tend to diffuse away from the electrode or a barrier proximate the electrode. However, an interface between an ion conductor and a barrier is generally imperfect and includes defects capable of trapping ions. Thus, at least a portion of ions remain at or proximate an interface between a barrier and an ion conductor. If a write voltage is reversed, the ions may suitably be dispersed away from the interface.
A programmable structure in accordance with the present invention may be used in many applications which would otherwise utilize traditional technologies such as EEPROM, FLASH or DRAM. Advantages provided by the present invention over present memory techniques include, among other things, lower production cost and the ability to use flexible fabrication techniques which are easily adaptable to a variety of applications. The programmable structures of the present invention are especially advantageous in applications where cost is the primary concern, such as smart cards and electronic inventory tags. Also, an ability to form the memory directly on a plastic card is a major advantage in these applications as this is generally not possible with other forms of semiconductor memories.
Further, in accordance with the programmable structures of the present invention, memory elements may be scaled to less than a few square microns in size, the active portion of the device being less than on micron. This provides a significant advantage over traditional semiconductor technologies in which each device and its associated interconnect can take up several tens of square microns.
Additionally, the devices of the present invention require relatively low energy and do not require “refreshing.” Thus, the devices are well suitable for portable device applications.
Although the present invention is set forth herein in the context of the appended drawing figures, it should be appreciated that the invention is not limited to the specific form shown. For example, while the programmable structure is conveniently described above in connection with programmable memory devices, the invention is not so limited; the structure of the present invention may suitably be employed as programmable active or passive devices within a microelectronic circuit. Furthermore, although only some of the devices are illustrated as including buffer, barrier, or transistor components, any of these components may be added to the devices of the present invention. Various other modifications, variations, and enhancements in the design and arrangement of the method and apparatus set forth herein, may be made without departing from the spirit and scope of the present invention as set forth in the appended claims.

Claims (31)

We claim:
1. A microelectronic programmable structure comprising:
an ion conductor formed of an ion conductive material and conductive ions;
an oxidizable electrode proximate the ion conductor; and
an indifferent electrode proximate the ion conductor.
2. The microelectronic programmable structure ofclaim 1, further comprising a buffer layer between the oxidizable electrode and the ion conductor.
3. The microelectronic programmable structure ofclaim 2, wherein the buffer layer comprises a material selected from the group consisting of AgxO, AgxS, AgxSe, AgxTe, where x≧2, AgyI, where y≧1, CuI2, CuO, CuS, CuSe, CuTe, GeO2, and SiO2.
4. The microelectronic programmable structure ofclaim 1, wherein the indifferent electrode comprises platinum.
5. The microelectronic programmable structure ofclaim 1, wherein the oxidizable electrode comprises a material selected from the group consisting of a transition metal sulfide and a transition metal selenide.
6. The microelectronic programmable structure ofclaim 5, wherein the oxidizable electrode further comprises intercalated silver.
7. The microelectronic programmable structure ofclaim 5, wherein the oxidizable electrode comprises TaS2.
8. The microelectronic programmable structure ofclaim 1, wherein the oxidizable electrode comprises AgI.
9. The microelectronic programmable structure ofclaim 8, wherein the oxidizable electrode comprises excess silver.
10. The microelectronic programmable structure ofclaim 1, wherein the ion conductor comprises a solid solution selected from the group consisting of AsxS1−x—Ag, GexSe1−x—Ag, GexS1−x—Ag, AsxS1−x—Cu, GexSe1−x—Cu, GexS1−x—Cu, where x ranges from about 0.1 to about 0.5.
11. The microelectronic programmable structure ofclaim 10, wherein the ion conductor comprises a filler material.
12. The microelectronic programmable structure ofclaim 11, wherein the filler material comprises a dielectric and is present in the ion conductor at a volume percent of up to about 50 percent.
13. The microelectronic programmable structure ofclaim 11, wherein the filler material comprises a dielectric and is present in the ion conductor at a volume percent of up to about 5 percent.
14. The microelectronic programmable structure ofclaim 11, wherein the filler material comprises silver.
15. The microelectronic programmable structure ofclaim 1, wherein the ion conductor comprises a glass having a composition of Ge0.17Se0.83to Ge0.25Se0.75.
16. The microelectronic programmable structure ofclaim 15, wherein the ion conductor further comprises up to about 34 percent silver.
17. The microelectronic programmable structure ofclaim 1, further comprising a transistor in contact with one of the oxidizable or the indifferent electrodes.
18. The microelectronic programmable structure ofclaim 1, further comprising a diode in contact with one of the oxidizable or the indifferent electrodes.
19. The microelectronic programmable structure ofclaim 1, wherein the ion conductor is formed within a via in an insulating material layer.
20. The microelectronic programmable structure ofclaim 19, further comprising a diode formed within the via.
21. The microelectronic programmable structure ofclaim 19, wherein the ion conductor contacts the indifferent electrode about a portion of the perimeter of the ion conductor.
22. The microelectronic programmable structure ofclaim 21, wherein the ion conductor contacts the indifferent electrode about a sloped portion of the perimeter of the ion conductor.
23. The microelectronic programmable structure ofclaim 1, wherein the indifferent electrode, the oxidizable electrode, and the ion conductor are formed on a surface of an insulating material layer.
24. The microelectronic programmable structure ofclaim 1, wherein the ion conductor is formed within a via of a first insulating material layer, and wherein the programmable structure further comprises a second insulating material formed within the via.
25. The microelectronic programmable structure ofclaim 1, wherein the ion conductor is formed along a sidewall of a via formed within an insulating layer.
26. The microelectronic programmable structure ofclaim 1, wherein the ion conductor is formed within a sloped via within an insulating material layer.
27. The microelectronic programmable structure ofclaim 1, further comprising a barrier layer between the indifferent electrode and the ion conductor.
28. The microelectronic programmable structure ofclaim 27, wherein the barrier layer comprises a conductive material.
29. The microelectronic programmable structure ofclaim 27, wherein the barrier layer comprises an insulating material.
30. The microelectronic programmable structure ofclaim 1, wherein surface area of the indifferent electrode in contact with the ion conductor is less than the surface area of the oxidizable electrode in contact with the ion conductor.
31. The microelectronic programmable structure ofclaim 1, wherein an interface between the indifferent electrode and the ion conductor is roughened.
US09/951,8821998-12-042001-09-10Microelectronic programmable device and methods of forming and programming the sameExpired - LifetimeUS6635914B2 (en)

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US09/951,882US6635914B2 (en)2000-09-082001-09-10Microelectronic programmable device and methods of forming and programming the same
AU2002311808AAU2002311808A1 (en)2001-04-062002-04-08Microelectronic device, structure, and system, including a memory structure having a variable programmable property and method of forming the same
PCT/US2002/011082WO2002082452A2 (en)2001-04-062002-04-08Microelectronic device, structure, and system, including a memory structure having a variable programmable property and method of forming the same
US10/163,059US6914802B2 (en)2000-02-112002-06-04Microelectronic photonic structure and device and method of forming the same
US10/268,107US6985378B2 (en)1998-12-042002-10-09Programmable microelectronic device, structure, and system and method of forming the same
US10/335,705US6865117B2 (en)2000-02-112003-01-02Programming circuit for a programmable microelectronic device, system including the circuit, and method of forming the same
US10/390,268US6927411B2 (en)2000-02-112003-03-17Programmable structure, an array including the structure, and methods of forming the same
US10/452,041US6998312B2 (en)1998-12-042003-05-30Microelectronic programmable device and methods of forming and programming the same
US10/458,551US20040124407A1 (en)2000-02-112003-06-09Scalable programmable structure, an array including the structure, and methods of forming the same
US10/796,808US7101728B2 (en)2000-02-112004-03-08Programmable structure including an oxide electrolyte and method of forming programmable structure
US11/117,229US7169635B2 (en)2000-02-112005-04-28Programmable structure, an array including the structure, and methods of forming the same
US11/276,097US7405967B2 (en)1998-12-042006-02-14Microelectronic programmable device and methods of forming and programming the same
US11/744,382US7385219B2 (en)2000-02-112007-05-04Optimized solid electrolyte for programmable metallization cell devices and structures
US11/760,556US7372065B2 (en)2000-02-112007-06-08Programmable metallization cell structures including an oxide electrolyte, devices including the structure and method of forming same
US12/119,393US7728322B2 (en)2000-02-112008-05-12Programmable metallization cell structures including an oxide electrolyte, devices including the structure and method of forming same
US12/136,629US7560722B2 (en)2000-02-112008-06-10Optimized solid electrolyte for programmable metallization cell devices and structures
US12/166,261US7675766B2 (en)2000-02-112008-07-01Microelectric programmable device and methods of forming and programming the same
US12/475,271US8022384B2 (en)2000-02-112009-05-29Optimized solid electrolyte for programmable metallization cell devices and structures
US12/701,060US7929331B2 (en)2000-07-272010-02-05Microelectronic programmable device and methods of forming and programming the same
US12/895,509US8134140B2 (en)2000-02-112010-09-30Programmable metallization cell structure including an integrated diode, device including the structure, and method of forming same
US13/090,193US8213217B2 (en)2000-07-272011-04-19Microelectronic programmable device and methods of forming and programming the same
US13/229,417US8218350B2 (en)2000-02-112011-09-09Programmable metallization cell structure including an integrated diode, device including the structure, and method of forming same
US13/237,809US8213218B2 (en)2000-02-112011-09-20Optimized solid electrolyte for programmable metallization cell devices and structures

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US23143200P2000-09-082000-09-08
US23134500P2000-09-082000-09-08
US23135000P2000-09-082000-09-08
US23134600P2000-09-082000-09-08
US23142700P2000-09-082000-09-08
US23134300P2000-09-082000-09-08
US28204501P2001-04-062001-04-06
US28359101P2001-04-132001-04-13
US29188601P2001-05-182001-05-18
US09/951,882US6635914B2 (en)2000-09-082001-09-10Microelectronic programmable device and methods of forming and programming the same

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US10/118,276Continuation-In-PartUS6825489B2 (en)1998-12-042002-04-08Microelectronic device, structure, and system, including a memory structure having a variable programmable property and method of forming the same
US10/163,059Continuation-In-PartUS6914802B2 (en)2000-02-112002-06-04Microelectronic photonic structure and device and method of forming the same
US10/268,107Continuation-In-PartUS6985378B2 (en)1998-12-042002-10-09Programmable microelectronic device, structure, and system and method of forming the same
US10/452,041DivisionUS6998312B2 (en)1998-12-042003-05-30Microelectronic programmable device and methods of forming and programming the same
US11/276,097DivisionUS7405967B2 (en)1998-12-042006-02-14Microelectronic programmable device and methods of forming and programming the same
US11/744,382Continuation-In-PartUS7385219B2 (en)2000-02-112007-05-04Optimized solid electrolyte for programmable metallization cell devices and structures

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Cited By (97)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US20030192350A1 (en)*2002-04-122003-10-16Stefan UhlenbrockLarge scale synthesis of germanium selenide glass and germanium selenide glass compounds
US20030209728A1 (en)*1998-12-042003-11-13Kozicki Michael N.Microelectronic programmable device and methods of forming and programming the same
US20040044841A1 (en)*2002-08-292004-03-04Gilton Terry L.Software refreshed memory device and method
US20040161894A1 (en)*2000-12-082004-08-19Gilton Terry L.Non-volatile resistance variable devices and method of forming same, analog memory devices and method of forming same, programmable memory cell and method of forming same, and method of structurally changing a non-volatile device
US6813176B2 (en)2001-08-302004-11-02Micron Technology, Inc.Method of retaining memory state in a programmable conductor RAM
US20050045920A1 (en)*2003-09-032005-03-03Kozicki Michael N.Micromechanical structure, device including the structure, and methods of forming and using same
US6864521B2 (en)*2002-08-292005-03-08Micron Technology, Inc.Method to control silver concentration in a resistance variable memory element
US20050077515A1 (en)*2003-10-082005-04-14Kostylev Sergey A.Programmable resistance memory element with threshold switching material
US6888155B2 (en)2001-08-302005-05-03Micron Technology, Inc.Stoichiometry for chalcogenide glasses useful for memory devices and method of formation
US20050094461A1 (en)*2003-09-022005-05-05Martin PernerIntegrated semiconductor memory
US6930909B2 (en)2003-06-252005-08-16Micron Technology, Inc.Memory device and methods of controlling resistance variation and resistance profile drift
US20050250281A1 (en)*2004-04-262005-11-10Infineon Technologies AgMethod for manufacturing resistively switching memory devices
US20060044878A1 (en)*2004-09-022006-03-02Perner Frederick AProgramming of programmable resistive memory devices
US20060077706A1 (en)*2004-10-082006-04-13Chien-Ming LiMultilevel phase-change memory, operating method and manufacture method thereof
US20060077741A1 (en)*2004-10-082006-04-13Wen-Han WangMultilevel phase-change memory, manufacturing and status transferring method thereof
US20060142905A1 (en)*2004-12-292006-06-29Snap-On IncorporatedVehicle or engine diagnostic systems with advanced non-volatile memory
US20060142906A1 (en)*2004-12-292006-06-29Snap-On IncorporatedVehicle or engine diagnostic systems supporting fast boot and reprogramming
DE102005004593A1 (en)*2005-02-012006-08-17Infineon Technologies AgIntegrated semiconductor memory e.g. dynamic random access memory, has electrolytic memory cells whose thickness sequence is oriented in memory cell planes, where ohmic resistance of sequence is reduced by applying programming current
US20060240616A1 (en)*2005-04-222006-10-26Micron Technology, Inc.Memory elements having patterned electrodes and method of forming the same
JP2006344976A (en)*2005-06-102006-12-21Hynix Semiconductor IncPhase transformation memory element and its manufacturing method
US7183141B1 (en)2001-05-072007-02-27Spansion LlcReversible field-programmable electric interconnects
US7190048B2 (en)*2004-07-192007-03-13Micron Technology, Inc.Resistance variable memory device and method of fabrication
EP1686590A3 (en)*2005-01-282007-04-11Infineon Technologies AGIntegrated semiconductor memory comprising an arrangement of non-volatile storage cells and method
US20070097481A1 (en)*2005-10-112007-05-03Sage Electrochromics, Inc.Electrochromic devices having improved ion conducting layers
US20070102691A1 (en)*2002-02-202007-05-10Campbell Kristy ASilver-selenide/chalcogenide glass stack for resistance variable memory
US20070285967A1 (en)*2003-03-182007-12-13Kabushiki Kaisha ToshibaResistance change memory device
US20070285966A1 (en)*2003-03-182007-12-13Kabushiki Kaisha ToshibaResistance change memory device
US7326950B2 (en)*2004-07-192008-02-05Micron Technology, Inc.Memory device with switching glass layer
US7354793B2 (en)*2004-08-122008-04-08Micron Technology, Inc.Method of forming a PCRAM device incorporating a resistance-variable chalocogenide element
US20080217600A1 (en)*2007-03-092008-09-11Commissariat A L'energie AtomiqueMulti-level data memorisation device with phase change material
US20080237567A1 (en)*2000-02-112008-10-02Axon Technologies CorporationOptimized solid electrolyte for programmable metallization cell devices and structures
US20080265285A1 (en)*2000-02-112008-10-30Axon Technologies CorporationMicroelectronic programmable device and methods of forming and programming the same
US7460698B2 (en)1996-09-252008-12-02Kabushiki Kaisha ToshibaUltrasonic picture processing method and ultrasonic picture processing apparatus
US20080310211A1 (en)*2007-06-122008-12-18Kabushiki Kaisha ToshibaResistance change memory device
JP2009065184A (en)*2006-03-302009-03-26Panasonic Corp Nonvolatile memory element and manufacturing method thereof
US20090212273A1 (en)*2008-02-212009-08-27Samsung Electronics Co., Ltd.Semiconductor Devices Having Resistive Memory Elements
US20090233421A1 (en)*2008-03-172009-09-17Samsung Electronics Co., Ltd,Methods of Fabricating Semiconductor Device Including Phase Change Layer
US20090251199A1 (en)*2005-09-272009-10-08National Institute Of Advanced Industrial Science And TechnologySwitching Element
US20090289371A1 (en)*2005-12-152009-11-26Nec CorporationSwitching element and method of manufacturing the same
US20100038619A1 (en)*2007-03-282010-02-18Ayuka TadaVariable resistance element, manufacturing method thereof, and electronic device
US20100140582A1 (en)*2008-12-062010-06-10James NesselChalcogenide nanoionic-based radio frequency switch
US20100157688A1 (en)*2008-12-232010-06-24Actel CorporationPush-pull memory cell configured for simultaneous programming of n-channel and p-channel non-volatile transistors
WO2010077622A1 (en)2008-12-082010-07-08Arizona Board Of Regents, Acting For And On Behalf Of Arizona State UniversityElectrical devices including dendritic metal electrodes
US20100195371A1 (en)*2007-08-062010-08-05Sony CorporationMemory element and memory device
US20100208520A1 (en)*2009-02-132010-08-19Actel CorporationArray and control method for flash based fpga cell
US7791058B2 (en)2006-08-292010-09-07Micron Technology, Inc.Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication
US20110001108A1 (en)*2009-07-022011-01-06Actel CorporationFront to back resistive random access memory cells
US20110038497A1 (en)*2007-11-182011-02-17Arizona Board Of Regents, Acting For And On Behalf Of Arizona State UniversityMicrophone Devices and Methods for Tuning Microphone Devices
US7968927B2 (en)2005-04-222011-06-28Micron Technology, Inc.Memory array for increased bit density and method of forming the same
US20110315947A1 (en)*2000-02-112011-12-29Axon Technologies CorporationProgrammable metallization cell structure including an integrated diode, device including the structure, and method of forming same
US8107273B1 (en)2008-07-282012-01-31Adesto Technologies CorporationIntegrated circuits having programmable metallization cells (PMCs) and operating methods therefor
US8274842B1 (en)2008-09-252012-09-25Adesto Technologies CorporationVariable impedance memory device having simultaneous program and erase, and corresponding methods and circuits
US8294488B1 (en)2009-04-242012-10-23Adesto Technologies CorporationProgrammable impedance element circuits and methods
US8331128B1 (en)2008-12-022012-12-11Adesto Technologies CorporationReconfigurable memory arrays having programmable impedance elements and corresponding methods
US20120314479A1 (en)*2011-06-102012-12-13Sony CorporationMemory element and memory device
US8426839B1 (en)2009-04-242013-04-23Adesto Technologies CorporationConducting bridge random access memory (CBRAM) device structures
US8624219B1 (en)2012-04-122014-01-07Adesto Technologies CorporationVariable impedance memory element structures, methods of manufacture, and memory devices containing the same
US8654561B1 (en)2010-10-292014-02-18Adesto Technologies CorporationRead methods, circuits and systems for memory devices
US8687403B1 (en)2010-06-102014-04-01Adesto Technologies CorporationCircuits having programmable impedance elements
US8730752B1 (en)2012-04-022014-05-20Adesto Technologies CorporationCircuits and methods for placing programmable impedance memory elements in high impedance states
US8816314B2 (en)2011-05-132014-08-26Adesto Technologies CorporationContact structure and method for variable impedance memory element
US8824038B2 (en)2009-07-222014-09-02Jean-Christophe GironElectrochromic device
US8829482B1 (en)2010-09-232014-09-09Adesto Technologies CorporationVariable impedance memory device structure and method of manufacture including programmable impedance memory cells and methods of forming the same
US8847192B2 (en)2011-09-132014-09-30Adesto Technologies France SarlResistive switching devices having alloyed electrodes and methods of formation thereof
US8847191B1 (en)2012-03-272014-09-30Adesto Technologies CorporationProgrammable impedance memory elements, methods of manufacture, and memory devices containing the same
US8854873B1 (en)2011-05-052014-10-07Adesto Technologies CorporationMemory devices, architectures and methods for memory elements having dynamic change in property
US8895953B1 (en)2011-07-152014-11-25Adesto Technologies CorporationProgrammable memory elements, devices and methods having physically localized structure
US8947913B1 (en)2010-05-242015-02-03Adesto Technologies CorporationCircuits and methods having programmable impedance elements
US8995173B1 (en)2011-09-292015-03-31Adesto Technologies CorporationMemory cells, devices and method with dynamic storage elements and programmable impedance shadow elements
US9000506B2 (en)2010-11-192015-04-07Panasonic Intellectual Property Management Co., Ltd.Variable resistance nonvolatile memory element and method for manufacturing the same
US8999819B2 (en)2010-11-142015-04-07Arizona Board of Regents, A Body Corporate of the State of Arizona Acting For on Behalf of Arizona State UniversityDendritic metal structures, methods for making dendritic metal structures, and devices including them
US9099175B1 (en)2011-03-012015-08-04Adesto Technologies CorporationMemory devices and methods for read and write operation to memory elements having dynamic change in property
US9099633B2 (en)2012-03-262015-08-04Adesto Technologies CorporationSolid electrolyte memory elements with electrode interface for improved performance
US9147464B1 (en)2012-05-152015-09-29Adesto Technologies CorporationSystem architecture with multiple memory types, including programmable impedance memory elements
US9165648B1 (en)2011-12-232015-10-20Adesto Technologies CorporationResistive memory devices, circuits and methods having read current limiting
US9177639B1 (en)2010-12-092015-11-03Adesto Technologies CorporationMemory devices, circuits and methods having data values based on dynamic change in material property
US9208870B2 (en)2012-09-132015-12-08Adesto Technologies CorporationMulti-port memory devices and methods having programmable impedance elements
EP2998949A1 (en)2013-03-122016-03-23Arizona Board of Regents, a Body Corporate of the State of Arizona acting for and on behalf of Arizona State UniversityDendritic structures and tags as physical unclonable function for anti-counterfeiting
US9305643B2 (en)2012-03-272016-04-05Adesto Technologies CorporationSolid electrolyte based memory devices and methods having adaptable read threshold levels
US9330755B1 (en)2013-02-082016-05-03Adesto Technologies CorporationLatch circuits and methods with programmable impedance elements
US9401472B1 (en)2010-09-232016-07-26Adesto Technologies CorporationProgrammable impedance elements and devices that include such elements
US9711719B2 (en)2013-03-152017-07-18Adesto Technologies CorporationNonvolatile memory elements having conductive structures with semimetals and/or semiconductors
US10128852B2 (en)2015-12-172018-11-13Microsemi SoC CorporationLow leakage ReRAM FPGA configuration cell
US10147485B2 (en)2016-09-292018-12-04Microsemi Soc Corp.Circuits and methods for preventing over-programming of ReRAM-based memory cells
US10466969B2 (en)2017-05-082019-11-05Arizona Board Of Regents On Behalf Of Arizona State UniversityTunable true random number generator using programmable metallization cell(s)
US10522224B2 (en)2017-08-112019-12-31Microsemi Soc Corp.Circuitry and methods for programming resistive random access memory devices
US10546633B2 (en)2016-12-092020-01-28Microsemi Soc Corp.Resistive random access memory cell
US10710070B2 (en)2015-11-242020-07-14Arizona Board Of Regents On Behalf Of Arizona State UniversityLow-voltage microfluidic valve device and system for regulating the flow of fluid
US10777268B2 (en)2016-05-132020-09-15Adesto Technologies CorporationStatic random access memories with programmable impedance elements and methods and devices including the same
US10810731B2 (en)2014-11-072020-10-20Arizona Board Of Regents On Behalf Of Arizona State UniversityInformation coding in dendritic structures and tags
US10984861B1 (en)2017-07-122021-04-20Adesto Technologies CorporationReference circuits and methods for resistive memories
US11127694B2 (en)2017-03-232021-09-21Arizona Board Of Regents On Behalf Of Arizona State UniversityPhysical unclonable functions with copper-silicon oxide programmable metallization cells
US11244722B2 (en)2019-09-202022-02-08Arizona Board Of Regents On Behalf Of Arizona State UniversityProgrammable interposers for electrically connecting integrated circuits
US11430233B2 (en)2017-06-162022-08-30Arizona Board Of Regents On Behalf Of Arizona State UniversityPolarized scanning of dendritic identifiers
US11598015B2 (en)2018-04-262023-03-07Arizona Board Of Regents On Behalf Of Arizona State UniversityFabrication of dendritic structures and tags
US11935843B2 (en)2019-12-092024-03-19Arizona Board Of Regents On Behalf Of Arizona State UniversityPhysical unclonable functions with silicon-rich dielectric devices
US12307323B2 (en)2021-10-182025-05-20Arizona Board Of Regents On Behalf Of Arizona State UniversityAuthentication of identifiers by light scattering

Families Citing this family (151)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US8134140B2 (en)*2000-02-112012-03-13Axon Technologies CorporationProgrammable metallization cell structure including an integrated diode, device including the structure, and method of forming same
US6638820B2 (en)2001-02-082003-10-28Micron Technology, Inc.Method of forming chalcogenide comprising devices, method of precluding diffusion of a metal into adjacent chalcogenide material, and chalcogenide comprising devices
US6727192B2 (en)2001-03-012004-04-27Micron Technology, Inc.Methods of metal doping a chalcogenide material
US6818481B2 (en)2001-03-072004-11-16Micron Technology, Inc.Method to manufacture a buried electrode PCRAM cell
US6734455B2 (en)2001-03-152004-05-11Micron Technology, Inc.Agglomeration elimination for metal sputter deposition of chalcogenides
WO2002091495A2 (en)*2001-05-072002-11-14Coatue CorporationMolecular memory device
KR100900080B1 (en)*2001-05-072009-06-01어드밴스드 마이크로 디바이시즈, 인코포레이티드 Memory device having self-assembled polymer film and manufacturing method thereof
US6873540B2 (en)*2001-05-072005-03-29Advanced Micro Devices, Inc.Molecular memory cell
CN100367528C (en)2001-05-072008-02-06先进微装置公司 Switching device with memory effect
DE60233486D1 (en)2001-05-072009-10-08Advanced Micro Devices Inc FLOATING GATE MEMORY BUILDING PART USING COMPOUND MOLECULAR MATERIAL
US7102150B2 (en)2001-05-112006-09-05Harshfield Steven TPCRAM memory cell and method of making same
US6951805B2 (en)2001-08-012005-10-04Micron Technology, Inc.Method of forming integrated circuitry, method of forming memory circuitry, and method of forming random access memory circuitry
US6858481B2 (en)*2001-08-132005-02-22Advanced Micro Devices, Inc.Memory device with active and passive layers
US6806526B2 (en)2001-08-132004-10-19Advanced Micro Devices, Inc.Memory device
US6838720B2 (en)*2001-08-132005-01-04Advanced Micro Devices, Inc.Memory device with active passive layers
US6737312B2 (en)2001-08-272004-05-18Micron Technology, Inc.Method of fabricating dual PCRAM cells sharing a common electrode
US6881623B2 (en)2001-08-292005-04-19Micron Technology, Inc.Method of forming chalcogenide comprising devices, method of forming a programmable memory cell of memory circuitry, and a chalcogenide comprising device
US6784018B2 (en)2001-08-292004-08-31Micron Technology, Inc.Method of forming chalcogenide comprising devices and method of forming a programmable memory cell of memory circuitry
US6955940B2 (en)*2001-08-292005-10-18Micron Technology, Inc.Method of forming chalcogenide comprising devices
US6709958B2 (en)2001-08-302004-03-23Micron Technology, Inc.Integrated circuit device and fabrication using metal-doped chalcogenide materials
US6815818B2 (en)2001-11-192004-11-09Micron Technology, Inc.Electrode structure for use in an integrated circuit
US6791859B2 (en)2001-11-202004-09-14Micron Technology, Inc.Complementary bit PCRAM sense amplifier and method of operation
US6873538B2 (en)2001-12-202005-03-29Micron Technology, Inc.Programmable conductor random access memory and a method for writing thereto
US6909656B2 (en)2002-01-042005-06-21Micron Technology, Inc.PCRAM rewrite prevention
US20030143782A1 (en)2002-01-312003-07-31Gilton Terry L.Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures
US6867064B2 (en)2002-02-152005-03-15Micron Technology, Inc.Method to alter chalcogenide glass for improved switching characteristics
US6791885B2 (en)2002-02-192004-09-14Micron Technology, Inc.Programmable conductor random access memory and method for sensing same
US6809362B2 (en)2002-02-202004-10-26Micron Technology, Inc.Multiple data state memory cell
US6891749B2 (en)2002-02-202005-05-10Micron Technology, Inc.Resistance variable ‘on ’ memory
US7087919B2 (en)2002-02-202006-08-08Micron Technology, Inc.Layered resistance variable memory device and method of fabrication
US6847535B2 (en)2002-02-202005-01-25Micron Technology, Inc.Removable programmable conductor memory card and associated read/write device and method of operation
US6937528B2 (en)2002-03-052005-08-30Micron Technology, Inc.Variable resistance memory and method for sensing same
US6849868B2 (en)*2002-03-142005-02-01Micron Technology, Inc.Methods and apparatus for resistance variable material cells
US6751114B2 (en)2002-03-282004-06-15Micron Technology, Inc.Method for programming a memory cell
US6858482B2 (en)2002-04-102005-02-22Micron Technology, Inc.Method of manufacture of programmable switching circuits and memory cells employing a glass layer
US6855975B2 (en)2002-04-102005-02-15Micron Technology, Inc.Thin film diode integrated with chalcogenide memory cell
US6864500B2 (en)*2002-04-102005-03-08Micron Technology, Inc.Programmable conductor memory cell structure
WO2003094227A1 (en)*2002-04-302003-11-13Japan Science And Technology AgencySolid electrolyte switching device, fpga using same, memory device, and method for manufacturing solid electrolyte switching device
US6731528B2 (en)*2002-05-032004-05-04Micron Technology, Inc.Dual write cycle programmable conductor memory system and method of operation
US6890790B2 (en)2002-06-062005-05-10Micron Technology, Inc.Co-sputter deposition of metal-doped chalcogenides
US6825135B2 (en)*2002-06-062004-11-30Micron Technology, Inc.Elimination of dendrite formation during metal/chalcogenide glass deposition
US7015494B2 (en)2002-07-102006-03-21Micron Technology, Inc.Assemblies displaying differential negative resistance
US7209378B2 (en)2002-08-082007-04-24Micron Technology, Inc.Columnar 1T-N memory cell structure
US7018863B2 (en)2002-08-222006-03-28Micron Technology, Inc.Method of manufacture of a resistance variable memory cell
US6867114B2 (en)2002-08-292005-03-15Micron Technology Inc.Methods to form a memory cell with metal-rich metal chalcogenide
US6867996B2 (en)*2002-08-292005-03-15Micron Technology, Inc.Single-polarity programmable resistance-variable memory element
US7163837B2 (en)2002-08-292007-01-16Micron Technology, Inc.Method of forming a resistance variable memory element
US6856002B2 (en)2002-08-292005-02-15Micron Technology, Inc.Graded GexSe100-x concentration in PCRAM
US7364644B2 (en)2002-08-292008-04-29Micron Technology, Inc.Silver selenide film stoichiometry and morphology control in sputter deposition
US6831019B1 (en)2002-08-292004-12-14Micron Technology, Inc.Plasma etching methods and methods of forming memory devices comprising a chalcogenide comprising layer received operably proximate conductive electrodes
US7294527B2 (en)2002-08-292007-11-13Micron Technology Inc.Method of forming a memory cell
US7012276B2 (en)*2002-09-172006-03-14Advanced Micro Devices, Inc.Organic thin film Zener diodes
US6903394B2 (en)*2002-11-272005-06-07Micron Technology, Inc.CMOS imager with improved color response
DE10256486A1 (en)*2002-12-032004-07-15Infineon Technologies Ag Method for producing a memory cell, memory cell and memory cell arrangement
US20040115945A1 (en)*2002-12-132004-06-17Lowrey Tyler A.Using an electron beam to write phase change memory devices
US6656763B1 (en)*2003-03-102003-12-02Advanced Micro Devices, Inc.Spin on polymers for organic memory devices
US6813178B2 (en)*2003-03-122004-11-02Micron Technology, Inc.Chalcogenide glass constant current device, and its method of fabrication and operation
US7022579B2 (en)2003-03-142006-04-04Micron Technology, Inc.Method for filling via with metal
US7778062B2 (en)*2003-03-182010-08-17Kabushiki Kaisha ToshibaResistance change memory device
JP4377817B2 (en)2003-03-182009-12-02株式会社東芝 Programmable resistance memory device
US7050327B2 (en)2003-04-102006-05-23Micron Technology, Inc.Differential negative resistance memory
US6961277B2 (en)2003-07-082005-11-01Micron Technology, Inc.Method of refreshing a PCRAM memory device
US7061004B2 (en)2003-07-212006-06-13Micron Technology, Inc.Resistance variable memory elements and methods of formation
KR100537278B1 (en)*2003-09-052005-12-19주식회사 하이닉스반도체Method of manufacturing in flash memory devices
US7529123B2 (en)*2003-09-082009-05-05Ovonyx, Inc.Method of operating a multi-terminal electronic device
US6903361B2 (en)2003-09-172005-06-07Micron Technology, Inc.Non-volatile memory structure
DE10345489B3 (en)*2003-09-302005-04-14Infineon Technologies Ag Apparatus for use in the synchronization of clock signals, and clock synchronization methods
US7050319B2 (en)*2003-12-032006-05-23Micron Technology, Inc.Memory architecture and method of manufacture and operation thereof
US7153721B2 (en)*2004-01-282006-12-26Micron Technology, Inc.Resistance variable memory elements based on polarized silver-selenide network growth
DE102004010243A1 (en)*2004-03-032005-05-19Infineon Technologies AgStatic memory cell, has circuit for limiting current through PMC resistance when changing from high-resistance state to low-resistance state
DE102004011431B4 (en)*2004-03-092007-09-27Infineon Technologies Ag Method for producing a non-volatile semiconductor memory
US7583551B2 (en)2004-03-102009-09-01Micron Technology, Inc.Power management control and controlling memory refresh operations
US7098068B2 (en)2004-03-102006-08-29Micron Technology, Inc.Method of forming a chalcogenide material containing device
DE102005003675A1 (en)*2004-04-292005-11-24Infineon Technologies AgCBRAM memory cell comprises a metallic material incorporated in or deposited on a matrix-host material, and a memory cell having a memory switching mechanism based on the variation of the metallic material
WO2005124788A2 (en)*2004-06-142005-12-29Axon Technologies CorporationNanoscale programmable structures and methods of forming and using same
US7365411B2 (en)2004-08-122008-04-29Micron Technology, Inc.Resistance variable memory with temperature tolerant materials
US7289353B2 (en)*2004-08-172007-10-30Spansion, LlcSystems and methods for adjusting programming thresholds of polymer memory cells
DE102004042171A1 (en)*2004-08-312006-04-20Infineon Technologies AgMemory arrangement e.g. conductive bridging RAM, for storing information, has memory cells whose status is modified by applying voltage at two poles of cells, where poles of memory cells are short-circuited through switching arrangement
US7151688B2 (en)2004-09-012006-12-19Micron Technology, Inc.Sensing of resistance variable memory devices
DE102004045219B4 (en)*2004-09-172011-07-28Qimonda AG, 81739 Arrangement and method for reading resistance memory cells
DE102004046804B4 (en)*2004-09-272006-10-05Infineon Technologies Ag Resistively switching semiconductor memory
JP4529654B2 (en)*2004-11-152010-08-25ソニー株式会社 Storage element and storage device
US20060131555A1 (en)*2004-12-222006-06-22Micron Technology, Inc.Resistance variable devices with controllable channels
US7374174B2 (en)2004-12-222008-05-20Micron Technology, Inc.Small electrode for resistance variable devices
FR2880177B1 (en)2004-12-232007-05-18Commissariat Energie Atomique MEMORY PMC HAVING IMPROVED RETENTION TIME AND WRITING SPEED
JP5135798B2 (en)*2004-12-272013-02-06日本電気株式会社 Switching element, switching element driving method, rewritable logic integrated circuit, and memory element
US7964867B2 (en)*2004-12-282011-06-21Nec CorporationSwitching element, switching element fabriction method, reconfigurable logic integrated circuit, and memory element
US7768014B2 (en)*2005-01-312010-08-03Semiconductor Energy Laboratory Co., Ltd.Memory device and manufacturing method thereof
DE102005005325B4 (en)*2005-02-042011-12-15Adesto Technology Corp., Inc. Method for producing a resistively switching non-volatile memory cell
US7317200B2 (en)2005-02-232008-01-08Micron Technology, Inc.SnSe-based limited reprogrammable cell
US7269044B2 (en)2005-04-222007-09-11Micron Technology, Inc.Method and apparatus for accessing a memory array
US20060291364A1 (en)*2005-04-252006-12-28Kozicki Michael NSolid electrolyte probe storage device, system including the device, and methods of forming and using same
JP2006319028A (en)*2005-05-112006-11-24Nec Corp Switching element, rewritable logic integrated circuit, and memory element
US7407885B2 (en)*2005-05-112008-08-05Micron Technology, Inc.Methods of forming electrically conductive plugs
US7269079B2 (en)2005-05-162007-09-11Micron Technology, Inc.Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory
US7973301B2 (en)*2005-05-202011-07-05Qimonda AgLow power phase change memory cell with large read signal
US20060284156A1 (en)*2005-06-162006-12-21Thomas HappPhase change memory cell defined by imprint lithography
US7233520B2 (en)2005-07-082007-06-19Micron Technology, Inc.Process for erasing chalcogenide variable resistance memory bits
US7274034B2 (en)2005-08-012007-09-25Micron Technology, Inc.Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication
US7332735B2 (en)2005-08-022008-02-19Micron Technology, Inc.Phase change memory cell and method of formation
US7317567B2 (en)2005-08-022008-01-08Micron Technology, Inc.Method and apparatus for providing color changing thin film material
US7579615B2 (en)2005-08-092009-08-25Micron Technology, Inc.Access transistor for memory device
US7304368B2 (en)2005-08-112007-12-04Micron Technology, Inc.Chalcogenide-based electrokinetic memory element and method of forming the same
KR100657967B1 (en)*2005-08-122006-12-14삼성전자주식회사 Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof
US7251154B2 (en)2005-08-152007-07-31Micron Technology, Inc.Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
US7277313B2 (en)2005-08-312007-10-02Micron Technology, Inc.Resistance variable memory element with threshold device and method of forming the same
US8492810B2 (en)*2006-02-282013-07-23Qimonda AgMethod of fabricating an integrated electronic circuit with programmable resistance cells
US9178141B2 (en)2006-04-042015-11-03Micron Technology, Inc.Memory elements using self-aligned phase change material layers and methods of manufacturing same
US7812334B2 (en)*2006-04-042010-10-12Micron Technology, Inc.Phase change memory elements using self-aligned phase change material layers and methods of making and using same
US20080073751A1 (en)*2006-09-212008-03-27Rainer BruchhausMemory cell and method of manufacturing thereof
US20080078983A1 (en)*2006-09-282008-04-03Wolfgang RabergLayer structures comprising chalcogenide materials
EP2153477B1 (en)*2007-05-012014-06-04ImecNon-volatile memory device
US20080273370A1 (en)*2007-05-022008-11-06Jan KellerIntegrated Circuit, Method of Operating an Integrated Circuit, Memory Cell Array, and Memory Module
DE102007032865A1 (en)*2007-07-132009-01-15Qimonda AgIntegrated circuit for resistivity changing devices, has memory cell, which comprises two resistivity changing layers stacked one above other, in which each resistivity changing layer serves as separate data storage layer
FR2922368A1 (en)*2007-10-162009-04-17Commissariat Energie Atomique METHOD FOR MANUFACTURING A CBRAM MEMORY HAVING IMPROVED RELIABILITY
US20090103351A1 (en)*2007-10-232009-04-23Cay-Uwe PinnowIntegrated Circuit, Method of Manufacturing an Integrated Circuit, and Memory Module
DE102007050604A1 (en)*2007-10-232009-04-30Qimonda AgIntegrated circuit for use in memory module, has intermediate layer arranged between electrolyte and reactive layers, where parameter of intermediate layer is selected such that crystallization of electrolyte layer is partially suppressed
US8064243B2 (en)*2007-11-132011-11-22Qimonda AgMethod and apparatus for an integrated circuit with programmable memory cells, data system
US20090140232A1 (en)*2007-11-302009-06-04Klaus-Dieter UfertResistive Memory Element
JP4466738B2 (en)*2008-01-092010-05-26ソニー株式会社 Storage element and storage device
US7768812B2 (en)2008-01-152010-08-03Micron Technology, Inc.Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US20090200535A1 (en)*2008-02-122009-08-13Klaus-Dieter UfertNon-Volatile Memory Element with Improved Temperature Stability
US8034655B2 (en)2008-04-082011-10-11Micron Technology, Inc.Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays
US8211743B2 (en)*2008-05-022012-07-03Micron Technology, Inc.Methods of forming non-volatile memory cells having multi-resistive state material between conductive electrodes
US7786463B2 (en)*2008-05-202010-08-31Seagate Technology LlcNon-volatile multi-bit memory with programmable capacitance
US7977722B2 (en)*2008-05-202011-07-12Seagate Technology LlcNon-volatile memory with programmable capacitance
US8134137B2 (en)*2008-06-182012-03-13Micron Technology, Inc.Memory device constructions, memory cell forming methods, and semiconductor construction forming methods
US9343665B2 (en)2008-07-022016-05-17Micron Technology, Inc.Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array
US8467236B2 (en)2008-08-012013-06-18Boise State UniversityContinuously variable resistor
US7772583B2 (en)*2008-08-212010-08-10Micron Technology, Inc.Memory devices and methods of forming the same
US7839681B2 (en)*2008-12-122010-11-23Actel CorporationPush-pull FPGA cell
US8907455B2 (en)*2009-01-282014-12-09Hewlett-Packard Development Company, L.P.Voltage-controlled switches
JP2010192800A (en)*2009-02-202010-09-02Toshiba CorpNonvolatile semiconductor memory device
WO2010136056A1 (en)*2009-05-292010-12-02Rheinisch-Wetfälische Technische Hochschule AachenResistive storage cell, crossbar array circuit, resistive random access memory device and read-out-method
EP3273444A1 (en)*2009-05-292018-01-24Forschungszentrum Jülich GmbHMemory element, stacking, memory matrix and method for operating
US8411477B2 (en)2010-04-222013-04-02Micron Technology, Inc.Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8427859B2 (en)2010-04-222013-04-23Micron Technology, Inc.Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
US8289763B2 (en)2010-06-072012-10-16Micron Technology, Inc.Memory arrays
US8351242B2 (en)2010-09-292013-01-08Micron Technology, Inc.Electronic devices, memory devices and memory arrays
US8759809B2 (en)2010-10-212014-06-24Micron Technology, Inc.Integrated circuitry comprising nonvolatile memory cells having platelike electrode and ion conductive material layer
US8796661B2 (en)2010-11-012014-08-05Micron Technology, Inc.Nonvolatile memory cells and methods of forming nonvolatile memory cell
US8526213B2 (en)2010-11-012013-09-03Micron Technology, Inc.Memory cells, methods of programming memory cells, and methods of forming memory cells
WO2012065076A1 (en)*2010-11-142012-05-18Arizona Board Of Regents, A Body Corporate Of The State Of Arizona Acting For And On Behalf Of Arizona State UniversityPlasmonic structures, methods for making plasmonic structures, and devices including them
US9454997B2 (en)2010-12-022016-09-27Micron Technology, Inc.Array of nonvolatile memory cells having at least five memory cells per unit cell, having a plurality of the unit cells which individually comprise three elevational regions of programmable material, and/or having a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells; array of vertically stacked tiers of nonvolatile memory cells
US8431458B2 (en)2010-12-272013-04-30Micron Technology, Inc.Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells
US8791447B2 (en)2011-01-202014-07-29Micron Technology, Inc.Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US8488365B2 (en)2011-02-242013-07-16Micron Technology, Inc.Memory cells
US8537592B2 (en)2011-04-152013-09-17Micron Technology, Inc.Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
US9147839B2 (en)2013-09-052015-09-29Micron Technology, Inc.Memory cells with recessed electrode contacts
TWI696997B (en)2014-10-072020-06-21美商愛德斯托科技公司Memory elements having conductive cap layers and methods therefor
US10483462B1 (en)*2015-06-172019-11-19Crossbar, Inc.Formation of structurally robust nanoscale Ag-based conductive structure

Citations (8)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US5177567A (en)*1991-07-191993-01-05Energy Conversion Devices, Inc.Thin-film structure for chalcogenide electrical switching devices and process therefor
US5315131A (en)*1990-11-221994-05-24Matsushita Electric Industrial Co., Ltd.Electrically reprogrammable nonvolatile memory device
US5541869A (en)1991-10-221996-07-30British Telecommunications, PlcResistive memory element
US5912839A (en)1998-06-231999-06-15Energy Conversion Devices, Inc.Universal memory element and method of programming same
US5914893A (en)*1996-05-301999-06-22Axon Technologies CorporationProgrammable metallization cell structure and method of making same
US5933365A (en)1997-06-191999-08-03Energy Conversion Devices, Inc.Memory element with energy control mechanism
US5993986A (en)*1995-11-161999-11-30The Dow Chemical CompanySolide oxide fuel cell stack with composite electrodes and method for making
US6418049B1 (en)*1997-12-042002-07-09Arizona Board Of RegentsProgrammable sub-surface aggregating metallization structure and method of making same

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US4701035A (en)*1984-08-141987-10-20Canon Kabushiki KaishaReflection optical system
US5040882A (en)*1988-11-071991-08-20General Signal CorporationUnit magnification optical system with improved reflective reticle
US5031977A (en)*1989-12-271991-07-16General Signal CorporationDeep ultraviolet (UV) lens for use in a photolighography system
JP3010365B2 (en)*1990-05-152000-02-21オリンパス光学工業株式会社 Objective lens
DE69332342T2 (en)*1992-04-102003-06-05Sun Active Glass Electrochromics, Inc. ELECTROCHROME STRUCTURES AND METHODS
US5305138A (en)*1992-07-311994-04-19International Business Machines CorporationSuperachromatic UV and visible focusing objective lens
US5781336A (en)*1995-11-281998-07-14Lockheed Martin CorporationMethod and system for multi-spectral imaging in the visible and infrared spectrums
US5815310A (en)*1995-12-121998-09-29Svg Lithography Systems, Inc.High numerical aperture ring field optical reduction system
US5686728A (en)*1996-05-011997-11-11Lucent Technologies IncProjection lithography system and method using all-reflective optical elements
US5717518A (en)*1996-07-221998-02-10Kla Instruments CorporationBroad spectrum ultraviolet catadioptric imaging system
US6169627B1 (en)*1996-09-262001-01-02Carl-Zeiss-StiftungCatadioptric microlithographic reduction objective
DE19704936A1 (en)*1997-02-101998-08-13Zeiss Carl Fa Optical link and manufacturing process
JP3925576B2 (en)*1997-07-242007-06-06株式会社ニコン Projection optical system, exposure apparatus including the optical system, and device manufacturing method using the apparatus
DE19939088A1 (en)*1998-08-182000-02-24Nikon CorpExposure apparatus, especially in photolithography for producing e.g. semiconductor devices, chips and thin film magnetic heads, has a projection system with refractive optical components of different crystalline fluorides
US6195047B1 (en)*1998-10-282001-02-27Raytheon CompanyIntegrated microelectromechanical phase shifting reflect array antenna
DE19855108A1 (en)*1998-11-302000-05-31Zeiss Carl Fa Microlithographic reduction lens, projection exposure system and method
DE19855106A1 (en)*1998-11-302000-05-31Zeiss Carl Fa Illumination system for VUV microlithography
US6635914B2 (en)*2000-09-082003-10-21Axon Technologies Corp.Microelectronic programmable device and methods of forming and programming the same
US6487106B1 (en)*1999-01-122002-11-26Arizona Board Of RegentsProgrammable microelectronic devices and method of forming and programming same
US6295508B1 (en)*1999-09-012001-09-25Perkinelmer Instruments, Inc.Automatic pole-zero adjustment circuit for an ionizing radiation spectroscopy system and method

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US5315131A (en)*1990-11-221994-05-24Matsushita Electric Industrial Co., Ltd.Electrically reprogrammable nonvolatile memory device
US5177567A (en)*1991-07-191993-01-05Energy Conversion Devices, Inc.Thin-film structure for chalcogenide electrical switching devices and process therefor
US5541869A (en)1991-10-221996-07-30British Telecommunications, PlcResistive memory element
US5993986A (en)*1995-11-161999-11-30The Dow Chemical CompanySolide oxide fuel cell stack with composite electrodes and method for making
US5914893A (en)*1996-05-301999-06-22Axon Technologies CorporationProgrammable metallization cell structure and method of making same
US5933365A (en)1997-06-191999-08-03Energy Conversion Devices, Inc.Memory element with energy control mechanism
US6418049B1 (en)*1997-12-042002-07-09Arizona Board Of RegentsProgrammable sub-surface aggregating metallization structure and method of making same
US5912839A (en)1998-06-231999-06-15Energy Conversion Devices, Inc.Universal memory element and method of programming same

Non-Patent Citations (11)

* Cited by examiner, † Cited by third party
Title
Electric field enhanced phase separation and memory switching in amorphous electric triselenide; David D. Thornburg and Robert M. White; J. Appl. Phys., vol. 43, No. 11, Nov. 1972.
Electrical switching in Agl based fast ion conducting glasses: Possibility for newer applications; B. Vaidhyanathan and K.J. Rao, S. Prakash, S. Murugavel, and S. Asokan; J. Appl. Phys 75 (2), Jul. 15, 1995; 1995 American Institute of Physics; pp. 1358-1360.
Ion Transport In Solids Under Conditions Which Include Large Electric Fields; M.J. Dignam; Pergamon Press 1968 vol. 29, pp. 249-260.
Letter; Thin Solid Films, 70 (1980) pp. L1-L4.
Nucleation in External Electric Field; D. Kashchiev; Journal of Crystal Growth 13/14 (1972) pp. 128-130.
Nucleation in Solid Solution Stimulated by Non-Equilibrium Electrons; I. Electronic Model; S. Stoyanov, D. Kashchiev, and M. Georgiev, phys. stat.sol. 41, pp. 387-394 1970.
Nucleation in Solid Solution Stimulated by Non-Equilibrium Electrons; II. Electronic Model; S. Stoyanov, D. Kaschiev, and M. Georgiev; phys. stat.sol. 41, pp. 395-404 1970.
Percolation transition Ag-doped germanium chalcogenide-based glasses: conductivity and silver diffusion results; E. Bychkov, V. Tsegelnik, Yu. Vlasov, A. Pradel, M. Ribes; Journal of Non-Crystalline Solids 208 (1996) pp. 1-20.
Polarized Memory Switching Effects in Ag2Se/Se/M Thin Film Sandwiches; Thin Solid Films, 97 (1982) pp. 165-171.
Polarized Memory Switching In Mis Thin Films; L.C. Bernede; Thin Solid Films, 81 (1981) pp. 155-160.
Short Communication; Electrical Characterization of M/Se Structures (M=Ni, Bi) Materials Chemistry and Physics, 28 (1991) 253-258.

Cited By (201)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US7460698B2 (en)1996-09-252008-12-02Kabushiki Kaisha ToshibaUltrasonic picture processing method and ultrasonic picture processing apparatus
US6998312B2 (en)*1998-12-042006-02-14Axon Technologies CorporationMicroelectronic programmable device and methods of forming and programming the same
US20030209728A1 (en)*1998-12-042003-11-13Kozicki Michael N.Microelectronic programmable device and methods of forming and programming the same
US7405967B2 (en)1998-12-042008-07-29Axon Technologies CorporationMicroelectronic programmable device and methods of forming and programming the same
US8213218B2 (en)*2000-02-112012-07-03Axon Technologies CorporationOptimized solid electrolyte for programmable metallization cell devices and structures
US7675766B2 (en)*2000-02-112010-03-09Axon Technologies CorporationMicroelectric programmable device and methods of forming and programming the same
US20080237567A1 (en)*2000-02-112008-10-02Axon Technologies CorporationOptimized solid electrolyte for programmable metallization cell devices and structures
US20080265285A1 (en)*2000-02-112008-10-30Axon Technologies CorporationMicroelectronic programmable device and methods of forming and programming the same
US8218350B2 (en)*2000-02-112012-07-10Axon Technologies CorporationProgrammable metallization cell structure including an integrated diode, device including the structure, and method of forming same
US7560722B2 (en)*2000-02-112009-07-14Axon Technologies CorporationOptimized solid electrolyte for programmable metallization cell devices and structures
US20120014165A1 (en)*2000-02-112012-01-19Axon Technologies CorporationOptimized solid electrolyte for programmable metallization cell devices and structures
US20110315947A1 (en)*2000-02-112011-12-29Axon Technologies CorporationProgrammable metallization cell structure including an integrated diode, device including the structure, and method of forming same
US20100135071A1 (en)*2000-07-272010-06-03Axon Technologies CorporationMicroelectronic programmable device and methods of forming and programming the same
US7929331B2 (en)*2000-07-272011-04-19Axon Technologies CorporationMicroelectronic programmable device and methods of forming and programming the same
US20110194339A1 (en)*2000-07-272011-08-11Axon Technologies CorporationMicroelectronic programmable device and methods of forming and programming the same
US8213217B2 (en)*2000-07-272012-07-03Axon Technologies CorporationMicroelectronic programmable device and methods of forming and programming the same
US20040161894A1 (en)*2000-12-082004-08-19Gilton Terry L.Non-volatile resistance variable devices and method of forming same, analog memory devices and method of forming same, programmable memory cell and method of forming same, and method of structurally changing a non-volatile device
US7061071B2 (en)2000-12-082006-06-13Micron Technology, Inc.Non-volatile resistance variable devices and method of forming same, analog memory devices and method of forming same, programmable memory cell and method of forming same, and method of structurally changing a non-volatile device
US7183141B1 (en)2001-05-072007-02-27Spansion LlcReversible field-programmable electric interconnects
US6813176B2 (en)2001-08-302004-11-02Micron Technology, Inc.Method of retaining memory state in a programmable conductor RAM
US6888155B2 (en)2001-08-302005-05-03Micron Technology, Inc.Stoichiometry for chalcogenide glasses useful for memory devices and method of formation
US20070102691A1 (en)*2002-02-202007-05-10Campbell Kristy ASilver-selenide/chalcogenide glass stack for resistance variable memory
US7646007B2 (en)*2002-02-202010-01-12Micron Technology, Inc.Silver-selenide/chalcogenide glass stack for resistance variable memory
US8080816B2 (en)2002-02-202011-12-20Micron Technology, Inc.Silver-selenide/chalcogenide glass stack for resistance variable memory
US20100140579A1 (en)*2002-02-202010-06-10Campbell Kristy ASilver-selenide/chalcogenide glass stack for resistance variable memory
US8466445B2 (en)2002-02-202013-06-18Micron Technology, Inc.Silver-selenide/chalcogenide glass stack for resistance variable memory and manufacturing method thereof
US6874335B2 (en)*2002-04-122005-04-05Micron Technology, Inc.Large scale synthesis of germanium selenide glass and germanium selenide glass compounds
US20030192350A1 (en)*2002-04-122003-10-16Stefan UhlenbrockLarge scale synthesis of germanium selenide glass and germanium selenide glass compounds
US7307908B2 (en)2002-08-292007-12-11Micron Technology, Inc.Software refreshed memory device and method
US7768861B2 (en)2002-08-292010-08-03Micron Technology, Inc.Software refreshed memory device and method
US7564731B2 (en)2002-08-292009-07-21Micron Technology, Inc.Software refreshed memory device and method
US7944768B2 (en)2002-08-292011-05-17Micron Technology, Inc.Software refreshed memory device and method
US6864521B2 (en)*2002-08-292005-03-08Micron Technology, Inc.Method to control silver concentration in a resistance variable memory element
US7010644B2 (en)*2002-08-292006-03-07Micron Technology, Inc.Software refreshed memory device and method
US7692177B2 (en)*2002-08-292010-04-06Micron Technology, Inc.Resistance variable memory element and its method of formation
US20040044841A1 (en)*2002-08-292004-03-04Gilton Terry L.Software refreshed memory device and method
US7223627B2 (en)2002-08-292007-05-29Micron Technology, Inc.Memory element and its method of formation
US20070285967A1 (en)*2003-03-182007-12-13Kabushiki Kaisha ToshibaResistance change memory device
US20070285966A1 (en)*2003-03-182007-12-13Kabushiki Kaisha ToshibaResistance change memory device
US7400522B2 (en)*2003-03-182008-07-15Kabushiki Kaisha ToshibaResistance change memory device having a variable resistance element formed of a first and second composite compound for storing a cation
US7394680B2 (en)*2003-03-182008-07-01Kabushiki Kaisha ToshibaResistance change memory device having a variable resistance element with a recording layer electrode served as a cation source in a write or erase mode
US6930909B2 (en)2003-06-252005-08-16Micron Technology, Inc.Memory device and methods of controlling resistance variation and resistance profile drift
US20050094461A1 (en)*2003-09-022005-05-05Martin PernerIntegrated semiconductor memory
US7057201B2 (en)2003-09-022006-06-06Infineon Technologies AgIntegrated semiconductor memory
US7180104B2 (en)*2003-09-032007-02-20Axon Technologies CorporationMicromechanical structure, device including the structure, and methods of forming and using same
US20050045920A1 (en)*2003-09-032005-03-03Kozicki Michael N.Micromechanical structure, device including the structure, and methods of forming and using same
US6992369B2 (en)*2003-10-082006-01-31Ovonyx, Inc.Programmable resistance memory element with threshold switching material
US20050077515A1 (en)*2003-10-082005-04-14Kostylev Sergey A.Programmable resistance memory element with threshold switching material
US20060118911A1 (en)*2003-10-082006-06-08Kostylev Sergey AProgrammable resistance memory element with threshold switching material
US7459762B2 (en)*2003-10-082008-12-02Ovonyx, Inc.Programmable resistance memory element with threshold switching material
US7442605B2 (en)2004-04-262008-10-28Infineon Technologies AgResistively switching memory
DE102004020297B4 (en)*2004-04-262007-06-21Infineon Technologies Ag Process for producing resistively switching memory components
DE102004020297A1 (en)*2004-04-262005-11-17Infineon Technologies Ag Process for producing resistively switching memory components
US20050250281A1 (en)*2004-04-262005-11-10Infineon Technologies AgMethod for manufacturing resistively switching memory devices
US7749853B2 (en)2004-07-192010-07-06Microntechnology, Inc.Method of forming a variable resistance memory device comprising tin selenide
US7190048B2 (en)*2004-07-192007-03-13Micron Technology, Inc.Resistance variable memory device and method of fabrication
US7282783B2 (en)*2004-07-192007-10-16Micron Technology, Inc.Resistance variable memory device and method of fabrication
US7348209B2 (en)*2004-07-192008-03-25Micron Technology, Inc.Resistance variable memory device and method of fabrication
US7326950B2 (en)*2004-07-192008-02-05Micron Technology, Inc.Memory device with switching glass layer
KR100917095B1 (en)2004-07-192009-09-15마이크론 테크놀로지, 인크 Variable resistance memory device and manufacturing method
US7785976B2 (en)*2004-08-122010-08-31Micron Technology, Inc.Method of forming a memory device incorporating a resistance-variable chalcogenide element
US8487288B2 (en)2004-08-122013-07-16Micron Technology, Inc.Memory device incorporating a resistance variable chalcogenide element
US8334186B2 (en)2004-08-122012-12-18Micron Technology, Inc.Method of forming a memory device incorporating a resistance variable chalcogenide element
US20080206920A1 (en)*2004-08-122008-08-28Campbell Kristy APCRAM device with switching glass layer
US7354793B2 (en)*2004-08-122008-04-08Micron Technology, Inc.Method of forming a PCRAM device incorporating a resistance-variable chalocogenide element
US20060044878A1 (en)*2004-09-022006-03-02Perner Frederick AProgramming of programmable resistive memory devices
US7224598B2 (en)2004-09-022007-05-29Hewlett-Packard Development Company, L.P.Programming of programmable resistive memory devices
US20060077741A1 (en)*2004-10-082006-04-13Wen-Han WangMultilevel phase-change memory, manufacturing and status transferring method thereof
US20070249083A1 (en)*2004-10-082007-10-25Industrial Technology Research InstituteMultilevel phase-change memory element and operating method
US7254059B2 (en)2004-10-082007-08-07Industrial Technology Research InstitutMultilevel phase-change memory element and operating method
US20060077706A1 (en)*2004-10-082006-04-13Chien-Ming LiMultilevel phase-change memory, operating method and manufacture method thereof
US7634337B2 (en)2004-12-292009-12-15Snap-On IncorporatedVehicle or engine diagnostic systems with advanced non-volatile memory
US7937198B2 (en)2004-12-292011-05-03Snap-On IncorporatedVehicle or engine diagnostic systems supporting fast boot and reprogramming
US20060142906A1 (en)*2004-12-292006-06-29Snap-On IncorporatedVehicle or engine diagnostic systems supporting fast boot and reprogramming
US20060142905A1 (en)*2004-12-292006-06-29Snap-On IncorporatedVehicle or engine diagnostic systems with advanced non-volatile memory
EP1686590A3 (en)*2005-01-282007-04-11Infineon Technologies AGIntegrated semiconductor memory comprising an arrangement of non-volatile storage cells and method
US7277312B2 (en)2005-01-282007-10-02Infineon Technologies AgIntegrated semiconductor memory with an arrangement of nonvolatile memory cells, and method
DE102005004593A1 (en)*2005-02-012006-08-17Infineon Technologies AgIntegrated semiconductor memory e.g. dynamic random access memory, has electrolytic memory cells whose thickness sequence is oriented in memory cell planes, where ohmic resistance of sequence is reduced by applying programming current
DE102005004593B4 (en)*2005-02-012007-04-12Infineon Technologies Ag Integrated semiconductor memory with an arrangement of nonvolatile memory cells
US7663133B2 (en)*2005-04-222010-02-16Micron Technology, Inc.Memory elements having patterned electrodes and method of forming the same
US7968927B2 (en)2005-04-222011-06-28Micron Technology, Inc.Memory array for increased bit density and method of forming the same
US20060240616A1 (en)*2005-04-222006-10-26Micron Technology, Inc.Memory elements having patterned electrodes and method of forming the same
US7709289B2 (en)*2005-04-222010-05-04Micron Technology, Inc.Memory elements having patterned electrodes and method of forming the same
JP2006344976A (en)*2005-06-102006-12-21Hynix Semiconductor IncPhase transformation memory element and its manufacturing method
US8093518B2 (en)*2005-09-272012-01-10National Institute Of Advanced Industrial Science And TechnologySwitching element relying on nanogap electrodes
US20090251199A1 (en)*2005-09-272009-10-08National Institute Of Advanced Industrial Science And TechnologySwitching Element
US20110135837A1 (en)*2005-10-112011-06-09Mark Samuel BurdisElectrochromic devices having improved ion conducting layers
US7593154B2 (en)*2005-10-112009-09-22Sage Electrochromics, Inc.Electrochromic devices having improved ion conducting layers
US20070097481A1 (en)*2005-10-112007-05-03Sage Electrochromics, Inc.Electrochromic devices having improved ion conducting layers
US8004744B2 (en)2005-10-112011-08-23Sage Electrochromics, Inc.Electrochromic devices having improved ion conducting layers
US8730552B2 (en)2005-10-112014-05-20Sage Electrochromics, Inc.Electrochromic devices having improved ion conducting layers
US20090289371A1 (en)*2005-12-152009-11-26Nec CorporationSwitching element and method of manufacturing the same
JP2009065184A (en)*2006-03-302009-03-26Panasonic Corp Nonvolatile memory element and manufacturing method thereof
US7884346B2 (en)*2006-03-302011-02-08Panasonic CorporationNonvolatile memory element and manufacturing method thereof
US20090174519A1 (en)*2006-03-302009-07-09Takumi MikawaNonvolatile memory element and manufacturing method thereof
US8227786B2 (en)2006-03-302012-07-24Panasonic CorporationNonvolatile memory element
JP4989631B2 (en)*2006-03-302012-08-01パナソニック株式会社 Nonvolatile memory element
US20110140828A1 (en)*2006-03-302011-06-16Panasonic CorporationNonvolatile memory element and manufacturing method thereof
US7791058B2 (en)2006-08-292010-09-07Micron Technology, Inc.Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication
US8030636B2 (en)2006-08-292011-10-04Micron Technology, Inc.Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication
US20080217600A1 (en)*2007-03-092008-09-11Commissariat A L'energie AtomiqueMulti-level data memorisation device with phase change material
US7943923B2 (en)*2007-03-092011-05-17Commissariat A L'energie AtomiqueMulti-level data memorisation device with phase change material
US20100038619A1 (en)*2007-03-282010-02-18Ayuka TadaVariable resistance element, manufacturing method thereof, and electronic device
US20080310211A1 (en)*2007-06-122008-12-18Kabushiki Kaisha ToshibaResistance change memory device
US7692951B2 (en)2007-06-122010-04-06Kabushiki Kaisha ToshibaResistance change memory device with a variable resistance element formed of a first and a second composite compound
US8492740B2 (en)*2007-08-062013-07-23Sony CorporationMemory element and memory device
US20100195371A1 (en)*2007-08-062010-08-05Sony CorporationMemory element and memory device
US20110038497A1 (en)*2007-11-182011-02-17Arizona Board Of Regents, Acting For And On Behalf Of Arizona State UniversityMicrophone Devices and Methods for Tuning Microphone Devices
US8345910B2 (en)2007-11-182013-01-01Arizona Board Of RegentsMicrophone devices and methods for tuning microphone devices
US20090212273A1 (en)*2008-02-212009-08-27Samsung Electronics Co., Ltd.Semiconductor Devices Having Resistive Memory Elements
US7838863B2 (en)2008-02-212010-11-23Samsung Electronics Co. Ltd.Semiconductor devices having resistive memory elements
US20090233421A1 (en)*2008-03-172009-09-17Samsung Electronics Co., Ltd,Methods of Fabricating Semiconductor Device Including Phase Change Layer
US7838326B2 (en)2008-03-172010-11-23Samsung Electronics Co., Ltd.Methods of fabricating semiconductor device including phase change layer
US8107273B1 (en)2008-07-282012-01-31Adesto Technologies CorporationIntegrated circuits having programmable metallization cells (PMCs) and operating methods therefor
US8274842B1 (en)2008-09-252012-09-25Adesto Technologies CorporationVariable impedance memory device having simultaneous program and erase, and corresponding methods and circuits
US8331128B1 (en)2008-12-022012-12-11Adesto Technologies CorporationReconfigurable memory arrays having programmable impedance elements and corresponding methods
US7923715B2 (en)2008-12-062011-04-12The United States Of America As Represented By The Administrator Of National Aeronautics And Space AdministrationChalcogenide nanoionic-based radio frequency switch
US20100140582A1 (en)*2008-12-062010-06-10James NesselChalcogenide nanoionic-based radio frequency switch
US8742531B2 (en)2008-12-082014-06-03Arizona Board Of Regents, Acting For And On Behalf Of Arizona State UniversityElectrical devices including dendritic metal electrodes
WO2010077622A1 (en)2008-12-082010-07-08Arizona Board Of Regents, Acting For And On Behalf Of Arizona State UniversityElectrical devices including dendritic metal electrodes
US7929345B2 (en)2008-12-232011-04-19Actel CorporationPush-pull memory cell configured for simultaneous programming of n-channel and p-channel non-volatile transistors
US20100157688A1 (en)*2008-12-232010-06-24Actel CorporationPush-pull memory cell configured for simultaneous programming of n-channel and p-channel non-volatile transistors
US20100208520A1 (en)*2009-02-132010-08-19Actel CorporationArray and control method for flash based fpga cell
US8120955B2 (en)2009-02-132012-02-21Actel CorporationArray and control method for flash based FPGA cell
US8294488B1 (en)2009-04-242012-10-23Adesto Technologies CorporationProgrammable impedance element circuits and methods
US8426839B1 (en)2009-04-242013-04-23Adesto Technologies CorporationConducting bridge random access memory (CBRAM) device structures
US10855286B2 (en)2009-07-022020-12-01Microsemi Soc Corp.Front to back resistive random-access memory cells
US8269204B2 (en)2009-07-022012-09-18Actel CorporationBack to back resistive random access memory cells
US8415650B2 (en)2009-07-022013-04-09Actel CorporationFront to back resistive random access memory cells
US9991894B2 (en)2009-07-022018-06-05Microsemi Soc Corp.Resistive random access memory cells
US8320178B2 (en)2009-07-022012-11-27Actel CorporationPush-pull programmable logic device cell
US8269203B2 (en)2009-07-022012-09-18Actel CorporationResistive RAM devices for programmable logic devices
US20110001115A1 (en)*2009-07-022011-01-06Actel CorporationResistive ram devices for programmable logic devices
US10256822B2 (en)2009-07-022019-04-09Microsemi Soc Corp.Front to back resistive random access memory cells
US20110001108A1 (en)*2009-07-022011-01-06Actel CorporationFront to back resistive random access memory cells
US20110001116A1 (en)*2009-07-022011-01-06Actel CorporationBack to back resistive random access memory cells
US8723151B2 (en)2009-07-022014-05-13Microsemi SoC CorporationFront to back resistive random access memory cells
US8981328B2 (en)2009-07-022015-03-17Microsemi SoC CorporationBack to back resistive random access memory cells
US8824038B2 (en)2009-07-222014-09-02Jean-Christophe GironElectrochromic device
US8947913B1 (en)2010-05-242015-02-03Adesto Technologies CorporationCircuits and methods having programmable impedance elements
US8687403B1 (en)2010-06-102014-04-01Adesto Technologies CorporationCircuits having programmable impedance elements
US8829482B1 (en)2010-09-232014-09-09Adesto Technologies CorporationVariable impedance memory device structure and method of manufacture including programmable impedance memory cells and methods of forming the same
US9401472B1 (en)2010-09-232016-07-26Adesto Technologies CorporationProgrammable impedance elements and devices that include such elements
US8654561B1 (en)2010-10-292014-02-18Adesto Technologies CorporationRead methods, circuits and systems for memory devices
US8999819B2 (en)2010-11-142015-04-07Arizona Board of Regents, A Body Corporate of the State of Arizona Acting For on Behalf of Arizona State UniversityDendritic metal structures, methods for making dendritic metal structures, and devices including them
US9000506B2 (en)2010-11-192015-04-07Panasonic Intellectual Property Management Co., Ltd.Variable resistance nonvolatile memory element and method for manufacturing the same
US9177639B1 (en)2010-12-092015-11-03Adesto Technologies CorporationMemory devices, circuits and methods having data values based on dynamic change in material property
US9099175B1 (en)2011-03-012015-08-04Adesto Technologies CorporationMemory devices and methods for read and write operation to memory elements having dynamic change in property
US8854873B1 (en)2011-05-052014-10-07Adesto Technologies CorporationMemory devices, architectures and methods for memory elements having dynamic change in property
US8816314B2 (en)2011-05-132014-08-26Adesto Technologies CorporationContact structure and method for variable impedance memory element
KR101997924B1 (en)2011-06-102019-10-01소니 주식회사Memory element and memory device
US20140376301A1 (en)*2011-06-102014-12-25Sony CorporationMemory element and memory device
US8885385B2 (en)*2011-06-102014-11-11Sony CorporationMemory element and memory device
KR20120137236A (en)*2011-06-102012-12-20소니 주식회사Memory element and memory device
US20120314479A1 (en)*2011-06-102012-12-13Sony CorporationMemory element and memory device
US9231200B2 (en)*2011-06-102016-01-05Sony CorporationMemory element and memory device
US8895953B1 (en)2011-07-152014-11-25Adesto Technologies CorporationProgrammable memory elements, devices and methods having physically localized structure
US8847192B2 (en)2011-09-132014-09-30Adesto Technologies France SarlResistive switching devices having alloyed electrodes and methods of formation thereof
US8995173B1 (en)2011-09-292015-03-31Adesto Technologies CorporationMemory cells, devices and method with dynamic storage elements and programmable impedance shadow elements
US9165648B1 (en)2011-12-232015-10-20Adesto Technologies CorporationResistive memory devices, circuits and methods having read current limiting
US9099633B2 (en)2012-03-262015-08-04Adesto Technologies CorporationSolid electrolyte memory elements with electrode interface for improved performance
US9305643B2 (en)2012-03-272016-04-05Adesto Technologies CorporationSolid electrolyte based memory devices and methods having adaptable read threshold levels
US8847191B1 (en)2012-03-272014-09-30Adesto Technologies CorporationProgrammable impedance memory elements, methods of manufacture, and memory devices containing the same
US8730752B1 (en)2012-04-022014-05-20Adesto Technologies CorporationCircuits and methods for placing programmable impedance memory elements in high impedance states
US8624219B1 (en)2012-04-122014-01-07Adesto Technologies CorporationVariable impedance memory element structures, methods of manufacture, and memory devices containing the same
US9147464B1 (en)2012-05-152015-09-29Adesto Technologies CorporationSystem architecture with multiple memory types, including programmable impedance memory elements
US9208870B2 (en)2012-09-132015-12-08Adesto Technologies CorporationMulti-port memory devices and methods having programmable impedance elements
US9330755B1 (en)2013-02-082016-05-03Adesto Technologies CorporationLatch circuits and methods with programmable impedance elements
US9836633B2 (en)2013-03-122017-12-05Arizona Board Of Regents, A Body Corporate Of The State Of Arizona Acting For And On Behalf Of Arizona State UniversityDendritic structures and tags
US9773141B2 (en)2013-03-122017-09-26Arizona Board Of Regents, A Body Corporate Of The State Of Arizona Acting For And On Behalf Of Arizona State UniversityDendritic structures and tags
EP2998950A1 (en)2013-03-122016-03-23Arizona Board of Regents, a Body Corporate of the State of Arizna acting for and on behalf of Arizon State UniversityDendritic structures and tags as physical unclonable function for anti-counterfeiting
EP2998949A1 (en)2013-03-122016-03-23Arizona Board of Regents, a Body Corporate of the State of Arizona acting for and on behalf of Arizona State UniversityDendritic structures and tags as physical unclonable function for anti-counterfeiting
US10074000B2 (en)2013-03-122018-09-11Arizona Board Of Regents, A Body Corporate Of The State Of Arizona Acting For And On Behalf Of Arizona State UniversityDendritic structures and tags
EP3958241A1 (en)2013-03-122022-02-23Arizona Board of Regents, a Body Corporate of the State of Arizona acting for and on behalf of Arizona State UniversityDendritic structures and tags
US11170190B2 (en)2013-03-122021-11-09Arizona Board Of Regents, A Body Corporate Of The State Of Arizona Acting For And On Behalf Of Arizona State UniversityDendritic structures and tags
US10223567B2 (en)2013-03-122019-03-05Arizona Board Of Regents, A Body Corporate Of The State Of Arizona Acting For And On Behalf Of Arizona State UniversityDendritic structures and tags
EP3007155A1 (en)2013-03-122016-04-13Arizona Board of Regents, a Body Corporate of the State of Arizona acting for and on behalf of Arizona State UniversityImage processing of dendritic structures used in tags as physical unclonable function for anti-counterfeiting
EP3467809A1 (en)2013-03-122019-04-10Arizona Board of Regents, a Body Corporate of the State of Arizona acting for and on behalf of Arizona State UniversityImage processing of dendritic structures used in tags as physical unclonable function for anti-counterfeiting
EP3002744A1 (en)2013-03-122016-04-06Arizona Board of Regents, a Body Corporate of the State of Arizona acting for and on behalf of Arizona State UniversityImage processing of dendritic structures used in tags as physical unclonable function for anti-counterfeiting
US10467447B1 (en)2013-03-122019-11-05Arizona Board Of Regents, A Body Corporate Of The State Of Arizona Acting For And On Behalf Of Arizona State UniversityDendritic structures and tags
US9711719B2 (en)2013-03-152017-07-18Adesto Technologies CorporationNonvolatile memory elements having conductive structures with semimetals and/or semiconductors
US11875501B2 (en)2014-11-072024-01-16Arizona Board Of Regents On Behalf Of Arizona State UniversityInformation coding in dendritic structures and tags
US10810731B2 (en)2014-11-072020-10-20Arizona Board Of Regents On Behalf Of Arizona State UniversityInformation coding in dendritic structures and tags
US11592016B2 (en)2015-11-242023-02-28Arizona Board Of Regents On Behalf Of Arizona State UniversityLow-voltage microfluidic valve device and system for regulating the flow of fluid
US10710070B2 (en)2015-11-242020-07-14Arizona Board Of Regents On Behalf Of Arizona State UniversityLow-voltage microfluidic valve device and system for regulating the flow of fluid
US10270451B2 (en)2015-12-172019-04-23Microsemi SoC CorporationLow leakage ReRAM FPGA configuration cell
US10128852B2 (en)2015-12-172018-11-13Microsemi SoC CorporationLow leakage ReRAM FPGA configuration cell
US10777268B2 (en)2016-05-132020-09-15Adesto Technologies CorporationStatic random access memories with programmable impedance elements and methods and devices including the same
US10147485B2 (en)2016-09-292018-12-04Microsemi Soc Corp.Circuits and methods for preventing over-programming of ReRAM-based memory cells
US10546633B2 (en)2016-12-092020-01-28Microsemi Soc Corp.Resistive random access memory cell
US11127694B2 (en)2017-03-232021-09-21Arizona Board Of Regents On Behalf Of Arizona State UniversityPhysical unclonable functions with copper-silicon oxide programmable metallization cells
US11869852B2 (en)2017-03-232024-01-09Arizona Board Of Regents On Behalf Of Arizona State UniversityPhysical unclonable functions with copper-silicon oxide programmable metallization cells
US10466969B2 (en)2017-05-082019-11-05Arizona Board Of Regents On Behalf Of Arizona State UniversityTunable true random number generator using programmable metallization cell(s)
US11430233B2 (en)2017-06-162022-08-30Arizona Board Of Regents On Behalf Of Arizona State UniversityPolarized scanning of dendritic identifiers
US10984861B1 (en)2017-07-122021-04-20Adesto Technologies CorporationReference circuits and methods for resistive memories
US10650890B2 (en)2017-08-112020-05-12Microsemi Soc Corp.Circuitry and methods for programming resistive random access memory devices
US10522224B2 (en)2017-08-112019-12-31Microsemi Soc Corp.Circuitry and methods for programming resistive random access memory devices
US11598015B2 (en)2018-04-262023-03-07Arizona Board Of Regents On Behalf Of Arizona State UniversityFabrication of dendritic structures and tags
US11244722B2 (en)2019-09-202022-02-08Arizona Board Of Regents On Behalf Of Arizona State UniversityProgrammable interposers for electrically connecting integrated circuits
US11935843B2 (en)2019-12-092024-03-19Arizona Board Of Regents On Behalf Of Arizona State UniversityPhysical unclonable functions with silicon-rich dielectric devices
US12307323B2 (en)2021-10-182025-05-20Arizona Board Of Regents On Behalf Of Arizona State UniversityAuthentication of identifiers by light scattering

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