US6566858B1 - Circuit for protecting chips against IDD fluctuation attacks - Google Patents
Circuit for protecting chips against IDD fluctuation attacksDownload PDFInfo
- Publication number
- US6566858B1 US6566858B1US09/112,763US11276398AUS6566858B1US 6566858 B1US6566858 B1US 6566858B1US 11276398 AUS11276398 AUS 11276398AUS 6566858 B1US6566858 B1US 6566858B1
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- United States
- Prior art keywords
- integrated circuit
- attack
- lfsr
- circuit
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034methodMethods0.000claimsabstractdescription11
- 238000012544monitoring processMethods0.000claimsabstractdescription6
- 230000003247decreasing effectEffects0.000claimsdescription2
- 101150048848ART10 geneProteins0.000description1
- 102100041023Coronin-2AHuman genes0.000description1
- 101000748858Homo sapiens Coronin-2AProteins0.000description1
- 101001106523Homo sapiens Regulator of G-protein signaling 1Proteins0.000description1
- 102100021269Regulator of G-protein signaling 1Human genes0.000description1
- 238000013461designMethods0.000description1
- 238000001514detection methodMethods0.000description1
- 238000011161developmentMethods0.000description1
- 230000000694effectsEffects0.000description1
- 125000001033ether groupChemical group0.000description1
- 238000012986modificationMethods0.000description1
- 230000004048modificationEffects0.000description1
- 230000002265preventionEffects0.000description1
- 238000011160researchMethods0.000description1
Images
Classifications
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/002—Countermeasures against attacks on cryptographic mechanisms
- H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/08—Randomization, e.g. dummy operations or using noise
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
- H04L2209/127—Trusted platform modules [TPM]
Definitions
- the present inventionrelates to tamper proof integrated circuit devices.
- a method of providing for resistance to attack of an integrated circuit by means of monitoring current changes in a current signal in the integrated circuitcomprising the step of including a spurious noise generation circuit as part of said integrated circuit for emitting electromagnetic noise and reducing Signal to Noise Ratio to obscure information in the current signal that is meaningful for the attack.
- the noise generation circuitcan comprises a random number generator such as a LFSR (Linear Feedback Shift Register).
- LFSRLinear Feedback Shift Register
- a LFSRLinear Feedback Shift Register
- the noise generatorcan be incorporated on any chip that manipulates secure data. This includes Smart Cards, Authentication chips, electronic keys, and cryptographic equipment. It can also be used as a source of pseudo-random bits for other Tamper Prevention and Detection circuitry.
- the method of protecting against I dd fluctuation attacksis to decrease the SNR (Signal to Noise Ratio) in the I dd signal. This is accomplished by increasing the amount of circuit noise and decreasing the amount of signal.
- the Noise Generator circuit described herewill cause enough state changes each cycle to obscure any meaningful information in the I dd signal.
- the Noise Generator circuitgenerates continuous circuit noise which interferes with other electromagnetic emissions from the chip's regular activities and adds noise to the I dd signal. Placement of the noise generator is not an issue on the chip due to the length of the emission wavelengths.
- the Noise Generator circuitcan comprise a maximal period LFSR, where the number of bits in the LFSR is comparable to other state changes in the chip that must be protected. For example, a 32-bit microprocessor can be protected by a 64-bit maximal period LFSR seeded with a non-zero number.
- the clock used for the noise generatorshould be running at the maximum clock rate for the chip in order to generate as much noise as possible.
- Tap selection of the 64 bits for a maximal-period LFSRyields bits 63 , 3 , 2 , 1 , and 0 , as shown in the drawing.
- the LFSRis sparse, in that not many bits are used for feedback (only 5 out of 160 bits are used).
- a suitable LFSR designis shown in the drawing.
- the present inventionhas been developed for utilization in an Artcam device.
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- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
The following co-pending U.S. patent applications, identified by their U.S. patent application serial numbers. (USSN) and Docket numbers (in brackets), were filed simultaneously to the present application on Jul. 10, 1998, and are hereby incorporated by cross-reference:
| 09/113,060 | 09/113,070 | 09/113,073 | 09/112,748 (ART04) |
| (ART01) | (ART02) | (ART03) | |
| 09/112,747 | 09/112,776 | 09/112,750 | 09/112,746 (ART09) |
| (ART06) | (ART07) | (ART08) | |
| 09/112,743 | 09/112,742 | 09/112,741 | 09/112,740 (ART13) |
| (ART10) | (ART11) | (ART12) | |
| 09/112,739 | 09/113,053 | 09/112,738 | 09/113,067 (ART18) |
| (ARTI5) | (ART16) | (ART17) | |
| 09/113,063 | 09/113,069 | 09/112,744 | 09/113,058 (ART22) |
| (ART19) | (ART20) | (ART21) | |
| 09/112,777 | 09/113,224 | 09/112,804 | 09/112,805 (ART27) |
| (ART24) | (ART25) | (ART26) | |
| 09/113,072 | 09/112,785 | 09/112,797 | 09/112,796 (ART31) |
| (ART28) | (ART29) | (ART30) | |
| 09/113,071 | 09/112,824 | 09/113,090 | 09/112,823 (ART38) |
| (ART32) | (ART33) | (ART34) | |
| 09/113,222 | 09/112,786 | 09/113,051 | 09/112,782 (ART44) |
| (ART39) | (ART42) | (ART43) | |
| 09/113,056 | 09/113,059 | 09/113,091 | 09/112,753 (ART48) |
| (ART45) | (ART46) | (ART47) | |
| 09/113,055 | 09/113,057 | 09/113,054 | 09/112,752 (ART53) |
| (ART50) | (ART51) | (ART52) | |
| 09/112,759 | 09/112,757 | 09/112,758 | 09/113,107 (ART58) |
| (ART54) | (ARTS6) | (ART57) | |
| 09/112,829 | 09/112,792 | 09/112,791 | 09/112,790 (ART62) |
| (ART59) | (ART60) | (ART61) | |
| 09/112,789 | 09/112,788 | 09/112,795 | 09/112,749 (ART66) |
| (ART63) | (ART64) | (ART65) | |
| 09/112,784 | 09/112,783 | 09/112,781 | 09/113,052 (DOT02) |
| (ART68) | (ART69) | (DOT01) | |
| 09/112,834 | 09/113,103 | 09/113,101 | 09/112,751 (IJ01) |
| (Fluid01) | (Fluid02) | (Fluid03) | |
| 09/112,787 | 09/112,802 | 09/112,803 (IJ04) | 09/113,097 (IJ05) |
| (IJ02) | (IJ03) | ||
| 09/113,099 | 09/113,084 | 09/113,066 (IJ08) | 09/112,778 (IJ09) |
| (IJ06) | (IJ07) | ||
| 09/112,779 | 09/113,077 | 09/113,061 (IJ12) | 09/112,818 (IJ13) |
| (IJ10) | (IJ11) | ||
| 09/112,816 | 09/112,772 | 09/112,819 (IJ16) | 09/112,815 (IJ17) |
| (IJ14) | (IJ15) | ||
| 09/113,096 | 09/113,068 | 09/113,095 (IJ20) | 09/112,808 (IJ21) |
| (IJ18) | (1J19) | ||
| 09/112,809 | 09/112,780 | 09/113,083 (IJ24) | 09/113,121 (IJ25) |
| (IJ22) | (IJ23) | ||
| 09/113,122 | 09/112,793 | 09/112,794 (IJ28) | 09/113,128 (IJ29) |
| (IJ26) | (IJ27) | ||
| 09/113,127 | 09/112,756 | 09/112,755 (IJ32) | 09/112,754 (IJ33) |
| (IJ30) | (IJ31) | ||
| 09/112,811 | 09/112,812 | 09/112,813 (IJ36) | 09/112,814 (IJ37) |
| (IJ34) | (IJ35) | ||
| 09/112,764 | 09/112,765 | 09/112,767 (IJ40) | 09/112,768 (IJ41) |
| (IJ38) | (IJ39) | ||
| 09/112,807 | 09/112,806 | 09/112,820 (IJ44) | 09/112,821 (IJ45) |
| (IJ42) | (IJ43) | ||
| 09/112,822 | 09/112,825 | 09/112,826 (IJM03) | 09/112,827 (IJM04) |
| (IJM01) | (1JM02) | ||
| 09/112,828 | 09/113,111 | 09/113,108 (IJM07) | 09/113,109 (IJM08) |
| (IJM05) | (IJM06) | ||
| 09/113,123 | 09/113,114 | 09/113,115 (IJM11) | 09/113,129 (1JM12) |
| (IJM09) | (IJM10) | ||
| 09/113,124 | 09/113,125 | 09/113,126(IJM15) | 09/113,119 (IJM16) |
| (IJM13) | (IJM14) | ||
| 09/113,120 | 09/113,221 | 09/113,116 (IJM19) | 09/113,118 (IJM20) |
| (IJM17) | (IJMI8) | ||
| 09/113,117 | 09/113,113 | 09/113,130 (IJM23) | 09/113,110 (IJM24) |
| (IJM21) | (IJM22) | ||
| 09/113,112 | 09/113,087 | 09/113,074 (IJM27) | 09/113,089 (IJM28) |
| (IJM25) | (IJM26) | ||
| 09/113,088 | 09/112,771 | 09/112,769 (IJM31) | 09/112,770 (IJM32) |
| (IJM29) | (IJM30) | ||
| 09/112,817 | 09/113,076 | 09/112,798 (IJM35) | 09/112,801 (IJM36) |
| (IJM33) | (IJM34) | ||
| 09/112,800 | 09/112,799 | 09/113,098 (IJM39) | 99/112,833 (IJM40) |
| (IJM37) | (IJM38) | ||
| 09/112,832 | 09/112,831 | 09/112,830 (IJM43) | 09/112,836 (IJM44) |
| (IJM41) | (IJM42) | ||
| 09/112,835 | 09/113,102 | 09/113,106 (IR02) | 09/113,105 (IR04) |
| (JM45) | (IR01) | ||
| 09/113,104 | 09/112,810 | 09/112,766 (IR10) | 09/113,085 (IR12) |
| (IR05) | (IR06) | ||
| 09/113,086 | 09/113,094 | 09/112,760 (IR16) | 09/112,773 (IR17) |
| (IR13) | (IR14) | ||
| 09/112,774 | 09/112,775 | 09/112,745 (IR20) | 09/113,092 (R21) |
| (IR18) | (IR19) | ||
| 09/113,100 | 09/113,093 | 09/113,062 | 09/113,064 |
| (MEMS02) | (MEMS03) | (MEMS04) | (MEMS05) |
| 09/113,082 | 09/113,081 | 09/113,080 | 09/113,079 |
| (MEMS06) | (MEMS07) | (MEMS09) | (MEMS10) |
| 09/113,065 | 09/113,078 | 09/113,075 | |
| (MEMS11) | (MEMS12) | (MEMS13). | |
Not applicable.
The present invention relates to tamper proof integrated circuit devices.
There is a fluctuation in current whenever an integrated circuit register change state. If there is a high enough signal to noise ratio, it is possible for an attacker of a tamper proof security system to monitor the difference in a standard Iddcurrent line that may occur when programming over either a high or a low bit. The change in Iddcan reveal information about keys or data. This is obviously undesirable.
It is an object of the present invention to provide a system resistant to attack by means of monitoring fluctuations in current lines.
In accordance with a first aspect of the present invention there is provided a method of providing for resistance to attack of an integrated circuit by means of monitoring current changes in a current signal in the integrated circuit, said method comprising the step of including a spurious noise generation circuit as part of said integrated circuit for emitting electromagnetic noise and reducing Signal to Noise Ratio to obscure information in the current signal that is meaningful for the attack.
The noise generation circuit can comprises a random number generator such as a LFSR (Linear Feedback Shift Register).
Notwithstanding any ether forms which may fall within the scope of the present invention, preferred forms of the invention will now be described, by way of example only, with reference to the accompanying drawing which illustrates a Linear Feedback Shift Register suitable for use with the preferred embodiment.
In the preferred embodiment, a LFSR (Linear Feedback Shift Register) is utilized as a noise generator for the purpose of obscuring the Iddfluctuations in a chip. The noise generator can be incorporated on any chip that manipulates secure data. This includes Smart Cards, Authentication chips, electronic keys, and cryptographic equipment. It can also be used as a source of pseudo-random bits for other Tamper Prevention and Detection circuitry. The method of protecting against Iddfluctuation attacks is to decrease the SNR (Signal to Noise Ratio) in the Iddsignal. This is accomplished by increasing the amount of circuit noise and decreasing the amount of signal. The Noise Generator circuit described here will cause enough state changes each cycle to obscure any meaningful information in the Iddsignal.
The Noise Generator circuit generates continuous circuit noise which interferes with other electromagnetic emissions from the chip's regular activities and adds noise to the Iddsignal. Placement of the noise generator is not an issue on the chip due to the length of the emission wavelengths. In a first embodiment the Noise Generator circuit can comprise a maximal period LFSR, where the number of bits in the LFSR is comparable to other state changes in the chip that must be protected. For example, a 32-bit microprocessor can be protected by a 64-bit maximal period LFSR seeded with a non-zero number. The clock used for the noise generator should be running at the maximum clock rate for the chip in order to generate as much noise as possible.
Tap selection of the 64 bits for a maximal-period LFSR (i.e. the LFSR will cycle through all 264−1 states, 0 is not a valid state) yields bits63,3,2,1, and0, as shown in the drawing. The LFSR is sparse, in that not many bits are used for feedback (only 5 out of 160 bits are used). A suitable LFSR design is shown in the drawing.
It would be appreciated by a person skilled in the art that numerous variations and/or modifications may be made to the present invention as shown in the specific embodiment without departing from the spirit or scope of the invention as broadly described. The present embodiment is, therefore, to be considered in all respects to be illustrative and not restrictive.
The present invention has been developed for utilization in an Artcam device.
Claims (9)
1. A method of providing for resistance to attack of an integrated circuit by means of monitoring current changes in a current signal in the integrated circuit, said method comprising the step of including as part of said integrated circuit a spurious electromagnetic noise generation circuit for emitting electromagnetic noise and reducing a Signal to Noise Ratio to obscure information in the current signal that is meaningful for the attack.
2. A method as claimed inclaim 1 wherein said noise generation circuit comprises a random number generator.
3. A method as claimed inclaim 2 wherein said random number generator comprises a LFSR (Linear Feedback Shift Register).
4. A method as claimed inclaim 3 further including the step of clocking said LFSR at a maximum clock rate of the integrated circuit.
5. An integrated circuit resistant to attack by monitoring current changes in a current signal in the integrated circuit the integrated circuit including a spurious electromagnetic noise generation circuit for emitting electromagnetic noise and decreasing a Signal to Noise Ratio to obscure information in the current signal that is meaningful for the attack.
6. An integrated circuit as claimed inclaim 5 wherein said noise generation circuit comprises a random number generator.
7. An integrated circuit as claimed inclaim 6 wherein said random number generator comprises a LFSR (Linear Feedback Shift Register).
8. A method as claimed inclaim 3 wherein a number of bits in the LFSR is comparable to other state changes in the integrated circuit that are to be protected from the attack.
9. An integrated circuit as claimed inclaim 7 wherein a number of bits in the LFSR is comparable to other state changes in the integrated circuit that are to be protected from the attack.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/112,763US6566858B1 (en) | 1998-07-10 | 1998-07-10 | Circuit for protecting chips against IDD fluctuation attacks |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/112,763US6566858B1 (en) | 1998-07-10 | 1998-07-10 | Circuit for protecting chips against IDD fluctuation attacks |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US6566858B1true US6566858B1 (en) | 2003-05-20 |
Family
ID=22345718
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US09/112,763Expired - LifetimeUS6566858B1 (en) | 1998-07-10 | 1998-07-10 | Circuit for protecting chips against IDD fluctuation attacks |
Country Status (1)
| Country | Link |
|---|---|
| US (1) | US6566858B1 (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030185392A1 (en)* | 2002-03-26 | 2003-10-02 | Inng-Lane Sun | Random number generator |
| US7052117B2 (en) | 2002-07-03 | 2006-05-30 | Dimatix, Inc. | Printhead having a thin pre-fired piezoelectric layer |
| US20060138545A1 (en)* | 2004-12-24 | 2006-06-29 | Hon Hai Precision Industry Co., Ltd. | Protective circuit for protecting chip from misoperation |
| US20060139825A1 (en)* | 2004-12-23 | 2006-06-29 | Hon Hai Precision Industry Co., Ltd. | Protective circuit for protecting chip from misoperation |
| US7988247B2 (en) | 2007-01-11 | 2011-08-02 | Fujifilm Dimatix, Inc. | Ejection of drops having variable drop size from an ink jet printer |
| US8459768B2 (en) | 2004-03-15 | 2013-06-11 | Fujifilm Dimatix, Inc. | High frequency droplet ejection device and method |
| US8491076B2 (en) | 2004-03-15 | 2013-07-23 | Fujifilm Dimatix, Inc. | Fluid droplet ejection devices and methods |
| US8708441B2 (en) | 2004-12-30 | 2014-04-29 | Fujifilm Dimatix, Inc. | Ink jet printing |
| US20160371487A1 (en)* | 2015-06-16 | 2016-12-22 | Intel Corporation | Enhanced security of power management communications and protection from side channel attacks |
| US9928978B1 (en) | 2015-03-30 | 2018-03-27 | Sean Butler | Device monitoring prevention in power systems |
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| US4495560A (en)* | 1980-07-09 | 1985-01-22 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Fluctuating drive system |
| US4771276A (en)* | 1985-04-15 | 1988-09-13 | International Business Machines Corporation | Electromagnetic touch sensor input system in a cathode ray tube display device |
| US5095270A (en)* | 1989-08-16 | 1992-03-10 | U.S. Philips Corporation | Method of suppressing current distribution noise in a dc squid |
| US5804975A (en)* | 1996-09-18 | 1998-09-08 | Lucent Technologies Inc. | Detecting breakdown in dielectric layers |
| US5872849A (en)* | 1994-01-13 | 1999-02-16 | Certco Llc | Enhanced cryptographic system and method with key escrow feature |
- 1998
- 1998-07-10USUS09/112,763patent/US6566858B1/ennot_activeExpired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4495560A (en)* | 1980-07-09 | 1985-01-22 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Fluctuating drive system |
| US4771276A (en)* | 1985-04-15 | 1988-09-13 | International Business Machines Corporation | Electromagnetic touch sensor input system in a cathode ray tube display device |
| US5095270A (en)* | 1989-08-16 | 1992-03-10 | U.S. Philips Corporation | Method of suppressing current distribution noise in a dc squid |
| US5872849A (en)* | 1994-01-13 | 1999-02-16 | Certco Llc | Enhanced cryptographic system and method with key escrow feature |
| US5804975A (en)* | 1996-09-18 | 1998-09-08 | Lucent Technologies Inc. | Detecting breakdown in dielectric layers |
Non-Patent Citations (1)
| Title |
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| Telecommunicatins media.* |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030185392A1 (en)* | 2002-03-26 | 2003-10-02 | Inng-Lane Sun | Random number generator |
| US7526087B2 (en)* | 2002-03-26 | 2009-04-28 | Industrial Technology Research Institute | Random number generator |
| US8162466B2 (en) | 2002-07-03 | 2012-04-24 | Fujifilm Dimatix, Inc. | Printhead having impedance features |
| US7052117B2 (en) | 2002-07-03 | 2006-05-30 | Dimatix, Inc. | Printhead having a thin pre-fired piezoelectric layer |
| US7303264B2 (en) | 2002-07-03 | 2007-12-04 | Fujifilm Dimatix, Inc. | Printhead having a thin pre-fired piezoelectric layer |
| US8491076B2 (en) | 2004-03-15 | 2013-07-23 | Fujifilm Dimatix, Inc. | Fluid droplet ejection devices and methods |
| US8459768B2 (en) | 2004-03-15 | 2013-06-11 | Fujifilm Dimatix, Inc. | High frequency droplet ejection device and method |
| US20060139825A1 (en)* | 2004-12-23 | 2006-06-29 | Hon Hai Precision Industry Co., Ltd. | Protective circuit for protecting chip from misoperation |
| US20060138545A1 (en)* | 2004-12-24 | 2006-06-29 | Hon Hai Precision Industry Co., Ltd. | Protective circuit for protecting chip from misoperation |
| US8708441B2 (en) | 2004-12-30 | 2014-04-29 | Fujifilm Dimatix, Inc. | Ink jet printing |
| US9381740B2 (en) | 2004-12-30 | 2016-07-05 | Fujifilm Dimatix, Inc. | Ink jet printing |
| US7988247B2 (en) | 2007-01-11 | 2011-08-02 | Fujifilm Dimatix, Inc. | Ejection of drops having variable drop size from an ink jet printer |
| US9928978B1 (en) | 2015-03-30 | 2018-03-27 | Sean Butler | Device monitoring prevention in power systems |
| US20160371487A1 (en)* | 2015-06-16 | 2016-12-22 | Intel Corporation | Enhanced security of power management communications and protection from side channel attacks |
| US9721093B2 (en)* | 2015-06-16 | 2017-08-01 | Intel Corporation | Enhanced security of power management communications and protection from side channel attacks |
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Legal Events
| Date | Code | Title | Description |
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| AS | Assignment | Owner name:SILVERBROOK RESEARCH PTY LTD, AUSTRALIA Free format text:ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SILVERBROOK, KIA;WALMSLEY, SIMON;REEL/FRAME:009509/0960 Effective date:19980702 | |
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| FPAY | Fee payment | Year of fee payment:8 | |
| AS | Assignment | Owner name:ZAMTEC LIMITED, IRELAND Free format text:ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SILVERBROOK RESEARCH PTY. LIMITED;REEL/FRAME:031506/0489 Effective date:20120503 | |
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