US6456220B1 - Analog-to-digital converter for processing differential and single-ended inputs - Google Patents

Abstract

An analog-to-digital converter configurable for converting both differential and single-ended analog signals. Charge sharing between two input capacitors and a DAC capacitor allow the full dynamic range of the ADC device to be used when full scale differential analog input signals are converted. When configured for single-ended operation, charge sharing of the half scale single-ended input analog voltage occurs between one input capacitor and the DAC capacitor to allow the full dynamic range of the ADC device to again be utilized.

Description

TECHNICAL FIELD OF THE INVENTION

The present invention relates in general to analog-to-digital converters, and more particularly to converters adapted for processing single ended and differential input signals.

BACKGROUND OF THE INVENTION

Although a substantial portion of signal processing is carried out with digital circuits, there are many applications that require the generation and a processing of analog signals. When mixed signal processing is involved, it is a common practice to convert the analog signals to corresponding digital signals for processing by a microprocessor, or the like. Indeed, many microprocessor chips are commercially available with on-board analog-to-digital converters (ADC's). The particular type of analog signals themselves utilized may require different types of conversion circuits and techniques. For example, various circuits generate analog signals on a single conductor, referenced with respect to ground. This type of signal is known as “single ended”, meaning that the magnitude of the signal is measured with respect to a known reference voltage, such as ground. Other circuits generate differential analog signals on a pair of conductors. One analog signal on one conductor is measured with respect to the other conductor, and not with respect to a circuit ground. Such type of signals can be generated by transformers, differential output amplifiers as well as many other circuits.

The design and construction of an ADC for converting signal-ended signals is less complex than that of ADC devices for converting differential signals. It is not uncommon for a differential ADC to include two main capacitor arrays, two sets of analog switches, a differential comparator and successive-approximation logic. There are also many situations in which single-ended and differential signals are available, and it would be desirable to employ a single ADC for processing both types of signals.

From the foregoing, it can be seen that a need exists for an analog-to-digital converter that can process both single-ended and differential analog signals. Another need exists for an ADC that is efficient in design, and does not require duplicated circuits for processing differential-type analog signals. Yet another need exists for an ADC design that can be configured to convert both differential and single-ended analog signals without compromising the dynamic range of the ADC device. It would also be desirable to provide an ADC device that includes a comparator that can be configured as a high gain operational amplifier, and can be operated with a lower gain so that the comparator operates at a high speed. Another need exists for utilizing plural low gain stages to provide an overall high gain and high speed operation. Another need exists for an improved ADC that provides an efficient programmable gain circuit.

SUMMARY OF THE INVENTION

In accordance with the principles and concepts of the invention, there is disclosed an analog-to-digital converter for processing both single-ended and differential type of analog signals. The disclosed embodiment of the ADC can process both types of analog signals without compromising the dynamic range of the converter.

In accordance with the disclosed embodiment of the invention, a single digital-to-analog converter is employed with the ADC to process both differential and single-ended signals. The capacitor inputs to a high speed comparator can be switched to store a sample of a differential input signal, and then switched so as to be placed in series, and then combined with a SAR-generated analog reference. The series-connected input capacitors can share the sampled charge of the +/− full scale differential signals and utilize the full dynamic range of the ADC device. When configured for single-ended operation, only one input capacitor is utilized with the full scale single-ended analog voltage to utilize the full dynamic range of the ADC device.

An operational amplifier is utilized in the disclosed ADC device, and configured as a high precision unity gain amplifier with a very high open-loop gain to sample the analog input voltage on the input capacitors, and reconfigured to provide an open loop, moderate gain comparator to provide a high speed and high resolution of whether the input analog voltage(s) is greater or less than the SAR-generated analog reference. To provide even higher gain comparator operation, plural moderate-gain amplifiers provide additional high speed amplification to the comparator output.

In another embodiment, programmable gain can be provided in the ADC device by utilizing different-valued capacitors switched in parallel with capacitors driven by the digital-to-analog converter. By employing charge-sharing between the input capacitors and the programmable gain capacitors, an effective change in the gain of the ADC can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS

Further features and advantages will become apparent from the following and more particular description of the preferred and other embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters generally refer to the same parts or elements throughout the views, and in which:

FIG. 1 is a detailed electrical schematic diagram of the ADC constructed according to one embodiment of the invention;

FIG. 2 is a set of electrical waveforms illustrating the timing of the various circuits of the ADC of FIG. 1; and

FIG. 3 illustrates the alternative circuits for providing programmable gain to the ADC of FIG.1.

DETAILED DESCRIPTION OF THE INVENTION

TheADC device10 illustrated in FIG. 1 is adapted for utilizing the same circuits in the conversion of both differential and single-ended analog signals. Theconverter10 is of the type utilizing successive approximation circuits for generating an analog reference voltage for comparing with the input analog voltage to be converted. To that end, theADC10 includes a successive approximation register and associatedcircuits12 of the type that is well known in the field. A successiveapproximation register control14 controls theSAR12 in a traditional manner to generate a N-bit digital word on theoutput16. In the preferred form of the invention, a 12-bit word is generated onbus16. The 12-bit bus16 provides thedigital output18 of theADC device10.

The digital word produced by thesuccessive approximation register12 is also coupled onbus16 to a digital-to-analog converter (DAC)device20. TheDAC device20 can be of conventional design for converting N-bit digital signals to a corresponding analog reference signal onoutput22. Briefly, the operation of thesuccessive approximation register12 is described as follows. A counter register known as a SAR register in theSAR12 is reset so that all bits are zero, except the most significant bit (MSB). TheDAC20 produces a corresponding analog reference signal that is compared by thecomparator circuit24 with an analog signal provided at thedevice input26. Depending on the logic state of the output of thecomparator circuit24, the most significant bit of the initial digital word remains a logic 1, or is reset to a logic 0. The next significant bit of the counter in theSAR12 is then set and another iteration is carried out to determine if the analog input signal to be converted is greater or less than the corresponding analog reference signal generated by theDAC device20. The process is repeated down to the least significant bit (LSB), at which time the counter register in theSAR12 provides the resultant digital word onbus16 as anoutput18 for theADC device10.

Thecomparator portion24 of theADC device10 includes a differential input, differential output type ofoperational amplifier28. As will be described below, thecomparator circuit24 is configured as a unity feedback amplifier with high open-loop gain to sample the analog input signals, and reconfigurable with a lower gain to function as a high speed comparator. Thecomparator28 includes aninverting input30 and a correspondingnoninverting output32. In like manner, anoninverting input34 and corresponding invertingoutput36 are provided by thecomparator28. A commonmode reference voltage38 is coupled to thecomparator28. Acommon mode output40 of thecomparator28 is coupled to the invertingoutput36, the operation of which will be described below. Coupled between the invertinginput30 andnoninverting output32 of thecomparator28 is asemiconductor switch42. In practice, theswitch42 can be one or more transistor switches controlled by a phase1 clock signal, designated ph1. In like manner, thenoninverting input34 and invertingoutput36 of thecomparator28 have coupled therebetween a corresponding phase1switch44. Connected in parallel with the phase1switch44 is a phase3switch46. Acapacitor48 is connected between thenoninverting input34 of thecomparator28, and ground. Thecapacitor48 provides impedance matching on thenoninverting input34 of thecomparator28 to balance the capacitance ofcapacitor50 coupled to theoutput22 of theDAC device20.

The invertinginput30 of thecomparator28 is coupled through aseries input capacitor52 to a phase2switch54. The phase2switch54 is coupled to the A_in+analog input56 of theADC device10. Similarly, the other differential input A_in−58 is coupled through a phase2switch60 and aseries input capacitor62 to thenoninverting input34 of thecomparator28. At the junction between the phase2switch54 and theseries input capacitor52 associated with the invertinginput30, is a phase3switch64 which, when operated, connects theplate66 ofinput capacitor52 to ground. Another phase3switch68 is coupled to the junction of the phase2switch60 and theinput capacitor62, and ground. When operated, theswitch68 grounds oneplate70 ofinput capacitor62. Phase3 switches64 and68 are operated only in the single-ended operation of theADC device10. Lastly, a phase3switch72 is connected between the differential input conductors so that when operated, a short circuit is placed between theplates66 and70 ofrespective capacitors52 and62. The phase3switch72 is operated only during differential operation of theADC device10. The various switches are controlled by clock signals, as shown in FIG.2.

A gain-determiningresistor74 is coupled between thenoninverting output32 and invertingoutput36 of thecomparator28. The value of gain-settingresistor74 is selected to provide nominal gain of about ten thousand to thecomparator28 when configured as an amplifier. The second gain-determiningresistor76 is connected at its ends by way of respective phase3switches78 and80 between thenoninverting output32 and invertingoutput36 of thecomparator28. When the phase3switches78 and80 are operated, theresistor76 is placed in parallel withresistor74, thereby reducing the gain of thecomparator28. The gain of thecomparator28 is about ten when configured as a comparator. As will be described below, the purpose for this is that while the gain is reduced, the speed of thecomparator28 is increased, thereby providing high speed conversions of analog signals to corresponding digital signals.

Thenoninverting output32 andnoninverting output36 of thecomparator28 are coupled to the differential inputs of asecond amplifier stage82. The differential outputs of theamplifier stage82 are coupled to the corresponding differential inputs of athird amplifier stage84. Theamplifiers82 and84 are each configured with respective gains of about six. The differential outputs of thesecond amplifier84 are coupled to aconventional sense amplifier86 constructed much like that utilized in a typical DRAM memory. Thesense amplifier86 is controlled by a latch signal generated by theSAR control14. The differential outputs of thesense amplifier86 are coupled to the return-to-zero (RTZ)slave latch88. Theslave latch88 is much like a set-reset type of latch well known in the art. Theslave latch88 is controlled by a latch signal generated by theSAR control14. The setoutput90 of theslave latch88 is coupled to the successiveapproximation register circuit12.

With reference to FIG. 2, there is illustrated the timing waveforms generated by theSAR control14 and utilized to control the various phase1, phase2 and phase3 switches identified above. Atrack signal100 can be applied to theADC device10 by a user to commence the conversion process of analog signals to corresponding digital signals. As illustrated, thetrack signal100 is driven to a logic low at time T₀to initiate the 12-bit conversion process which continues until thetrack signal100 returns to a logic high level shown by risingedge108. A phase1clock signal102 is driven to a logic low between times T₁and T₂to open the phase1switches42 and44. When driven to a logic high level, the phase1signal102 maintains the corresponding switches42 and44 closed. At times T₂, a phase2signal104 is driven to a logic low to open the corresponding switches54 and60. During the logic high levels of the phase2signal104, theswitches54 and60 are closed, thereby allowing theinput capacitors52 and62 to charge to respective voltages corresponding to the analog inputs. Lastly, a phase3signal106, which is initially at a logic low level, is driven to a logic high level at time T₃. At time T₄, the phase3signal106 is at a logic high level, thereby closing therespective switches46,64,68,72,78 and80. As noted in FIG. 2, the phase1clock signal102, phase2clock signal104 and phase3clock signal106 return to their initial logic levels after thetrack signal100 has returned to its high state, indicating termination of the conversion process.

As will be described in detail below, when anoptional switch59 associated with thenoninverting input34 of thecomparator28 is closed, theADC device10 functions to convert single-ended analog signals to corresponding digital signals. Otherwise, whenswitch59 is open, differential analog signals can be applied toinputs56 and58 of theADC device10. The operation of theADC device10 will first be described in conjunction with the conversion of differential analog signals coupled to the device. For purposes of example only, it is assumed that a differential voltage of +5 volt is applied to input56 and −5 volts is applied toinput58. It is further assumed that thecommon mode output40 of thecomparator28 maintains the invertingoutput36 at about a 0 volt level. In the described embodiment of the invention, the conversion cycle noted in FIG. 2 takes place in about 400 nanoseconds for each of the twelve bits. Accordingly, in order to provide a conversion of the input analog signal to the corresponding 12-bit word takes in the neighborhood of about 4.8 microseconds.

Because the phase1signal102 is initially at a logic high level prior to time T₁, the feedback switches42 and44 are closed, thereby forcing thecomparator28 to operate as a closed-loop, unity gain operational amplifier with an open loop gain of about ten thousand. Additionally, when phase1switch44 is closed, a common mode voltage of about 0 volts is applied from the invertingoutput36 to thenoninverting input34. One plate ofinput capacitor62 is thus maintained at the common mode voltage of 0 volts. When phase1switch42 is closed, any offset voltage of thecomparator28 is captured at the invertinginput30. Thus, the plate of theseries input capacitor52 is maintained at the offset voltage. By initially maintaining one plate of theinput capacitor52 at the offset voltage of thecomparator28, the effects of such offset voltage do not adversely affect the conversion process, especially with the least significant bits. This process of capturing the comparator offset on thecapacitor52 is known as an auto-zeroing process. Once thecomparator28 is configured as an operational amplifier at time times T₁, the phase2switches54 and60 close between times T₁and times T₂. Differential analog voltages applied to thedifferential inputs56 and58 are thus coupled torespective plates66 and70 ofseries input capacitors52 and62. As noted above,input capacitors52 and62 are of essentially the same capacitance value. As an example, if +5 volts is applied to input56 and −5 volts is applied to input58,capacitors52 and62 will charge with the polarities shown in FIG.1.

Between times T₃and times T₄(FIG.2), the phase3signal106 driven to a logic high level, thereby closing switches46,72,78 and80. It is noted that during this time, phase1switches42 and44 are open, and the phase2switches54 and60 are also open. Once theseries input capacitors52 and62 are charged to voltages corresponding to the input analog voltages, the gain of thecomparator28 is reduced when a new gain-settingresistor76 is bridged across the other gain-determiningresistor74. The gain is reduced from about ten thousand to a factor of about ten, thereby increasing the speed of thecomparator28. This is due to the constant gain bandwidth product of operational amplifiers. Importantly, the closing of phase3switch72 short circuits theplate66 ofinput capacitor52 to theplate70 ofinput capacitor62. It is noted that when the phase3switch46 is closed, the common mode voltage (0 volts) is maintained at thenoninverting input34 of thecomparator28 When the phase3switch72 closes, the voltage at thenoninverting input34 of thecomparator28 remains the same, i.e., at about 0 volts, while the invertinginput30 goes to a voltage of about −10 volts +V_offset. The differential output voltage of thecomparator28 is applied thesecond amplifier stage82 which, in turn, has the output differential voltage thereof applied to thethird amplifier stage84. Depending on the polarity of the differential voltage at the output of thethird amplifier stage84, thesense amplifier86 is latched to either a logic 0 or a logic 1 output. The slave latch88 stores the digital signal, and applies the same to an input of theSAR12.

TheSAR control14 controls theSAR12 to produce a 12-bit digital signal according to standard operation of such type of circuits. The 12-bit word is applied onbus16 to theDAC20, which produces a corresponding analog signal onoutput22. In one embodiment of the invention, thecapacitor50 is of the same value as theseries input capacitors52 and62. Stated another way, the composite capacitance value of series-connectedinput capacitors52 and62 is one-half that of theindividual capacitors52 or62. The analog reference voltage generated by theDAC20 thus need only be one-half of the voltage that exists at the invertinginput30 of thecomparator28. Thus, in order to offset the composite analog voltage at the invertinginput30 of thecomparator28, the analog reference voltage generated at theDAC output22 need only be half of the voltage on the invertinginput30. This is a result of the charge that is shared betweencapacitors50,52 and62.

In any event, as will be described below, by providing a variable capacitor in lieu ofcapacitor50, the effective gain of theADC device10 can be programmably changed. By successively generating digital words by theSAR12, and producing corresponding analog signals for comparing with the input analog signal, the various digital bits are generated such that overall digital word is equivalent to the input analog differential voltage.

With regard to the single-ended operation of theADC device10, the user can program various inputs thereto for choosing whether differential or single-ended operation is desired. In response to an input indicating single-ended operation, the timing as shown in FIG. 2 does not change, but rather various input switches are responsive to either single or differential operation. For example, the phase3switch72 is operable only during differential operation, and not during single-ended operation. In contrast, phase3switches64 and68 are responsive only to single-ended operation during phase3, and not responsive to differential operation. Moreover, during single-ended operation, it is assumed that the analog signals to be converted are applied to input56, andADC input58 can either remain externally open-circuited, or can be connected to ground via theoptional switch59.

In single-ended operation, thenoninverting input34 of thecomparator28 remains at the common mode voltage of about 0 volts, much like that described above in connection with the differential operation of theADC device10. Further, assuming a single-ended analog voltage of +5 volts is applied to input terminal56, the conversion to corresponding digital signals is carried out in the following manner. Initially, phase1switches42 and44 are closed so that thecomparator28 operates in a unity gain configuration with high open-loop gain to provide sampling of the single-ended analog input voltage. The input analog voltage is applied to plate66 ofinput capacitor52 by way of the closed phase2switch54. Although the phase2switch60 is also closed, no analog voltage is applied to such ADC input. Those skilled in the art may choose to utilize a switch connected from theADC input terminal58 to ground, and close such switch during a single-ended operation of theADC device10. At time T₃(FIG.2), the phase1 switches open, as do the phase2 switches. The phase3 switches, except forswitch72, then operate, in which event three things occur. First, the phase3switches78 and80 close to thereby reduce the gain of thecomparator28 and thereby increase the speed by which the comparison occurs. Secondly, phase3switch46 closes so that the common mode voltage oncomparator output36 is coupled to thenoninverting comparator input34. As noted above, in the preferred form of the invention, the common mode voltage selected is 0 volts, although other voltages may be selected to satisfy other constraints. Thirdly, the phase3switch64 closes, thereby transferring the +5 volts stored oninput capacitor52 to the invertinginput30 of thecomparator28 When theplate66 of theinput capacitor52 is grounded by the phase3switch64, −5 volts is transferred to the invertinginput30 of thecomparator28.

In the single-ended operation, the phase3switch72 does not close, and thus theinput capacitors52 and62 are not placed in series, as was done in the differential mode of operation. In the differential mode, the series-connectedinput capacitors52 and62 together thus represent half the composite capacitance of thecapacitors52 and62. In contrast, for single-ended operation, the value ofcapacitor52 is not otherwise reduced, and thus it is of the same value as thecapacitor50 associated with theDAC20. The charge sharing in the single-ended operation is thus between the equal-value capacitors50 and52. As such, if the analog voltage at the invertinginput30 of thecomparator28 is +5 volts +V_offset, in order to switch theoutput32 of thecomparator28, thecapacitor50 need only couple a voltage of equal magnitude and opposite polarity, as compared to the voltage on thecomparator input30. With this arrangement, the full dynamic range of theADC device10 is utilized in the single-ended mode. The conversion process is carried out in the same manner noted above, where theSAR circuit12 carries out an iteration of different digital values which, when converted to corresponding analog reference voltages, approach the magnitude of the voltage on the invertinginput30 of thecomparator28.

A Table of the comparison during single-ended operation and the differential operation of theADC device10 is set forth below.

TABLE 1
Differential Operation

	Input Analog Voltage	Digital Output (2's Complement)

	Minimum	−Vref	1000 . . . 0
	Maximum	+Vref	0111 . . . 1

Single-Ended Operation

	Input Analog Voltage	Digital Output (Unsigned Magnitude)

	Minimum	0 volts	0000 . . . 0
	Maximum	+Vref	1111 . . . 1

As can be seen by the foregoing Table 1, the full dynamic range of theADC device10 is utilized in both the differential and the single-ended operation. This advantage is realized even though the input voltage range in the differential mode is twice that of the input voltage range during the single-ended mode of operation. It can be appreciated that the full dynamic range of theADC device10 is utilized by way of the arrangement in which theinput capacitors52 and62 are configured during the different modes of operation. It can also be appreciated that only asingle DAC20 need be employed, because thenoninverting input34 of thecomparator28 is always maintained at a common mode voltage during both modes of operation. An efficient and costeffective ADC device10 is thereby achieved.

In FIG. 3, there is illustrated another embodiment of theADC device100 constructed according to the principles and concepts of the invention. Included within thisADC device100 is aprogrammable gain circuit102 which constitutes a number of switched capacitors for providing different capacitance values connected to the invertinginput30 of thecomparator28. The switchedcapacitors102 can effectively provide avariable capacitor50 in connection with theADC device10 shown in FIG.1. As shown in FIG. 3, theinput capacitors52 and62 are of identical value, designated nominally by the value “C”. In practice, the value ofinput capacitors52 and62 are about 5 pf. The capacitance values of theprogrammable gain circuit102, includes various values of a nominal value “C”. In this example, C=16 C′.

Theoutput22 of theDAC20 is coupled to a number ofswitches104, each connected in series with arespective capacitor106. Theswitches104 can selectively be closed by theSAR control14 to place thevarious capacitors106 in parallel with each other. A plate of eachcapacitor106 is connected in common to aconductor108 which is connected to the invertinginput30 of thecomparator28. In the example, there are sixcapacitors106 with respective values C′, C′, 2 C′, 4 C′, 8 C′ and 16 C′. Therespective switches104 are effective to couple one or more of thecapacitors106 between theDAC output22 and the invertinginput30 of thecomparator28. When so connected, the switches are considered “on”.Switches104 are also switchable for connecting one plate of eachcapacitor106 to ground. When so connected, the switch position is considered “GND”. The TABLE 2 set forth below lists the various combinations ofcapacitors106 and theswitch settings104 in order to produce different programmable gains. The various combination of gains can be one-half, 1, 2, 4, 8, or 16. The gain of one-half is made available for users of theADC device100 when input signals are greater in magnitude than the reference voltage produced at theoutput22 of theDAC20. As can be seen from TABLE 2, the less capacitance that is switched on, the greater the gain.

TABLE 2
PROGRAMMABLE GAIN-SWITCH CONNECTION

Gain

	16C'	8C'	4C'	2C'	1C'	1C'
	½	ON	ON	ON	ON	ON	ON
	1	GND	ON	ON	ON	ON	ON
	2	GND	GND	ON	ON	ON	ON
	4	GND	GND	GND	ON	ON	ON
	8	GND	GND	GND	GND	ON	ON
	16	GND	GND	GND	GND	GND	ON

Although the preferred embodiment has been described in detail, it should be understood that various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (23)

What is claimed is:

1. An ADC, comprising:

a comparator having differential inputs;

said comparator configured to provide a first gain during an analog sampling of input analog signals to be converted, and a second gain when functioning as a comparator;

an input switching circuit for switching a pair of input capacitors for single-ended and differential storage of analog signals;

a single DAC operable to provide reference analog voltages during operation in converting single-ended and differential analog signals to corresponding digital signals; and

SAR circuits for receiving a signal generated by said comparator and for generating digital signals coupled to said DAC.

2. The ADC ofclaim 1, wherein said comparator has a differential output, and configured to maintain one output of said differential output at a common mode voltage level.

3. The ADC ofclaim 2, further including a feedback circuit between one output of said differential output and a corresponding input of said comparator to maintain said comparator input at said common mode voltage level during an analog to digital conversion.

4. The ADC ofclaim 3, wherein said feedback comprises a switch.

5. The ADC ofclaim 1, wherein said switching circuit includes one or more switches for connecting said pair of input capacitors in series during a differential operating mode and for utilizing only one said input capacitor to store an analog signal amplitude during a single-ended operating mode.

6. The ADC ofclaim 5, wherein said pair of input capacitors are each coupled between a respective differential input of said ADC, and a respective differential input of said comparator.

7. The ADC ofclaim 6, wherein a reference analog voltage generated by said DAC is coupled to one input of said differential input of said comparator.

8. The ADC ofclaim 1, wherein each said input capacitor is in series between a respective ADC input and a differential input of said comparator, and wherein said input switching circuit includes at least one switch for placing said input capacitors in series with each other to share electrical charge therebetween.

9. The ADC ofclaim 1, wherein a first input capacitor of said pair of capacitors is coupled between a first input of a differential ADC input and a first input of the comparator differential input, and a second input capacitor of said pair of capacitors is coupled between a second input of the differential ADC input and a second input of the comparator differential input.

10. The ADC ofclaim 9, wherein said input switching circuit includes a respective switch in series with each said first and second input capacitor which, when closed, allow said pair of capacitors to sample an input analog voltage to be converted.

11. The ADC ofclaim 9, wherein an output of said DAC is coupled to said first input of said comparator.

12. The ADC ofclaim 11, further including a capacitor coupling said DAC output to said comparator first input.

13. The ADC ofclaim 12, wherein said input switching circuit is operable to couple said DAC output capacitor and said first and second input capacitors all in series to share charge therebetween.

14. The ADC ofclaim 13, wherein said first and second input capacitors are of substantially equal capacitance.

15. The ADC ofclaim 1, wherein one capacitor plate of one said first or second input capacitor is maintained at a common mode voltage during a conversion process.

16. The ADC ofclaim 9, wherein said input switching circuit is operative to connect said first and second input capacitors during conversion of analog input differential signals so that a full dynamic range of the ADC is utilized, and operative to reconnect said first and second input capacitors during conversion of single-ended input analog signals so that a full dynamic range of the ADC is utilized.

17. The ADC ofclaim 1 wherein said input switching circuit is operative to disconnect one said input capacitor from an ADC input during single-ended operation, and ground one plate of said one input capacitor.

18. An ADC, comprising:

a comparator having a differential input and a differential output;

a DAC providing an analog reference voltage via a capacitor to an input of said comparator;

a first input capacitor coupled to an inverting input of said comparator;

a second input capacitor coupled to a noninverting input of said comparator;

a first switch for coupling said first input capacitor to a first differential input of said ADC, said first switch being operated to provide a sample of an input analog voltage to said first input capacitor;

a second switch for coupling said second input capacitor to a second differential input of said ADC, said second switch being operated to provide a sample of an input analog voltage to said second input capacitor;

a third switch for short circuiting a plate of each said first and second input capacitors together during a conversion of differential input analog signals and for removing the short circuit during conversion of single-ended input analog signals; and

at least one differential amplifier coupled to the differential output of said comparator.

19. The ADC ofclaim 18, further including a single DAC providing an analog reference signal via a capacitor to the inverting of said comparator.

20. The ADC ofclaim 18, further including a feedback from an output of the comparator to the noninverting input for maintaining the noninverting input at a common voltage during a conversion of an input analog signal to a corresponding digital signal.

21. An ADC, comprising:

a comparator having a differential input and a differential output;

a single DAC providing an analog reference voltage via a coupling capacitor to an inverting input of said comparator;

a first input capacitor coupled to an inverting input of said comparator;

a second input capacitor coupled to a noninverting input of said comparator;

a first switch for coupling said first input capacitor to a first differential input of said ADC, said first switch being operated to provide a sample of an input analog voltage to said first input capacitor;

a second switch for coupling said second input capacitor to a second differential input of said ADC, said second switch being operated to provide a sample of an input analog voltage to said second input capacitor; and

a third switch for short circuiting a plate of each said first and second input capacitors together during a conversion of differential input analog signals and for removing the short circuit during conversion of single-ended input analog signals.

22. The ADC ofclaim 21, further including a feedback from an output of the comparator to the noninverting input for maintaining the noninverting input at a common voltage during a conversion of an input analog signal to a corresponding digital signal.

23. The ADC ofclaim 21, further including at least one differential amplifier coupled to the differential output of said comparator.

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