US5410169A - Dynamic random access memory having bit lines buried in semiconductor substrate - Google Patents

Abstract

There is provided a DRAM memory cell structure. The semiconductor structure includes a semiconductor substrate of a first conductivity type having a main surface, source and drain regions of a second conductivity type formed in the main surface area of the semiconductor substrate, word lines extending in a first plane direction and formed on those portions of the semiconductor substrate which respectively lie between the source and drain regions, capacitors each having one of the source and drain regions as a storage node electrode, and bit lines buried in the semiconductor substrate and electrically connected to the source or drain regions, respectively.

Description

This application is a continuation of application Ser. No. 07/659,570, filed Feb. 22, 1991, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a dynamic random access memory (DRAM) and more particularly to the construction of memory cells thereof.

2. Description of the Related Art

The integration density and memory capacity of a DRAM in which each memory cell is formed of one transistor and one capacitor are rapidly increased with the progress of fine patterning technique. Use of a stacked capacitor cell structure is known as a method of increasing the capacitances of capacitors in the DRAM.

FIG. 1 is a cross sectional view of the conventional stacked capacitor cell taken along a bit line direction.

In order to form the stacked capacitor cell, afield oxide film 502 serving as an element isolation region is formed on a P-type silicon substrate 501 by local oxidation of silicon. After this, agate oxide film 503,gate electrode 504 and source/drain diffusedregions 505 are formed to constitute a transfer transistor. Further, aninterlevel insulator 506 is disposed on the resultant structure and astorage node electrode 508 with a film thickness of 3000 Å, for example, is formed of phosphorus doped polysilicon in acontact hole 507 formed in theinterlevel insulator 506. In order to electrically connect thestorage node electrode 508 to the source/drain diffusedregions 505, phosphorus is generally ion-implanted into thesubstrate 501 andstorage node electrode 508 to approximately 1×10¹⁶ cm^-2 (dose).

Then, aplate electrode 510 is formed of phosphorus doped polysilicon to a film thickness of 3000 Å, for example, with a capacitordielectric film 509 disposed between theplate electrode 510 and thestorage node electrode 508 and the like so as to form a stacked capacitor. After this, aninterlevel insulator 511 is formed on the resultant structure and acontact hole 512 is continuously formed in theinterlevel insulators 511 and 506. A bit line which is connected to thedrain region 505 via thecontact hole 512 is formed of amolybdenum silicide film 513, for example.

The DRAM stacked capacitor cell is formed through the above manufacturing process.

When the DRAM having the above stacked capacitor cell is formed with a high integration density, the following problems may occur.

That is, since thecontact hole 512 is formed after the transfer transistor is formed and the stacked capacitor cell is formed, and then the bit line is connected to thedrain region 505, it is necessary to form a deep contact hole, thus increasing the step in level of the bit line.

SUMMARY OF THE INVENTION

An object of this invention is to provide a semiconductor device having flat memory cells suitable for high integration.

The above object can be attained by a semiconductor memory device comprising a semiconductor substrate of a first conductivity type having a main surface; source and drain regions of a second conductivity type formed in the main surface area of the semiconductor substrate; word lines extending in a first plane direction and formed on those portions of the semiconductor substrate which respectively lie between the source and drain regions; capacitors each having one of the source and drain regions as a storage node electrode; and bit lines buried in the semiconductor substrate and electrically connected to the source or drain regions, respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.

FIG. 1 is a cross sectional view of a conventional stacked capacitor cell;

FIG. 2 is pattern plan view of a memory cell area of a DRAM according to a first embodiment of the present invention;

FIG. 3 is a view showing the arrangement of transistors of FIG. 2;

FIG. 4 is a cross sectional view taken along theline 4--4 of FIG. 2;

FIG. 5 is a cross sectional view taken along theline 5--5 of FIG. 2;

FIG. 6 is a cross sectional view taken along theline 6--6 of FIG. 2;

FIGS. 7A to FIG. 7F are perspective views showing a method of manufacturing the DRAM memory cell according to a first embodiment of the present invention;

FIGS. 7G to FIG. 7I are perspective views showing a method of manufacturing the DRAM memory cell according to a modification of a first embodiment;

FIG. 8 is a cross sectional view of the same portion as that of FIG. 5 and shows a DRAM memory cell according to a second embodiment of the present invention;

FIG. 9 is a cross sectional view of the same portion as that of FIG. 5 and shows a DRAM memory cell according to a modification of the second embodiment.

FIG. 10 is a pattern plan view of a memory cell area of a DRAM according to a third embodiment of the present invention;

FIG. 11 is a view showing the arrangement of transistors of FIG. 10;

FIG. 12 is a cross sectional view taken along theline 12--12 of FIG. 10;

FIG. 13 is a cross sectional view taken along theline 13--13 of FIG. 10;

FIG. 14 is a cross sectional view taken along theline 14--14 of FIG. 10;

FIG. 15 is a pattern plan view of a memory cell area of a DRAM according to a fourth embodiment of the present invention;

FIG. 16 is a view showing the arrangement of transistors of FIG. 15;

FIG. 17 is a cross sectional view taken along theline 17--17 of FIG. 15;

FIG. 18 is a cross sectional view taken along theline 18--18 of FIG. 15;

FIG. 19 is a cross sectional view taken along theline 19--19 of FIG. 15;

FIG. 20 is a view showing a pattern in which the positions of contacts between the bit lines and the drain regions of the transfer transistors are deviated by 1/2n (n is an integer);

FIG. 21 is a pattern plan view of a memory cell area of a DRAM according to a fifth embodiment of the present invention;

FIG. 22 is a view showing the arrangement of transistors of FIG. 21;

FIG. 23 is a cross sectional view taken along theline 23--23 of FIG. 21; and

FIG. 24 is a cross sectional view taken along theline 24--24 of FIG. 21.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

There will now be described an embodiment of this invention with reference to the accompanying drawings.

FIG. 2 is a pattern plan view of a memory cell area of a DRAM according to a first embodiment of this invention, FIG. 3 is a view showing the arrangement of transistors in the above pattern, FIG. 4 is a cross sectional view taken along theline 4--4 of FIG. 2, FIG. 5 is a cross sectional view taken along theline 5--5 of FIG. 2, FIG. 6 is a cross sectional view taken along theline 6--6 of FIG. 2, and FIGS. 7A to 7F are perspective views showing a method of manufacturing the DRAM.

The DRAM according to the first embodiment and the method for manufacturing the same are explained.

First,field oxide films 102 for element isolation are formed at a regular interval on a P-type semiconductor substrate 101 by local oxidation of silicon, for example (refer to FIG. 7A).

Next,thermal oxide film 150 is formed by thermally oxidizing the surface of thesubstrate 101. Then, asilicon nitride film 151 and asilicon oxide film 152 are sequentially formed on thesubstrate 101 by use of a CVD method, for example. After this, thesilicon oxide film 152, thenitride film 151 andthermal oxide film 150 are sequentially etched by photo engraving technique. Thesubstrate 101 is sequentially etched with the patterned thesilicon oxide film 152, thenitride film 151 andthermal oxide film 150 used as a mask so as to formgrooves 103 in the substrate 101 (refer to FIG. 7B).

Next, thesilicon oxide film 152 used as the mask is removed. Then,thermal oxide films 104 having a film thickness of approximately 500 Å, for example, are formed on the exposed surfaces of thegrooves 103 by thermal oxidation. After this, a photoresist is used as a mask to selectively etch thethermal oxide films 104 on the exposed surfaces of thegrooves 103 so as to formopenings 105 therein. Then, arsenic ions are implanted in an oblique direction into thesemiconductor substrate 101 via theopenings 105 to approximately 1×10¹⁵ cm^-2 (dose) so as to form n-type diffusedlayers 101a (refer to FIGS. 2 and 5). After this, a conductive film, for example, phosphorus doped polysilicon is deposited on the entire surface of thesemiconductor substrate 101 and is etched back by RIE, for example, to fill thegrooves 103 and form bit lines 106. At this time, theopenings 105 are also filled with the bit lines 106.

Next, the exposed top surface of the bit lines 106 is thermally oxidized with thenitride film 151 used as a mask to formthermal oxide films 107. As this time, thebit lines 106 may be connected to the n-type diffusedlayer 101a (refer to FIG. 7C).

After this, thenitride film 151 andthermal oxide film 150 are sequentially and selectively etched out to expose the surface of the substrate 101 (refer to FIG. 7D).

Next,gate oxide films 108 of approximately 100 Å, for example, are formed on respective element regions each of which is surrounded by adjacent two of thefield oxide films 102, 102 and a corresponding one of thegrooves 103 by thermal oxidation. Then, a conductive film, for example, phosphorus doped polysilicon is deposited to a thickness of approximately 2000 Å and is patterned to formgate electrodes 109 of the transfer transistors (FIG. 7E) by photo engraving technique.

After this, for example, arsenic ions are implanted into portions of thesemiconductor substrate 101 on both sides of eachgate electrode 109 to approximately 1×10¹⁶ cm^-2 (dose) so as to form n-type diffusedlayers 116 serving as the source and drain of each transistor (refer to FIGS. 4 to 7F). Next, an insulation film, for example,oxide film 110 is formed on the resultant structure by use of the CVD method and then contactholes 111 are formed by RIE, for example, on the n-type diffusedlayers 116 which lie outside thegate electrode 109 by RIE by photo engraving technique (refer to FIGS. 4 to 6). Next, a conductive film, for example, phosphorus doped polysilicon is deposited on theoxide films 110 and in the contact holes 111 and is then patterned to form storage node electrodes 112 (FIG. 7F).

Next, alaminated film 113 of SiO₂, SiNx and SiO₂ is formed as a capacitor dielectric film on thestorage node electrodes 112 and the like to a thickness equivalent to a thickness of approximately 50 Å of an SiO₂ film and then, for example, phosphorus doped polysilicon is deposited as plate electrodes 114 (refer to FIGS. 4 and 6). After this, an insulation film (not shown) is formed on theplate electrodes 114. Then, contact holes are formed in the above insulation film by photo engraving technique and Al wirings which are connected to thegate electrodes 109, for example, are formed to complete the semiconductor device.

According to the above embodiment, since thebit lines 106 are formed before the transistor and capacitors are formed, contacts between the bit lines and the n-type diffused layers of the transistors can be easily formed. Further, the contacts can be made simply by selectively removing part of thethermal oxide film 104 formed on the internal surface of thegroove 103. Therefore, it is not necessary to form contact holes like the deep contact holes 512 of the conventional memory cell shown in FIG. 1. Since the bit lines are buried in thesemiconductor substrate 101, the memory cell area can be made flat on substantially the entire surface. As a result, the possibility of breakage of wires at the stepped portions in the semiconductor device becomes small, and therefore a semiconductor structure suitable for high integration can be obtained.

Formation of thegrooves 103 and oxide films on thebit lines 106 can be effected according to the following method.

FIGS. 7G to 7I are perspective views of semiconductor structures for illustrating a method for manufacturing the DRAM memory cell according to a modification of the first embodiment.

As shown in FIG. 7G, thefield oxide films 102 are formed. Then, a photoresist is formed and a pattern of thegrooves 103 is formed in the photoresist by a photo etching process. The patterned photoresist is used as a mask to selectively etch out thesemiconductor substrate 101 so as to form thegrooves 103. Then, the photoresist is removed. After this, the exposed silicon surfaces such as the internal surfaces of thegrooves 103 are thermally oxidized to formthermal oxide films 104A and 104B. Then, a photoresist is again formed and a pattern of theopenings 105 is formed in the photoresist by a photo etching process. The patterned photoresist is used as a mask to selectively etch out theoxide films 104B formed on the internal surfaces of thegrooves 103 so as to form the openings 105 (FIG. 7G).

Next, a conductive film, for example, phosphorus doped polysilicon is deposited on the entire surface of the resultant structure and the polysilicon is etched back by RIE to leave the polysilicon only in thegrooves 103. As a result, thebit lines 106 are formed. After this, the exposed top surfaces of thebit lines 106 are thermally oxidized to formthermal oxide films 107 which are thicker than thethermal oxide films 104A (FIG. 7H).

Next, thethermal oxide films 104A and 107 are etched. Since, at this time, theoxide film 104A is thinner than thethermal oxide film 107, thethermal oxide film 104A is completely etched out to expose part of the surface of thesemiconductor substrate 101. On the other hand, thethermal oxide film 107 is not completely etched out and partly left behind on the surface of the bit lines 106.

After this, a method explained with reference to FIGS. 7E to 7F is effected.

FIG. 8 is a cross sectional view of the same portion as that of FIG. 5 and shows a DRAM according to a second embodiment of this invention. In FIG. 8, portions which are the same as those of FIGS. 2 to 6 are denoted by the same reference numerals and only different portions are explained.

In the first embodiment, thebit lines 106 and the n-type diffusedlayers 116 of one of the transistors are connected together via theopenings 105 formed in thegrooves 103, but in this embodiment, they are connected together without forming theopenings 105 in thegrooves 103.

That is, in this embodiment, thebit lines 106 and the n-type diffusedlayer 116 of one of the transistors are connected together via a phosphorus dopedpolysilicon layer 115 formed over theoxide film 104, for example. Further, in the case of this embodiment, since there is a possibility that a capacitor may be formed between the phosphorus dopedpolysilicon layer 115 and theplate electrode 114, it is preferable to form aninsulation film 120 having a sufficiently large film thickness onpolysilicon layer 115. The capacitance between thepolysilicon layer 115 and theplate electrode 114 can be reduced by forming theinsulation film 120, thereby making it possible to prevent a capacitor from being formed between them.

With the above construction, the same effect as that of the first embodiment can be obtained.

FIG. 9 is a cross sectional view of the same portion as that of FIG. 5 and shows a modification of the second embodiment.

That is, in this modification, apolysilicon layer 115A which is formed in the opening by the selective epitaxial growth is used instead of thepolysilicon layer 115.

With this construction, the same effect as that of the first embodiment can be attained.

FIG. 10 is a pattern plan view of a memory cell area of a DRAM according to a third embodiment of this invention, FIG. 11 is a view showing the arrangement of transistors in this pattern, FIG. 12 is a cross sectional view taken along theline 12--12 of FIG. 10, FIG. 13 is a cross sectional view taken along theline 13--13 of FIG. 10, and FIG. 14 is a cross sectional view taken along theline 14--14 of FIG. 10.

In the first and second embodiments, bit lines are formed in the semiconductor substrate, but in this embodiment, capacitors are formed in the semiconductor substrate in addition to the bit lines.

That is,field oxide films 202 for element isolation are formed at a regular interval on the surface of a P-type semiconductor substrate 201 (refer to FIGS. 10, 12 and 14).

Next,grooves 203 are formed in thesemiconductor substrate 201 and thenthermal oxide films 204 having a film thickness of approximately 500 Å, for example, are formed on the internal surfaces of thegrooves 203 by thermal oxidation (refer to FIGS. 10, 13 and 14).

After this,openings 205 are formed by partly etching the respectivethermal oxide films 204 on the internal surfaces of thegrooves 203 with a photoresist used as a mask. Then, ions are implanted via theopenings 205 in an oblique direction to ion-implant arsenic to approximately 1×10¹⁵ cm^-2 (dose), for example, into portions of thesemiconductor substrate 201 exposed to theopenings 205 so as to form n-type diffused layers 201a (refer to FIG. 14).

Next, a conductive film, for example, phosphorus doped polysilicon is deposited on the entire surface of thesemiconductor substrate 201 and is etched back by RIE, for example, to fill thegrooves 203, thus forming bit lines 206 (refer to FIGS. 10, 13 and 14). At this time, theopenings 205 are filled with the bit lines 206.

Next,oxide films 207 are formed on the exposed top surfaces of thebit lines 206 by thermal oxidation. The bit lines 206 are connected to the respective n-type diffused layers 201a (refer to FIGS. 13 and 14).

After this, trenchs 208 of approximately 10 μm, for example, are formed in element regions andfield oxide 202 each of which is surrounded by the adjacentfield oxide films 202 and a corresponding one of thegrooves 203 by RIE with a photoresist used as a mask and then arsenic ions, for example, are implanted therein to approximately 1×10¹⁵ cm^-2 (dose) to form n-type diffused layers (storage rode electrodes) 208a on the internal surfaces of the trenchs 208 (refer to FIGS. 10, 12 and 13).

Next, alaminated film 209 formed of SiO₂, SiNx dielectric film to a film thickness equivalent to a film thickness of approximately 90 Å of an SiO₂ film, then phosphorus doped polysilicon is deposited, for example, and it is patterned to formplate electrodes 210 with a photoresist used as a mask. After this, a thermal oxidation process is effected to form aninsulation film 211 on the plate electrode 210 (refer to FIGS. 10, 12 to 14).

Further,gate oxide films 212 of approximately 100 Å, for example, are formed on element regions each of which is surrounded by thegrooves 203 and theplate electrode 210, and then a conductive film, for example, phosphorus doped polysilicon is deposited to approximately 2000 Å and is patterned to formgate electrodes 213 of transfer transistors. After this, n-type diffusedlayers 214 serving as the source and drain regions of the transistors are formed by implanting arsenic ion, for example, into thesemiconductor substrate 201 to approximately 1×10¹⁵ cm^-2 (dose) (refer to FIGS. 10, 12 to 14).

After this, an interlevel insulator (not shown) is formed on the entire surface of the resultant structure. Then, contact holes are formed in the above interlevel insulator with a photoresist used as mask, and then Al wirings which are connected to word lines (gate electrodes 213), for example, are formed to complete the semiconductor device.

Since the bit lines are formed in the semiconductor substrate in the third embodiment, a contact between the bit line and one of the n-type diffusedlayers 214 of the transistor may be easily formed. Further, since the cell area may be made flat, the high integration density may be easily attained.

FIG. 15 is a pattern plan view of a memory cell area of a DRAM according to a fourth embodiment of this invention, FIG. 16 is a view showing the arrangement of transistors in the pattern, FIG. 17 is a cross sectional view taken along theline 17--17 of FIG. 15, FIG. 18 is a cross sectional view taken along theline 18--18 of FIG. 15, and FIG. 19 is a cross sectional view taken along theline 19--19 of FIG. 15.

In the third embodiment, thebit lines 206 and the n-type diffused layers (storage node electrodes) 208a,laminated films 208 andplate electrodes 210 which constitute capacitors are formed in the semiconductor substrate, but in this embodiment, bit lines are buried in the semiconductor substrate and the semiconductor substrate is used as a plate electrode of the capacitor.

That is,field oxide films 302 are formed on the surface of a P-type semiconductor substrate 301 with a preset distance set therebetween (refer to FIGS. 15, 17 to 19).

Next, trenchs 303 of approximately 10 μm, for example, are formed in desired portions of the element regions andfield oxide films 302 by RIE andoxide films 304 of approximately 100 Å used as capacitor dielectric films are formed on the internal side surfaces of thetrenchs 303 by thermal oxidation (refer to FIGS. 15, 17 and 18).

Then, a portion of theoxide film 304 is selectively etched with a photoresist used as a mask to formopenings 305. After this, the photoresist is removed and ions are implanted via theopenings 305 in an oblique direction to ion-implant arsenic to approximately 1×10¹⁵ cm^-2 (dose), for example, into those portions of thesemiconductor substrate 301 which are exposed to theopenings 305 so as to form n-type diffusedlayers 301a. Then, a conductive film, for example, phosphorus doped polysilicon is deposited in thetrenchs 303 and etched back by RIE, for example, to form storage node electrodes 306 (FIGS. 17 and 18).

Next,thermal oxide films 307 are formed on the exposed top exposed surfaces of thestorage node electrodes 306 by thermal oxidation. At this time, thestorage node electrodes 306 are connected to the respective n-type diffusedlayers 301a via the openings 305 (refer to FIG. 17).

After this,grooves 308 are formed with a preset distance set therebetween in thesemiconductor substrate 301 and thenthermal oxide films 309 of approximately 500 Å are formed on the internal surfaces of thegrooves 308 by thermal oxidation (refer to FIGS. 15, 18 and 19).

Next, portions of thethermal oxide films 309 are etched with a photoresist used as a mask to formopenings 310. Then, ions are implanted via theopenings 310 in an oblique direction to ion-implant arsenic to approximately 1×10¹⁵ cm^-2 (dose), for example, into those portions of thesemiconductor substrate 301 which are exposed to theopenings 310 so as to form n-type diffused layers 301b (refer to FIGS. 15 and 19).

After this, a conductive film, for example, phosphorus doped polysilicon is deposited on the entire surface of thesemiconductor substrate 301 and then etched back to fill thegrooves 308 by RIE, for example, so as to form bit lines 311 (refer to FIGS. 15, 18 and 19).

Further,thermal oxide films 312 are formed on the top exposed surface of thebit lines 311 by thermal oxidation. At this time, thebit lines 311 are connected to the n-type diffused layers 301b via the openings 310 (refer to FIG. 19).

Next,gate oxide films 313 of 100 Å, for example, are formed on element regions surrounded by thefield oxide film 302 andgrooves 308 by thermal oxidation and a conductive film, for example, phosphorus doped polysilicon is deposited to approximately 2000 Å on the resultant structure and is patterned to formgate electrodes 314 of the transfer transistors. After this, for example, arsenic ions are implanted to approximately 1×10¹⁵ cm^-2 (dose) for example, into thesubstrate 301 to form n-type diffusedlayers 315 serving as the source and drain regions of the transistors (FIGS. 17 and 19).

After this, an interlevel insulator (not shown) is formed and contact holes are formed in the interlevel insulator with a photoresist used as a mask, and then Al wirings which are electrically connected to thegate electrodes 314, for example, and the like are formed to complete the semiconductor device.

FIG. 20 is a view showing a pattern in which the positions of contacts between the bit lines and the drain regions of the transfer transistors are deviated by 1/2n (n is an integer) pitch, FIG. 21 is a pattern plan view of a memory cell area of a DRAM according to a fifth embodiment of this invention, FIG. 22 is a view showing the arrangement of transistors in the pattern, FIG. 23 is a cross sectional view taken along theline 23--23 of FIG. 21, and FIG. 24 is a cross sectional view taken along theline 24--24 of FIG. 21.

This embodiment is different from the first embodiment in the arrangement of the memory cells of the DRAM and the construction of the cell is the same as that shown in FIGS. 2 to 6. In FIGS. 20 to 24, portions which are the same as those of FIGS. 2 to 6 are denoted by the same reference numerals.

That is, in this embodiment, a pattern in which the positions of contacts between the bit lines and the drain regions of the transfer transistors are deviated by 1/2n (n is an integer) pitch is used. The pattern is schematically shown in FIG. 20.

In the pattern shown in FIG. 20, the positions of contacts are deviated by 1/4 pitch and the pattern is called a folded bit line pattern because of the arrangement of the bit lines. That is, bitline sense amplifiers 407 and 408 are connected to the opposite ends of a plurality ofbit lines 106 which are arranged in parallel. More specifically, two bit lines lying on both sides of an odd-numbered or even-numbered bit line and making a complementary pair are connected at one or the other end thereof to one of thesense amplifiers 407 and 408.

Each of the bit lines 106 hascontacts 105 for the drains (or sources) of the transfer transistors arranged at a constant pitch in the lengthwise direction thereof. In this case, the contact position of one of the bit lines are deviated from the contact position of the adjacent bit line by 1/4 pitch in the lengthwise direction of the bit line.

FIGS. 20 to 24 show the arrangement of the memory cells explained in the first embodiment in the above pattern.

That is, as shown in FIGS. 20 to 24, the bit lines and word lines are arranged in directions to intersect each other and an element region for two transfer transistors are formed to cross two bit lines and two adjacent word lines. Further, each of the bit lines are connected to capacitors corresponding to two transfer transistors at portions which intersect the element regions at a constant pitch P in the lengthwise direction thereof so as to form two cells of one-transistor/one-capacitor structure in each element region.

In a plurality of bit lines arranged in parallel, the position of contact of each of the bit lines are deviated from the position of contact of the adjacent bit line by substantially 1/4 pitch in the lengthwise direction of the bit line.

As described above, according to this invention, there can be provided a semiconductor memory device and a method for manufacturing the same in which since the cell structure can be made flat by burying the bit lines in the internal portion of the semiconductor substrate, bit line contacts may be easily obtained in comparison with the prior art case.

Further, this invention is not limited to the above embodiments and can be variously modified without departing from the technical scope thereof.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details, representative devices, and illustrated examples shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

Claims (15)

What is claimed is:

1. A semiconductor memory device, comprising:

a semiconductor body of a first conductivity type having first and second spaced-apart parallel grooves which extend in a first direction formed therein, said first and second grooves defining a middle region therebetween;

first and second field insulating films formed on the surface of said middle region, each of said first and second field insulating films extending so as to contact both said first and second grooves;

first and second spaced-apart parallel word lines extending in a second direction perpendicular to the first direction;

a first semiconductor region of a second conductivity type formed in a first portion of said middle region, said first portion of said middle region being disposed between one of said first and second words lines and one of said first and second field insulating films, and said first semiconductor region serving as a source of a first memory cell and being connected to a first memory capacitor;

a second semiconductor region of the second conductivity type formed in a second portion of said middle region, said second portion of said middle region being disposed between the other of said first and second word lines and the other of said first and second field insulating films, and said second semiconductor region serving as a source of a second memory cell and being connected to a second memory capacitor;

a third semiconductor region of the second conductivity type formed in a third portion of said middle region, said third portion of said middle region being disposed between said first and second word lines and serving as a drain which is common to said first and second memory cells;

a first insulating film formed on an exposed surface of said first groove and having an opening therein which extends to said third semiconductor region;

a second insulating film formed on an exposed surface of said second groove;

a first bit line formed in said first groove, said first bit line being connected to said third semiconductor region via an electrical path which extends through said opening in a direction substantially perpendicular to a direction of current paths between said sources of the first and second memory cells and said common drain; and

a second bit line formed in said second groove.

2. A semiconductor memory device according to claim 1, wherein said first and second grooves provide element isolation in the second direction.

3. A semiconductor memory device according to claim 2, wherein said first memory capacitor comprises a storage node electrode connected to said first semiconductor region and said second memory capacitor comprises a storage node electrode connected to said second semiconductor region.

4. A semiconductor memory device according to claim 3, wherein each of said first and second memory capacitors is a stacked-type memory capacitor, and wherein said first and second memory capacitors further comprise:

a plate electrode formed on an entire surface of said semiconductor body.

5. A semiconductor memory device according to claim 3, wherein said storage node electrodes of said first and second memory capacitors overlap said first and second grooves.

6. A semiconductor memory device according to claim 5, wherein each of said first and second memory capacitors is a stacked-type memory capacitor, and wherein said first and second memory capacitors further comprise:

a plate electrode formed on an entire surface of said semiconductor body.

7. A semiconductor memory device according to claim 4, wherein said first and second bit lines are composed of phosphorus-doped polysilicon.

8. A semiconductor memory device, comprising:

a semiconductor body having a major surface;

first and second grooves in said major surface of said semiconductor body;

first and second field insulating film portions on said major surface of said semiconductor body between said first and second grooves, said first and second field insulating film portions extending to said first and second grooves to define an active region surrounded by said first and second grooves and said first and second field insulating film portions;

source and drain regions in said active region, wherein a junction between said source region and said semiconductor body extends to both said first and second grooves and a junction between said drain region and said semiconductor body extends to both said first and second grooves;

a gate electrode insulatively arranged on a channel region between said source and drain regions;

a first insulating film on portions of said semiconductor body exposed by said first and second grooves;

a first conductive film on said first insulating film and filling in said grooves to define first and second bit lines; and

connecting means for electrically connecting one of said first and second bit lines to a first one of said source and drain regions.

9. A semiconductor memory device according to claim 8, wherein said connecting means comprises:

an opening in said first insulating film adjacent to said first one of said source and drain regions; and

a diffusion region contacting said one of said first and second bit lines and said first one of said source and drain regions and extending through said opening.

10. A semiconductor memory device according to claim 8, wherein said connecting means comprises:

a second conductive film contacting an upper surface of said first one of said source and drain regions and an upper surface of said one of said first and second bit lines.

11. A semiconductor memory device according to claim 10, wherein said second conductive film is a phosphorous-doped polysilicon layer.

12. A semiconductor memory device according to claim 8, further comprising:

a capacitor having a storage node contact electrode connected to a second one of said source and drain regions.

13. A semiconductor memory device according to claim 12, further comprising:

a trench in said active region,

wherein said storage node contact electrode of said capacitor comprises a second conductive film on a portion of said semiconductor body exposed by said trench.

14. A semiconductor memory device according to claim 13, wherein said capacitor further comprises:

a dielectric layer on said storage node contact electrode; and

a third conductive film on said dielectric layer and filling in said trench to define a plate electrode.

15. A semiconductor memory device according to claim 12, further comprising a trench in said active region and wherein said capacitor comprises:

a second insulating film on portions of said semiconductor body exposed by said trench;

a third conductive film on said second insulating film and filling in said trench to define said storage node contact electrode; and

wherein said semiconductor body comprises a plate electrode.

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