US5296738A - Moisture relief for chip carrier - Google Patents
Moisture relief for chip carrierDownload PDFInfo
- Publication number
- US5296738A US5296738AUS07/927,774US92777492AUS5296738AUS 5296738 AUS5296738 AUS 5296738AUS 92777492 AUS92777492 AUS 92777492AUS 5296738 AUS5296738 AUS 5296738A
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- Prior art keywords
- semiconductor die
- substrate
- printed circuit
- chip carrier
- package
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Definitions
- This inventionrelates to printed circuit board chip carriers, and more particularly to overmolded and glob top chip carriers that allow for moisture relief.
- Over Molded Carrierssuch as the Over Molded Pad Array Carrier (OMPAC), the Over Molded Peripheral Chip Carrier (OMPCC), and the Over Molded Pin Grid Array (OMPGA) and their equivalent glob top printed circuit board chip carriers are susceptible to moisture during manufacturing.
- OMPACOver Molded Pad Array Carrier
- OMPCCOver Molded Peripheral Chip Carrier
- OMPGAOver Molded Pin Grid Array
- the die attach adhesiveis usually a hygroscopic material. Exposure of the package to solder reflow temperatures after the die attach adhesive absorbs moisture, causes the rapid expansion of the moisture into water vapor. This causes the die to delaminate from the substrate. Thus the "popcorn" effect.
- U.S. Pat. No. 4,866,506 by Nambu Et. Al.discusses a flat plastic-sealed IC device and lead frame in a package that has an opening in the back surface of the package, allowing exposure to the atmosphere and the release of moisture when subjected to heat.
- This packagealso known as the Quad Flat Pack (QFP)
- QFPQuad Flat Pack
- the QFPdoes not use a substrate or printed circuit board as in OMPAC, OMPCC, and OMPGA and their glob top equivalents; thus, a different solution is required.
- the present inventionprovides a means for releasing moisture in a completely different structure.
- An integrated circuit packagecomprises a semiconductor die having a top surface and a bottom surface, and a substrate for receiving the semiconductor die.
- the substrateshould have an aperture(s) below the semiconductor die.
- An adhesive applied to the substrateallows for mounting the semiconductor die to the substrate. Then, an over molded encapsulant or a glob top for sealing the top surface of the semiconductor die is formed over the semiconductor die and portions of the substrate.
- FIG. 1is an exploded peripheral view of an overmolded chip carrier in accordance with the present invention.
- FIG. 2is an exploded peripheral view of a overmolded pad array carrier in accordance with the present invention.
- FIG. 3is a cut view of overmolded pin grid array in accordance with the present invention.
- FIG. 4is a cut view of a glob top pin grid array in accordance with the present invention.
- FIG. 5is a top plan view of a glob top peripheral chip carrier in accordance with the present invention.
- FIG. 6is an exploded peripheral view of a glob top pad array carrier in accordance with the present invention.
- the chip carrieris an overmolded pad array carrier, an overmolded pin grid array, an overmolded peripheral chip carrier, or alternatively, a glob top pad array carrier, a glob top pin grid array, or a glob top peripheral chip carrier.
- the present inventionis applicable to any printed circuit board chip carrier having integrated circuits and an encapsulant such as an over mold or glob top.
- a substrate 16 for receiving a semiconductor die 14has printed circuitry 22 on the substrate 16.
- a hole(s) or aperture(s) 18is arranged and constructed so as to reside below the semiconductor die 14.
- the hole 18is preferably small enough (less than a 30 mil diameter) not to alter the design of the solder connections on the bottom of the package.
- a die attach adhesive 20such as a bisphenol-epichlorhydrin based epoxy which is preferably filled with silver is applied in the die attach region.
- the adhesiveis preferably dispensed onto the substrate, although other means of applying the adhesive is within contemplation of the present invention.
- the adhesiveis cured by using heat.
- the hole 18is usually partially filled with the adhesive after curing. The partially filled hole prevents mechanical damage to the die back plane, but allows water vapor to be expunged during temperature excursions such as during reflow soldering.
- an overmolded compound 12is applied over the die and portions of the substrate 16 forming the overmolded peripheral chip carrier 10 shown in FIG. 1.
- This overmolded pad array carrier 30further includes solder pads 38 on the bottom portion of a substrate 36 for receiving a semiconductor die 34 that has printed circuitry (not shown).
- a hole(s) or aperture(s) 42is arranged and constructed so as to reside below the semiconductor die 34.
- the hole 42is preferably small enough (less than a 30 mil diameter) not to alter the design of a solder bumped pad array on the bottom of a package as shown.
- a die attach adhesive 40is applied either to the bottom of the die 34 or the top surface of the substrate 36.
- the adhesive 40is preferably dispensed or screened onto the substrate 36, although other means of applying the adhesive is within contemplation of the present invention.
- an overmolded compound 32is formed over the die and portions of the substrate 36.
- FIG. 3there is shown a cut view of an overmolded pin grid array (OMPGA) 50.
- the OMPGAis formed essentially as described above in FIG. 2, with the addition of pins 51 protruding from the bottom of the package.
- the OMPGA 50comprises a substrate 56 having at least one aperture 55 residing below a semiconductor die 54.
- the back plane of the die 54is attached to the substrate 56 via an adhesive 58.
- Some of the conductive runners 57 on the substrate 56are coupled to the die 54 via a wirebond 53.
- an overmold 52is formed above the substrate and die.
- FIG. 4there is shown a cut view of an glob top pin grid array 60.
- the device 60is formed essentially as described above in FIG. 2, with the addition of pins 61 protruding from the bottom of the package and a glob top instead of an overmold.
- the device 60comprises a substrate 66 having at least one aperture 65 residing below a semiconductor die 64.
- the back plane of the die 64is attached to the substrate 66 via an adhesive 58.
- Some of the conductive runners 67 on the substrate 66are coupled to the die 64 via a wirebond 63. Once the die is wirebonded, then an glob top 62 is formed above the substrate and die.
- FIG. 5there is shown a top plan view of an glob top peripheral chip carrier 70.
- the device 70is formed essentially as described above in FIG. 1, with a glob top instead of an overmold.
- the device 70comprises a substrate 76 having at least one aperture 75 residing below a semiconductor die 74.
- the back plane of the die 74is attached to the substrate 76 via an adhesive (not shown).
- Some of the conductive runners 77 on the substrate 76are coupled to the die 74 via a wirebond 73.
- a glob top 72is formed above the substrate and die.
- FIG. 6there is shown an exploded peripheral view of an glob top pad array carrier 80.
- the device 80is formed essentially as described above in FIG. 2, with a glob top instead of an overmold.
- the device 80comprises a substrate 86 having at least one aperture 85 residing below a semiconductor die 84.
- the substrate 86further comprises several solder pads 81 on the bottom surface of the substrate 86.
- the back plane of the die 84is attached to the substrate 86 via an adhesive 88. Once the die is wirebonded, then a glob top 82 is formed above the substrate and die.
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Investigating Or Analysing Biological Materials (AREA)
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Abstract
Description
This is a continuation of application Ser. No. 07/726,660, filed Jul. 8, 1991, and now abandoned.
This invention relates to printed circuit board chip carriers, and more particularly to overmolded and glob top chip carriers that allow for moisture relief.
Over Molded Carriers such as the Over Molded Pad Array Carrier (OMPAC), the Over Molded Peripheral Chip Carrier (OMPCC), and the Over Molded Pin Grid Array (OMPGA) and their equivalent glob top printed circuit board chip carriers are susceptible to moisture during manufacturing. These integrated circuit packages suffer from "Popcorning" when subjected to heat. This problem is particularly noticeable in surface mount packages using printed circuit boards, which experience higher thermal and mechanical stresses due to the exposure of the entire package to solder reflow temperatures. Typically, these integrated circuit packages are baked prior to solder assembly to remove moisture. Moisture usually penetrates the over mold top or glob top, the substrate, the die or integrated circuit residing between the over mold top or glob top and the substrate, and especially the adhesive used to attach the die to the substrate. The die attach adhesive is usually a hygroscopic material. Exposure of the package to solder reflow temperatures after the die attach adhesive absorbs moisture, causes the rapid expansion of the moisture into water vapor. This causes the die to delaminate from the substrate. Thus the "popcorn" effect.
U.S. Pat. No. 4,866,506 by Nambu Et. Al. discusses a flat plastic-sealed IC device and lead frame in a package that has an opening in the back surface of the package, allowing exposure to the atmosphere and the release of moisture when subjected to heat. This package, also known as the Quad Flat Pack (QFP), is easily manufactured, but leaves the bottom surface of the lead frame exposed to the atmosphere. The QFP does not use a substrate or printed circuit board as in OMPAC, OMPCC, and OMPGA and their glob top equivalents; thus, a different solution is required. The present invention provides a means for releasing moisture in a completely different structure.
An integrated circuit package comprises a semiconductor die having a top surface and a bottom surface, and a substrate for receiving the semiconductor die. The substrate should have an aperture(s) below the semiconductor die. An adhesive applied to the substrate allows for mounting the semiconductor die to the substrate. Then, an over molded encapsulant or a glob top for sealing the top surface of the semiconductor die is formed over the semiconductor die and portions of the substrate.
FIG. 1 is an exploded peripheral view of an overmolded chip carrier in accordance with the present invention.
FIG. 2 is an exploded peripheral view of a overmolded pad array carrier in accordance with the present invention.
FIG. 3 is a cut view of overmolded pin grid array in accordance with the present invention.
FIG. 4 is a cut view of a glob top pin grid array in accordance with the present invention.
FIG. 5 is a top plan view of a glob top peripheral chip carrier in accordance with the present invention.
FIG. 6 is an exploded peripheral view of a glob top pad array carrier in accordance with the present invention.
Referring to FIG. 1, there is shown achip carrier 10 in accordance with the present invention. Preferably, the chip carrier is an overmolded pad array carrier, an overmolded pin grid array, an overmolded peripheral chip carrier, or alternatively, a glob top pad array carrier, a glob top pin grid array, or a glob top peripheral chip carrier. Essentially, the present invention is applicable to any printed circuit board chip carrier having integrated circuits and an encapsulant such as an over mold or glob top. Typically, asubstrate 16 for receiving asemiconductor die 14 has printedcircuitry 22 on thesubstrate 16. A hole(s) or aperture(s) 18 is arranged and constructed so as to reside below thesemiconductor die 14. Thehole 18 is preferably small enough (less than a 30 mil diameter) not to alter the design of the solder connections on the bottom of the package. Then adie attach adhesive 20 such as a bisphenol-epichlorhydrin based epoxy which is preferably filled with silver is applied in the die attach region. The adhesive is preferably dispensed onto the substrate, although other means of applying the adhesive is within contemplation of the present invention. Once thedie 14 is attached to the substrate 16 (via the adhesive 20), the adhesive is cured by using heat. Thehole 18 is usually partially filled with the adhesive after curing. The partially filled hole prevents mechanical damage to the die back plane, but allows water vapor to be expunged during temperature excursions such as during reflow soldering. After wire bonding, an overmoldedcompound 12 is applied over the die and portions of thesubstrate 16 forming the overmoldedperipheral chip carrier 10 shown in FIG. 1.
Referring to FIG. 2, there is shown another overmoldedchip carrier 30 in accordance with the present invention. This overmoldedpad array carrier 30 further includessolder pads 38 on the bottom portion of asubstrate 36 for receiving asemiconductor die 34 that has printed circuitry (not shown). A hole(s) or aperture(s) 42 is arranged and constructed so as to reside below thesemiconductor die 34. Thehole 42 is preferably small enough (less than a 30 mil diameter) not to alter the design of a solder bumped pad array on the bottom of a package as shown. Then a die attach adhesive 40 is applied either to the bottom of the die 34 or the top surface of thesubstrate 36. The adhesive 40 is preferably dispensed or screened onto thesubstrate 36, although other means of applying the adhesive is within contemplation of the present invention. Then an overmoldedcompound 32 is formed over the die and portions of thesubstrate 36.
Referring to FIG. 3, there is shown a cut view of an overmolded pin grid array (OMPGA) 50. The OMPGA is formed essentially as described above in FIG. 2, with the addition ofpins 51 protruding from the bottom of the package. The OMPGA 50 comprises asubstrate 56 having at least oneaperture 55 residing below asemiconductor die 54. The back plane of the die 54 is attached to thesubstrate 56 via anadhesive 58. Some of theconductive runners 57 on thesubstrate 56 are coupled to the die 54 via awirebond 53. Once the die is wirebonded, then an overmold 52 is formed above the substrate and die.
Referring to FIG. 4, there is shown a cut view of an glob toppin grid array 60. Thedevice 60 is formed essentially as described above in FIG. 2, with the addition ofpins 61 protruding from the bottom of the package and a glob top instead of an overmold. Thedevice 60 comprises asubstrate 66 having at least oneaperture 65 residing below asemiconductor die 64. The back plane of the die 64 is attached to thesubstrate 66 via anadhesive 58. Some of theconductive runners 67 on thesubstrate 66 are coupled to the die 64 via awirebond 63. Once the die is wirebonded, then anglob top 62 is formed above the substrate and die.
Referring to FIG. 5, there is shown a top plan view of an glob topperipheral chip carrier 70. Thedevice 70 is formed essentially as described above in FIG. 1, with a glob top instead of an overmold. Thedevice 70 comprises a substrate 76 having at least oneaperture 75 residing below asemiconductor die 74. The back plane of the die 74 is attached to the substrate 76 via an adhesive (not shown). Some of theconductive runners 77 on the substrate 76 are coupled to the die 74 via awirebond 73. Once the die is wirebonded, then aglob top 72 is formed above the substrate and die.
Referring to FIG. 6, there is shown an exploded peripheral view of an glob toppad array carrier 80. Thedevice 80 is formed essentially as described above in FIG. 2, with a glob top instead of an overmold. Thedevice 80 comprises asubstrate 86 having at least oneaperture 85 residing below asemiconductor die 84. Thesubstrate 86 further comprisesseveral solder pads 81 on the bottom surface of thesubstrate 86. The back plane of the die 84 is attached to thesubstrate 86 via an adhesive 88. Once the die is wirebonded, then aglob top 82 is formed above the substrate and die.
Claims (12)
1. An overmolded pad array chip carrier package, comprising:
a semiconductor die;
a printed circuit board substrate for receiving said semiconductor die, said printed circuit board substrate having first and second opposed major surfaces and said substrate having at least one hole below said die;
an adhesive applied to said printed circuit board substrate for mounting said semiconductor die to said printed circuit board substrate, at least a portion of said adhesive filling at least a portion of said hole;
at least one wirebond from said printed circuit board substrate to said semiconductor die;
an overmolded epoxy cover encapsulating said semiconductor die, said at least one wirebond, and portions of said printed circuit board substrate first surface so as to expose said portion of said adhesive to an environment.
2. The chip carrier package of claim 1, wherein said at least one hole is less than 30 mils in diameter.
3. An integrated circuit package, comprising:
a semiconductor die having a top surface and a bottom surface;
a printed circuit substrate for receiving said semiconductor die, said printed circuit substrate having a die mounting area with a hole extending through the printed circuit substrate;
an adhesive applied to the printed circuit substrate for mounting said semiconductor die to said printed circuit substrate, a portion of said adhesive at least partially filling said hole;
at least one wirebond from said printed circuit substrate to said semiconductor die,
a glob top encapsulant for sealing the top surface of said semiconductor die, said wirebonds and only an upper surface of said printed circuit substrate.
4. The integrated circuit package of claim 3, wherein said integrated circuit package comprises a glob top pad array carrier.
5. The integrated circuit package of claim 3, wherein said integrated circuit package comprises a glob top pin grid array.
6. The integrated circuit package of claim 3, wherein said integrated circuit package comprises a glob top peripheral chip carrier.
7. The integrated circuit package of claim 3, wherein said adhesive comprises a bisphenol-epichlorhydrin based epoxy.
8. The integrated circuit package of claim 3, wherein said hole(s) is less than 30 mils in diameter.
9. A chip carrier package, comprising:
a semiconductor die having a perimeter;
a printed circuit board for receiving said semiconductor die, said printed circuit board having first and second opposed major surfaces and having at least one hole within an area bounded by said semiconductor die perimeter;
an adhesive applied to said first major surface for mounting said semiconductor die to said printed circuit board, said adhesive filling at least a portion of said hole;
at least one wirebond from said printed circuit board to said semiconductor die;
an over molded cover encapsulating said semiconductor die, said at least one wirebond, portions of said printed circuit board first surface, and arranged so as to leave a portion of said hole in said second major surface exposed.
10. The chip carrier package of claim 1, wherein said chip carrier package comprises an over molded pad array carrier.
11. The chip carrier package of claim 1, wherein said chip carrier package comprises an over molded pin grid array.
12. The chip carrier package of claim 1, wherein said chip carrier package comprises an over molded peripheral chip carrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/927,774US5296738A (en) | 1991-07-08 | 1992-08-10 | Moisture relief for chip carrier |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US72666091A | 1991-07-08 | 1991-07-08 | |
| US07/927,774US5296738A (en) | 1991-07-08 | 1992-08-10 | Moisture relief for chip carrier |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US72666091AContinuation | 1991-07-08 | 1991-07-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US5296738Atrue US5296738A (en) | 1994-03-22 |
Family
ID=24919498
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US07/927,774Expired - LifetimeUS5296738A (en) | 1991-07-08 | 1992-08-10 | Moisture relief for chip carrier |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5296738A (en) |
| EP (1) | EP0603198A4 (en) |
| JP (1) | JPH07500947A (en) |
| KR (1) | KR0134902B1 (en) |
| WO (1) | WO1993001619A1 (en) |
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| US8522426B2 (en)* | 2010-06-05 | 2013-09-03 | Raytheon Company | Vent blocking on vented ball grid arrays to provide a cleaner solution barrier |
| US9914638B2 (en) | 2015-01-14 | 2018-03-13 | Sensirion Ag | Sensor package |
| US9818703B2 (en)* | 2015-11-17 | 2017-11-14 | Samsung Electronics Co., Ltd. | Printed circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0603198A1 (en) | 1994-06-29 |
| KR0134902B1 (en) | 1998-04-20 |
| EP0603198A4 (en) | 1994-08-17 |
| JPH07500947A (en) | 1995-01-26 |
| WO1993001619A1 (en) | 1993-01-21 |
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