US5166096A - Process for fabricating self-aligned contact studs for semiconductor structures - Google Patents

Abstract

A contact stud for semiconductor structure is fabricated by providing a semiconductor substrate having an alignment structure, which includes a sidewall, and the semiconductor structure formed thereon, forming a sidewall spacer contiguous with the semiconductor structure and the sidewall of the alignment structure, depositing an insulating layer contiguous with the sidewall spacer so as to insulate the semiconductor structure, etching the sidewall spacer selectively to the sidewall of the alignment structure, the semiconductor structure and the insulating layer forming a contact window opening for allowing access to the semiconductor structure, and backfilling the contact window opening with a conductive material so as to contact the semiconductor structure for forming the stud.

Description

RELATED U.S. APPLICATION DATA

This application is a divisional application of U.S. Ser. No. 07/784,193 filed Oct. 29, 1991, pending.

TECHNICAL FIELD

The present invention relates generally to semiconductor devices and, more particularly, to the structure and fabrication of a stud for a semiconductor device or structure thereof, used for connecting the device or structure to another electronic device or component.

BACKGROUND OF THE INVENTION

Semiconductor fabrication technology continues in a trend towards increasing circuit density and further microminiaturization of semiconductor structures. A semiconductor structure in this context is defined as any region, device, component, or element thereof that can be grown, formed, diffused, implanted, deposited, etc. into or onto a semiconductor substrate. For example, the gate conductor in today's high speed semiconductor transistor devices has diminished to a width of 0.4×10^-6 meters, and it is foreseen that this width will be further decreased to 0.1×10^-6 meters.

A stud is an electrically conductive element which contacts a structure or element of a semiconductor device and allows the device to be connected with another semiconductor structure or electronic device. As the dimensions of a semiconductor structure decreases, the available area for forming a stud to adequately contact the structure also decreases. Thus, a high degree of accuracy is required to properly form and align a stud so as to contact a microminiaturized semiconductor structure. In other words, increased microminiaturization of semiconductor structures leads to the problem of decreased alignment error tolerance when fabricating contact studs for such structures.

Moreover, minimizing contact resistance between a contact stud and a semiconductor structure is important for increasing speed and optimizing circuit performance. In this regard, a contact stud is generally fabricated so as to contact the top surface of a semiconductor structure. Thus, the available area for the stud to contact the structure is dictated by and limited to the width of the top surface of the structure.

Although further increasing of circuit layout density does not generally require considerable decrease in the height of the structure, it does require significant diminishment in the overall width of the structure. In other words, the aspect ratio (width to height ratio) of the structure is decreased in order to increase circuit layout density. Accordingly, the available area of width on the top portion of the structure for the stud to contact the structure is also decreased. Unfortunately, the area of contact between the stud and the structure controls the amount of contact resistance therebetween, such that a decrease in the area of contact leads to an undesirable increase in contact resistance.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to further increase circuit density and allow for further microminiaturization of semiconductor devices.

It is another object of the present invention to provide a manufacturing process which can accurately and properly form and align a contact stud for a semiconductor structure.

It is yet a further object of the invention to minimize contact resistance by increasing the contact region between a contact stud and a semiconductor structure.

It is another further object of the invention to increase the contact region between a contact stud and a semiconductor structure by contacting the stud along a sidewall of the structure.

It is still another object of the invention to provide a manufacturing process which self-aligns a contact stud along a sidewall of a structure on a semiconductor substrate.

In order to accomplish the above and other objects of the invention, a process for fabricating a stud for a semiconductor structure includes the steps of providing a semiconductor substrate having an alignment structure, which includes a sidewall, and the semiconductor structure formed thereon, forming a sidewall spacer contiguous with the semiconductor structure and the sidewall of the alignment structure, with the sidewall spacer being of substantially the same height as the alignment structure, depositing an insulating layer contiguous with the sidewall spacer so as to insulate the semiconductor structure, with the insulating layer being of substantially the same height as the sidewall spacer, etching the sidewall spacer selectively to the sidewall of the alignment structure, the semiconductor structure and the insulating layer for forming a contact window opening for allowing access to the semiconductor structure, and backfilling the contact window opening with a conductive material so as to contact the semiconductor structure for forming the stud.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, features, aspects and advantages will be more readily apparent and better understood from the following detailed description of the invention, in which:

FIGS. 1A-1G are diagrammatic cross-sectional views showing a portion of a substrate during various stages of processing during formation of a stud for a ate conductor in accordance with the present invention; and

FIGS. 2A-2H are diagrammatic cross-sectional views showing a portion of a substrate during various stages of processing during formation of a stud for a diffusion region in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Although the following description refers to the structure and formation of studs for a gate conductor and a diffusion region, the invention contemplates forming studs to contact any structure or region as may be required for a semiconductor device. Furthermore, although the description refers to the use of an oxide cap, a gate conductor and a spacer as alignment structures used for aligning the studs thereto, it should be fully understood that the studs can be aligned to any structure existing on a wafer.

FIGS. 1A-1G illustrate the formation of a stud for a gate conductor, using the gate conductor and an oxide cap as alignment structures to which the stud is aligned. Advantageously, the contact region of the stud to the gate conductor is substantially along a sidewall of the gate conductor.

Referring initially to FIG. 1A, there is shown a portion of asilicon wafer 10 having asubstrate 12 withdiffusion regions 14,15, agate oxide 16, a gate electrode orconductor 18 havingsidewalls 24,26 and being comprised of appropriate metal (such as polysilicon, titanium silicide, or the like), anoxide cap 20 havingsidewalls 21,22, and adielectric layer 23.

Thediffusion regions 14,15,gate oxide 16,gate conductor 18 andoxide cap 20 are formed and patterned using conventional processes, such as deposition, diffusion, implantation, photolithography, and etching.

Thedielectric layer 23 is deposited, such as by chemical vapor deposition, so as to coat thediffusion regions 14,15, thesidewalls 24,26 of thegate conductor 18, and theoxide cap 20. Thedielectric layer 23 is then etched selectively to thediffusion regions 14,15 and the top of theoxide cap 20 such that only the dielectric which is contiguous with thesidewalls 21,22 of theoxide cap 20 and contiguous with thesidewalls 24,26 of thegate conductor 18 remain unetched. This remaining dielectric forms thesidewall spacers 28,30, as shown in FIG. 1B.

Note that the dimensions of thedielectric layer 23 determines the dimensions of thesidewall spacers 28,30, and the dimensions of thesidewall spacers 28,30 determine the dimensions of the stud being formed to contact thegate conductor 18. Therefore, the required dimensions of the stud must be taken into account at the time of deposition of thedielectric layer 23.

In this example, for reasons set forth hereinbelow, thedielectric layer 23 which forms thesidewall spacers 28,30 not only can be etched selectively to thediffusion regions 14,15 and theoxide cap 24, but thedielectric layer 23 and resultingsidewall spacers 28,30 can also be etched selectively to thegate conductor 18. Moreover, oxide can be polished selectively to thedielectric layer 23. Boron nitride (BN), silicon nitride, silicon boron nitride, and carbon boron nitride are examples of dielectrics having such selectivity.

Preferably, thedielectric layer 23 is deposited to a substantially uniform thickness, and the etching technique used to etch thedielectric layer 23 is directional or anisotropic. Illustratively, if a substantially uniform layer of BN is used as thedielectric layer 23 to form thesidewall spacers 28,30, a reactive ion etching (RIE) technique provides adequate anisotropy and etch selectivity to thediffusion regions 14,15 and to theoxide cap 20, using approximately the following parameters:

10% CF₄ in O₂ or 12% CHF₃ in O₂

80 mTORR of pressure

400 watts of power

20 Gauss of magnetic field

Optionally,silicided junctions 32,33 are applied to thediffusion regions 14,15 to improve conductivity to these regions. Thesilicided junctions 32,33 are formed and patterned using known fabrication techniques. Although thesilicided junctions 32,33 are shown as being applied to thediffusion regions 14,15 subsequent to deposition of thedielectric layer 23, it should be understood that thesilicided junctions 32,33 can also be applied to thediffusion regions 14,15 prior to deposition of thedielectric layer 23.

Next, as shown in FIG. 1C, aninsulating layer 34, such as an oxide layer, is deposited, such as by chemical vapor deposition, so as to be contiguous with thesidewall spacers 28,30 and so as to cover and insulate thediffusion regions 14,15. Theoxide layer 34 is then planarized or polished so that the top of theoxide layer 34 is substantially coplanar with the top of thesidewall spacers 28,30, i.e., theoxide layer 34 is polished until it is of substantially the same height as thesidewall spacers 28,30. It is to be understood that polishing is a method of planarizing materials during fabrication.

Since oxide polishes selectively to the dielectric used to form thesidewall spacers 28,30, i.e., thesidewall spacers 28,30 polish at a slower rate than oxide, thesidewall spacers 28,30 function as a "stop" during the polishing step. It should be realized that the use of oxide as the insulatinglayer 26 is for illustration purposes only and, as such, other dielectrics which polish at a faster rate than the dielectric used for thesidewall spacers 28,30 can be used in lieu of oxide. For example, a doped oxide such as phosphosilicate glass or borophosphosilicate glass can also be used.

Optionally, since the top of theoxide cap 20 is substantially coplanar with the top of thesidewall spacers 28,30, the top of theoxide cap 20 can be used as the polish stop in lieu of thesidewall spacers 28,30. In such an embodiment, a thin layer of material which is polish selective to oxide, such as silicon nitride, is deposited on top of theoxide cap 20. Such a layer can be deposited before formation of thegate conductor 18 andoxide cap 20, and must then be removed after the polishing step. However, it is preferable that thesidewall spacers 28,30 be used as the polish stop since an additional layer of material need not be added to serve as the polish stop and removed after the polishing step. In other words, use of thesidewall spacers 28,30 as the polish stop when polishing theoxide layer 34 is desirable over use of theoxide cap 20 because a reduction in the number of required steps is realized.

Next, a layer of photoresist is applied over thepolished oxide layer 34. The photoresist layer is patterned using standard photolithographic techniques of exposure and development so as to form aphotoresist blockout mask 36, as shown in FIG. 1D. Thephotoresist blockout mask 36 covers or blocks outsidewall spacer 30, but leavessidewall spacer 28 exposed. As further described hereinafter,sidewall spacer 28 is exposed for etching for forming a gate conductor contact window. Although FIG. 1D showssidewall spacer 28 exposed, the choice as to exposingsidewall spacer 28 orsidewall spacer 30 depends on the requirements of the semiconductor device being fabricated, as eithersidewall spacer 28,30 can be etched to form a gate conductor contact window. However, it is important that thephotoresist blockout mask 36 be patterned to cover the sidewall spacer which will not be used to form the gate conductor contact window, so that it will remain unetched.

Moreover, note that thephotoresist blockout mask 36 does not cover theoxide cap 20 or theoxide layer 34 adjacent to thesidewall spacer 28 which is used to form the gate conductor contact window. Since thesidewall spacer 28 etches selectively to oxide, neither theoxide cap 20 nor theoxide layer 34 adjacent to thesidewall spacer 28 need to be covered by thephotoresist blockout mask 36. Thus, thesidewall spacer 28 will be removed during etching and theoxide cap 20 and theoxide layer 34 will remain unetched. Accordingly, a high degree of accuracy is not required when forming thephotoresist blockout mask 36 for etching thesidewall spacer 28.

Thesidewall spacer 28 is then etched selectively to theoxide cap 20, theoxide layer 34 and thegate conductor 18. Again using BN as an example of the material used for thesidewall spacer 28, a RIE process using the parameters already set forth hereinabove will yield the required selectivity.

As shown in FIG. 1E, thesidewall spacer 28 is etched until aresidual portion 38 of thesidewall spacer 28 remains, thus forming a gate conductor contact opening orwindow 40 which is a void having boundaries defined by theoxide layer 34, thesidewall 21 of theoxide cap 20, thesidewall 24 of thegate conductor 18, and theresidual portion 38. As such, the etch selectivity properties of thesidewall spacer 28 allows formation of the gateconductor contact window 40 to be "self-aligned" to thesidewall 24 of thegate conductor 18 and to thesidewall 21 of theoxide cap 20. Further, thesidewall spacer 28 functions, at least in part, as a "sacrificial" structure in that thesidewall spacer 28 is etched and removed for forming the gateconductor contact window 40.

Theresidual portion 38 prevents thegate conductor 18 from shorting to thediffusion region 14 through thesilicided junction 32 when the gateconductor contact window 40 is backfilled with stud material. Illustratively, theresidual portion 38 measures approximately 750 Angstroms-1250 Angstroms in height, however, theresidual portion 38 can be of any height that will prevent thegate conductor 18 from shorting to thediffusion region 14.

Thephotoresist blockout mask 36 is then stripped using standard techniques; and thewafer 10 is cleaned using, for example, a hydrofluoric acid cleaning process. The result is shown in FIG. 1F.

If required, before backfilling the gateconductor contact window 40 with stud material, a liner (not shown) can be deposited so as to line the gateconductor contact window 40. The liner reduces contact resistance between the stud and thegate conductor 18, and improves adhesion of the stud to thegate conductor 18 andoxide layer 34, thus solving any problems of delamination. By way of example, the liner can comprise titanium, titanium nitride, or other similar conductive material.

Next, the gateconductor contact window 40 is backfilled with appropriate stud material, for example titanium, titanium nitride, tungsten, or other appropriate metallurgy. As shown in FIG. 1G, the stud material is then polished to form the gate conductor contact stud 42 which includes an exposedsurface 44 serving as an electrical contact point for connecting to other electrical devices. Thus, the boundaries of the gate conductor contact stud 42 are defined by theresidual portion 38, thesidewall 24 of thegate conductor 18, thesidewall 21 of theoxide cap 20, and theoxide layer 34; and the gate conductor contact stud 42 is "self-aligned" to theoxide cap 20 andgate conductor 18.

Accordingly, the contact region of the gate conductor contact stud 42 to thegate conductor 18 is substantially along theentire sidewall 24 of thegate conductor 18, i.e., the contact region extends from the top of theresidual portion 38 to the top of thegate conductor 18. Advantageously, contacting thegate conductor 18 along thesidewall 24 rather than on its top portion, increases the contact area between the gate conductor contact stud 42 and thegate conductor 18, thus minimizing contact resistance therebetween.

FIGS. 2A-2H illustrate the use of a spacer as an alignment structure for forming a stud for a diffusion region.

Referring now to FIG. 2A, there is shown a portion of asilicon wafer 44 having asubstrate 46 withdiffusion regions 48,49, agate oxide 50, agate conductor 52 havingsidewalls 54,56 and being comprised of appropriate metal (such as polysilicon, titanium silicide, or the like), anoxide cap 58 havingsidewalls 60,62, and afirst layer 66 which is comprised of a dielectric material.

Thediffusion regions 48,49,gate oxide 50,gate conductor 52 andoxide cap 58 are formed and patterned using conventional processes of diffusion, deposition and photolithography. Thefirst layer 66 is then deposited so as to coat thediffusion regions 48,49, thesidewalls 54,56 of thegate conductor 52, and theoxide cap 58. Thefirst layer 66 is then etched selectively to thediffusion regions 48,49 and the top of theoxide cap 58 such that only the material which is contiguous with thesidewalls 60,62 of theoxide cap 58 and contiguous with thesidewalls 54,56 of thegate conductor 58 remain unetched. This remaining material forms the first set ofspacers 68,70, as shown in FIG. 2B. Thus, it is important that the dielectric material used to form thefirst layer 66 has etch selectivity to diffusion regions and oxide. For example, using nitride with a conventional directional etching technique, such as a RIE technique, will yield the desired selectivity.

Optionally, thesilicided junctions 64,65 are then applied to thediffusion regions 48,49 to improve conductivity of these regions. Thesilicided junctions 64,65 are formed and patterned using known fabrication techniques.

Next, as shown in FIG. 2C, asecond layer 72 is deposited, such as by chemical vapor deposition, so as to coat thesilicided junctions 64,65, the first set ofspacers 68,70, and the top of theoxide cap 58. Thesecond layer 72 is then etched selectively to thesilicided junctions 64,65, the top of theoxide cap 58 and the first set ofspacers 68,70 such that only the material which is contiguous with the first set ofspacers 68,70 remains unetched. Thus, the remaining material forms a second set ofspacers 74,76 which are of substantially the same height as the first set ofspacers 68,70, as shown in FIG. 2D.

It should be realized that the dimensions of thesecond layer 72 determines the dimensions of the second set ofspacers 74,76, and the dimensions of the second set ofspacers 74,76 determine the dimensions of the stud being formed to contact thediffusion region 48. Therefore, the required dimensions of the stud must be taken into account at the time of deposition of thesecond layer 72.

In this example, for reasons set forth hereinbelow, thesecond layer 72 which forms the second set ofspacers 74,76 not only can be etched selectively to thesilicided junctions 64,65, theoxide cap 58 and the first set ofspacers 68,70, but oxide can also be polished selectively to thesecond layer 72 and resulting second set ofspacers 74,76. In this regard, it can be realized that selection of the material used to form thesecond layer 72 depends in part on the dielectric material used to form the first set ofspacers 68,70. For instance, if the first set ofspacers 68,70 comprise nitride, then boron nitride, silicon boron nitride, carbon boron nitride, and silicon nitride have the required etch and polish selectivities to be used to form the second set ofspacers 74,76.

Preferably, thesecond layer 72 is deposited in a uniform thickness, and the etching technique used to etch thesecond layer 72 is directional or anisotropic. Illustratively, if a substantially uniform layer of BN is used as thesecond layer 72 to form the second set ofspacers 74,76, then a reactive ion etching (RIE) technique using the parameters set forth hereinabove provides the required anisotropy and etch selectivity.

Reference is now made to FIG. 2E. An insulatinglayer 78, such as an oxide layer, is deposited, such as by chemical vapor deposition, so as to be contiguous with the second set ofspacers 74,76 and so as to cover and insulate thesilicided junctions 64,65 anddiffusion regions 48,49. Theoxide layer 78 is then polished so that the top of theoxide layer 78 is substantially coplanar with the top of the first set ofspacers 68,70 and second set ofspacers 74,76, i.e., theoxide layer 78 is polished until it is of substantially the same height as thesecond spacers 74,76. Since oxide polishes selectively to the dielectric material used to form the second set ofspacers 74,76, i.e., the second set ofspacers 74,76 polish at a slower rate than oxide, the second set ofspacers 74,76 function as a "stop" during the polishing step. It should be realized that the use of oxide as the insulatinglayer 78 is for illustration purposes only and, as such, other dielectrics which polish at a faster rate than the dielectric used for the second set ofspacers 74,76 can be used in lieu of oxide. For example, a doped oxide such as phosphosilicate glass or borophosphosilicate glass can also be used.

Optionally, since the top of theoxide cap 58 and the top of the first set ofspacers 68,70 are substantially coplanar with the top of the second set ofspacers 74,76, the top of such structures can also be used as the polish stop in lieu of the second set ofspacers 74,76. A thin layer of material which is polish selective to oxide, such as silicon nitride, may be required to be deposited on top of theoxide cap 58 and/or first set ofspacers 68,70 for such structures to function as the polish stop. The thin layer would then have to be removed subsequent to the polishing step.

In accordance with the next step of the invention, a layer of photoresist is applied over thepolished oxide layer 78. The photoresist layer is patterned using standard photolithographic techniques of exposure and development so as to form aphotoresist blockout mask 80, as shown in FIG. 2F. Thephotoresist blockout mask 80 covers or blocks outspacer 70 andspacer 76, but leavesspacer 68 andspacer 74 exposed. As further described hereinafter,spacer 74 is exposed for etching for forming a diffusion contact window. Although FIG. 2F shows spacer 74 exposed, the choice as to exposingspacer 74 orspacer 76 depends on the requirements of the semiconductor device being fabricated, as eitherspacer 74 orspacer 76 can be etched to form a diffusion contact window. However, it is important that thephotoresist blockout mask 80 be patterned to cover the spacer which will not be used to form the diffusion contact window, so that it will remain unetched.

Moreover, note that thephotoresist blockout mask 80 does not cover theoxide cap 58 or theoxide layer 78 adjacent to thespacer 74 being used to form the diffusion contact window. Since thespacer 74 etches selectively to oxide, neither theoxide cap 58 nor theoxide layer 78 adjacent to thespacer 74 need to be covered by thephotoresist blockout mask 80. Thus, thespacer 74 will be removed during etching and theoxide cap 58 and theoxide layer 78 will remain unetched. Accordingly, a high degree of accuracy is not required when forming thephotoresist blockout mask 80 for etching thespacer 74. In this regard, sincespacer 74 also etches selectively tospacer 70, if desired,spacer 70 also need not be covered by thephotoresist blockout mask 80.

Thespacer 74 is then etched selectively to theoxide cap 58, theoxide layer 78 andspacer 68. Again using BN as an example of the material used to form thespacer 74, a RIE process using the parameters already set forth hereinabove will yield the required selectivity.

As shown in FIG. 2G, thespacer 74 is etched and removed, thus forming diffusion contact opening orwindow 82 which is a void having boundaries defined byoxide layer 78,spacer 68 andsilicided junction 64. As such, the etch selective properties of thespacer 74 allows formation of thediffusion contact window 82 to be "self-aligned" to thespacer 68. Further, thespacer 74 functions as a "sacrificial" structure in that thespacer 74 is etched and removed for forming thediffusion contact window 82.

Thespacer 68 prevents thegate conductor 52 from shorting to thediffusion region 48 through thesilicided junction 64 when thediffusion contact window 82 is backfilled with stud material.

Thephotoresist blockout mask 80 is then stripped using standard techniques; and thewafer 44 is cleaned using, for example, a hydrofluoric acid cleaning process. The result is shown in FIG. 2H.

Next, thediffusion contact window 82 is backfilled with appropriate stud material, for example titanium, titanium nitride, tungsten, or other appropriate metallurgy. The stud material is then polished to form thediffusion contact stud 84, as shown in FIG. 2H. It can be seen that thespacer 68 separates and insulates thegate conductor 52 so as to prevent thegate conductor 52 from shorting with thediffusion region 48 via thediffusion contact stud 84 andsilicided junction 64.

Thus, the boundaries of thediffusion contact stud 84 are defined by thespacer 68, theoxide layer 34 and thesilicided junction 64; and the diffusion contact stud 42 is "self-aligned" to thespacer 68.

While the invention has been described in terms of specific embodiments, it is evident in view of the foregoing description that numerous alternatives, modifications and variations will be apparent to those skilled in the art. Thus, the invention is intended to encompass all such alternatives, modifications and variations which fall within the scope and spirit of the invention and the appended claims.

Claims (18)

What is claimed is:

1. A process for fabricating a stud for a semiconductor structure, comprising:

providing a semiconductor substrate having an alignment structure and said semiconductor structure formed thereon, said alignment structure including a sidewall;

forming a sidewall spacer contiguous with said semiconductor structure and said sidewall of said alignment structure, said sidewall spacer being of substantially the same height as said alignment structure;

depositing an insulating layer contiguous with said sidewall spacer so as to effectively insulate said semiconductor structure, said insulating layer being of substantially the same height as said sidewall spacer;

etching said sidewall spacer selectively to said sidewall of said alignment structure, said semiconductor structure and said insulating layer, for forming a contact window opening for allowing access to said semiconductor structure; and

backfilling said contact window opening with a conductive material so as to contact said semiconductor structure for forming said stud.

2. A process according to claim 1, wherein said sidewall spacer is formed by

coating said semiconductor structure and said alignment structure, including said sidewall of said alignment structure, with a layer of material having etch selectivity to said semiconductor structure and said alignment structure; and

etching said material selectively to said semiconductor structure and said alignment structure so that the material coating said sidewall of said alignment structure remains unetched for forming said sidewall spacer.

3. A process according to claim 2, wherein said layer of material has a substantially uniform thickness, and said etching of said material comprises a substantially anisotropic etching.

4. A process according to claim 3, wherein said anisotropic etching comprises reactive ion etching.

5. A process according to claim 1, further comprising a planarizing step for planarizing said insulating layer until said insulating layer is substantially the same height as said sidewall spacer.

6. A process according to claim 5, wherein said sidewall spacer planarizes at a slower rate than said insulating layer so that said sidewall spacer functions as a stop during said planarizing step.

7. A process according to claim 1, wherein said sidewall spacer comprises a dielectric material.

8. A process according to claim 7, wherein a residual portion of said sidewall spacer remains unetched during said etching step for preventing said alignment structure from shorting to said semiconductor structure.

9. A process according to claim 8, wherein said residual portion has an approximate height of between 750 Angstroms and 1250 Angstroms.

10. A process according to claim 1, wherein said etching of said sidewall spacer comprises a substantially anisotropic etching.

11. A process according to claim 10, wherein said anisotropic etching comprises reactive ion etching.

12. A process according to claim 1, further including a step of forming a junction on said semiconductor structure for improving conductivity of said semiconductor structure.

13. A process according to claim 1, wherein said sidewall of said alignment structure comprises an insulating spacer which prevents shorting of said alignment structure with said semiconductor structure via said stud.

14. A process according to claim 13, wherein said insulating spacer comprises nitride.

15. A process according to claim 14, wherein said sidewall spacer comprises boron nitride.

16. A process according to claim 1, wherein said sidewall of said alignment structure is an element of said semiconductor structure.

17. A process according to claim 16, wherein said stud contacts said semiconductor structure along said sidewall of said alignment structure.

18. A process according to claim 1, wherein said sidewall spacer comprises boron nitride.

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