US4953130A - Memory circuit with extended valid data output time - Google Patents

Abstract

A memory device (10) having an asymmetrical delay circuit (34) in a data output path of the memory device (10) is disclosed. The memory device (10) employs a precharge circuit (28) to impress a precharge state in a read memory access cycle. The asymmetrical delay circuit (34) imposes a relatively slow propagation delay on data signals which transition toward this precharge state, but imposes a relatively fast propagation delay on data signals which transition away from this precharge state. Specific embodiments of an output portion (32) of the memory device (10) are presented to accommodate a high impedance state in an output buffer (38) during signal transitions and to accommodate various polarity precharge states.

Description

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to semiconductor memory devices. More specifically the present invention relates to circuits employed in connection with such memory devices.

BACKGROUND OF THE INVENTION

In the design of semiconductor memory devices, attention is continually given to simplifying circuits utilized in connection with such devices. Simplified circuits typically require less space, consume less power, and operate more reliably than more complicated circuits. However, as the speed at which such memory devices operate increases, complexity of circuit designs used in connection with such devices tends to increase.

For example, in a typical semiconductor memory device, such as an SRAM, DRAM, PROM, EPROM, or the like, a change in an address supplied to the device causes data previously output from the device to become invalid after some typically short specified period of time. When the device is being operated at maximum speed, the address changes as soon as the output data becomes valid. Consequently, data remains valid at the device output for only a short period of time. The device is difficult to utilize when operated at maximum speed because the data output does not remain valid for an acceptably long period of time. Moreover, as device speed increases, a precharge portion of an access cycle tends to occur more quickly after an address change, and this rapid precharge tends to further decrease valid data output time.

One solution to this shrinking valid data output time problem has been to incorporate a latch in a memory device. However, the timing and control circuitry used in connection with such a latch tends to be undesirably complicated. The complication arises due to a very critical timing requirement in capturing valid data and to a very critical timing requirement in connection with releasing data so that a subsequent access cycle will not be delayed by operation of the latch.

In addition, many semiconductor memory devices tolerate a certain amount of crowbar current in connection with data transitions at output buffers of the memory devices. Crowbar current represents a current surge which flows between power rails through the output buffer. It typically results from momentary, simultaneous activation of two, series connected active devices located between the power rails. These current surges are undesirable because they cause excess power consumption and because they produce voltage surges within the memory device. As memory device speed increases, internal circuitry tends to become more susceptible to the undesirable effects of such voltage surges. Consequently, circuit complexity tends to increase to ensure that such surges are minimized and to ensure that such surges do not adversely affect the circuits.

One solution to the crowbar current problem has been to utilize differences in rise and fall times of the circuits driving the active devices to deactivate one of the tWo active devices a very short amount of time before beginning to activate the second of the two active devices. However, this solution is undesirable because the insubstantial timing difference tends not to significantly reduce crowbar currents, and because these relative activation and deactivation rates can reverse in the presence of radiation or at extreme temperatures.

Consequently, a need exists for a simple circuit which addresses the valid output data time and crowbar current problems.

SUMMARY OF THE INVENTION

Accordingly, it is an advantage of the present invention that an improved memory device is provided which incorporates a circuit to extend the length of time for which output data remains valid.

Another advantage of the present invention :s that a circuit is provided which resides in a data path of a memory device and does not require generation of timing signals for its operation.

The above and other advantages of the present invention are carried out in one form by a memory device in which a precharge portion of a read access cycle causes an output of the memory device to exhibit data in a first logical state. The memory device includes a first structure which delays transition of data at the memory device output from the first logical state to a second logical state. In addition, the memory device includes a structure which delays data at the memory device output when this data transitions from the second logical state to the first logical state. Moreover, the first structure and second structure are configured so that the data transitions from the first logical state to the second logical state substantiallY quicker than it transitions from the second logical state to the first logical state.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present invention may be derived by referring to the detailed description and claims when considered in connection with the FIGURES, wherein like reference numbers refer to similar items throughout the FIGURES, and:

FIG. 1 shows a block diagram of a memory device constructed in accordance with the present invention;

FIG. 2 shows a logical diagram of a first embodiment of an output portion of the memory device shown in FIG. 1;

FIG. 3 shows a logical diagram of a second embodiment of the output portion of the memory device shown in FIG. 1;

FIG. 4 shows a logical diagram of a third embodiment of the output portion of the memory device shown in FIG. 1; and

FIG. 5 shows a logical diagram of a fourth embodiment of the output portion of the memory device shown in FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a simplified block diagram of amemory device 10 constructed in accordance with the present invention.Memory device 10 may represent an SRAM, DRAM, PROM. EPROM, or other semiconductor memory device. In FIG. 1,memory device 10 receives anaddress bus 12, which couples to an addresstransition detection circuit 14. In addition, a row address portion ofaddress bus 12, couples to arow address decoder 16, and a column address portion ofaddress bus 12 couples to a column address decoder 19. Outputs fromrow address decoder 16 couple toword lines 18 of amemory cell array 20. In addition, outputs from column address decoder 19 couple tomemory cell array 20 and to selection inputs of amultiplexer 22.Bit lines 24 ofmemory cell array 20 couple to inputs ofsense amplifiers 26, and outputs ofsense amplifiers 26 couple to inputs ofmultiplexer 22. An output from addresstransition detection circuit 14 couples to an input of aprecharge circuit 28, and outputs ofprecharge circuit 28 couple tobit lines 24 ofmemory cell array 20 and to senseamplifiers 26.

Memory cell array 20 contains a multiplicity ofsemiconductor memory cells 30. Each ofmemory cells 30 is located at an intersection between aword line 18 and abit line 24. Thus,memory cells 30 are arranged in an array of rows and columns. Each ofcells 30 is intended to store one bit of data whenmemory device 10 represents a one bit wide memory device or more bits of data ifmemory device 10 represents a memory device which saves more than one bit of data at each address. A particular one ofmemory cells 30 is selected by an address value supplied onaddress bus 12 and decoded byrow address decoder 16 andcolumn address decoder 18. In the preferred embodiment,row address decoder 16,column address decoder 18, andmemory cell array 20 represent conventional memory structures which may advantageously be implemented in a conventional fashion.

Addresstransition detection circuit 14 monitors each bit of an address value presented onaddress bus 12 to detect when this address value changes. The output signal from addresstransition detection circuit 14 indicates when one of these address bits changes logical states. When this event occurs, the output signal from addresstransition detection circuit 14commands precharge circuit 28 to introduce a predetermined voltage level on each ofbit lines 24 ofmemory cell array 20. In addition, the preferred embodiment of the present invention supplies a precharge signal to senseamps 26. The predetermined voltage established onbit lines 24 may then be influenced by the programming ofcells 30 inmemory array 20. Specifically,cells 30 residing on aword line 18 which is specified by the row address portion ofaddress bus 12 may forcecorresponding bit lines 24 to a state which would cause an output opposite to that caused by the precharge state, depending upon the programming of such cells. Sense amps 26 detect voltages onbit lines 24, and multiplexer 22 selects a particular column, orbit line 24 as a source of data output frommemory device 10. In the preferred embodiment of the present invention,address detection circuit 14,precharge circuit 28,sense amps 26, andmultiplexer 22 represent conventional structures in the fabrication of memory devices, and conventional implementations for these structures are contemplated by the present invention.

An output frommultiplexer 22 drives anoutput portion 32 ofmemory device 10.Output portion 32 includes anasymmetrical delay circuit 34, an optional latch 36 (shown in dotted lines), and anoutput buffer 38. Specifically, the output ofmultiplexer 22 couples to an input ofasymmetrical delay circuit 34 at aninput node 40 thereof. Moreover, an output ofprecharge circuit 28 couples to an optional input (shown as a dotted line) ofasymmetrical delay circuit 34 at anode 42. An output ofasymmetrical delay circuit 34 couples to an input oflatch 36, and an output oflatch 36 couples to an input ofoutput buffer 38. An output ofoutput buffer 38 couples to anode 44, which serves as the output frommemory device 10 and provides data recalled frommemory device 10.

Asymmetrical delay circuit 34 delays data signals propagating therethrough. More specifically,asymmetrical delay circuit 34 delays signals which transition from a first logical state to a second logical state a different period of time than it delays signals which transition from the second logical state to the first logical state. For example, if the precharge state impressed onbit lines 24 byprecharge circuit 28. uninfluenced by programming ofmemory cells 30, causes a logical 1 to appear atnode 40, thenasymmetrical delay circuit 34 introduces a relatively slow delay in propagating a transition of this signal to a logical 1 at the output ofasymmetrical delay circuit 34. On the other hand, in this situationasymmetrical delay circuit 34 introduces a relatively fast propagation delay on signals transitioning from a logical 1 to a logical 0 atnode 40.

Latch 36 represents an optional structure which is conventional memory device designs.Latch 36 may serve to hold output data even longer than occurs through the operation ofasymmetrical delay circuit 34. However, the timing and control considerations forlatch 36 are not critical becauseasymmetrical delay circuit 34 tends to extend the time for which data recalled frommemory cell array 20 remains valid at the output ofasymmetrical delay circuit 34.

Output buffer 38 includes logic circuitry to control a high impedance output state ofmemory device 10 so that multiple memory devices may be coupled together at the outputs thereof. In addition,output buffer 38 provides sufficient drive capability to interfacememory device 10 to inputs of other devices (not shown).

Table 1, shown below, presents all possible data transitions which may occur between two successive read memory access cycles. Data output frommemory device 10 during these two access cycles are listed in the "Last Output" and "Next Output" columns of Table 1. In addition, data presented in the "Precharge" column of Table 1 defines the precharge state of data atoutput node 44. Cases 1-4 illustrate the operation ofmemory device 10 when the precharge state produces a logical 1 atoutput node 44, and cases 5-8 illustrate the operation ofmemory device 10 when the precharge state produces a logical 0 atoutput node 44. In the preferred embodiment,memory device 10 is designed to operate either only in connection with cases 1-4 or only in connection with cases 5-8. In other words, the precharge state shown in TABLE 1 results from the design ofmemory device 10, and does not change due to the operation ofmemory device 10.

              TABLE 1                                                     ______________________________________                                    Last Output      Precharge NextOutput                                    ______________________________________                                    Case 1  0            1         0                                          Case 2  0            1         1                                          Case 3  1            1         0                                          Case 4  1            1         1                                          Case 5  0            0         0                                          Case 6  0            0         1                                          Case 7  1            0         0                                          Case 8  1            0         1                                          ______________________________________

In a typical sequence of events occurring in connection with two successive read access cycles ofmemory device 10,memory device 10 outputs a Last Output value shown in Table 1. Then, as a change in address is detected at addresstransition detection circuit 14, a Precharge value is output frommemory device 10. Finally, after the precharge state has been established, a Next Output value becomes valid, presenting data specified by the new address value.

In cases 1-4 of Table 1,asymmetrical delay circuit 34 imposes a slower delay on data changing from a logical 0 state to a logical 1 state than it imposes on data changing from a logical 1 state to a logical 0 state. Consequently, the Last Output value incases 1 and 2 remains valid for a relatively long period of time before the output exhibits the Precharge state. In cases 3 and 4,asymmetrical delay circuit 34 has substantially no effect because the output data does not change logical states. On the other hand, sinceasymmetrical delay circuit 34 imposes only a minimal delay on data transitioning from a logical 1 to a logical 0 state, the Next Output incases 1 and 3 is not significantly delayed. Moreover, no delay occurs in cases 2 and 4 because the Next Output does not change states from the Precharge state.

Cases 5-8 of Table 1 occur when the Precharge condition produces a logical 0 atoutput 44. Thus, for cases 5-8asymmetrical delay circuit 34 delays data transitions from a logical 1 state to a logical 0 state more than it delays data transitions from a logical 0 state to a logical 1 state. In case 5, no data transitions occur, so the Last Output remains valid through the Precharge time period. Likewise, in case 6, the Last Output is a logical 0 value and it remains valid through the Precharge period. However, in cases 7 and 8,asymmetrical delay circuit 34 causes a relatively slow transition from a logical 1 Last Output value to a logical 0 Precharge state. This extends the time for which output data remains valid. In cases 5 and 7, no data transitions occur from the precharge state to the Next Output. Therefore,asymmetrical delay circuit 34 does not delay the subsequent read access cycle. Moreover, in cases 6 and 8,asymmetrical delay circuit 34 imposes only an insubstantial delay in transitioning from a logical 0 Precharge state to a logical 1 Next Output value.

In the preferred embodiment of the present invention, the longer one of the delay periods produced byasymmetrical delay circuit 34 approximately equals the amount of time required for the precharge state. However, there is no requirement that this delay has any specific relationship to the precharge time so long as it remains less than the entire memory read access cycle. On the other hand, the faster of the two delays imposed byasymmetrical delay circuit 34 represents only an insubstantial propagation delay which may be as little as one fourth the precharge time or less.

Output portion 32 ofmemory device 10 is discussed in more detail in FIGS. 2-5. Specifically, FIGS. 2 and 3 show first and second embodiments ofoutput portion 32 for use in cases 1-4 and 5-8, respectively, of Table 1. Likewise, FIGS. 4 and 5 show third and fourth embodiments ofoutput portion 32 for use in cases 1-4 and 5-8, respectively.

Referring to FIG. 2,asymmetrical delay circuit 34 includes an ANDelement 46 and adelay element 48. A first input of ANDelement 46 couples tonode 40, and a second input of ANDelement 46 couples to an output ofdelay element 48. Delayelement 48 includes aninverter 50, acapacitor 52, and aNAND element 54. An input ofinverter 50 serves as the input to delayelement 48 and couples tonode 40. An output ofinverter 50 couples to a first node ofcapacitor 52 and to a first input ofNAND element 54. A second input ofNAND element 54 serves as a control input to delayelement 48 and couples tonode 42. An output ofNAND element 54 couples to a second node ofcapacitor 52 and serves as the output ofdelay element 48.

Although a specific implementation is shown fordelay element 48, the present invention contemplates the use of any delay element known to those skilled in the art fordelay element 48. As discussed above in connection with FIG. I, the present invention contemplates thatdelay element 48 should insert a delay approximately equal to the length of the precharge state formemory device 10. However, this delay value is not critical and need not be specifically related to the length of the precharge state. On the other hand, the length of this delay is anticipated to be substantially longer than propagation delays associated with ANDelement 46 orlatch 36.

The output ofasymmetrical delay circuit 34 couples to a data input oflatch 36, and a data output oflatch 36 couples to a data input ofoutput buffer 38. A clock input oflatch 36 couples to anode 56, which supplies a signal that controls the latching of data inlatch 36. The timing of this signal is not critical in the present invention due to the use ofasymmetrical delaY circuit 34 prior to latch 36.

Output buffer 38 includes aNAND element 58, aninverter 60, and a NORelement 62. In addition,output buffer 38 includes a P channel field effect transistor (FET) 64 and anN channel FET 66. A first input ofNAND element 58 couples to a first input of NORelement 62, and these first inputs serve as the data input tooutput buffer 38. Anode 68 couples to a second input ofNAND element 58 and to an input ofinverter 60. An output ofinverter 60 couples to a second input of NORelement 62. An output ofNAND element 58 couples to a control input, or gate, ofFET 64, and an output of NORelement 62 couples to a control input, or gate, ofFET 66. An input, or source, ofFET 64 couples to a terminal 70, which is adapted to receive a positive voltage. An input, or source, ofFET 66 couples to a terminal 72, which is adapted to receive a ground or negative potential with reference to the potential applied atterminal 70. Output nodes, or drains, of FETS 64 and 66 couple together and tonode 44 to provide data output from memory device 10 (see FIG. 1). The present invention contemplates implementing the logic elements shown in FIG. 2 using conventional techniques and the inclusion of additional conventional stages (not shown) for buffering to increase drive capabilities to FETS 64 and 66.

The signal supplied atnode 42 enables and disablesdelay element 48. The signal supplied atnode 42 exhibits a logical 1 when a read access cycle occurs in which the precharge mode is utilized. However,memory device 10 contemplates permitting the occurrence of read access cycles in certain situations without a prior precharge cycle. In such situations, the signal supplied atnode 42 exhibits a logical 0, and delayelement 48 is disabled. Whendelay element 48 is disabled,asymmetrical delay circuit 34 provides approximately equal delays for 0 to 1 on 1 to 0 transitions.

In FIG. 2, the output ofasymmetrical delay circuit 34 exhibits a logical 1 only after both a data signal presented atnode 40 and a delayed signal presented at the output ofdelay element 48 each exhibit a logical 1. Consequently, transitions of data from a logical 0 to a logical 1 occur relatively slowly because the period of time associated withdelay element 48 must first transpire before the output of ANDelement 46 can transition to a logical 1 value. On the other hand, when the data presented atnode 40 transitions from a logical 1 to a logical 0, the output ofasymmetrical delay circuit 34 likewise exhibits a logical 0 after only a propagation delay associated with ANDelement 46. Delayelement 48 has no influence on this 1 to 0 transition.

The signal supplied atnode 68 and logical elements 58-62 together serve to enable and disable FETS 64 and 66. When this signal is a logical 0, each of FETS 64 and 66 is disabled, andoutput node 44 exhibits a high impedance. However, when this signal is a logical 1,output buffer 38 is enabled, and the output presented atnode 44 reflects a data state provided at the output oflatch 36. Specifically, if the output data atlatch 36 is a logical 1, thenFET 64 is activated,FET 66 is deactivated, andoutput node 44 exhibits a logical 1. 0n the other hand, if the data output fromlatch 36 is a logical 0, thenFET 64 is deactivated,FET 66 is activated, andoutput node 44 exhibits a logical 0.

FIG. 3 shows a logical diagram of a second embodiment ofoutput portion 32 of memory device 10 (see FIG. 1). The second embodiment shown in FIG. 3 may advantageously be used when the precharge state causes the data value atnode 40 to exhibit a logical 0, or for cases 5-8 discussed above in connection with Table 1. The logical diagram shown in FIG. 3 is similar to the logical diagram discussed above in connection with FIG. 2, and the discussion presented therewith applies to the FIG. 3 structure as well. However, the FIG. 3 logical diagram differs from that discussed above in connection with FIG. 2 in thatoptional latch 36 has not been included in the FIG. 3 structure, the optional disabling function presented atnode 42 of FIG. 2 has not been included in the FIG. 3 structure, and AND element 46 (see FIG. 2) has been replaced with anOR element 74 in the FIG. 3 structure. One input of ORelement 74 couples to inputnode 40, and a second input oflogical 0R element 74 couples to the output ofdelay element 48. An output of logical ORelement 74 couples to the data input ofoutput buffer 38.

Consequently,asymmetrical delay circuit 34 inserts a relatively slow propagation delay when a data value presented atinput node 40 transitions from a logical 1 to a logical 0 but inserts a relatively fast propagation delay when this data transitions from a logical 0 to a logical 1. Only when both the data value presented atnode 40 and the output signal fromdelay element 48 equal a logical 0 will the output fromasymmetrical delay circuit 34 exhibit a logical 0. The time delay associated withdelay element 48 must first transpire before both exhibit a logical 0. However, when a data transition to a logical 1 is applied atnode 40, an output fromasymmetrical delay circuit 34 exhibits a logical 1 after only a propagation delay associated with ORelement 74. This asymmetrical delay is reflected in the output signal provided atnode 44 ofoutput buffer 38 in a similar manner to that described above in connection with FIG. 2.

The first and second embodiments ofoutput portion 32 shown in FIGS. 2 and 3 may cause a crowbar current to flow throughFETS 64 and 66 as a signal presented atoutput 44 transitions from one logical state to another. This crowbar current occurs when both of FETS 64 and 66 are fully or partially activated at any instant in time. However, the data signal presented tooutput buffer 38 in FIGS. 2 and 3 fromasymmetrical delay circuit 34 switches signals at control nodes ofFET 64 and 66 at approximately the same point in time. Thus, this crowbar current is minimized. Nevertheless, the third and fourth embodiments ofoutput portion 32 of memory device 10 (see FIG. 1) which are presented in FIGS. 4 and 5, respectively, utilizeasymmetrical delay circuit 34 to guarantee that one ofFETS 64 and 66 is deactivated prior to the activation of the other of FETS 64 and 66.

Specifically, FIG. 4 shows a logical diagram of a third embodiment ofoutput portion 32. This third embodiment may be used when the precharge state presents a logical 1 atnode 40. The FIG. 4 structure is also similar to the FIG. 2 structure. However, the FIG. 4 structure differs from the FIG. 2 structure in thatoptional latch 36 has been omitted, and the optional disabling ofdelay element 48 has been omitted. Moreover, the logical function performed by two input ANDelement 46 and twoinput NAND element 58 in FIG. 2 has been combined into a single threeinput NAND element 76 in FIG. 4. Thus, the asymmetrical delay function in the FIG. 4 structure occurs through operation ofdelay element 48 andNAND element 76.

Moreover, this asymmetrical delay function influences onlyP channel FET 64 and notN channel FET 66.N channel FET 66 is influenced only from data supplied directly atinput node 40. As a result, a logical 0 to logical 1 transition of data presented atinput node 40 causes FET 66 to quickly deactivate. This deactivation occurs after only a propagation delay through NORelement 62. On the other hand, this logical 0 to logical 1 transition of data atinput node 40 causes FET 64 to activate only after a delay which is imposed bydelay element 48. As a result,output 44 exhibits a high impedance state for a length of time roughly equivalent to the delay imposed bydelay element 48. In circuits using memory device 10 (see FIG. 1), capacitance associated withoutput node 44 and devices coupled thereto (not shown) tends to hold a logical 0 data value atoutput node 44 for this length of delay Moreover, no crowbar current flow throughFETS 64 and 66. This structure is especially adaptable for use in connection with driving CMOS devices withoutput node 44 and for driving conventional TTL type inputs fromoutput node 44 when the delay imposed bydelay element 48 is sufficiently short.

On the other hand, when data atinput node 40 transitions from a logical 1 to a logical 0,FET 64 deactivates simultaneously with the activation ofFET 66. Thus, no substantial delay is imposed, and valid data from a successive read access cycle of memory device 10 (see FIG. 1) may be presented atoutput node 44 as soon as possible.

FIG. 5 shows a logic diagram of a fourth embodiment ofoutput portion 32 of memory device 10 (see FIG. 1). This fourth embodiment is intended to be used when the precharge state presents a logical 0 atnode 40. The structure shown in FIG. 5 closely resembles the structure shown in FIG. 3, except thatasymmetrical delay circuit 34 drives onlyN channel FET 66 and notP channel FET 64. In addition, a buffer 78 resides in series with the first input ofNAND element 58, and the input of buffer 78 couples to inputnode 40. Input buffer 78 merely inserts a propagation delay so that logical 0 to logical 1 data transitions atinput node 40 influence control nodes of FETS 64 and 66 at substantially identical points in time. On the other hand, the operation ofasymmetrical delay circuit 34 causes a logical 1 to logical 0 transition of data presented atinput node 40 to first deactivateP channel FET 64, then wait an amount of time controlled by the delay ofdelay element 48 before activatingN channel FET 66. Consequently,output node 44 exhibits a high impedance state for this length of delay, and crowbar current is prevented.

In summary, the present invention provides animproved memory device 10 which incorporatesasymmetrical delay circuit 34 to extend the length of time for which output data frommemory device 10 remains valid. In addition,asymmetrical delay circuit 34 resides in the data path from memory cell array 20 (see FIG. 1) tooutput 44 ofmemory device 10 and does not require circuitry to generate complicated timing and control signals. The use ofasymmetrical delay circuit 34 may extend the valid output data time sufficiently long so that a latch, such aslatch 36, is not required in many applications. Moreover, even applications which require the use oflatch 36 benefit from the use ofasymmetrical delay circuit 34 because timing and control signals which operatelatch 36 may be simplified due to the extended valid output data time. Still further, the present invention contemplates the use of various embodiments ofoutput portion 32 ofmemory device 10 to accommodate various polarities of data produced by the precharge state and to further reduce crowbar current.

The foregoing description discusses preferred embodiments of the present invention, which may be changed or modified without departing from the scope of the present invention. For example, the P channel FETS discussed above may be replaced with N channel FETS in some applications, and appropriate polarity changes in controlling signals are required. Moreover, the N channel and P channel FETS discussed above generally represent active devices which may be replaced with bipolar or other technology active devices. Still further, those skilled in the art will understand that the logical elements described above may be formed using a wide variety of logical gates employing any polarity of input or output signals, and that the logical values described above may be implemented using different voltage polarities. As an example, an AND element may be formed using an AND gate or a NAND gate when all input signals employ a positive logic convention, or it may be formed using an OR gate or a NOR gate when all input signals exhibit a negative logic convention. These and other changes and modifications are intended to be included within the scope of the present invention.

Claims (12)

What is claimed is:

1. A memory device for recalling data stored therein, said memory device comprising:

a memory cell array having a plurality of memory cells, each of said cells being for storing data therein, and each of said cells being coupled to a bit line of said memory cell array;

a sensing circuit, coupled to said bit line of said memory cell array, for sensing data presented thereon;

an asymmetrical delay circuit having an input coupled to said sensing circuit and having an output, said asymmetrical delay circuit, being operable for causing data at said asymmetrical delay circuit output to transistion from a first logical state to a second logical state faster than dat at said asymmetrical delay circuit output transitions from said second logical state to said first logical state, said asymmetrical delay circuit being additionally operable to switch said electrical circuit into it precharge state at a rate faster than it switches said electrical circuit out of said state;

an output buffer coupled to said asymmetrical delay circuit output for presenting data recalled from said memory device; and

a precharge circuit coupled to said delay circuit and to at least one of said bit lines of said memory cell array and said sensing circuit, said precharge circuit causing a predetermined logic level at said asymmetrical delay circuit input prior to recalling data stored in one of said memory cells.

2. A memory device as claimed in claim 1 wherein said asymmetrical delay circuit is configured so that said predetermined logic level causes said output of said asymmetrical delay circuit to exhibit said first logical state.

3. A memory device as claimed in claim 1 wherein said predetermined logic level is a logical 1 value, and said asymmetrical delay circuit comprises:

a delay circuit having an input coupled to said sensing circuit and having an output; and

a logical AND element having a first input coupled to said delay circuit input, a second input coupled to said delay circuit output, and an output which serves as said asymmetrical delay circuit output.

4. A memory device as claimed in claim 3 wherein said output buffer comprises:

a first active device having a control node coupled to said logical AND element output and having an output node;

a second active device having a control node coupled to said delay circuit input and having an output node coupled to said first active device output node so that said first actiVe device activates and said second active device deactivates when said predetermined logic level is presented at said asymmetrical delay circuit input.

5. A memory device as claimed in claim 4 wherein said first active device is a PMOS transistor and said second active device is an NMOS transistor.

6. A memory device as claimed :n claim 1 wherein said predetermined logic level is a logical 0 value, and said asymmetrical delay circuit comprises:

a delay circuit having an input coupled to said sensing circuit and having an output; and

a logical OR element having a first input coupled to said delay circuit input, a second input coupled to said delay circuit output, and an output which serves as said asymmetrical delay circuit output.

7. A memory device as claimed in claim 6 wherein said output buffer comprises:

a first active device having a control node coupled to said delay circuit input and having an output node;

a second active device having a control node coupled to said logical OR element output and having an output node coupled to said first active device output node so that said second active device activates and said first active device deactivates when said predetermined logic level is presented at said asymmetrical delay circuit input.

8. A memory device as claimed in claim 7 wherein said first active device is a PMOS transistor and said second active device is an NMOS transistor.

9. A memory device as claimed in claim 1 wherein said output buffer comprises:

a first active device having a control node and an output node;

a second active device having a control node and having an output node coupled to said first active device output node so that said output nodes of said first and second devices together present data recalled from said memory device; and

means, coupled between at least one of said first and second active device control nodes and said asymmetrical delay circuit output, for causing one of said first and second active devices to deactivate prior to activation of the other of said first and second active devices.

10. A memory device as claimed in claim 9 wherein:

said asymmetrical delay circuit is configured so that said predetermined logic level causes said first active device to activate and said second active device to deactivate; and

said means for causing is configured so that said second active device deactivates prior to activation of said first active device.

11. A memory device as claimed in claim 10 wherein said means for causing is configured so that said first active device deactivates at approximately the same time as said second active device activates.

12. A memory device as claimed in claim 1 wherein:

said memory device permits recall of data stored therein without said precharge circuit causing said predetermined logic level at said asymmetrical delaY circuit input prior to recalling data stored in one of said memory cells; and

said asymmetrical delaY circuit comprises means for causing data at said asymmetrical delay circuit output to transition from said first logical state to said second logical state in approximatelY the same duration as data transitions from said second logical state to said first logical state when data is recalled from said memory device without said precharge circuit causing said predetermined logic level at said asymmetrical delay circuit input prior to recalling data stored in said memory device.

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