US4787686A - Monolithic programmable attenuator - Google Patents

Abstract

A programmable attenuator includes a plurality of field effect transistors (FETS) arranged together to provide an attenuation network. Each one of the FETS has a plurality of cell portions, each cell portion having drain, gate and source regions, the source and drain regions of the cell portions being connected in parallel. A first selected portion of the gate regions of each one of said FETS is connected to a gate electrode. A second selected remaining portion of the gate regions of each one of the FETS has the gate regions thereof physically isolated from the gate electrode. A signal fed to the gate electrode of each FET is distributed to the connected gate regions of each field effect transistor. In response to such signal, the total drain-source resistance of such FET is changed between a predetermined low value and a predetermined high value, with the resistance of the predetermined high value being determined, in part, by the number of such isolated gate regions.

Description

This application is a divisional application of Ser. No. 810,900 filed on Dec. 20, 1985 now U.S. Pat. No. 4,684,965 which is a continuation of Ser. No. 492,857 filed on May 9, 1983 now abandoned.

BACKGROUND OF THE INVENTION

This invention relates generally to radio frequency circuits and more particularly to radio frequency circuits for selectively attenuating a signal fed thereto.

As is known in the art, attenuators are used for a variety of applications, for automatic gain control circuits, and in particular, in broadband temperature compensated microwave amplifiers for temperature compensation of gain over an operating range of temperatures. One type of attenuator often used is a programmable attenuator. A programmable attenuator provides a selected predetermined fixed attenuation in response to a set of signals fed thereto. A general technique for providing a programmable attenuator, such as those described in U.S. Pat. No. 3,765,020 and U.S. Pat. No. 4,121,183, employs field effect transistors to selectively switch passive elements such as resistors to provide a properly configured attenuation network to thereby provide, in response to a signal fed to such network, a predetermined attenuated output signal. While these attenuators are useful in certain applications, one problem associated with these types of attenuators is that such circuits are not particularly well suited for fabrication on a common substrate such as by using monolithic microwave integrated circuit techniques since a resistor ladder network is required to provide attenuation, and an impedance matching network is required for matching the attenuator to external circuits.

SUMMARY OF THE INVENTION

In accordance with the present invention, a programmable attenuator includes a plurality of field effect transistor cells interconnected to provide an attenuation network. Each one of the field effect transistors has a plurality of cell portions, each cell portion having drain, gate and source regions, the source and drain regions of the cell portions being connected in parallel. A first selected portion of the gate regions of each one of said FETS is connected to a gate electrode. A second selected remaining portion of the gate regions of each one of the FET cells has the gate regions thereof physically isolated from the gate electrode. A signal fed to the gate electrode of each FET is distributed to the connected gate regions of each FET. In response to such signal, the total resistance of a drain-source channel of each FET is changed between a predetermined low resistance value and a predetermined high resistance value with the predetermined high resistance value being determined in part by the number of such isolated gate regions. With such an arrangement, by selecting values of channel resistance for the FET in the high state and the low state, an attenuation network may be provided to have a constant characteristic impedance related to the characteristic impedance of an input circuit connected thereto. Further, such a circuit can be easily fabricated on a common substrate using monolithic microwave integrated circuit techniques.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing features of this invention, as well as the invention itself, may be more fully understood from the following detailed description read together with the accompanying drawings, in which:

FIG. 1 is a schematic representation of an attenuator in accordance with the invention;

FIG. 2 is an equivalent circuit of the attenuator of FIG. 1;

FIG. 2A is a simplified equivalent circuit of the attenuator of FIG. 2 showing a conventional T network for use in deriving certain equations useful in understanding the present invention;

FIG. 3 is a plan view of the attenuator shown in FIG. 1 fabricated as a monolithic integrated circuit;

FIG. 4 is an exploded plan view of a transistor used in the attenuator of FIG. 3;

FIG. 4A is a cross-sectional view of the transistor shown in FIG. 4 taken alongline 4A--4A; and

FIG. 5 is an exploded plan view of a dual gate transistor used in the attenuator of FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIG. 1, an r.f.energy source 20 is shown connected, via a radiofrequency transmission line 19a to a 1-bit two statedigital attenuator 10. Thedigital attenuator 10 is shown to include a plurality of field effect transistors, here 14a, 14b, 14c, each one of such field effect transistors havinggate electrodes 15a, 15b, 15c,drain electrodes 16a, 16b, 16c andsource electrodes 17a, 17b and 17c, respectively. Two of such field effect transistors (FET) here FETS 14a, 14b are connected in series with the input radiofrequency transmission line 19a, and an output radio frequency (r.f.)transmission line 19d with thedrain electrode 16a of FET 14a being connected to the r.f.transmission line 19a, source electrode 17a thereof being connected viatransmission lines 19b, 19c to thedrain electrode 16b ofFET 14b and source electrode 17b being connected to theoutput transmission line 19d. Output r.f.transmission line 19d is connected to aload 22.Load 22 here has a characteristic impedance (Z_o) equal to 50 ohms. The thirdfield effect transistor 14c connected in shunt between the interconnection ofFETS 14a, 14b and ground, hasdrain electrode 16c connected at the interconnection oftransmission lines 19b and 19c, and hassource electrode 17c connected to ground, as shown.

Gate bias forgate electrodes 15a, 15b offield effect transistors 14a, 14b is provided at a bias terminal V₁. The gate bias circuit includes adecoupling capacitor 12a connected in shunt between terminal V₁ and ground, a first length oftransmission line 13a connected between bias point V₁ and one end of a resistor R_a with a second end of resistor R_a being connected togate electrode 15a offield effect transistor 14a, and a second, here equal length oftransmission line 13b connected between bias point V₁ and a first end of a resistor R_b, the second end of resistor R_b being connected to thegate electrode 15b offield effect transistor 14b. In a similar manner, the gate bias circuit forfield effect transistor 14c includes abypass capacitor 12b connected in shunt between ground and a bias point V₂ and a length oftransmission line 13c connected between bias point V₂ andgate electrode 15c, and with resistor R_c being connected to thegate electrode 15c andfield effect transistor 14c.

By feeding voltage signals from a bias control means 21 to terminal V₁ and to terminal V₂, the equivalent values of channel resistance of eachFET 14a-14c here represented as resistors R₁, R₂, R₃ (FIG. 2A) will change between values of resistance R_1L, R_1H and R_2L, R_2H and R_3L, R_3H, respectively, in accordance with the value of the voltage level signal fed thereto. FET's 14a-14c are here depletion mode metal electrode semiconductor field effect transistors (MESFET's). Typically, a voltage level signal of zero volts with respect to the source electrode is applied to the gate electrode of such an FET to select a low value of channel resistance (R_1L, R_2L, R_3L) (FIG. 2) and a value of voltage corresponding to the pinch-off voltage, typically -5V is applied to the gate electrode to select a high value of channel resistance R_1H, R_2H, R_3H (FIG. 2). Resistors R_a, R_b, R_c are used to limit drain-gate current under a strong r.f. drive and also increases isolation between drain and gate electrodes. There is no drain bias circuit forattenuator 10 since FET's 14a-14b are here operated as variable resistors and as such passive operation does not require the use of a drain bias.

Referring now to FIG. 2, an equivalent circuit 10' for the attenuator 10 (FIG. 1) is shown to include a first parallel combination of resistors R_1L and R_1H and a switch S₁ which selects a path betweeninput transmission line 19a, and the switch S₁ through one of such resistors R_1L, R_1H. The parallel combination of R_1L, R_1H, and the switch S₁ here represents the equivalent circuit ofFET 14a and is connected in series with a switch S₂ which selects a path between the switch S₂ and one resistor of a second parallel combination of resistors R_2L and R_2H. The switch S₂ and the parallel combination of resistors R_2L, R_2H here represents the equivalent circuit ofFET 14b. In a preferred embodiment of the invention, R_1L =R_2L and R_1H =R_2H. A third parallel combination of resistors R_3L and R_3H and a series connected switch S₃ here representingFET 14c is coupled in shunt with the interconnection of the switches S₁ and S₂, as shown. Resistors R_1L, R_2L, R_3L here represent the value of the low state or unpinched channel resistance of thecorresponding FETS 14a-14c (FIG. 1), whereas, resistors R_1H, R_2H, R_3H here represent the value of pinched-off or high state value of channel resistance forFETS 14a-14c in accordance with the invention, and switches S₁ -S₃ here represent the switch states of theFETS 14a-14c, respectively. In response to control signals from bias control means 21 (FIG. 1) fed togate electrodes 15a-15c of FETS 14a-14c (FIG. 1), the value of channel resistance of eachFET 14a-14c is selectively changed between the high state and the low state in accordance with the level of the signal. Therefore, as shown in FIG. 2, switches S₁ -S₃ here represent the switching action of thefield effect transistors 14a-14c, changing the value of channel resistance between R_1L -R_3L and R_1H -R_3H, in accordance with the voltage level of such control signals. In a preferred embodiment of the invention, FETS 14a, 14b and 14c are designed to provide values of resistance in the pinched-off state and the on-state, so that the selected combination of such channel resistances will provide selected predetermined values of attenuation for the attenuator 10 (FIG. 1) and will provide values of input and output impedance substantially equal to a predetermined characteristic impedance value. Preferably, the input and output impedances of theattenuator 10 are equal to the characteristic impedances of the input and output r.f.transmission lines 19a, 19d, respectively. Suffice it here to say that each one of the values of channel resistance of each FET are selected to provide in combination such predetermined value of input impedance in a manner to be described.

Referring now to FIG. 2A, a simplified equivalent circuit of attenuator 10 (FIG. 1) is shown as a conventional T-section attenuator network 10" having branch resistor values R₁, R₂ and a shunt resistor R₃. It is to be noted that other attenuation networks such as a π-section network or a ladder network may also be used with the invention. Further, a multi-bit programmable attenuator having a plurality of FET's in each branch and shunt arm may be fabricated using the invention. Resistors R₁ -R₃ here represent channel resistances ofFETS 14a-14c in each one of the selected states forsuch FETS 14a-14c. Here, in operation, the control signal is applied to thegate electrodes 15a, 15b ofFETS 14a, 14b respectively and the complement of such signal is applied to thegate electrode 15c ofFET 14c to switch said FETS in response to such signals to the selected channel resistance represented by resistor values R_1L or R_1H, R_2L or R_2H, and R_3H or R_3L in accordance with the voltage level of the signals applied to thegate electrodes 15a-15c. Resistance values R_1L, R_1H, R_2L, R_2H, R_3L, R_3H are here selected such that any predetermined combination of such resistance values provides an input impedance Z_in of theattenuator 10, here preferably equal to Z_o, the characteristic impedance of the radiofrequency transmission lines 19a, 19d. With these constraints, the input impedance Z_in of the simplified equivalent circuit (FIG. 2A) is given as:

Z.sub.in =(R.sub.1.sup.2 +2R.sub.1 R.sub.3).sup.1/2        Equation (1)

Further, since the network is symmetrical, the output impedance Z_out is likewise given by (R₂² +2 R₂ R₃)¹⁷⁸ where R₁ =R₂.

In a similar manner, a loop analysis of the simplified equivalent circuit of FIG. 2A will provide the following equation for the power attenuation factor for the condition Z_in =Z_o :

A=P.sub.in /P.sub.o =(R.sub.1 +R.sub.3 +Z.sub.o /R.sub.3).sup.2 Equation (2)

Using the constraints that the input impedance equals the characteristic impedance, and the attenuation factor is related to the characteristic impedance, the values for resistors R₁, R₂ and R₃ can be shown to be equal to:

R.sub.1 =Z.sub.o ((A).sup.1/2 -1)/((A).sup.1/2 +1) and     Equation (3)

R.sub.3 =2 Z.sub.o (A).sup.1/2 /(A-1)                      Equation (4)

R.sub.1 =R.sub.2 Equation (5)

              TABLE 1                                                     ______________________________________                                    Z.sub.o = 50 ohms                                                         (values given are in ohms)                                                                                       Z.sub.o                            A (Eq. 1)  R.sub.1 (Eq. 3)                                                                     R.sub.2 (Eq. 3)                                                                     R.sub.3 (Eq. 4)                                                                   (Eq. 2)                            ______________________________________RXL  2 db (1.58)                                                                          5.7 (R.sub.1L)                                                                      5.7 (R.sub.2L)                                                                    47 (R.sub.3H)                                                                    49.9                             RXH  8 db (6.3)                                                                          21.5 (R.sub.1H)                                                                     21.5 (R.sub.2H)                                                                   215 (R.sub.3L)                                                                    49.7                             ______________________________________

As an example, as shown in Table I, for selected values of attenuation, and the selected value of characteristic impedance Z_o, the values for R₁, R₂ and R₃ of the equivalent circuit shown in FIG. 2A are calculated for each attenuationstate using equations 3, 4 and 5.

Referring now to FIG. 3, thedigital attenuator circuit 10 is shown formed as a monolithic circuit on asubstrate 30, here of semi-insulating gallium arsenide having on a bottom surface thereof aconductive ground plane 32, here of plated gold. On a surface ofsubstrate 30 opposite theground plane conductor 32 are formed active regions (not shown) wherein are formedFETS 14a, 14b, 14c (FIG. 1).FETS 14a-14c here each include a plurality of channel regions C_x (FIGS. 4A, 5), said channels including gate regions G_x disposed between pairs of source (S) and drain (D) regions.Capacitors 12a-12b are conventionally fabricated parallel plate capacitors having a bottom plate (not shown) coupled to the ground plane by viaholes 12a', 12b'.Conductive bonding pads 15a, 15b are provided for connection to bias control means 21 (FIG. 1). On thesemi-insulating substrate 30 are providedstrip conductors 19a'-19d' and 13a'-13c' for respective ones oftransmission lines 19a-19d and 13a-13c (FIG. 1). Thus, here microstrip transmission lines are provided by a combination of the aforementioned strip conductors,semi-insulating substrate 30 andground plane conductor 32. Further,conventional overlay metallizations 19a"-19d" and 19b" are provided to interconnect like ones of drain and source electrodes of eachFET 14a-14c, as shown.

Referring now to FIGS. 4 and 4A,FET 14a, also representative ofFET 14b, is shown to include a mesa-shaped active region 34a, contact region 36a, a plurality ofrecesses 35 in contact region 36a exposing underlying portions of active layer 34a, and a plurality of channel regions C₁ -C₁₀ disposed in active region 36a between pairs of drain D and source S electrodes and underlying corresponding ones of gate fingers G₁ -G₁₀. Gate fingers G₁ -G₈ are connected to a gate pad 35a (representative ofgate electrode 15a, FIG. 1). Gate pad 35a is connected to the resistor R_a, and is adapted to receive a control signal from control means 21 at bias point V₁ (FIG. 1). Gate fingers G₉, G₁₀ are connected to gate pad 35a' here spaced from gate pad 35a by achannel 40 provided between said gate pads 35a and 35a'. Further as shown in FIG. 4, gate finger G₈ covers a portion of the active region thereunder between respective drain and source contacts. In this manner,field effect transistor 14a is designed to have a selected value of resistance R_1H when a voltage signal is applied to gate pad 35a to pinch-off each of the drain source channel regions C₁ -C₁₀. As is known in the art, when a conventional depletion mode field effect transistor, for example, is supplied with a voltage sufficient to cause pinch-off of the channel, a very high channel impedance, typically in the range of thousands of ohms is provided. Here, in order to provide an attenuator having the desired degree of attenuation values and values of resistance to provide in combination a predetermined input impedance preferably equal to the impedance of the radio frequency transmission lines, thefield effect transistor 14a, for example, is designed to have a selected value of channel resistance R_1L when the field effect transistor is in the "on state" and a selected value of channel resistance R_1H when the field effect transistor is in the pinch-off state. TheFET 14a further includes conventional drain andsource overlay metallization 19a"-19b" used to interconnect corresponding ones of drain (D) and source (S) electrodes, as shown.

Referring to FIG. 5,FET 14c is here a dual gate FET having gate finger pairs G_1a, G_1b, G_2a, G_2b, G_3a, G_3b and G_4a, G_4b. Resistors R_c1 -R_c5 are provided in combination with the pairs of dual gates to increase the isolation between gate and drain electrodes and to increase current limiting and the drain-gate breakdown voltage. Gate pairs G_1a, G_1b, G_2a, G_2b, G_3a, G_3b and G_4a, G_4b are connected to a gate pad 35c (FIG. 3, representative ofgate electrode 15c, FIG. 1) through resistors R_c1 -R_c5, as shown. Source electrodes (S) ofFET 14c are connected to asource pad 39c which is connected to ground through a viahole 39c'.

In operation, a two level voltage signal having a first level sufficient to pinch-off the channel is fed to gate electrode pad 35a. Such voltage signal is distributed to gate electrode fingers G₁ -G₈ disposed between adjacently spaced source and drain electrodes to pinch-off the corresponding source-drain channels C₁ -C₈ of each one of the corresponding FET cells. Thus, such channels C₁ -C₈ disposed under the connected gate fingers G₁ -G₈ will be placed in a pinch-off state. However, since the pinch-off voltage signal is not fed to the portion of the gate pad 35a' spaced bychannel 40 from gate pad 35a, such signal therefore is not distributed to channels C₉, C₁₀ underlying gate fingers G₉, G₁₀. Further, that portion of the channel C₈ isolated from gate finger G₈ is in a like manner not pinched-off. Thus, the source-drain channel underlying gate fingers G₉, G₁₀ will not be placed in a pinch-off state and will present an impedance equal to the "on-state" channel resistance of such channel, and the gate finger G₈ disposed on a portion of the total channel C₉ width will provide a lower channel resistance in the pinch-off state than those channels C₁ -C₈ having a complete gate finger disposed thereon. Since the channels are coupled in parallel, the total resistance of the field effect transistor between thedrain electrode 16a and source electrode 17a when a pinch-off voltage level signal is applied to the gate electrode will be selectively lower than conventional field effect transistors wherein all gate fingers G₁ -G₁₀, for example, would be fed a voltage level signal to place each one of the channels thereof in a pinch-off state.

A generalized equation for finding the equivalent resistance (R_1H) in pinch-off for the field effect transistor such as that shown in FIG. 4 having n channels, with m channels and portions thereof isolated from the gate pad 35a, having a selected on-state channel resistance equal to R_o ohms per channel, and a selected pinch-off channel resistance of R_p ohms per channel is given as:

1/R.sub.1H =m/R.sub.0 +(1/(R.sub.p /(n-m)))                (Equation 6)

As a design example, theFET 14a is selected to have a predetermined resistance gate periphery characteristic. Here, FET's 14a, 14b are each selected to have a resistance-gate periphery characteristic equal to R_XL =3.5 ohm-mm in the on-state (state where no pinch-off voltage is applied), and a resistance-width characteristic equal to R_XH =2.0 K ohm-mm in the off-state (state where a pinch-off voltage is applied).

Selecting theFET 14a to have 10 cells, then each unit cell will have a unit cell width w_o given by w_o =1 mm/n=1 mm/10=100 μm. Further, each cell will have a unit cell on-state resistance (r_o) given by R_XL /w_o =3.5 ohm-mm/(100 μm/cell)= 35 ohms and a unit off-state (pinch-off) channel resistance given by R_XH /w_o =2.0K ohms-mm/100 μm/cell=20 K ohms.

The required gate periphery G_p for each ofFETS 14a, 14b is determined by the desired value of on-state channel resistance (R_1L) in accordance with the following equation R_XL /R_1L =G_p where G_p equals the total gate periphery. In the present example, G_p is given as:

G.sub.p =R.sub.XL /R.sub.1L =3.5 ohm-mm/5.7 ohm=0.614 mm.

Having found the required total gate periphery (G_p) forFET 14a, such total gate periphery G_p is selectively partitioned into the plurality of (n) channels, each channel having a width W_c such that nW_c =G_p. In the present example, n=10 as selected above and W_c is thus given by:

W.sub.c =0.614 mm/10=0.0614 mm =61.4 μm.

Knowing unit channel resistance valves r_o and r_p, unit channel width w_o, and having determined the actual width W_c =61.4 μm for each one of the channels C₁ -C₁₀ ofFETS 14a, 14b, scaled resistance values per channel (R_o, R_p) for theFETS 14a, 14b having a 3.5 ohm-mm characteristic, with each cell having a width of 61.4 μm, are determined as follows:

w.sub.o r.sub.o /W.sub.c =R.sub.o =(100 μm)(35 ohms)/61.4 μm=57.0 ohms

w.sub.o r.sub.p /W.sub.c =R.sub.p =(100 μm)(20K ohms)/61.4μm=32.5K ohms

Thus, having determined R_1H from equation 3, the FET resistance in the pinch-off state, and having calculated R_o the resistance per channel ofFETS 14a, 14b in the on-state and R_p the pinch-off resistance per channel ofFETS 14a, 14b in the pinch-off state, equation 6 can be solved for m to provide the number of channels required to be isolated from the gate pad 35a to provide the value of FET resistance R_1H as determined from equation 3 and given in Table 1. For the above example, solving equation 6 for m provides:

m=((R.sub.o R.sub.p /R.sub.XH)-R.sub.o n)/(R.sub.p -R.sub.o) or

for R.sub.p >R.sub.o n

m≃R.sub.o /R.sub.XH ≃57 ohms/21.5 ohms≃2.65

Therefore, as shown in FIG. 4, gate fingers G₉ and G₁₀ are isolated from gate pads 35a and 0.65×61.4 μm=40 μm of channel C₈ is isolated from gate pad 35a.

In a similar manner,FET 14c is designed. Here due to the relatively high on-state channel impedance R_1L, theFET 14c channel is selectively doped such that theFET 14c has a resistance-width characteristic R_XL =14.0 ohm-mm in the on-state and a resistance-width characteristic equal to R_XH =8K ohm-mm in the off-state (64.0 ohms per cell on-state and 32K ohms per cell off-state). The total gate periphery G_p is given by G_p =R_XL /R_3L =14 ohm-mm/47 ohms=0.280 mm. Having determined the total gate periphery, the number of cells can be selected to be an integral number, here 4 and the width of each one of said cells is then given as: W_c =280 μm/4 cells=75 μm/cell. Thus, in a similar manner, r_o =R_XL n and r_p =R_XH n or r_o =64 ohms per cell and r_o =R_XL n and r_p =R_XH n or r_o =64 ohms per cell and r_p =32K ohms per cell. Normalized or scaled valves R_o, R_p for 75 μm wide cells are determined for the 75 μm wide cells ofFET 14c in accordance with w_o (r_o)/W_c =R_o or 100 μm(64 ohms)/75 μm=85 ohms and w_o r_o /W_c =R_p =100 μm(32K ohms)/75 μm=43.7K ohms. Equation 6 is then solved for m to provide: m≃0.4. Therefore, as shown in FIG. 3, (0.4)(75 μm)=30 μm of channel C₁ ofFET 14c is isolated from gate pad 35c.

Having described preferred embodiments of the invention, it will now be apparent to one of skill in the art that other embodiments incorporating its concept may be used. It is felt, therefore, that this invention should not be restricted to the disclosed embodiments, but rather should be limited only by the spirit and scope of the appended claims.

Claims (4)

What is claimed is:

1. A radio frequency circuit having an input terminal and an output terminal comprising:

a pair of field effect transistors, each transistor having drain, source and gate electrodes, with a first one of such drain and source electrodes of a first one of such pair of transistors being electrically coupled to the input terminal, a first one of such drain and source electrodes of a second one of the pair of transistors being electrically coupled to the output terminal, and the remaining one of drain and source electrodes of each one of the pair of transistors being electrically coupled at a common point;

a third field effect transistor having a drain, source and gate electrodes with first one of such drain and source electrodes being electrically coupled with the aforementioned pair of transistors at the common point and the remaining one of such drain and source electrodes being electrically coupled to a reference potential;

each field effect transistor having at least one pair of drain and source contacts disposed on a corresponding pair of drain and source regions and coupled to respective ones of the drain and source electrodes, and at least one gate contact disposed on a corresponding gate region between said pair of drain and source contacts; and

wherein a selected portion of the gate region of each field effect transistor is physically separated from the gate contact having the gate electrode attached thereto.

2. The radio frequency circuit as recited in claim 1 wherein each gate region physically separated from the gate contact of each field effect transistor is selected to provide a predetermined resistance between corresponding source and drain electrodes in response to a signal fed to the corresponding gate electrode of each field effect transistor.

3. The radio frequency circuit as recited in claim 2 wherein the predetermined resistance between source and drain electrodes of each field effect transistor is selected to provide, in combination, a predetermined impedance at said input and output terminals.

4. The radio frequency circuit as recited in claim 3 wherein a first set of voltage level signals is fed to the corresponding gate electrode of each one of the field effect transistors providing a first set of resistance values between drain and source electrodes of each one of such field effect transistors, and in response thereto, an input signal fed to the input terminal of the circuit appears at the output terminal of the circuit having an amplitude related to the first set of resistance values between said source and drain electrodes, and wherein a second different set of voltage level signals is fed to the corresponding gate electrode of each one of the field effect transistors providing a second different set of resistance values between source and drain electrodes, and in response thereto, an input signal fed to the input terminal of the circuit appears at the output terminal of the circuit with a second different amplitude related to the values of the second different set of resistance values between source and drain electrodes.

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