US4055801A

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Publication number: US4055801A
Application number: US05/064,703
Authority: US
Inventors: Harold L. Pike; G. Lamar Thomas; Ronald L. Ketchum; John F. Evans
Original assignee: Individual
Current assignee: Individual
Priority date: 1970-08-18
Filing date: 1970-08-18
Publication date: 1977-10-25
Anticipated expiration: 1994-10-25
Also published as: FR2101335A5; CA941013A; GB1319349A; DE2061483C2; DE2061483A1

Abstract

A method and apparatus for the automatic testing of electronic equipment in which a general purpose digital computer is programmed for the equipment to be tested to generate appropriate stimulus waveforms for application to the equipment to be tested and for the measurement and evaluation of the waveforms responsively generated by the equipment tested. The computer directly controls the point-by-point generation of the analog stimulus waveforms by a plurality of analog to digital and analog to synchro converters, the application of the stimulus waveforms to selected leads of the unit to be tested, and the application of the response waveforms to a selected measurement circuit for conversion to digital form for subsequent evaluation by the computer against programmed standards.

Description

BACKGROUND OF THE INVENTION

The subject invention relates to the automatic testing of electronic equipment and more specifically to a method and apparatus for evaluating the performance of electronic equipment.

The prior art approach to the automatic testing of electronic equipment has generally utilized a general purpose digital computer programmed by means of punched cards, magnetic tape, or the like, with information relative to the selection of one of a plurality of waveform generators, the interconnections between the selected waveform generator and an output terminal to which the equipment to be tested is connected, and the selective interconnection of the output terminal to one of a plurality of evaluation circuits for evaluation of the waveforms generated in the electronic equipment in response to the application of the waveforms applied. Systems of this type are inherently limited by the number of different waveform or function generators and by the number of different evaluation circuits provided. As the electronic systems to be tested grow in complexity, the number of function generators and the number of evaluation circuits also increase, resulting in larger and larger, and correspondingly more expensive, test installations.

It is accordingly a primary object of the present invention to provide a novel method and apparatus for the automatic checkout, or testing, of electronic equipment which obviates the necessity for large numbers of function generators and evaluation circuits. This object is accomplished by programming a general purpose digital computer both for numeric waveform generation and for the evaluation of the response waveforms generated by the equipment tested.

A further object of the present invention is to provide a novel method and apparatus for the utilization of a general purpose digital computer to fully integrate all of the functional electronics in the automatic testing of electronic equipment.

It is another object of the present invention to provide a novel method and apparatus with infinite expansion possibilities both as to measurement and the stimulation of the equipment to be tested with a relatively small increase in test equipment, and which minimizes the expense of test labor costs through faster testing with fewer people.

It is yet another object of the present invention to provide a novel method and apparatus for utilizing a general purpose digital computer to control all system sequencing; signal interfacing; power application to the unit under test; control of peripheral components such as printers, memory and assorted display units; responsive waveform processing without special hardware; and the evaluation of the response waveforms against limits for the appropriate unit to be tested.

THE DRAWINGS

FIG. 1 is a functional block diagram of the overall system of the present invention;

FIG. 2 is a functional block diagram of the stimulus unit of FIG. 1;

FIG. 3 is a functional block diagram of the isolation circuit of the stimulus unit of FIG. 2;

FIG. 3 (A) is a timing diagram of the waveforms at various points in the block diagram of FIG. 3;

FIG. 4 is a functional block diagram of the controller of FIG. 2;

FIG. 5 is a schematic circuit diagram of the interface circuit of FIG. 4;

FIG. 6 is a functional block diagram of the digital to analog converter No. 1 (D/A 1) of FIG. 1;

FIG. 7 is a schematic circuit diagram of the switch logic of FIG. 6;

FIG. 8 is a functional block diagram of the digital to analog converter No. 2 (D/A 2) of FIG. 2;

FIG. 9 is a schematic circuit diagram of the digital to analog converters Nos. 3 and 4 (D/A3 and D/A 4) of FIG. 2;

FIG. 10 is a schematic circuit diagram of the digital to analog converter No. 5 (D/A 5) of FIG. 2;

FIG. 11 is a schematic circuit diagram of the digital to synchro converters Nos. 1 and 2 (D/S 1 and D/S 2) of FIG. 2;

FIG. 12 is a schematic circuit diagram of the octant selector and transformer of FIG. 11;

FIG. 13 is a functional block diagram of the evaluation circuit of FIG. 1;

FIG. 14 is a functional block diagram of the signal conditioning circuit of FIG. 13; and

FIG. 15 is a functional block diagram of the demodulator of FIG. 14.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

With reference now to FIG. 1, a general purposedigital computer 10 is provided with suitableconventional control unit 12 interconnected therewith to provide manual control of the programming of the computer and the computer as programmed. Thecontrol unit 12 may comprise keyboard apparatus and/or other conventional input mechanisms operable manually by an operator.

Also shown schematically in FIG. 1 is adisplay unit 14 adapted to receive the display data from thecomputer 10. The data displayed may relate to the operation of theunit 16 under test and/or the condition of the remaining units in the system. The individual units in the display section may comprise any suitable conventional display apparatus such as typewriters, status/alarm lights, pen recorders, or the like, and may be utilized to cue the operator in the use of thecontrol unit 12 in the operation of the system to test theunit 16.

Thecomputer 10 may be programmed in any suitable conventional manner such as by means of apertured cards, tapes, or the like in conformance with the particular piece of equipment to be tested. The test routine includes data relating to the waveforms to be generated by thestimulus unit 18, the routing of the generated stimulus signals through theswitching unit 20 to theunit 16 under test, the routing of the signals produced by theunit 16 to themeasurement unit 22, the acceptable limits of the signals to be evaluated, and the type of display to be produced.

To implement the system, thecomputer 10 is provided with anoutput bus 24 interconnected with thestimulus unit 18 hereinafter described in more detail in FIGS. 2-12, themeasurement unit 22 hereinafter described in more detail in FIGS. 13-15, and theswitching circuit 20. Theswitching circuit 20 may be any suitable conventional switching circuit, desirably solid state, which is operable under the control of thecomputer 10 to connect the output signals from thestimulus unit 18 to theunit 16 under test and the output signals from theunit 16 under test to themeasurement unit 22 for measurement purposes. Themeasurement unit 22 is directly connected to thecomputer 10 by way of aninput bus 26.

In the preferred mode of operation, the operator utilizes thecontrol unit 12 to cause thecomputer 10 to select the appropriate program for theunit 16 to be tested. The selection of the program will be displayed to the operator by thedisplay unit 14 for conformation and the computer then activated by the operator to begin the test routine of the program selected.

The program responsive signals from thecomputer 10 will be used to address and effect the operation of the various components of thestimulus unit 18 to cause the generation of the appropriate a.c. and d.c. signals to be applied through theswitching circuit 20 to theunit 16 under test. The response of theunit 16 under test is fed back through theswitching circuit 20 to themeasurement unit 22. The measured values are then applied to thecomputer 10 for evaluation in specific units thereof against the particular values dictated by the computer program. The results of the computer evaluation may be stored in the computer for subsequent display by thedisplay unit 14.

The operation of the various components of the system as preferably embodied is hereinafter explained in greater detail in accordance with the following Table of Contents:

TABLE OF CONTENTS

1. stimulus Unit (FIG. 2)

A. isolation (FIGS. 3 and 3(A))

B. controller (FIGS. 4 and 5)

C. d/a 1 (figs. 6 and 7)

D. d/a 2 (fig. 8)

e. d/as 3 and 4 (FIG. 9)

F. d/a 5 (fig. 10)

g. d/ss 1 and 2 (FIGS. 11 and 12)

2. Evaluation Unit (FIG. 13)

A. signal Conditioner (FIG. 14)

B. demodulator (FIG. 15)

C. operation (FIGS. 13, 14 and 15)

1. STIMULUS UNIT

With reference now to the block diagram of FIG. 2, the digital signals from thecomputer 10 are applied to aninput terminal 28 of thestimulus unit 18 of FIG. 1 where they are applied through anisolation circuit 30 to the

controllers

32 and 34 associated respectively with a pair of digital toanalog converters 36 and 38. These signals from the computer are also applied to the controllers 40-50 associated respectively with digital to analog controllers 52-56, and digital to synchro

converters

58 and 60.

The digital toanalog converters 36, 38 and 52-56 and the digital to synchro

converters

58 and 60 are each directly connected to an associated output terminal 66-78 which is, in turn, directly connected to the input terminals of the switchingcircuit 20 of FIG. 1. A d.c. and an a.c.

reference voltage generator

62 and 64, respectively, are provided and the input signal from the d.c.generator 62 is directly connected to aninput terminal 80 of the switchingcircuit 20. The output signal from the a.c.generator 64 is fed directly to anoutput terminal 82 of the switchingcircuit 20 and also through transformers 90-94 to output terminals 84-86 to provide the various a.c. signals hereinafter described.

The d.c.generator 62 may be any suitable commercial source of direct current and provides a regulated supply of 28 volt potential in the present embodiment.

The a.c.generator 64 may likewise be any suitable commercial source of alternating current and provides, in the preferred embodiment, a 115 volt signal at a frequency of 400 Hertz. The transformers 90-94 are conventional and are utilized to introduce appropriate relative phase shifts and to provide a three phase supply.

While not shown in FIG. 2, the d.c. and a.c.

generators

62 and 64 may be connected to theoutput box 24 of thecomputer 10 and provided with appropriate decoding logic circuitry so that thecomputer 10 may selectively control the energization thereof.

In operation, theisolation circuit 30 hereinafter more fully described in connection with FIG. 3 isolates the +5/0 volt signals from thecomputer 10 from the controllers associated with the digital toanalog converters 36 and 38. The controllers receive 10 bits of +5/0 volt value information as well as 6 bits of address information from the computer. The 10 value information bits are passed to the digital to analog converter to control the value of the analog output signal therefrom. The controller unit also receives both d.c. and a.c. reference input signals, selects the polarity thereof, and makes the reference signal available to the digital analog converter as appropriate under the direction of thecomputer 10. The

controller units

32, 34 and 40-46 for each of the digital toanalog converters 36, 38 and 52-56 are substantially identical and are the same as the

controllers

48 and 50 associated with the digital to synchro

converters

58 and 60.

A. ISOLATION

With reference now to FIG. 3, theisolation circuit 30 of thestimulus unit 18 illustrated in FIG. 2 comprises abi-phase transmitter 96 andreceiver 98. The direct current isolation achieved obviates the necessity for referencing both ends of thetransmission line 100 to ground potential.

As illustrated in FIG. 3, the transmitter comprises adecode unit 102, a storage register 104, aphase inverter 106 and apulse generator 108. Thedecode unit 102 is connected to receive a six-bit address word from theoutput bus 24 of thecomputer 10. Thedecode circuit 102 is conventional in its circuitry and operates, when properly addressed by thecomputer 10, to generate a signal online 109 which is utilized to enable the storage register 104.

The storage register 104 is also connected to theinput terminal 112 on thebus 24 and receives a four-bit address word and a sixteen-bit value word. As noted in FIG. 2, theisolation circuit 30 is utilized to isolate the

controllers

32 and 34 of the digital toanalog converters 36 and 38 from thecomputer 10output bus 24. The four-bit address word loaded into the storage register 104 is required to differentiate between the

controllers

32 and 34 of the two digital toanalog converters 36 and 38.

The circuitry and operation of the storage register 104 is conventional and will not be described in detail. The storage register 104, when enabled by thedecode circuit 102, provides twenty bits of serial data to thephase inverter 106 which receives the output signal from theconventional pulse generator 108. The pulses from thegenerator 108 may be any appropriate shape but conveniently each comprise a positive pulse followed by a negative pulse, as indicated in waveform (a) of FIG. 3 (A). The passage of a positive pulse followed by the negative pulse through thephase inverter 106 without a phase reversal or polarity inversion is utilized to indicate a binary logic ONE. The enabling of thephase inverter 106 to invert or phase reverse the signal from thegenerator 108 to produce a negative pulse followed by a positive pulse is utilized to indicate a binary logic ZERO. The exemplary waveforms are illustrated in FIG. 3 (A) wherein the output signal of thegenerator 108 is illustrated as waveform (a), the serial output signal of the storage register 104 is indicated as waveform (b), and the resultant output signal from thephase inverter 106 is illustrated as waveform (c).

The output of thephase inverter 106 is fed over theline 100 to thereceiver 98 which comprises aphase detector 110, apulse generator 112 and astorage register 114. Thephase detector 110,pulse generator 112 andstorage register 114 are all conventional in operation. Thedetector 110 is utilized to control the phase of the binary pulses generated by thegenerator 112 and serially loaded into thestorage register 114.Storage register 114 is utilized for reconverting the serial binary output signal from thepulse generator 112 to a parallel form for utilization by the

controllers

32 and 34 associated, respectively, with the digital toanalog converters 36 and 38 of FIG. 2. Appropriate and conventional timing circuits (not shown) are required to synchronize the clocking of the storage registers 104 and 114 with the

pulse generators

108 and 112. The output signal from thestorage register 114 constitutes the three-bit address word utilized to distinguish between the

controllers

32 and 34 as well as the sixteen-bit value word to be applied to the digital toanalog converters 36 or 38.

B. CONTROLLER

With reference now to the controller circuit illustrated in FIG. 4, the three-bit address word from theisolation circuit 30 of FIG. 6 (or the six-bit address word from thecomputer 10 when theoptional isolation circuit 30 is not utilized) are applied in parallel to suitable conventionaladdress logic circuitry 117 to provide an enabling signal over line 118 to astorage register 120 which receives the +5/0 volt binary signals, a 10 bit value word and a 6 bit control word. The circuitry and operation of thestorage register 120 is conventional and, when enabled, thestorage register 120 provides at its output terminals, a 6bit 5 volt word, a 1bit 5 volt control word utilized to control the operation of polarity switches 122 and 124, and a 1bit 5 volt control word utilized to control the operation of areference switch 126 whereby one of two reference signals are applied from the

output terminals

132 and 134 of suitable conventional sources (not shown) to the polarity switches 122 and 124. Ten bits of the 5 volt word are applied from thestorage register 120 to aninterface circuit 128, hereinafter described more completely in connection with FIG. 5, for conversion to 15 volt logic levels and application to output terminals collectively indicated at 130.

With continued reference to FIG. 4, the reference voltages applied to the

terminals

132 and 134 are selected by the program of thecomputer 10 as appropriate for the function which the digital to analog converters and digital to synchro converters of thestimulus unit 18 are to perform. Thereference switch 126 itself may be any suitable circuit for applying current through arelay coil 136 to effect control in a conventional manner over a switchingarm 138. Thecoil 136 of the relay may be paralleled by adiode 140 for transient suppression, if desired. Thereference switch 126 and associated relay may be replaced as desired by appropriate solid state switching.

The single bit polarity control word is applied from thestorage register 120 directly to one polarity switch 122 and through aconventional inverter 142 to the second polarity switch 124 so that the enabling of the two polarity switches 122 and 124 is mutually exclusive. With the application of a negative bit to the emitter electrode, NPN transistor Q1 saturates to ultimately control the operation of the fieldeffect transistor FET 1. The output signals from both of the polarity switches 122 and 124 are fed through an ORgate 144 to provide, onoutput terminal 146, the reference output signal utilized by the associated digital to analog or digital to synchro converter. The circuitry of the polarity switch 124 may be identical for that of the polarity switch 122 and exemplary values for the various circuit components are as follows:

______________________________________                                           Q1          EN 2222                                                       Q2          EN 2222                                                       Q3          EN 3502                                                       Q42N 2945A                                                      FET 1       U1 897E                                                       R1          20 K ohms                                                     R2          2.2 K ohms                                                    R3          8.2 K ohms                                                    R4          15 K ohms                                                     R5          100 Kohms                                                    R6          15 ohms                                                       R7          1000 K ohms                                                   D1          IN 4446                                                       D2          IN 4446                                                ______________________________________

The interface circuit of FIG. 4 is illustrated schematically in more detail in FIG. 5 and comprises a plurality of identical sectons, each energized by a positive 15 volt and a negative 15 volt direct current source (not shown). The +5/0 volt binary signals from thestorage register 120 of FIG. 4 are applied to therespective input terminals 148 associated one to each of the sections.

Each of the sections comprise transistors Q5, Q6 and Q7, a diode D4, and appropriate biasing resistors R8 - R11. The signal at thecorresponding output terminal 150 is a 15 volt logic binary signal and is effectively controlled by the 5 volt logic signal applied to thecorresponding input terminal 148. The removal of a positive signal from the emitter electrode of NPN transistor causes the successive conduction of transistors Q5, Q6 and Q7 to apply the +15 volt potential through the diode D4 and transistor Q7 to theoutput terminal 150. When the transistor Q7 is not conducting, the -15 volt potential is applied to theoutput terminal 150 through the resistor R11. The signals on theterminals 150 comprise the output signals from the collective terminal 130 (FIG. 4) of the

controllers

32, 34 and 40-50 to the digital to analog or digital to synchro converters, as appropriate.

Exemplary values for the various circuit components illustrated in FIG. 5 are as follows:

______________________________________                                           Q5           EN 2222                                                      Q6           EN 2222                                                      Q7           EN 3502                                                      D3           IN 4446                                                      R8           20 K ohms                                                    R9           2.2 K ohms                                                   R10          8.2 K ohms                                                   R11          100 K ohms                                            ______________________________________

The reference signals applied to the

input terminals

132 and 134 of the typical controller of FIG. 4 may differ with the digital to analog and digital to synchro converters, as will hereinafter be explained. These sources (not shown) of these reference signals are, however, conventional and selected as appropriate for the signal to be generated for application to the unit undertest 16.

C. DIGITAL TO ANALOG CONVERTER NO. 1

With reference to FIG. 6 where the digital to analog converter 36 (D/A 1) of FIG. 2 is illustrated in greater detail, the 10bit 15 volt value word from theoutput terminal 130 of thecontroller 32 of FIG. 4 is applied to aswitch logic circuit 152 which also receives a negative 5 volt direct current reference signal from thecontroller output terminal 146. As will be explained infra in connection with FIG. 7, the 10bit 15 volt value word is utilized to control the application of the negative 5 volt reference signal onterminal 146 to again control network 154. Thegain control network 154 may comprise a conventional resistance ladder network in which various resistors may be selectively switched into and out of the circuit and will not be hereinafter described.

The output signal from thegain control network 154 is a d.c. voltage which varies from 0 - 5 volts and which is applied to oneinput terminal 155 of thecomparator 156. The output terminal of thecomparator 156 is directly connected to a suitableelectronic switch 158 in the line 160 between a conventional 120 volt regulated d.c.power supply 162 and acapacitor 164. Aninductor 166 may, if desired, be added in series with thecapacitor 164 to suppress the transients normally associated with the operation of a switch.

Apotentiometer 168 connected in parallel across thecapacitor 164 may be utilized to pick off a feedback voltage which is applied to theother input terminal 170 of thedifferential amplifier 156.

The voltage accumulated on thecapacitor 164 is applied to theoutput terminal 66 of the digital to analog converter 36 either directly over aline 172 or through aconventional inverter 174 under the control of asuitable switch 176. Polarity control of the output signal may thus be achieved by control of theswitch 176 by asingle bit 5 volt control word derived from thecollective terminal 178 of the digital toanalog controller 32 of FIG. 4.

In operation, a 10 bit value word of 15 volt digital logic is received from thecontroller 32 on theinput terminal 130 is utilze to selectively control the application of the negative 5 volt reference signal from the terminal 146 to thegain control network 154, thereby establishing a voltage level related to the 10 bit word. This voltage level is applied to oneinput terminal 155 of thecomparator 156 which may comrpise a differential amplifier.

Assuming no voltage on thecapacitor 164, and thus no output signal appearing at theoutput terminal 66, thedifferential amplifier 156 will enable theswitch 158 effectively connecting the 120 volt d.c.power supply 162 to thecapacitor 164. As thecapacitor 164 charges from the 120volt power supply 162, a proportional potential is picked off thepotentiometer 168 and applied to theother input terminal 170 of thedifferential amplifier 156. Upon cancellation or equalization of the two voltages applied to the

input terminals

155 and 170 of thedifferential amplifier 156, the output signal from the differential amplifier will be lost, theswitch 158 disabled and the 120volt power supply 162 disconnected from thecapacitor 164. As dictated by thesingle bit 5 volt control word applied toterminal 178, the potential across thecapacitor 164 will be reflected with the proper polarity at theoutput terminal 66 of the digital to analog converter 36.

Theswitch logic circuit 152 of FIG. 6 may be of the type illustrated in FIG. 7 wherein only the first of ten identical sections is schematically illustrated. With reference now to FIG. 7, a bit of the 15 volt value word is applied to the appropriate one of theinput terminals 130 to control the operation of the PNP transistor Q8 and thus ultimately the operation of the fieldeffect transistor FET 2 from which the output signal for that section is taken. This output signal is applied by way of a terminal 178 to the resistance ladder of thegain control network 154 of FIG. 6.

Exemplary values for the various circuit components schematically illustrated in FIG. 7 are as follows:

______________________________________                                           Q82N 2945A                                                      FET 2       U1 897E                                                       D4          IN 4446                                                       D5          IN 4446                                                       R12         1000 K ohms                                                   R13         15 ohms                                                       R14         56 K ohms                                              ______________________________________

D. DIGITAL TO ANALOG CONVERTER NO. 2

The digital to analog converter 38 (D/A 2) of FIG. 2 is illustrated in more detail in FIG. 8. With reference to FIG. 8, a plus or minus 5 volt reference signal is applied to theinput terminal 146 from the like numbered output terminal of thecontroller 34 of FIG. 4 under the direction of thecomputer 10. This reference signal is passed through theswitch logic circuit 180 under the control of the 15volt 10 bit value word as passed through theinterface circuit 128 of FIG. 5. The output signals from theswitch logic circuit 180 are applied to the resistance ladder of thegain control network 182. Both theswitch logic 180 and gaincontrol networks 182 illustrated in block form in FIG. 8 may be identical to those circuits earlier described in connection with the digital toanalog converter 38 illustrated in FIG. 6.

The output signal from thegain control network 182 is thus a voltage level which changes incrementally with the changing of the 10 bit value word from thecomputer 10. This voltage level is passed by way of the normally closedcontacts 184 of amode control relay 186 through anamplifier 188 to avoltage output terminal 68. Theamplifier 188 is provided with mutually exclusive feedback paths through the normally closedcontacts 190 of arange relay 192 or the normallyopen contacts 194 of thesame range relay 192, whereby different values of resistance may be selectively utilized for signal attenuation.

Themode conrol relay 186 and therange control relay 192 may be of the type earlier described in connection with thereference switch relay 126 of the digital to analog controller of FIG. 4 and are operative under separatesingle bit 5 volt logic control words available from the controller of FIG. 4 on theoutput terminal 178.

Themode control relay 186 has twoadditional contacts 196 and 198 normally open in the voltage mode. Thecontacts 196 isolate theoutput terminal 200 of thegain control network 182 from ground potential and the contacts 198 isolate acurrent amplifier 202. When in the current mode, the closed contacts provide a current path through theamplifier 202 to thecurrent output terminal 68, theopen contacts 184 disconnect thevoltage amplifier 188 from the terminal 200, and theclosed contacts 196 ground theresistor 197 to establish a voltage source at terminal 200 from which current can be drawn.

E. DIGITAL TO ANALOG CONVERTERS NOS. 3 & 4

With reference to FIG. 9, where a typical circuit for both of the digital to

analog converters

52 and 54 is illustrated, a 2.5 volt, 400 Hertz a.c., or positive or negative 5 volt d.c., reference signal is selectively applied to aninput terminal 146 of theswitch logic circuit 204 under the control of theappropriate controller 42. The 10 bit, 15 volt digital value word available from theoutput terminal 130 of the controller of FIG. 4 controls the application of the appropriate reference signal from the terminal 146 to the resistance ladder of thegain control network 206 to produce an output signal onterminal 208.

This signal is amplified in anamplifier 210 and applied to a rangingcircuit 212. Theamplifier 210 is provided with a d.c. feedback path through the normallyopen contacts 214 of amode relay 216. A second and a.c. feedback path is provided through the normally closedcontacts 218 of thesame mode relay 216. Both the a.c. and d.c. feedback paths may contain two

resistors

220 and 222 of different values operably connected by means of the mutuallyexclusive contacts 224 and 226 of arange relay 228.

The output signal from theamplifier 210 may alternatively be passed through the normally closedcontacts 229 of thesame mode relay 216 to anoutput terminal 230 to provide a 0-5 volt a.c. suppressed carrier, or through the normallyopen contacts 232 of thesame mode relay 216 directly to the 0-1/0-10 volt d.c.output terminal 234. This signal is applied alternatively through the normally closedcontacts 236 to the 0-1/0-10 volt a.c.output terminal 238 on the secondary winding of an output transformer or through the normallyopen contacts 240 of the same relay to the 0.10/0.100 volt a.c.output terminal 242 on a different secondary winding of the transformer. Aninput terminal 244 and two

switch contacts

246 and 248 of asecond mode relay 219 provide the return signal path. The

output terminals

230, 234, 238 and 242 are illustrated collectively as the

output terminals

70 and 72, respectively, of the digital to

analog converters

52 and 54 of FIG. 2.

The operation of the d.c.range switch 250, the mode switch 252 and the a.c.range switch 254 are each individually controlled by asingle bit 5 volt control word available from theoutput terminal 178 of the

controller

40 or 42 of FIG. 4.

F. DIGITAL TO ANALOG CONVERTER NO. 5.

As indicated in the stimulus section of FIG. 2, the digital to analog converter No. 5 is provided with two

controllers

44 and 46. As indicated in FIG. 10, the purpose of the additional controller is to duplicate the switching logic and gain control networks with the addition of a phase shifter so that the single ranging circuit may receive both in-phase and quadrature signal components.

With reference to FIG. 10, theswitch logic 256 receives the 10bit 15 volt value word from theoutput terminal 130 of thecontroller 46 and a 400 Hertz, 2.5 volt reference signal from theoutput terminal 146 of the same controller. The output signals from theswitch logic circuit 256 are applied through thegain control network 258 to anoutput terminal 260.

The 10bit 15 volt value control word from theterminal 130 of thecontroller 44 of FIG. 2 is applied in parallel to theswitch logic circuit 262. A 400 Hertz, 2.5 volt reference signal is applied from theoutput terminal 146 of thecontroller 44 through aphase shift circuit 266 to the switchinglogic circuit 262. The output signals from the switchinglogic circuit 262 are applied to the gain control network 264 to produce an output signal which is displaced in phase by 90° from the signal from thegain control network 258. This signal is applied to the terminal 260 for combination with the in-phase output signal of thegain control network 258.

The combined signals are applied to a ranging circuit 268 to produce on the output terminals 270-276, respectively, a 0-0.5/0-5 volt a1c. signal, 0-1/0-10 volt d.c. signal, 0-1/0-10 volt a.c. signal, and 0-10/0-100 volt a.c. signal, all variable in phase.

The switching

logic circuits

256 and 262 are identical in circuitry and operation to the switching

logic circuits

180 and 204 earlier described. Likewise, thegain control networks 258 and 264 are identical in circuitry and operation to the

gain control networks

206 and 182 earlier described. The ranging circuit 268 is identical to the rangingcircuit 212 of the digital toanalog converters 3 and 4 illustrated in FIG. 9 and receives from theoutput terminal 178 of one of the

controllers

44 or 46 three single bit control words fro the d.c. range switch, the mode switch and the a.c. range switch described in connection with FIG. 9.

In operation, the quadrature signals combine in amplitude to produce an a.c. signal having a phase related to the then current value word provided by the program of thecomputer 10. The ranging circuit is operative to provide the various ranges desired.

G. DIGITAL TO SYNCHRO CONVERTERS NOS. 1 & 2

The two digital to synchro

converters

58 and 60 illustrated in block form in FIG. 2 are identical in circuitry and operation and are illustrated in more detail in FIGS. 11 and 12.

With reference now to FIG. 11, a 7bit 15 volt control word is supplied from theoutput terminal 130 of the associated

controller

48 or 50 of FIG. 4 simultaneously to the switching

logic circuits

278 and 280. The remaining three bits of the ten value bits available at the terminal 130 are applied to theinput terminal 283 of theoctant selector 282 subsequently to be described in more detail in connection with FIG. 12.

A 400 Hertz 2.5 volt rms reference signal is applied from theoutput terminal 146 of the appropriate controller through one of the normally open contacts 284 - 290 and the resistors 292 - 298 respectively associated therewith via aconventional amplifier 300 to the switchinglogic circuit 278. The reference signal from theterminal 146 of FIG. 4 is also applied through one of the normally open contacts 302 - 306 and the resistors 308 - 312 respectively associated the rewith via aconventional amplifier 314 to the switchinglogic circuit 280.

The switching

logic circuits

278 and 280 are identical to those earlier described with the exception that only seven of the ten sections are utilized. The output signals from the switching

logic circuits

278 and 280 control, respectively, the operation of the

gain control networks

316 and 318 in the manner earlier described in connection with the digital toanalog converters 36, 38 and 52 - 56.

The output signal from thegain control network 318 is combined with the output signal from theamplifier 300, amplified in aconventional amplifier 320 and applied as a cos θ signal to aninput terminal 322 of theoctant selector 282. The output signal from theamplifier 320 is also applied as a negative cos θ signal to aninput terminal 324 of theoctant selector 282 by way of aconventional inverter 326.

A 2 bit, 5/0 volt, control word from theoutput terminal 178 of FIG. 4 is applied to a suitableconventional logic circuit 344 which controls the operation of the previously mentioned relay contacts 302 - 306, 284 - 290, 328 and 336. In addition, thelogic circuit 344 controls the operation of normallyopen contacts 346 which are effective, when closed, to ground the input terminal of theamplifier 330, thereby effecting a sin θ = -sin θ = zero signal at theinput terminal 332 of theoctant selector 282.

One additional bit of the 5/0 volt signals from theoutput terminal 178 of the controller of FIG. 4 is applied by way of a line 348 to aninput terminal 350 of theoctant selector 282. Theoctant selector 282 is connected by a way of

terminals

352 and 354 to atransformer 356 having three output terminals 358 - 362 as will be described in more detail in connection with FIG. 12.

With reference now to FIG. 12, the positive and negative sin θ and cos θ signals from the like numbered terminals of FIG. 11 are applied respectively to the

input terminals

332, 342, 322 and 324 of theoctant selector 284 in digital to synchroconverter 60 of FIG. 2. The same four signals are derived from a circuit identical to that illustrated in FIG. 11 and are applied to like numbered terminals of theoctant selector 282 associated with digital to synchroconverter 58 of FIG. 2. Also applied to the

octant selectors

282 and 284 from the

respective controllers

48 and 50 is the 3 bit, 15 volt, octant switch control word from theoutput terminal 350, and the 1 bit, 5/0 volt, range switch control word from the terminal 283. The 1 bit, 5/0 volt and 3 bit, 15 volt control words are applied, respectively, to a suitable conventional octantswitch logic circuit 366 and rangeswitch logic circuit 368 which operate to effect control of the switch contacts to be described infra.

With reference to theoctant selectro 284 associated with the digital to synchro converter 53, and with continued reference to FIG. 12, the positive and negative sin θ and cos θ signals are applied by way of normally open contacts 370 - 376 of the octantselector switch logic 366 to anamplifier 378. The output signal from theamplifier 378 is applied to theinput terminal 354 of thetransformer 356 of FIG. 11. Theamplifier 378 is also provided with a pair of feedback paths including different resistance values and normally

closed relay contacts

380 and 382 and normallyopen contact 384 associated with previously mentioned rangeswitch logic circuit 368.

The positive and negative sin θ and cos θ signals from the

terminals

332, 342, 322 and 324 are also applied by way of normally open relay contacts 386 - 392 and the resistors associated therewith to the input terminal of anamplifier 394 whose output terminal is connected to theother input terminal 352 of thetransformer 356 of FIG. 11. Theamplifier 394 is also provided with two feedback paths containing different resistive values for range attenuation purposes. The feedback paths contain normally

closed relay contacts

396 and 398 and normallyopen contacts 400 associated with the rangeswitch logic circuit 368 earlier described.

Thetransformer 356 of FIG. 11 includes four separate windings in the digital to synchroconverter 60 of FIG. 2. These windings have different numbers of turns and are selectively connected to the

input terminals

352 and 354 by way of switch contacts 402 - 408 associated with the rangeswitch logic circuit 368. The output windings of theScot T transformer 356 are likewise connected by way of switch contacts 410 - 416 responsive to the rangeswitch logic circuit 368 to alternatively provide a 11.8 volt or 90 volt line-to-line maximum 3-wire synchro signal on the output terminals 358 - 362.

As previously mentioned, theoctant selector 282 associated with the digital to synchroconverter 60 is identical to that associated with thedigital synchro converter 58. However, thetransformer 356 of the digital to synchroconverter 60 contains only two windings and the 3-wire synchro output signals therefrom on the terminals 357 - 359 are 11.8 volts or 13.2 volts, as determined by the range switch logic of the associatedoctant selector 282.

In operation, and with reference to FIG. 11, the switch contacts 284 - 290, 302 - 306 and 336 are operated in pairs and correspond to angles of 0°,11.25°, 22.5° and 33.75°. The 400 Hertz, 2.5 volt rms reference signal on the terminal 146 is fed through the

switch logic circuits

278 and 280 to the resistance ladder network of the

gain control networks

316 and 318. The sin θ signal is fed back via line 334 where it is summed in theamplifier 314 with the reference signal, and this combined signal is combined in theamplifier 330 with the gain adjusted output signal of theamplifier 300. The output signal of theamplifier 314 is also modified in amplitude and combined with the output signal from theamplifier 300 to produce the cos θ signal.

The sin θ and cos θ are thus signals related in amplitude to the value of the sine and cosign of the phase angle θ. The relative amplitudes of the three phases of the output signal of thetransformer 356 are indicative of the desired angle and the switches of the

switch logic circuit

278 and 280 provide a least increment of 5.25 minutes.

These signals are fed to the octant selector of FIG. 12 where the octant is selected by the 3 bit word applied to the octantswitch logic circuit 366 and the desired range determined by the 1 bit control word applied to the rangeswitch logic circuit 368.

2. MEASUREMENT UNIT

As earlier described in connection with FIG. 1, themeasurement unit 22 receives signals from thecomputer 10 indicative of the particular circuit to be applied the signals generated by theunit 16 under test and supplied to themeasurement unit 22 by the switchingcircuit 20. The results of this measurement are fed to thecomputer 10 via theinput bus 26 to be subsequently evaluated and displayed to the operator by thedisplay unit 14. Themeasurement unit 22 of FIG. 1 is illustrated in greater detail in FIG. 13.

With reference now to FIG. 13, themeasurement unit 22 receives the analog signals generated by theunit 16 under test together with a 400 Hertz reference signal from the switchingcircuit 20 on aninput terminal 420 and receives the digital signals from thecomputer 10 over theoutput bus 24. The signals from themeasurement unit 22 are applied to thecomputer 10 via anoutput terminal 422 directly connected to theinput bus 26 of thecomputer 10.

The digital signals from thecomputer 10 are applied in parallel to

appropriate decode circuits

424 and 426. Thedecode circuit 426 receives a 6 bit address word from thecomputer 10 together with a 2 bit control word of 5/0 volt signals. If properly addressed for a synchro input signal, thedecode circuit 426 passes the 2 bit control word to the synchro todigital converter 428 to control the operation thereof. The

decode circuits

424 and 426 may be conventional logic circuitry conventional in operation. The synchro todigital converter 428 may also be conventional and may be, for example, of the type available from Data Devices Company of 100 Tec Street, Hicksville, New york as Model ESDC-L-3.

The synchro signals applied from theunit 16 under test via the switchingcircuit 22 to the sunchro todigital converter 428 are adjusted in amplitude to an 11.8, 13.2 or 90 volt range for application to theinput bus 26 of thecomputer 10. The output signal from the synchro todigital converter 428 is a 6 bit, 5/0 volt word containing 14 value bits and 2 bits of range information.

Thedecode circuit 424 is supplied with a 6 bit, 5/0 volt, address word and a 6 bit, 5/0 volt control word. When properly addressed for other than a synchro input signal, thedecode circuit 424 produces a 6 bit control word for application to acontrol logic circuit 430. This 6 bit, 5/0 volt, control work contains a 2 bit word indicative of one of four ranges and a 4 bit control word indicative of the mode of operation, i.e., a.c., d.c., phase, resistance or current measurements. This 6 bit control word is applied to asignal conditioner circuit 432 which also receives a 400 Hertz reference signal from the switchingcircuit 20 together with the analog signal to be measured.

Thesignal conditioner 432 operates in a manner described infra in connection with FIGS. 14 and 15 to produce an analog output signal. This output signal from the signal conditioner circuit is applied to an analog todigital converter 434 which may be any suitable and conventional circuit such as the Series 2110 available from Datum, Inc., 170 East Liberty Street, Anaheim, California 92801, which operates at a 30 KHz sample rate to digitize the analog signal into a 16 bit, 5/0 volt, word acceptable to thecomputer 10. Eleven of the 16 bits are value information, 2 bits indicate range and 3 bits are indicative of mode. These signals are applied to thecomputer 10 over theinput bus 26 as earlier explained in connection with FIG. 1.

A. THE SIGNAL CONDITIONER

Thesignal conditioner circuit 432 of FIG. 13 is illustrated in greater detail in FIG. 14 wherein the 2 bit, 5/0 volt, range control word from thecontrol logic circuit 430 of FIG. 13 is applied to a suitably and conventionalrange control network 438 by way of aninput terminal 436. Therange control circuit 438 may comprise any resistance network, the attenuation of which is programmable.

Therange control circuit 438 also receives the analog signal to be measured from the terminal 420. The output signal from therange control circuit 438 is a 0 to 5 volt analog signal and is applied

With a continued reference to FIG. 14, three bits of the 4 bit mode control work are also applied from theterminal 436 of thecontrol logic circuit 430 of FIG. 13 to thedemodulator circuit 440. The 400 Hertz reference signal from the switchingcircuit 20 of FIG. 1 is applied by way of the terminal 420 to thedemodulator circuit 430 where measurements as to phase, suppressed carrier and unfiltered a.c. or d.c. are made in accordance with control word from thecontrol logic circuit 430 of FIG. 13.

The output signals from thedemodulator circuit 440 are fed through alow pass filter 444 to theterminal 446 of the analog todigital converter 434 of FIG. 13. Thelow pass filter 444, like thefilter 442, may be of the conventional Butterworth type, programmable, and desirably flat in its response to approximately 1 kilohertz. Aswitch 445 also receives a single bit of the 4 bit control word from thecontrol logic circuit 432 of FIG. 13 to control the energization thereof and the operation of

switch contacts

447 and 449. The output signal from thefilter 442 or thefilter 444, as appropriate, is applied directly to theinput terminal 446 of the analog todigital converter 434 of FIG. 13.

B. DEMODULATOR

Thedemodulator 440 of FIG. 14 is illustrated in greater detail in FIG. 15 wherein the 400 Hertz reference signal fromterminal 420 is applied to a suitable and conventionalsquare wave generator 448 which produces a 400 Hertz square wave output signal. This enabling square wave signal is applied to a pair of

polarity switches

452 and 454 which receive the 0 to 5 volt analog signal from theterminal 450 of therange control circuit 438 of FIG. 14. The output signal from the enabled one of the polarity switches 452 and 454 is applied to the input terminal of a conventionalvariable gain amplifier 456 whose output signal is applied to aterminal 458 of thelow pass filter 444 of FIG. 14.

Three bits of the 4 bit mode control word from thecontrol logic circuit 430 of FIG. 13 are applied by way ofterminal 436 to theamplifier 456 to control the gain thereof.

C. OPERATION

In operation, and assuming a d.c. input signal from theunit 16 under test via the switchingcircuit 22 of FIG. 1 on theterminal 420 of FIG. 13, this d.c. signal is adjusted in range and fed through theactive Butterworth filter 442 by way of theoutput terminal 446 of FIG. 14 and the analog todigital converter 434 of FIG. 13 to the terminal 422 on theinput bus 26 of thecomputer 10.

If a suppressed carrier a.c. signal is fed into the measurement unit via theinput terminal 420 of FIG. 13, the signal is amplified and applied to thedemodulator circuit 440 for measurement of 0.1 to 10 cycle modulation. The square wave output signal from thesquare wave generator 448 of FIG. 15 is effective to pass or to invert the 400 Hertz reference signal. If the input signal on the terminal 450 is in phase with the reference signal on the terminal 420, the output signal onterminal 458 will be a positive full wave rectified signal. If the input signal is 180° out of phase with the reference signal, the output signal on the terminal 458 will be a negative full wave rectified signal. Thefilter 444 is an active Butterworth filter flat in its frequency responseout to 10 cycles and having a 3 d.b. point at 20 cycles. If this filter is switched into the circuit by the control bits fromterminal 436 of FIG. 14, it will take out the 400 cycles and leave only the modulation, i.e., a suppressed carrier signal. The a.c. output signal from thefilter 444 is applied to thecomputer 10 where it is stored for a few cycles and in the rms or average or peak value, whichever is desired, computed.

To measure the phase shift of the 400 cycle signal, thecomputer 10 measures the received waveform using an in-phase reference, measures the waveform using a quadrature reference, and then performs the necessary calculations to obtain the tangent of the phase shift angle. If it is desired to measure the phase shift for the modulation frequency signals, i.e., from 0 to 10 cycles, thecomputer 10 generated waveforms are used as a reference and the time delay initiated by the beginning of the output signal to the beginning of the input signal measured to arrive at the phase shift.

To measure a 400 Hertz signal, the output signal from therange control circuit 438 is fed through thefilter 442 to the analog todigital converter 434 of FIG. 13 by way of the terminal 446. The analog todigital converter 434 tracks the analog input signal for several cycles in digital form. Thecomputer 10 of FIG. 1 receives the digital signals via the terminal 422 (FIG. 13) and the input bus 26 (FIG. 1), and computes the desired measurement value therefrom.

The present invention may thus be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The presently disclosed embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are, therefore, intended to be embraced therein.