US20240268099A1 - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor structure includes a semiconductor substrate, an isolation structure, and a conductive structure. The isolation structure is located on the semiconductor substrate. The isolation structure has a first top surface, a second top surface lower than the first top surface, and a lateral surface adjoining the first top surface and the second top surface. The conductive structure has a trench. The trench extends to the second top surface and the lateral surface of the isolation structure. The conductive structure surrounds the isolation structure. The conductive structure is in contact with the first top surface of the isolation structure. A sidewall of a lower portion of the conductive structure is in contact with the isolation structure and extends beyond the second top surface of the isolation structure.

Description

BACKGROUNDField of Invention
• The present disclosure relates to a semiconductor structure and a manufacturing method of the semiconductor structure.
Description of Related Art
• Generally speaking, a conductive electrode is located on a storage node contact (SNC) structure in a dynamic random access memory (DRAM) device to be electrically connected with the SNC structure. During the fabrication process of the conductive electrode, first of all, a conductive layer is deposited on the SNC structures of the DRAM device. Subsequently, a plurality of trenches are formed in the conductive layer, which divide the conductive layer into conductive electrodes respectively in contact with the SNC structures.
• Typically, the material of the conductive layer is tungsten. Hence, as the conductive layer is dry etched to form the trenches and the conductive electrodes, byproducts and polymers of tungsten are also produced in the trenches, which may induce shorting between the conductive electrodes.
SUMMARY
• One aspect of the present disclosure provides a semiconductor structure.
• According to some embodiments of the present disclosure, a semiconductor structure includes a semiconductor substrate, an isolation structure, and a conductive structure. The isolation structure is located on the semiconductor substrate. The isolation structure has a first top surface, a second top surface lower than the first top surface, and a lateral surface adjoining the first top surface and the second top surface. The conductive structure has a trench. The trench extends to the second top surface and the lateral surface of the isolation structure. The conductive structure surrounds the isolation structure. The conductive structure is in contact with the first top surface of the isolation structure. A sidewall of a lower portion of the conductive structure is in contact with the isolation structure and extends beyond the second top surface of the isolation structure.
• In some embodiments, the conductive structure further includes an upper portion located on the lower portion of the conductive structure and the first top surface of the isolation structure.
• In some embodiments, a distance between the lateral surface of the isolation structure and the sidewall of the lower portion of the conductive structure is less than a width of the trench surrounded by the upper portion of the conductive structure.
• In some embodiments, a sidewall of the upper portion of the conductive structure has a bottom concave surface adjoining the sidewall of the lower portion of the conductive structure.
• In some embodiments, a sidewall of the upper portion of the conductive structure has a bottom concave surface extending to the lateral surface of the isolation structure.
• In some embodiments, the semiconductor structure further includes a hard mask layer. The hard mask layer is located on the upper portion of the conductive structure.
• In some embodiments, the sidewall of the upper portion of the conductive structure has a top concave surface adjoining a top surface of the upper portion of the conductive structure.
• In some embodiments, the semiconductor structure further includes a hard mask layer. The hard mask layer is located on the upper portion of the conductive structure. The top concave surface of the sidewall of the upper portion of the conductive structure extends to a sidewall of the hard mask layer.
• In some embodiments, the first top surface, the lateral surface, and the second top surface of the isolation structure define a stepped surface.
• Another aspect of the present disclosure provides a manufacturing method of a semiconductor structure.
• According to some embodiments of the present disclosure, a manufacturing method of a semiconductor structure includes forming an isolation structure, a conductive structure surrounding and covering the isolation structure, and a hard mask layer on a semiconductor substrate sequentially, wherein the hard mask layer has an opening to expose the conductive structure; removing the exposed conductive structure to form a trench, such that a sidewall of an upper portion of the conductive structure has a bottom concave surface; forming a liner layer on the isolation structure, the sidewall of the upper portion of the conductive structure, and a sidewall and a top surface of the hard mask layer; removing a bottom portion of the liner layer to expose the isolation structure; removing the exposed isolation structure, such that the isolation structure has a first top surface covered by the conductive structure, a second top surface lower than the first top surface, and a lateral surface adjoining the first top surface and the second top surface, and the trench extends to the second top surface and the lateral surface of the isolation structure; and removing the liner layer to expose the sidewall of the upper portion of the conductive structure, and the sidewall and the top surface of the hard mask layer.
• In some embodiments, removing the bottom portion of the liner layer to expose the isolation structure further includes removing a byproduct layer on the isolation structure.
• In some embodiments, removing the exposed isolation structure is performed such that a sidewall of a lower portion of the conductive structure extends beyond the second top surface of the isolation structure.
• In some embodiments, removing the exposed isolation structure is performed by reactive-ion etching having selectivity between the isolation structure and each of the liner layer and the conductive structure.
• In some embodiments, forming the liner layer on the isolation structure, the sidewall of the upper portion of the conductive structure, and the sidewall and the top surface of the hard mask layer is performed by atomic layer deposition.
• Yet another aspect of the present disclosure provides a manufacturing method of a semiconductor structure.
• According to some embodiments of the present disclosure, a manufacturing method of a semiconductor structure includes forming an isolation structure, a conductive structure surrounding and covering the isolation structure, and a hard mask layer on a semiconductor substrate sequentially, wherein the hard mask layer has an opening to expose the conductive structure; forming a liner layer on a sidewall and a top surface of the hard mask layer and the exposed conductive structure; removing a bottom portion of the liner layer to expose the conductive structure; removing the conductive structure not covered by the hard mask layer and the liner layer to form a trench and expose the isolation structure, such that a sidewall of an upper portion of the conductive structure has a bottom concave surface; removing the exposed isolation structure, such that the isolation structure has a first top surface covered by the conductive structure, a second top surface lower than the first top surface, and a lateral surface adjoining the first top surface and the second top surface, and the trench extends to the second top surface and the lateral surface of the isolation structure; and removing the liner layer to expose the sidewall and the top surface of the hard mask layer.
• In some embodiments, forming the isolation structure, the conductive structure surrounding and covering the isolation structure, and the hard mask layer on the semiconductor substrate subsequently further includes removing the exposed conductive structure, such that the sidewall of the upper portion of the conductive structure further has a top concave surface extending to the sidewall of the hard mask layer.
• In some embodiments, forming the liner layer on the sidewall and the top surface of the hard mask layer and the exposed conductive structure is performed such that the liner layer is in contact with the top concave surface of the sidewall of the upper portion of the conductive structure.
• In some embodiments, removing the exposed isolation structure is performed such that a sidewall of a lower portion of the conductive structure extends beyond the second top surface of the isolation structure.
• In some embodiments, removing the conductive structure not covered by the hard mask layer and the liner layer to form the trench and expose the isolation structure is performed by reactive-ion etching having selectivity between the conductive structure and each of the liner layer and the isolation structure.
• In some embodiments, forming the liner layer on the sidewall and the top surface of the hard mask layer and the exposed conductive structure is performed by atomic layer deposition.
• In the aforementioned embodiments of the present disclosure, since the sidewall of the lower portion of the conductive structure of the semiconductor structure extends beyond the second top surface of the isolation structure, the cross-sectional area of the conductive structure adjacent to the first top surface of the isolation structure is increased compared with a traditional structure. As a result, the conductive structure is stronger, and the resistance of the conductive structure is reduced. The semiconductor structure may be applied in a dynamic random access memory (DRAM) device, and the conductive structure can act as an electrode of storage node contact (SNC) structure to reduce the resistance thereof. Furthermore, in the manufacturing method of the semiconductor structure, by forming the liner layer on the sidewall of the upper portion of the conductive structure and removing the bottom portion of the liner layer, byproducts and polymers of the conductive structure produced by a dry etching process can be prevented. Therefore, the manufacturing method of the semiconductor structure may be applied to fabricate DRAM device to avoid the shorting between electrodes of storage node contact (SNC) structures induced by the byproducts and the polymers.
BRIEF DESCRIPTION OF THE DRAWINGS
• Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
• FIG.1 is a cross-sectional view of a semiconductor structure according to one embodiment of the present disclosure.
• FIGS.2 to6 are cross-sectional views at intermediate stages of the manufacturing method of the semiconductor structure ofFIG.1.
• FIG.7 is a cross-sectional view of a semiconductor structure according to one embodiment of the present disclosure.
• FIGS.8 to11 are cross-sectional views at intermediate stages of the manufacturing method of the semiconductor structure ofFIG.7.
DETAILED DESCRIPTION
• The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
• Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
• FIG.1 is a cross-sectional view of asemiconductor structure100 according to one embodiment of the present disclosure. As shown inFIG.1, thesemiconductor structure100 includes asemiconductor substrate110, anisolation structure120, and aconductive structure130. Theisolation structure120 is located on thesemiconductor substrate110. Theisolation structure120 has a firsttop surface121, a secondtop surface122 lower than the firsttop surface121, and alateral surface123 adjoining the firsttop surface121 and the secondtop surface122. Theconductive structure130 has atrench131. Thetrench131 extends to the secondtop surface122 and thelateral surface123 of theisolation structure120. Hence, thetrench131 divides theconductive structure130 into two portions electrically insulated with each other. Theconductive structure130 surrounds theisolation structure120. Theconductive structure130 is in contact with the firsttop surface121 of theisolation structure120. Asidewall134 of alower portion132 of theconductive structure130 is in contact with theisolation structure120 and extends beyond the secondtop surface122 of theisolation structure120.
• In some embodiments, thesemiconductor structure100 is applied in a dynamic random access memory (DRAM) device. Thesemiconductor substrate110 may be a memory structure of the DRAM device. Theisolation structure120 may be in contact with a bit line (BL) structure of the DRAM device. Theconductive structure130 can act as an electrode of a storage node contact (SNC) structure of the DRAM device. Compared with the traditional designs of DRAM devices, since thesidewall134 of thelower portion132 of theconductive structure130 extends beyond the secondtop surface122 of theisolation structure120, the cross-sectional area of theconductive structure130 adjacent to the firsttop surface121 of theisolation structure120 is increased As a result, theconductive structure130 is stronger, and the resistance of theconductive structure130 is reduced. Therefore, the resistance of the storage node using theconductive structure130 as the electrode declines, which can save the energy consumption of the DRAM device. In some embodiments, a material of theisolation structure120 may include silicon nitride, and a material of theconductive structure130 may include tungsten, but the present disclosure is not limited in this regard.
• Moreover, theconductive structure130 of thesemiconductor structure100 further includes anupper portion133 located on thelower portion132 of theconductive structure130 and the firsttop surface121 of theisolation structure120. A distance D1 between thelateral surface123 of theisolation structure120 and thesidewall134 of thelower portion132 of theconductive structure130 is less than a width W of thetrench131 surrounded by theupper portion133 of theconductive structure130. In addition, the firsttop surface121, thelateral surface123, and the secondtop surface122 of theisolation structure120 define a stepped surface. Furthermore, asidewall135 of theupper portion133 of theconductive structure130 has a bottomconcave surface136 adjoining thesidewall134 of thelower portion132 of theconductive structure130, and asidewall137 of theupper portion133 of theconductive structure130 has a bottomconcave surface138 extending to thelateral surface123 of theisolation structure120. By the configuration of thetrench131, the bottomconcave surface136, and the bottomconcave surface138 of theconductive structure130, voids and defects of a material filled in thetrench131 can be prevented in subsequent manufacturing process.
• In this embodiment, thesemiconductor structure100 further includes ahard mask layer140. Thehard mask layer140 is located on theupper portion133 of theconductive structure130. Asidewall141 and asidewall142 of thehard mask layer140 respectively extend to thesidewall135 and thesidewall137 of theupper portion133 of theconductive structure130. In some embodiments, a material of thehard mask layer140 may include silicon nitride. Thehard mask layer140 can prevent the underlyingconductive structure130 and theunderlying isolation structure120 from etching.
• In the following description, the manufacturing method of thesemiconductor structure100 will be explained.
• FIGS.2 to6 are cross-sectional views at intermediate stages of the manufacturing method of thesemiconductor structure100 ofFIG.1. As shown inFIG.2, the manufacturing method of thesemiconductor structure100 includes forming theisolation structure120, theconductive structure130 surrounding and covering theisolation structure120, and thehard mask layer140 on asemiconductor substrate110 sequentially. Thehard mask layer140 may be patterned to has an opening O to expose theconductive structure130. In some embodiments, a portion of the exposedconductive structure130 is removed to form two topconcave surfaces139 and139′.
• As shown inFIG.3, thereafter, the exposedconductive structure130 may be removed to form thetrench131 by dry etching, such that thesidewall135 and thesidewall137 of theupper portion133 of theconductive structure130 respectively has the bottomconcave surface136 and the bottomconcave surface138. In this embodiment, the material of theconductive structure130 is tungsten, hence abyproduct layer160 is produced during the formation of thetrench131 in theconductive structure130, in which thebyproduct layer160 is located on theisolation structure120, and in contact with the bottomconcave surface136 and the bottomconcave surface138. In addition, because a material of thebyproduct layer160 may include tungsten, thesidewall135 and thesidewall137 of theupper portion133 of theconductive structure130 may be electrically connected with each other by thebyproduct layer160. In some embodiments, a thickness T2 (seeFIG.2) of thehard mask layer140 may be reduced to a thickness T1 after dry etching the exposedconductive structure130 to form thetrench131.
• As shown inFIGS.4 and5, thereafter, aliner layer150 may be formed on theisolation structure120, thesidewall135 and thesidewall137 of theupper portion133 of theconductive structure130, and thesidewall141, thesidewall142, and thetop surface143 of thehard mask layer140 by atomic layer deposition (ALD). Thebyproduct layer160 is located between theisolation structure120 and theliner layer150. Afterward, a bottom portion of theliner layer150 and thebyproduct layer160 on theisolation structure120 may be removed to expose theisolation structure120. In some embodiments, a material of theliner layer150 is oxide (e.g., silicon oxide), but the present disclosure is not limited in this regard.
• As shown inFIG.6, thereafter, the exposedisolation structure120 is removed by reactive-ion etching having selectivity between theisolation structure120 and each of theliner layer150 and theconductive structure130, such that theisolation structure120 has the firsttop surface121 covered by theconductive structure130, the secondtop surface122 lower than the firsttop surface121, and thelateral surface123 adjoining the firsttop surface121 and the secondtop surface122. The reactive-ion etching may lateral etch theconductive structure130 with obliquely incident plasma. Since theliner layer150 is formed on thesidewall135 and thesidewall137 of theupper portion133 of theconductive structure130, additional byproducts and polymers are not produced on thesidewalls135 and137 of theconductive structure130 during etching the exposedisolation structure120. Therefore, in some embodiments, theconductive structure130 can act as an electrode of a SNC structure of a DRAM device to avoid the shorting between electrodes induced by the byproducts and the polymers. In addition, a material of theisolation structure120 may include silicon nitride, a material of theconductive structure130 may include tungsten, and a material of theliner layer150 may include silicon oxide. The reactive-ion etching applied to remove theisolation structure120 exposed through thetrench131 has selectivity between the silicon nitride and each of the silicon oxide and tungsten.
• Afterward, theliner layer150 is removed to expose thesidewall135 and thesidewall137 of theupper portion133 of theconductive structure130, and thesidewall141, thesidewall142 and thetop surface143 of thehard mask layer140, thereby obtaining thesemiconductor structure100 ofFIG.1. Thereafter, an insulated structure may be filled in thetrench131. By the configuration of thetrench131 ofFIG.1, the voids and defects of the insulated structure in thetrench131 can be prevented. In some embodiments, a material of the insulated structure may include a nitride insulator (e.g., silicon nitride).
• It is to be noted that the connection relationships, the materials, and the advantages of the elements described above will not be repeated in the following description. In the following description, another type of a semiconductor structure will be described.
• FIG.7 is a cross-sectional view of asemiconductor structure100aaccording to one embodiment of the present disclosure. Thesemiconductor structure100aincludes thesemiconductor substrate110, theisolation structure120, theconductive structure130, and thehard mask layer140. The difference between this embodiment and the embodiment ofFIG.1 is that thesidewall135 and thesidewall137 of theupper portion133 of theconductive structure130 respectively has the topconcave surface139 and the topconcave surface139′. The topconcave surface139 of thesidewall135 of theupper portion133 of theconductive structure130 extends to thesidewall141 of thehard mask layer140, and the topconcave surface139′ of thesidewall137 of theupper portion133 of theconductive structure130 extends to thesidewall142 of thehard mask layer140. The width W of thetrench131 ofFIG.7 is smaller than the width W of thetrench131 ofFIG.1. Therefore, the cross-sectional area of theconductive structure130 ofFIG.7 is greater than theconductive structure130 ofFIG.1, and the resistance of theconductive structure130 may be further reduced. Furthermore, a distance D2 between thesidewall141 and thesidewall142 of thehard mask layer140 is greater than the width W of thetrench131 ofFIG.7.
• In the following description, the manufacturing method of thesemiconductor structure100awill be explained.
• FIGS.8 to11 are cross-sectional views at intermediate stages of the manufacturing method of thesemiconductor structure100aofFIG.7. As shown inFIG.8, after the structure ofFIG.2 is formed, theliner layer150 is formed on thesidewall141, thesidewall142 and thetop surface143 of thehard mask layer140, and the exposedconductive structure130. In addition, theliner layer150 is in contact with the topconcave surfaces139 and139′.
• As shown inFIGS.9 and10, afterwards, a bottom portion of theliner layer150 may be removed to expose theconductive structure130, such that theliner layer150 covers thesidewall141, thesidewall142 and thetop surface143 of thehard mask layer140. Thereafter, theconductive structure130 not covered by thehard mask layer140 and theliner layer150 may be removed by reactive-ion etching having selectivity between theconductive structure130 and each of theliner layer150 and theisolation structure120, such that thetrench131 can be formed to expose theisolation structure120. Since theliner layer150 covers thehard mask layer140, the thickness T2 of thehard mask layer140 is maintained after etching theconductive structure130. Moreover, the thickness T2 of thehard mask layer140 ofFIG.10 is greater than the thickness T1 of thehard mask layer140 ofFIG.3. Furthermore, the thickness T2 of thehard mask layer140 is thick enough to prevent thesidewall135 and thesidewall137 of theupper portion133 of theconductive structure130 from lateral etching with obliquely incident plasma, and hence avoid the production of byproducts and polymers.
• Furthermore, after etching theconductive structure130 not covered by thehard mask layer140 and theliner layer150, thesidewall135 and thesidewall137 of theupper portion133 of theconductive structure130 respectively has the topconcave surface139 and the topconcave surface139′. Theliner layer150 prevents the topconcave surface139 of thesidewall135 and the topconcave surface139′ of thesidewall137 from etching.
• As shown inFIGS.10 and11, thereafter, theisolation structure120 exposed through thetrench131 may be removed. Subsequently, theliner layer150 may be removed to obtain thesemiconductor structure100aofFIG.7.
• The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (20)

What is claimed is:

1. A semiconductor structure, comprising:

a semiconductor substrate;

an isolation structure located on the semiconductor substrate, wherein the isolation structure has a first top surface, a second top surface lower than the first top surface, and a lateral surface adjoining the first top surface and the second top surface; and

a conductive structure having a trench extending to the second top surface and the lateral surface of the isolation structure, wherein the conductive structure surrounds the isolation structure and is in contact with the first top surface of the isolation structure, and a sidewall of a lower portion of the conductive structure is in contact with the isolation structure and extends beyond the second top surface of the isolation structure.

2. The semiconductor structure ofclaim 1, the conductive structure further comprises an upper portion located on the lower portion of the conductive structure and the first top surface of the isolation structure.

3. The semiconductor structure ofclaim 2, wherein a distance between the lateral surface of the isolation structure and the sidewall of the lower portion of the conductive structure is less than a width of the trench surrounded by the upper portion of the conductive structure.

4. The semiconductor structure ofclaim 2, wherein a sidewall of the upper portion of the conductive structure has a bottom concave surface adjoining the sidewall of the lower portion of the conductive structure.

5. The semiconductor structure ofclaim 2, wherein a sidewall of the upper portion of the conductive structure further has a bottom concave surface extending to the lateral surface of the isolation structure.

6. The semiconductor structure ofclaim 5, further comprising:

a hard mask layer located on the upper portion of the conductive structure.

7. The semiconductor structure ofclaim 5, wherein the sidewall of the upper portion of the conductive structure further has a top concave surface adjoining a top surface of the upper portion of the conductive structure.

8. The semiconductor structure ofclaim 7, further comprising:

a hard mask layer located on the upper portion of the conductive structure, wherein the top concave surface of the sidewall of the upper portion of the conductive structure extends to a sidewall of the hard mask layer.

9. The semiconductor structure ofclaim 1, wherein the first top surface, the lateral surface, and the second top surface of the isolation structure define a stepped surface.

10. A manufacturing method of a semiconductor structure, comprising:

forming an isolation structure, a conductive structure surrounding and covering the isolation structure, and a hard mask layer on a semiconductor substrate sequentially, wherein the hard mask layer has an opening to expose the conductive structure;

removing the exposed conductive structure to form a trench, such that a sidewall of an upper portion of the conductive structure has a bottom concave surface;

forming a liner layer on the isolation structure, the sidewall of the upper portion of the conductive structure, and a sidewall and a top surface of the hard mask layer;

removing a bottom portion of the liner layer to expose the isolation structure;

removing the exposed isolation structure, such that the isolation structure has a first top surface covered by the conductive structure, a second top surface lower than the first top surface, and a lateral surface adjoining the first top surface and the second top surface, and the trench extends to the second top surface and the lateral surface of the isolation structure; and

removing the liner layer to expose the sidewall of the upper portion of the conductive structure, and the sidewall and the top surface of the hard mask layer.

11. The manufacturing method of the semiconductor structure ofclaim 10, wherein removing the bottom portion of the liner layer to expose the isolation structure further comprises:

removing a byproduct layer on the isolation structure.

12. The manufacturing method of the semiconductor structure ofclaim 10, wherein removing the exposed isolation structure is performed such that a sidewall of a lower portion of the conductive structure extends beyond the second top surface of the isolation structure.

13. The manufacturing method of the semiconductor structure ofclaim 10, wherein removing the exposed isolation structure is performed by reactive-ion etching having selectivity between the isolation structure and each of the liner layer and the conductive structure.

14. The manufacturing method of the semiconductor structure ofclaim 10, wherein forming the liner layer on the isolation structure, the sidewall of the upper portion of the conductive structure, and the sidewall and the top surface of the hard mask layer is performed by atomic layer deposition.

15. A manufacturing method of a semiconductor structure, comprising:

forming an isolation structure, a conductive structure surrounding and covering the isolation structure, and a hard mask layer on a semiconductor substrate sequentially, wherein the hard mask layer has an opening to expose the conductive structure;

forming a liner layer on a sidewall and a top surface of the hard mask layer and the exposed conductive structure;

removing a bottom portion of the liner layer to expose the conductive structure;

removing the conductive structure not covered by the hard mask layer and the liner layer to form a trench and expose the isolation structure, such that a sidewall of an upper portion of the conductive structure has a bottom concave surface;

removing the exposed isolation structure, such that the isolation structure has a first top surface covered by the conductive structure, a second top surface lower than the first top surface, and a lateral surface adjoining the first top surface and the second top surface, and the trench extends to the second top surface and the lateral surface of the isolation structure; and

removing the liner layer to expose the sidewall and the top surface of the hard mask layer.

16. The manufacturing method of the semiconductor structure ofclaim 15, wherein forming the isolation structure, the conductive structure surrounding and covering the isolation structure, and the hard mask layer on the semiconductor substrate subsequently further comprises:

removing the exposed conductive structure, such that the sidewall of the upper portion of the conductive structure further has a top concave surface extending to the sidewall of the hard mask layer.

17. The manufacturing method of the semiconductor structure ofclaim 16, wherein forming the liner layer on the sidewall and the top surface of the hard mask layer and the exposed conductive structure is performed such that the liner layer is in contact with the top concave surface of the sidewall of the upper portion of the conductive structure.

18. The manufacturing method of the semiconductor structure ofclaim 15, wherein removing the exposed isolation structure is performed such that a sidewall of a lower portion of the conductive structure extends beyond the second top surface of the isolation structure.

19. The manufacturing method of the semiconductor structure ofclaim 15, wherein removing the conductive structure not covered by the hard mask layer and the liner layer to form the trench and expose the isolation structure is performed by reactive-ion etching having selectivity between the conductive structure and each of the liner layer and the isolation structure.

20. The manufacturing method of the semiconductor structure ofclaim 15, wherein forming the liner layer on the sidewall and the top surface of the hard mask layer and the exposed conductive structure is performed by atomic layer deposition.

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