US20240020134A1 - Overflow detection and correction in state machine engines - Google Patents

Abstract

State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
• The present application is a continuation of U.S. application Ser. No. 17/328,701 entitled, “Overflow Detection and Correction in State Machine Engines,” and filed May 24, 2021, now U.S. Pat. No. 11,775,320 which issued on Oct. 3, 2023, which is a continuation of U.S. application Ser. No. 15/645,252, entitled, “Overflow Detection and Correction in State Machine Engines,” and filed Jul. 10, 2017, now U.S. Pat. No. 11,016,790 which issued on May 25, 2021, which is a continuation of U.S. application Ser. No. 13/838,637, entitled “Overflow Detection and Correction in State Machine Engines,” and filed Mar. 15, 2013, now U.S. Pat. No. 9,703,574 which issued on Jul. 11, 2017, the entirety of which is incorporated by reference herein for all purposes.
BACKGROUNDField of Invention
• Embodiments of the invention relate generally to electronic devices and, more specifically, in certain embodiments, to electronic devices with parallel devices for data analysis.
Description of Related Art
• Complex pattern recognition can be inefficient to perform on a conventional von Neumann based computer. A biological brain, in particular a human brain, however, is adept at performing pattern recognition. Current research suggests that a human brain performs pattern recognition using a series of hierarchically organized neuron layers in the neocortex. Neurons in the lower layers of the hierarchy analyze “raw signals” from, for example, sensory organs, while neurons in higher layers analyze signal outputs from neurons in the lower levels. This hierarchical system in the neocortex, possibly in combination with other areas of the brain, accomplishes the complex pattern recognition that enables humans to perform high level functions such as spatial reasoning, conscious thought, and complex language.
• In the field of computing, pattern recognition tasks are increasingly challenging. Ever larger volumes of data are transmitted between computers, and the number of patterns that users wish to identify is increasing. For example, spam or malware are often detected by searching for patterns in a data stream, e.g., particular phrases or pieces of code. The number of patterns increases with the variety of spam and malware, as new patterns may be implemented to search for new variants. Searching a data stream for each of these patterns can form a computing bottleneck. Often, as the data stream is received, it is searched for each pattern, one at a time. The delay before the system is ready to search the next portion of the data stream increases with the number of patterns. Thus, pattern recognition may slow the receipt of data.
• Hardware has been designed to search a data stream for patterns, but this hardware often is unable to process adequate amounts of data in an amount of time given. Some devices configured to search a data stream do so by distributing the data stream among a plurality of circuits. The circuits each determine whether the data stream matches a portion of a pattern. Often, a large number of circuits operate in parallel, each searching the data stream at generally the same time. However, there has not been a system that effectively allows for performing pattern recognition in a manner more comparable to that of a biological brain. Development of such a system is desirable.
BRIEF DESCRIPTION OF DRAWINGS
• FIG.1 illustrates an example of system having a state machine engine, according to various embodiments of the invention.
• FIG.2 illustrates an example of an FSM lattice of the state machine engine ofFIG.1, according to various embodiments of the invention.
• FIG.3 illustrates an example of a block of the FSM lattice ofFIG.2, according to various embodiments of the invention.
• FIG.4 illustrates an example of a row of the block ofFIG.3, according to various embodiments of the invention.
• FIG.5 illustrates an example of a Group of Two of the row ofFIG.4, according to various embodiments of the invention.
• FIG.6 illustrates an example of a finite state machine graph, according to various embodiments of the invention.
• FIG.7 illustrates an example of two-level hierarchy implemented with FSM lattices, according to various embodiments of the invention.
• FIG.8 illustrates an example of a method for a compiler to convert source code into a binary file for programming of the FSM lattice ofFIG.2, according to various embodiments of the invention. invention.
• FIG.9 illustrates a state machine engine, according to various embodiments of the
• FIG.10 illustrates a block diagram of a plurality of state machine engines coupled via a communication bus, according to various embodiments of the invention.
• FIG.11 illustrates a timing diagram of the operation of the plurality of state machine engines ofFIG.10, according to various embodiments of the invention.
• FIG.12 illustrates a flow chart illustrating a first process utilizing the instruction inter-rank bus control system ofFIG.9, according to various embodiments of the invention.
DETAILED DESCRIPTION
• Turning now to the figures,FIG.1 illustrates an embodiment of a processor-based system, generally designated byreference numeral10. The system10 (e.g., data analysis system) may be any of a variety of types such as a desktop computer, laptop computer, pager, cellular phone, personal organizer, portable audio player, control circuit, camera, etc. Thesystem10 may also be a network node, such as a router, a server, or a client (e.g., one of the previously-described types of computers). Thesystem10 may be some other sort of electronic device, such as a copier, a scanner, a printer, a game console, a television, a set-top video distribution or recording system, a cable box, a personal digital media player, a factory automation system, an automotive computer system, or a medical device. (The terms used to describe these various examples of systems, like many of the other terms used herein, may share some referents and, as such, should not be construed narrowly in virtue of the other items listed.)
• In a processor-based device, such as thesystem10, aprocessor12, such as a microprocessor, controls the processing of system functions and requests in thesystem10. Further, theprocessor12 may comprise a plurality of processors that share system control. Theprocessor12 may be coupled directly or indirectly to each of the elements in thesystem10, such that theprocessor12 controls thesystem10 by executing instructions that may be stored within thesystem10 or external to thesystem10.
• In accordance with the embodiments described herein, thesystem10 includes astate machine engine14, which may operate under control of theprocessor12. Thestate machine engine14 may employ any automaton theory. For example, thestate machine engine14 may employ one of a number of state machine architectures, including, but not limited to Mealy architectures, Moore architectures, Finite State Machines (FSMs), Deterministic FSMs (DFSMs), Bit-Parallel State Machines (BPSMs), etc. Though a variety of architectures may be used, for discussion purposes, the application refers to FSMs. However, those skilled in the art will appreciate that the described techniques may be employed using any one of a variety of state machine architectures.
• As discussed further below, thestate machine engine14 may include a number of (e.g., one or more) finite state machine (FSM) lattices (e.g., core of a chip). For purposes of this application the term “lattice” refers to an organized framework (e.g., routing matrix, routing network, frame) of elements (e.g., Boolean cells, counter cells, state machine elements, state transition elements). Furthermore, the “lattice” may have any suitable shape, structure, or hierarchical organization (e.g., grid, cube, spherical, cascading). Each FSM lattice may implement multiple FSMs that each receive and analyze the same data in parallel. Further, the FSM lattices may be arranged in groups (e.g., clusters), such that clusters of FSM lattices may analyze the same input data in parallel. Further, clusters of FSM lattices of thestate machine engine14 may be arranged in a hierarchical structure wherein outputs from state machine lattices on a lower level of the hierarchical structure may be used as inputs to state machine lattices on a higher level. By cascading clusters of parallel FSM lattices of thestate machine engine14 in series through the hierarchical structure, increasingly complex patterns may be analyzed (e.g., evaluated, searched, etc.).
• Further, based on the hierarchical parallel configuration of thestate machine engine14, thestate machine engine14 can be employed for complex data analysis (e.g., pattern recognition or other processing) in systems that utilize high processing speeds. For instance, embodiments described herein may be incorporated in systems with processing speeds of 1 GByte/sec. Accordingly, utilizing thestate machine engine14, data from high speed memory devices or other external devices may be rapidly analyzed. Thestate machine engine14 may analyze a data stream according to several criteria (e.g., search terms), at about the same time, e.g., during a single device cycle. Each of the FSM lattices within a cluster of FSMs on a level of thestate machine engine14 may each receive the same search term from the data stream at about the same time, and each of the parallel FSM lattices may determine whether the term advances thestate machine engine14 to the next state in the processing criterion. Thestate machine engine14 may analyze terms according to a relatively large number of criteria, e.g., more than 100, more than 1000, or more than 10,000. Because they operate in parallel, they may apply the criteria to a data stream having a relatively high bandwidth, e.g., a data stream of greater than or generally equal to 1 GByte/sec, without slowing the data stream.
• In one embodiment, thestate machine engine14 may be configured to recognize (e.g., detect) a great number of patterns in a data stream. For instance, thestate machine engine14 may be utilized to detect a pattern in one or more of a variety of types of data streams that a user or other entity might wish to analyze. For example, thestate machine engine14 may be configured to analyze a stream of data received over a network, such as packets received over the Internet or voice or data received over a cellular network. In one example, thestate machine engine14 may be configured to analyze a data stream for spam or malware. The data stream may be received as a serial data stream, in which the data is received in an order that has meaning, such as in a temporally, lexically, or semantically significant order. Alternatively, the data stream may be received in parallel or out of order and, then, converted into a serial data stream, e.g., by reordering packets received over the Internet. In some embodiments, the data stream may present terms serially, but the bits expressing each of the terms may be received in parallel. The data stream may be received from a source external to thesystem10, or may be formed by interrogating a memory device, such as thememory16, and forming the data stream from data stored in thememory16. In other examples, thestate machine engine14 may be configured to recognize a sequence of characters that spell a certain word, a sequence of genetic base pairs that specify a gene, a sequence of bits in a picture or video file that form a portion of an image, a sequence of bits in an executable file that form a part of a program, or a sequence of bits in an audio file that form a part of a song or a spoken phrase. The stream of data to be analyzed may include multiple bits of data in a binary format or other formats, e.g., base ten, ASCII, etc. The stream may encode the data with a single digit or multiple digits, e.g., several binary digits.
• As will be appreciated, thesystem10 may includememory16. Thememory16 may include volatile memory, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Synchronous DRAM (SDRAM), Double Data Rate DRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, etc. Thememory16 may also include non-volatile memory, such as read-only memory (ROM), PC-RAM, silicon-oxide-nitride-oxide-silicon (SONOS) memory, metal-oxide-nitride-oxide-silicon (MONOS) memory, polysilicon floating gate based memory, and/or other types of flash memory of various architectures (e.g., NAND memory, NOR memory, etc.) to be used in conjunction with the volatile memory. Thememory16 may include one or more memory devices, such as DRAM devices, that may provide data to be analyzed by thestate machine engine14. As used herein, the term “provide” may generically refer to direct, input, insert, issue, route, send, transfer, transmit, generate, give, output, place, write, etc. Such devices may be referred to as or include solid state drives (SSD's), MultimediaMediaCards (MMC's), SecureDigital (SD) cards, CompactFlash (CF) cards, or any other suitable device. Further, it should be appreciated that such devices may couple to thesystem10 via any suitable interface, such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Small Computer System Interface (SCSI), IEEE 1394 (Firewire), or any other suitable interface. To facilitate operation of thememory16, such as the flash memory devices, thesystem10 may include a memory controller (not illustrated). As will be appreciated, the memory controller may be an independent device or it may be integral with theprocessor12. Additionally, thesystem10 may include anexternal storage18, such as a magnetic storage device. The external storage may also provide input data to thestate machine engine14.
• Thesystem10 may include a number of additional elements. For instance, acompiler20 may be used to configure (e.g., program) thestate machine engine14, as described in more detail with regard toFIG.8. Aninput device22 may also be coupled to theprocessor12 to allow a user to input data into thesystem10. For instance, aninput device22 may be used to input data into thememory16 for later analysis by thestate machine engine14. Theinput device22 may include buttons, switching elements, a keyboard, a light pen, a stylus, a mouse, and/or a voice recognition system, for instance. Anoutput device24, such as a display may also be coupled to theprocessor12. Theoutput device24 may include an LCD, a CRT, LEDs, and/or an audio display, for example. They system may also include anetwork interface device26, such as a Network Interface Card (NIC), for interfacing with a network, such as the Internet. As will be appreciated, thesystem10 may include many other components, depending on the application of thesystem10.
• FIGS.2-5 illustrate an example of aFSM lattice30. In an example, theFSM lattice30 comprises an array ofblocks32. As will be described, eachblock32 may include a plurality of selectively couple-able hardware elements (e.g., configurable elements and/or special purpose elements) that correspond to a plurality of states in a FSM. Similar to a state in a FSM, a hardware element can analyze an input stream and activate a downstream hardware element, based on the input stream.
• The configurable elements can be configured (e.g., programmed) to implement many different functions. For instance, the configurable elements may include state machine elements (SMEs)34,36 (shown inFIG.5) that are hierarchically organized into rows38 (shown inFIGS.3 and4) and blocks32 (shown inFIGS.2 and3). The SMEs may also be considered state transition elements (STEs). To route signals between the hierarchically organizedSMEs34,36, a hierarchy of configurable switching elements can be used, including inter-block switching elements40 (shown inFIGS.2 and3), intra-block switching elements42 (shown inFIGS.3 and4) and intra-row switching elements44 (shown inFIG.4).
• As described below, the switching elements may include routing structures and buffers. ASME34,36 can correspond to a state of a FSM implemented by theFSM lattice30. TheSMEs34,36 can be coupled together by using the configurable switching elements as described below. Accordingly, a FSM can be implemented on theFSM lattice30 by configuring theSMEs34,36 to correspond to the functions of states and by selectively coupling together theSMEs34,36 to correspond to the transitions between states in the FSM.
• FIG.2 illustrates an overall view of an example of aFSM lattice30. TheFSM lattice30 includes a plurality ofblocks32 that can be selectively coupled together with configurableinter-block switching elements40. Theinter-block switching elements40 may include conductors46 (e.g., wires, traces, etc.) and buffers48 and50. In an example, buffers48 and50 are included to control the connection and timing of signals to/from theinter-block switching elements40. As described further below, thebuffers48 may be provided to buffer data being sent betweenblocks32, while thebuffers50 may be provided to buffer data being sent betweeninter-block switching elements40. Additionally, theblocks32 can be selectively coupled to an input block52 (e.g., a data input port) for receiving signals (e.g., data) and providing the data to theblocks32. Theblocks32 can also be selectively coupled to an output block54 (e.g., an output port) for providing signals from theblocks32 to an external device (e.g., another FSM lattice30). TheFSM lattice30 can also include a programming interface56 to configure (e.g., via an image, program) theFSM lattice30. The image can configure (e.g., set) the state of theSMEs34,36. For example, the image can configure theSMEs34,36 to react in a certain way to a given input at theinput block52. For example, aSME34,36 can be set to output a high signal when the character ‘a’ is received at theinput block52.
• In an example, theinput block52, theoutput block54, and/or the programming interface56 can be implemented as registers such that writing to or reading from the registers provides data to or from the respective elements. Accordingly, bits from the image stored in the registers corresponding to the programming interface56 can be loaded on theSMEs34,36. AlthoughFIG.2 illustrates a certain number of conductors (e.g., wire, trace) between ablock32,input block52,output block54, and aninter-block switching element40, it should be understood that in other examples, fewer or more conductors may be used.
• FIG.3 illustrates an example of ablock32. Ablock32 can include a plurality ofrows38 that can be selectively coupled together with configurableintra-block switching elements42. Additionally, arow38 can be selectively coupled to anotherrow38 within anotherblock32 with theinter-block switching elements40. Arow38 includes a plurality ofSMEs34,36 organized into pairs of elements that are referred to herein as groups of two (GOTs)60. In an example, ablock32 comprises sixteen (16)rows38.
• FIG.4 illustrates an example of arow38. AGOT60 can be selectively coupled to other GOTs60 and any other elements (e.g., a special purpose element58) within therow38 by configurable intra-row switching elements44. AGOT60 can also be coupled toother GOTs60 inother rows38 with theintra-block switching element42, orother GOTs60 inother blocks32 with aninter-block switching element40. In an example, aGOT60 has a first andsecond input62,64, and anoutput66. Thefirst input62 is coupled to a first SME34 of theGOT60 and thesecond input64 is coupled to asecond SME36 of theGOT60, as will be further illustrated with reference toFIG.5.
• In an example, therow38 includes a first and second plurality ofrow interconnection conductors68,70. In an example, aninput62,64 of aGOT60 can be coupled to one or morerow interconnection conductors68,70, and anoutput66 can be coupled to one or morerow interconnection conductor68,70. In an example, a first plurality of the row interconnection conductors68 can be coupled to eachSME34,36 of eachGOT60 within therow38. A second plurality of therow interconnection conductors70 can be coupled to only oneSME34,36 of eachGOT60 within therow38, but cannot be coupled to theother SME34,36 of theGOT60. In an example, a first half of the second plurality ofrow interconnection conductors70 can couple to first half of theSMEs34,36 within a row38 (one SME34 from each GOT60) and a second half of the second plurality ofrow interconnection conductors70 can couple to a second half of theSMEs34,36 within a row38 (theother SME34,36 from each GOT60), as will be better illustrated with respect toFIG.5. The limited connectivity between the second plurality ofrow interconnection conductors70 and theSMEs34,36 is referred to herein as “parity”. In an example, therow38 can also include aspecial purpose element58 such as a counter, a configurable Boolean logic element, look-up table, RAM, a field configurable gate array (FPGA), an application specific integrated circuit (ASIC), a configurable processor (e.g., a microprocessor), or other element for performing a special purpose function.
• In an example, thespecial purpose element58 comprises a counter (also referred to herein as counter58). In an example, thecounter58 comprises a 12-bit configurable down counter. The 12-bitconfigurable counter58 has a counting input, a reset input, and zero-count output. The counting input, when asserted, decrements the value of thecounter58 by one. The reset input, when asserted, causes thecounter58 to load an initial value from an associated register. For the 12-bit counter58, up to a 12-bit number can be loaded in as the initial value. When the value of thecounter58 is decremented to zero (0), the zero-count output is asserted. Thecounter58 also has at least two modes, pulse and hold. When thecounter58 is set to pulse mode, the zero-count output is asserted when thecounter58 reaches zero. For example, the zero-count output is asserted during the processing of an immediately subsequent next data byte, which results in thecounter58 being offset in time with respect to the input character cycle. After the next character cycle, the zero-count output is no longer asserted. In this manner, for example, in the pulse mode, the zero-count output is asserted for one input character processing cycle. When thecounter58 is set to hold mode the zero-count output is asserted during the clock cycle when thecounter58 decrements to zero, and stays asserted until thecounter58 is reset by the reset input being asserted.
• In another example, thespecial purpose element58 comprises Boolean logic. For example, the Boolean logic may be used to perform logical functions, such as AND, OR, NAND, NOR, Sum of Products (SoP), Negated-Output Sum of Products (NSoP), Negated-Output Product of Sume (NPoS), and Product of Sums (PoS) functions. This Boolean logic can be used to extract data from terminal state SMEs (corresponding to terminal nodes of a FSM, as discussed later herein) inFSM lattice30. The data extracted can be used to provide state data toother FSM lattices30 and/or to provide configuring data used to reconfigureFSM lattice30, or to reconfigure anotherFSM lattice30.
• FIG.5 illustrates an example of aGOT60. TheGOT60 includes a first SME34 and asecond SME36 havinginputs62,64 and having theiroutputs72,74 coupled to an OR gate76 and a 3-to-1multiplexer78. The 3-to-1multiplexer78 can be set to couple theoutput66 of theGOT60 to either the first SME34, thesecond SME36, or the OR gate76. The OR gate76 can be used to couple together bothoutputs72,74 to form thecommon output66 of theGOT60. In an example, the first andsecond SME34,36 exhibit parity, as discussed above, where theinput62 of the first SME34 can be coupled to some of the row interconnection conductors68 and theinput64 of thesecond SME36 can be coupled to otherrow interconnection conductors70 thecommon output66 may be produced which may overcome parity problems. In an example, the twoSMEs34,36 within aGOT60 can be cascaded and/or looped back to themselves by setting either or both of switchingelements79. TheSMEs34,36 can be cascaded by coupling theoutput72,74 of theSMEs34,36 to theinput62,64 of theother SME34,36. TheSMEs34,36 can be looped back to themselves by coupling theoutput72,74 to theirown input62,64. Accordingly, theoutput72 of the first SME34 can be coupled to neither, one, or both of theinput62 of the first SME34 and theinput64 of thesecond SME36. Additionally, as each of theinputs62,64 may be coupled to a plurality of row routing lines, an OR gate may be utilized to select any of the inputs from these row routing lines alonginputs62,64, as well as theoutputs72,74.
• In an example, astate machine element34,36 comprises a plurality ofmemory cells80, such as those often used in dynamic random access memory (DRAM), coupled in parallel to a detectline82. Onesuch memory cell80 comprises a memory cell that can be set to a data state, such as one that corresponds to either a high or a low value (e.g., a 1 or 0). The output of thememory cell80 is coupled to the detectline82 and the input to thememory cell80 receives signals based on data on the data stream line84. In an example, an input at theinput block52 is decoded to select one or more of thememory cells80. The selectedmemory cell80 provides its stored data state as an output onto the detectline82. For example, the data received at theinput block52 can be provided to a decoder (not shown) and the decoder can select one or more of the data stream lines84. In an example, the decoder can convert an 8-bit ACSII character to the corresponding 1 of 256 data stream lines84.
• Amemory cell80, therefore, outputs a high signal to the detectline82 when thememory cell80 is set to a high value and the data on the data stream line84 selects thememory cell80. When the data on the data stream line84 selects thememory cell80 and thememory cell80 is set to a low value, thememory cell80 outputs a low signal to the detectline82. The outputs from thememory cells80 on the detectline82 are sensed by adetection cell86.
• In an example, the signal on aninput line62,64 sets therespective detection cell86 to either an active or inactive state. When set to the inactive state, thedetection cell86 outputs a low signal on therespective output72,74 regardless of the signal on the respective detectline82. When set to an active state, thedetection cell86 outputs a high signal on therespective output line72,74 when a high signal is detected from one of thememory cells82 of therespective SME34,36. When in the active state, thedetection cell86 outputs a low signal on therespective output line72,74 when the signals from all of thememory cells82 of therespective SME34,36 are low.
• In an example, anSME34,36 includes 256memory cells80 and eachmemory cell80 is coupled to a different data stream line84. Thus, anSME34,36 can be programmed to output a high signal when a selected one or more of the data stream lines84 have a high signal thereon. For example, the SME34 can have a first memory cell80 (e.g., bit0) set high and all other memory cells80 (e.g., bits1-255) set low. When therespective detection cell86 is in the active state, the SME34 outputs a high signal on theoutput72 when the data stream line84 corresponding tobit0 has a high signal thereon. In other examples, the SME34 can be set to output a high signal when one of multiple data stream lines84 have a high signal thereon by setting theappropriate memory cells80 to a high value.
• In an example, amemory cell80 can be set to a high or low value by reading bits from an associated register. Accordingly, the SMEs34 can be configured by storing an image created by thecompiler20 into the registers and loading the bits in the registers into associatedmemory cells80. In an example, the image created by thecompiler20 includes a binary image of high and low (e.g., 1 and 0) bits. The image can configure theFSM lattice30 to implement a FSM by cascading theSMEs34,36. For example, a first SME34 can be set to an active state by setting thedetection cell86 to the active state. The first SME34 can be set to output a high signal when the data stream line84 corresponding tobit0 has a high signal thereon. Thesecond SME36 can be initially set to an inactive state, but can be set to, when active, output a high signal when the data stream line84 corresponding tobit1 has a high signal thereon. The first SME34 and thesecond SME36 can be cascaded by setting theoutput72 of the first SME34 to couple to theinput64 of thesecond SME36. Thus, when a high signal is sensed on the data stream line84 corresponding tobit0, the first SME34 outputs a high signal on theoutput72 and sets thedetection cell86 of thesecond SME36 to an active state. When a high signal is sensed on the data stream line84 corresponding tobit1, thesecond SME36 outputs a high signal on the output74 to activate anotherSME36 or for output from theFSM lattice30.
• In an example, asingle FSM lattice30 is implemented on a single physical device, however, in other examples two ormore FSM lattices30 can be implemented on a single physical device (e.g., physical chip). In an example, eachFSM lattice30 can include a distinctdata input block52, adistinct output block54, a distinct programming interface56, and a distinct set of configurable elements. Moreover, each set of configurable elements can react (e.g., output a high or low signal) to data at their correspondingdata input block52. For example, a first set of configurable elements corresponding to afirst FSM lattice30 can react to the data at a firstdata input block52 corresponding to thefirst FSM lattice30. A second set of configurable elements corresponding to asecond FSM lattice30 can react to a seconddata input block52 corresponding to thesecond FSM lattice30. Accordingly, eachFSM lattice30 includes a set of configurable elements, wherein different sets of configurable elements can react to different input data. Similarly, eachFSM lattice30, and each corresponding set of configurable elements can provide a distinct output. In some examples, anoutput block54 from afirst FSM lattice30 can be coupled to aninput block52 of asecond FSM lattice30, such that input data for thesecond FSM lattice30 can include the output data from thefirst FSM lattice30 in a hierarchical arrangement of a series ofFSM lattices30.
• In an example, an image for loading onto theFSM lattice30 comprises a plurality of bits of data for configuring the configurable elements, the configurable switching elements, and the special purpose elements within theFSM lattice30. In an example, the image can be loaded onto theFSM lattice30 to configure theFSM lattice30 to provide a desired output based on certain inputs. Theoutput block54 can provide outputs from theFSM lattice30 based on the reaction of the configurable elements to data at thedata input block52. An output from theoutput block54 can include a single bit indicating a match of a given pattern, a word comprising a plurality of bits indicating matches and non-matches to a plurality of patterns, and a state vector corresponding to the state of all or certain configurable elements at a given moment. As described, a number ofFSM lattices30 may be included in a state machine engine, such asstate machine engine14, to perform data analysis, such as pattern-recognition (e.g., speech recognition, image recognition, etc.) signal processing, imaging, computer vision, cryptography, and others.
• FIG.6 illustrates an example model of a finite state machine (FSM) that can be implemented by theFSM lattice30. TheFSM lattice30 can be configured (e.g., programmed) as a physical implementation of a FSM. A FSM can be represented as a diagram90, (e.g., directed graph, undirected graph, pseudograph), which contains one ormore root nodes92. In addition to theroot nodes92, the FSM can be made up of severalstandard nodes94 andterminal nodes96 that are connected to theroot nodes92 and otherstandard nodes94 through one or more edges98. Anode92,94,96 corresponds to a state in the FSM. Theedges98 correspond to the transitions between the states.
• Each of thenodes92,94,96 can be in either an active or an inactive state. When in the inactive state, anode92,94,96 does not react (e.g., respond) to input data. When in an active state, anode92,94,96 can react to input data. Anupstream node92,94 can react to the input data by activating anode94,96 that is downstream from the node when the input data matches criteria specified by anedge98 between theupstream node92,94 and thedownstream node94,96. For example, afirst node94 that specifies the character ‘b’ will activate asecond node94 connected to thefirst node94 by anedge98 when thefirst node94 is active and the character ‘b’ is received as input data. As used herein, “upstream” refers to a relationship between one or more nodes, where a first node that is upstream of one or more other nodes (or upstream of itself in the case of a loop or feedback configuration) refers to the situation in which the first node can activate the one or more other nodes (or can activate itself in the case of a loop). Similarly, “downstream” refers to a relationship where a first node that is downstream of one or more other nodes (or downstream of itself in the case of a loop) can be activated by the one or more other nodes (or can be activated by itself in the case of a loop). Accordingly, the terms “upstream” and “downstream” are used herein to refer to relationships between one or more nodes, but these terms do not preclude the use of loops or other non-linear paths among the nodes.
• In the diagram90, theroot node92 can be initially activated and can activatedownstream nodes94 when the input data matches anedge98 from theroot node92.Nodes94 can activatenodes96 when the input data matches anedge98 from thenode94.Nodes94,96 throughout the diagram90 can be activated in this manner as the input data is received. Aterminal node96 corresponds to a match of a sequence of interest in the input data. Accordingly, activation of aterminal node96 indicates that a sequence of interest has been received as the input data. In the context of theFSM lattice30 implementing a pattern recognition function, arriving at aterminal node96 can indicate that a specific pattern of interest has been detected in the input data.
• In an example, eachroot node92,standard node94, andterminal node96 can correspond to a configurable element in theFSM lattice30. Eachedge98 can correspond to connections between the configurable elements. Thus, astandard node94 that transitions to (e.g., has anedge98 connecting to) anotherstandard node94 or aterminal node96 corresponds to a configurable element that transitions to (e.g., provides an output to) another configurable element. In some examples, theroot node92 does not have a corresponding configurable element.
• As will be appreciated, although thenode92 is described as a root node andnodes96 are described as terminal nodes, there may not necessarily be a particular “start” or root node and there may not necessarily be a particular “end” or output node. In other words, any node may be a starting point and any node may provide output.
• When theFSM lattice30 is programmed, each of the configurable elements can also be in either an active or inactive state. A given configurable element, when inactive, does not react to the input data at a correspondingdata input block52. An active configurable element can react to the input data at thedata input block52, and can activate a downstream configurable element when the input data matches the setting of the configurable element. When a configurable element corresponds to aterminal node96, the configurable element can be coupled to theoutput block54 to provide an indication of a match to an external device.
• An image loaded onto theFSM lattice30 via the programming interface56 can configure the configurable elements and special purpose elements, as well as the connections between the configurable elements and special purpose elements, such that a desired FSM is implemented through the sequential activation of nodes based on reactions to the data at thedata input block52. In an example, a configurable element remains active for a single data cycle (e.g., a single character, a set of characters, a single clock cycle) and then becomes inactive unless re-activated by an upstream configurable element.
• Aterminal node96 can be considered to store a compressed history of past events. For example, the one or more patterns of input data required to reach aterminal node96 can be represented by the activation of thatterminal node96. In an example, the output provided by aterminal node96 is binary, for example, the output indicates whether the pattern of interest has been matched or not. The ratio ofterminal nodes96 tostandard nodes94 in a diagram90 may be quite small. In other words, although there may be a high complexity in the FSM, the output of the FSM may be small by comparison.
• In an example, the output of theFSM lattice30 can comprise a state vector. The state vector comprises the state (e.g., activated or not activated) of configurable elements of theFSM lattice30. In another example, the state vector can include the state of all or a subset of the configurable elements whether or not the configurable elements corresponds to aterminal node96. In an example, the state vector includes the states for the configurable elements corresponding toterminal nodes96. Thus, the output can include a collection of the indications provided by allterminal nodes96 of a diagram90. The state vector can be represented as a word, where the binary indication provided by eachterminal node96 comprises one bit of the word. This encoding of theterminal nodes96 can provide an effective indication of the detection state (e.g., whether and what sequences of interest have been detected) for theFSM lattice30.
• As mentioned above, theFSM lattice30 can be programmed to implement a pattern recognition function. For example, theFSM lattice30 can be configured to recognize one or more data sequences (e.g., signatures, patterns) in the input data. When a data sequence of interest is recognized by theFSM lattice30, an indication of that recognition can be provided at theoutput block54. In an example, the pattern recognition can recognize a string of symbols (e.g., ASCII characters) to, for example, identify malware or other data in network data.
• FIG.7 illustrates an example ofhierarchical structure100, wherein two levels ofFSM lattices30 are coupled in series and used to analyze data. Specifically, in the illustrated embodiment, thehierarchical structure100 includes a first FSM lattice30A and a second FSM lattice30B arranged in series. EachFSM lattice30 includes a respectivedata input block52 to receive data input, a programming interface block56 to receive configuring signals and anoutput block54.
• The first FSM lattice30A is configured to receive input data, for example, raw data at a data input block. The first FSM lattice30A reacts to the input data as described above and provides an output at an output block. The output from the first FSM lattice30A is sent to a data input block of the second FSM lattice30B. The second FSM lattice30B can then react based on the output provided by the first FSM lattice30A and provide acorresponding output signal102 of thehierarchical structure100. This hierarchical coupling of two FSM lattices30A and30B in series provides a means to provide data regarding past events in a compressed word from a first FSM lattice30A to a second FSM lattice30B. The data provided can effectively be a summary of complex events (e.g., sequences of interest) that were recorded by the first FSM lattice30A.
• The two-level hierarchy100 of FSM lattices30A,30B shown inFIG.7 allows two independent programs to operate based on the same data stream. The two-stage hierarchy can be similar to visual recognition in a biological brain which is modeled as different regions. Under this model, the regions are effectively different pattern recognition engines, each performing a similar computational function (pattern matching) but using different programs (signatures). By connecting multiple FSM lattices30A,30B together, increased knowledge about the data stream input may be obtained.
• The first level of the hierarchy (implemented by the first FSM lattice30A) can, for example, perform processing directly on a raw data stream. For example, a raw data stream can be received at aninput block52 of the first FSM lattice30A and the configurable elements of the first FSM lattice30A can react to the raw data stream. The second level (implemented by the second FSM lattice30B) of the hierarchy can process the output from the first level. For example, the second FSM lattice30B receives the output from anoutput block54 of the first FSM lattice30A at aninput block52 of the second FSM lattice30B and the configurable elements of the second FSM lattice30B can react to the output of the first FSM lattice30A. Accordingly, in this example, the second FSM lattice30B does not receive the raw data stream as an input, but rather receives the indications of patterns of interest that are matched by the raw data stream as determined by the first FSM lattice30A. The second FSM lattice30B can implement a FSM that recognizes patterns in the output data stream from the first FSM lattice30A. It should be appreciated that the second FSM lattice30B may receive inputs from multiple other FSM lattices in addition to receiving output from the FSM lattice30A. Likewise, the second FSM lattice30B may receive inputs from other devices. The second FSM lattice30B may combine these multiple inputs to produce outputs.
• FIG.8 illustrates an example of amethod110 for a compiler to convert source code into an image used to configure a FSM lattice, such aslattice30, to implement a FSM.Method110 includes parsing the source code into a syntax tree (block112), converting the syntax tree into an automaton (block114), optimizing the automaton (block116), converting the automaton into a netlist (block118), placing the netlist on hardware (block120), routing the netlist (block122), and publishing the resulting image (block124).
• In an example, thecompiler20 includes an application programming interface (API) that allows software developers to create images for implementing FSMs on theFSM lattice30. Thecompiler20 provides methods to convert an input set of regular expressions in the source code into an image that is configured to configure theFSM lattice30. Thecompiler20 can be implemented by instructions for a computer having a von Neumann architecture. These instructions can cause aprocessor12 on the computer to implement the functions of thecompiler20. For example, the instructions, when executed by theprocessor12, can cause theprocessor12 to perform actions as described inblocks112,114,116,118,120,122, and124 on source code that is accessible to theprocessor12.
• In an example, the source code describes search strings for identifying patterns of symbols within a group of symbols. To describe the search strings, the source code can include a plurality of regular expressions (regexs). A regex can be a string for describing a symbol search pattern. Regexes are widely used in various computer domains, such as programming languages, text editors, network security, and others. In an example, the regular expressions supported by the compiler include criteria for the analysis of unstructured data. Unstructured data can include data that is free form and has no indexing applied to words within the data. Words can include any combination of bytes, printable and non-printable, within the data. In an example, the compiler can support multiple different source code languages for implementing regexes including Perl, (e.g., Perl compatible regular expressions (PCRE)), PHP, Java, and .NET languages.
• Atblock112 thecompiler20 can parse the source code to form an arrangement of relationally connected operators, where different types of operators correspond to different functions implemented by the source code (e.g., different functions implemented by regexes in the source code). Parsing source code can create a generic representation of the source code. In an example, the generic representation comprises an encoded representation of the regexs in the source code in the form of a tree graph known as a syntax tree. The examples described herein refer to the arrangement as a syntax tree (also known as an “abstract syntax tree”) in other examples, however, a concrete syntax tree or other arrangement can be used.
• Since, as mentioned above, thecompiler20 can support multiple languages of source code, parsing converts the source code, regardless of the language, into a non-language specific representation, e.g., a syntax tree. Thus, further processing (blocks114,116,118,120) by thecompiler20 can work from a common input structure regardless of the language of the source code.
• As noted above, the syntax tree includes a plurality of operators that are relationally connected. A syntax tree can include multiple different types of operators. For example, different operators can correspond to different functions implemented by the regexes in the source code.
• Atblock114, the syntax tree is converted into an automaton. An automaton comprises a software model of a FSM and can accordingly be classified as deterministic or non-deterministic. A deterministic automaton has a single path of execution at a given time, while a non-deterministic automaton has multiple concurrent paths of execution. The automaton comprises a plurality of states. In order to convert the syntax tree into an automaton, the operators and relationships between the operators in the syntax tree are converted into states with transitions between the states. In an example, the automaton can be converted based partly on the hardware of theFSM lattice30.
• In an example, input symbols for the automaton include the symbols of the alphabet, the numerals 0-9, and other printable characters. In an example, the input symbols are represented by the byte values 0 through 255 inclusive. In an example, an automaton can be represented as a directed graph where the nodes of the graph correspond to the set of states. In an example, a transition from state p to state q on an input symbol α, i.e. δ(p,α), is shown by a directed connection from node p to node q. In an example, a reversal of an automaton produces a new automaton where each transition p→q on some symbol α is reversed q→p on the same symbol. In a reversal, start state becomes a final state and the final states become start states. In an example, the language recognized (e.g., matched) by an automaton is the set of all possible character strings which when input sequentially into the automaton will reach a final state. Each string in the language recognized by the automaton traces a path from the start state to one or more final states.
• Atblock116, after the automaton is constructed, the automaton is optimized to reduce its complexity and size, among other things. The automaton can be optimized by combining redundant states.
• Atblock118, the optimized automaton is converted into a netlist. Converting the automaton into a netlist maps each state of the automaton to a hardware element (e.g.,SMEs34,36, other elements) on theFSM lattice30, and determines the connections between the hardware elements.
• Atblock120, the netlist is placed to select a specific hardware element of the target device (e.g.,SMEs34,36, special purpose elements58) corresponding to each node of the netlist. In an example, placing selects each specific hardware element based on general input and output constraints for of theFSM lattice30.
• Atblock122, the placed netlist is routed to determine the settings for the configurable switching elements (e.g.,inter-block switching elements40,intra-block switching elements42, and intra-row switching elements44) in order to couple the selected hardware elements together to achieve the connections describe by the netlist. In an example, the settings for the configurable switching elements are determined by determining specific conductors of theFSM lattice30 that will be used to connect the selected hardware elements, and the settings for the configurable switching elements. Routing can take into account more specific limitations of the connections between the hardware elements that placement atblock120. Accordingly, routing may adjust the location of some of the hardware elements as determined by the global placement in order to make appropriate connections given the actual limitations of the conductors on theFSM lattice30.
• Once the netlist is placed and routed, the placed and routed netlist can be converted into a plurality of bits for configuring aFSM lattice30. The plurality of bits are referred to herein as an image (e.g., binary image).
• Atblock124, an image is published by thecompiler20. The image comprises a plurality of bits for configuring specific hardware elements of theFSM lattice30. The bits can be loaded onto theFSM lattice30 to configure the state ofSMEs34,36, thespecial purpose elements58, and the configurable switching elements such that the programmedFSM lattice30 implements a FSM having the functionality described by the source code. Placement (block120) and routing (block122) can map specific hardware elements at specific locations in theFSM lattice30 to specific states in the automaton. Accordingly, the bits in the image can configure the specific hardware elements to implement the desired function(s). In an example, the image can be published by saving the machine code to a computer readable medium. In another example, the image can be published by displaying the image on a display device. In still another example, the image can be published by sending the image to another device, such as a configuring device for loading the image onto theFSM lattice30. In yet another example, the image can be published by loading the image onto a FSM lattice (e.g., the FSM lattice30).
• In an example, an image can be loaded onto theFSM lattice30 by either directly loading the bit values from the image to theSMEs34,36 and other hardware elements or by loading the image into one or more registers and then writing the bit values from the registers to theSMEs34,36 and other hardware elements. In an example, the hardware elements (e.g.,SMEs34,36,special purpose elements58,configurable switching elements40,42,44) of theFSM lattice30 are memory mapped such that a configuring device and/or computer can load the image onto theFSM lattice30 by writing the image to one or more memory addresses.
• Method examples described herein can be machine or computer-implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code can include computer readable instructions for performing various methods. The code may form portions of computer program products. Further, the code may be tangibly stored on one or more volatile or non-volatile computer-readable media during execution or at other times. These computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.
• Referring now toFIG.9, an embodiment of the state machine engine14 (e.g., a single device on a single chip) is illustrated. As previously described, thestate machine engine14 is configured to receive data from a source, such as thememory16 over a data bus. In the illustrated embodiment, data may be sent to thestate machine engine14 through a bus interface, such as a double data rate three (DDR3)bus interface130. TheDDR3 bus interface130 may be capable of exchanging (e.g., providing and receiving) data at a rate greater than or equal to 1 GByte/sec. Such a data exchange rate may be greater than a rate that data is analyzed by thestate machine engine14. As will be appreciated, depending on the source of the data to be analyzed, thebus interface130 may be any suitable bus interface for exchanging data to and from a data source to thestate machine engine14, such as a NAND Flash interface, peripheral component interconnect (PCI) interface, gigabit media independent interface, etc. As previously described, thestate machine engine14 includes one ormore FSM lattices30 configured to analyze data. EachFSM lattice30 may be divided into two half-lattices. In the illustrated embodiment, each half lattice may include 24K SMEs (e.g., SMEs34,36), such that thelattice30 includes 48K SMEs. Thelattice30 may comprise any desirable number of SMEs, arranged as previously described with regard toFIGS.2-5. Further, while only oneFSM lattice30 is illustrated, thestate machine engine14 may includemultiple FSM lattices30, as previously described.
• Data to be analyzed may be received at thebus interface130 and provided to theFSM lattice30 through a number of buffers and buffer interfaces. In the illustrated embodiment, the data path includes data buffers132, an instruction buffer133, process buffers134, and an inter-rank (IR) bus and process buffer interface136. The data buffers132 are configured to receive and temporarily store data to be analyzed. In one embodiment, there are two data buffers132 (data buffer A and data buffer B). Data may be stored in one of the twodata buffers132, while data is being emptied from theother data buffer132, for analysis by theFSM lattice30. Thebus interface130 may be configured to provide data to be analyzed to the data buffers132 until the data buffers132 are full. After the data buffers132 are full, thebus interface130 may be configured to be free to be used for other purpose (e.g., to provide other data from a data stream until the data buffers132 are available to receive additional data to be analyzed). In the illustrated embodiment, the data buffers132 may be 32 KBytes each. The instruction buffer133 is configured to receive instructions from theprocessor12 via thebus interface130, such as instructions that correspond to the data to be analyzed and instructions that correspond to configuring thestate machine engine14. The IR bus and process buffer interface136 may facilitate providing data to the process buffer134. The IR bus and process buffer interface136 can be used to ensure that data is processed by theFSM lattice30 in order. The IR bus and process buffer interface136 may coordinate the exchange of data, timing data, packing instructions, etc. such that data is received and analyzed correctly. Generally, the IR bus and process buffer interface136 allows the analyzing of multiple data sets in parallel through a logical rank ofFSM lattices30. For example, multiple physical devices (e.g.,state machine engines14, chips, separate devices) may be arranged in a rank and may provide data to each other via the IR bus and process buffer interface136. For purposes of this application the term “rank” refers to a set ofstate machine engines14 connected to the same chip select. In the illustrated embodiment, the IR bus and process buffer interface136 may include a 32 bit data bus. In other embodiments, the IR bus and process buffer interface136 may include any suitable data bus, such as a 128 bit data bus.
• In the illustrated embodiment, thestate machine engine14 also includes a de-compressor138 and acompressor140 to aid in providing state vector data through thestate machine engine14. Thecompressor140 and de-compressor138 work in conjunction such that the state vector data can be compressed to minimize the data providing times. By compressing the state vector data, the bus utilization time may be minimized. Thecompressor140 and de-compressor138 can also be configured to handle state vector data of varying burst lengths. By padding compressed state vector data and including an indicator as to when each compressed region ends, thecompressor140 may improve the overall processing speed through thestate machine engine14. Thecompressor140 may be used to compress results data after analysis by theFSM lattice30. Thecompressor140 and de-compressor138 may also be used to compress and decompress configuration data. In one embodiment, thecompressor140 and de-compressor138 may be disabled (e.g., turned off) such that data flowing to and/or from thecompressor140 and de-compressor138 is not modified.
• As previously described, an output of theFSM lattice30 can comprise a state vector. The state vector comprises the state (e.g., activated or not activated) of theSMEs34,36 of theFSM lattice30 and the dynamic (e.g., current) count of thecounter58. Thestate machine engine14 includes astate vector system141 having a statevector cache memory142, a statevector memory buffer144, a state vectorintermediate input buffer146, and a state vector intermediate output buffer148. Thestate vector system141 may be used to store multiple state vectors of theFSM lattice30 and to provide a state vector to theFSM lattice30 to restore theFSM lattice30 to a state corresponding to the provided state vector. For example, each state vector may be temporarily stored in the statevector cache memory142. For example, the state of eachSME34,36 may be stored, such that the state may be restored and used in further analysis at a later time, while freeing theSMEs34,36 for further analysis of a new data set (e.g., search term). Like a typical cache, the statevector cache memory142 allows storage of state vectors for quick retrieval and use, here by theFSM lattice30, for instance. In the illustrated embodiment, the statevector cache memory142 may store up to512 state vectors.
• As will be appreciated, the state vector data may be exchanged between different state machine engines14 (e.g., chips) in a rank. The state vector data may be exchanged between the differentstate machine engines14 for various purposes such as: to synchronize the state of theSMEs34,36 of theFSM lattices30 of thestate machine engines14, to perform the same functions across multiplestate machine engines14, to reproduce results across multiplestate machine engines14, to cascade results across multiplestate machine engines14, to store a history of states of theSMEs34,36 used to analyze data that is cascaded through multiplestate machine engines14, and so forth. Furthermore, it should be noted that within astate machine engine14, the state vector data may be used to quickly configure theSMEs34,36 of theFSM lattice30. For example, the state vector data may be used to restore the state of theSMEs34,36 to an initialized state (e.g., to search for a new search term), to restore the state of theSMEs34,36 to prior state (e.g., to search for a previously searched search term), and to change the state of theSMEs34,36 to be configured for a cascading configuration (e.g., to search for a search term in a cascading search). In certain embodiments, the state vector data may be provided to thebus interface130 so that the state vector data may be provided to the processor12 (e.g., for analysis of the state vector data, reconfiguring the state vector data to apply modifications, reconfiguring the state vector data to improve efficiency of theSMEs34,36, and so forth).
• For example, in certain embodiments, thestate machine engine14 may provide cached state vector data (e.g., data stored by the state vector system141) from theFSM lattice30 to an external device. The external device may receive the state vector data, modify the state vector data, and provide the modified state vector data to thestate machine engine14 for configuring theFSM lattice30. Accordingly, the external device may modify the state vector data so that thestate machine engine14 may skip states (e.g., jump around) as desired.
• The statevector cache memory142 may receive state vector data from any suitable device. For example, the statevector cache memory142 may receive a state vector from theFSM lattice30, another FSM lattice30 (e.g., via the IR bus and process buffer interface136), the de-compressor138, and so forth. In the illustrated embodiment, the statevector cache memory142 may receive state vectors from other devices via the statevector memory buffer144. Furthermore, the statevector cache memory142 may provide state vector data to any suitable device. For example, the statevector cache memory142 may provide state vector data to the statevector memory buffer144, the state vectorintermediate input buffer146, and the state vector intermediate output buffer148.
• Additional buffers, such as the statevector memory buffer144, state vectorintermediate input buffer146, and state vector intermediate output buffer148, may be utilized in conjunction with the statevector cache memory142 to accommodate rapid retrieval and storage of state vectors, while processing separate data sets with interleaved packets through thestate machine engine14. In the illustrated embodiment, each of the statevector memory buffer144, the state vectorintermediate input buffer146, and the state vector intermediate output buffer148 may be configured to temporarily store one state vector. The statevector memory buffer144 may be used to receive state vector data from any suitable device and to provide state vector data to any suitable device. For example, the statevector memory buffer144 may be used to receive a state vector from theFSM lattice30, another FSM lattice30 (e.g., via the IR bus and process buffer interface136), the de-compressor138, and the statevector cache memory142. As another example, the statevector memory buffer144 may be used to provide state vector data to the IR bus and process buffer interface136 (e.g., for other FSM lattices30), thecompressor140, and the statevector cache memory142.
• Likewise, the state vectorintermediate input buffer146 may be used to receive state vector data from any suitable device and to provide state vector data to any suitable device. For example, the state vectorintermediate input buffer146 may be used to receive a state vector from an FSM lattice30 (e.g., via the IR bus and process buffer interface136), the de-compressor138, and the statevector cache memory142. As another example, the state vectorintermediate input buffer146 may be used to provide a state vector to theFSM lattice30. Furthermore, the state vector intermediate output buffer148 may be used to receive a state vector from any suitable device and to provide a state vector to any suitable device. For example, the state vector intermediate output buffer148 may be used to receive a state vector from theFSM lattice30 and the statevector cache memory142. As another example, the state vector intermediate output buffer148 may be used to provide a state vector to an FSM lattice30 (e.g., via the IR bus and process buffer interface136) and thecompressor140.
• Once a result of interest is produced by theFSM lattice30, results may be stored in aresults memory150. For example, a “match vector” indicating a match (e.g., detection of a pattern of interest) may be stored in theresults memory150. The match result can then be sent to a buffer152 for transmission over thebus interface130 to theprocessor12, for example. As previously described, the results may be compressed. Theresults memory150 may include two memory elements, memory element A and memory element B, each of which corresponds to one of the half-lattices of theFSM lattice30. In one embodiment, each of the memory elements may be DRAM memory elements or any other suitable storage devices. In some embodiments, the memory elements may operate as initial buffers to buffer the results received from theFSM lattice30, alongresults bus151. For example, memory element A may receive matches alongresults bus151 from half-lattice0 of theFSM lattice30. Similarly, memory element B may receive matches alongresults bus151 from half-lattice1 of theFSM lattice30.
• In one embodiment, the results provided to theresults memory150 may indicate that a final result has been found by theFSM lattice30. For example, the results may indicate that an entire pattern has been detected. Alternatively, the results provided to theresults memory150 may indicate, for example, that a particular state of theFSM lattice30 has been reached. For example, the results provided to theresults memory150 may indicate that one state (i.e., one portion of a pattern search) has been reached, so that a next state may be initiated. In this way, theresult memory150 may store a variety of types of results.
• In some embodiments, IR bus and process buffer interface136 may provide data tomultiple FSM lattices30 for analysis. This data may be time multiplexed. For example, if there are eightFSM lattices30, data for each of the eightFSM lattices30 may be provided to all of eight IR bus and process buffer interfaces136 that correspond to the eightFSM lattices30. Each of the eight IR bus and process buffer interfaces136 may receive an entire data set to be analyzed. Each of the eight IR bus and process buffer interfaces136 may then select portions of the entire data set relevant to theFSM lattice30 associated with the respective IR bus and process buffer interface136. This relevant data for each of the eightFSM lattices30 may then be provided from the respective IR bus and process buffer interfaces136 to therespective FSM lattice30 associated therewith. In this manner, data received by anyFSM lattice30 of thestate machine engine14 may be time multiplexed. Accordingly, as noted above, the results provided by analysis of this data may also be time multiplexed.
• Thus, theresults memory150 may operate to correlate each received result with a data input that generated the result. To accomplish this, a respective result indicator may be stored corresponding to, and in some embodiments, in conjunction with, each result received from theresults bus151. In one embodiment, the result indicators may be a single bit flag. In another embodiment, the result indicators may be a multiple bit flag. If the result indicators may include a multiple bit flag, the bit positions of the flag may indicate, for example, a count of the position of the results in input data stream, the lattice that the results correspond to, a position in set of results, or other identifying information. These results indicators may include one or more bits that identify each particular match result and allow for proper grouping and transmission of results, for example, tocompressor140. Moreover, the ability to identify particular results by their respective results indicators may allow for selective output of desired results from the match resultsmemory150. For example, only particular results generated by theFSM lattice30 may be selectively latched as an output. These result indicators may allow for proper grouping and provision of results, for example, tocompressor140. Moreover, the ability to identify particular results by their respective result indicators allow for selective output of desired results from theresult memory150. Thus, only particular results provided by theFSM lattice30 may be selectively provided tocompressor140.
• Additional registers and buffers may be provided in thestate machine engine14, as well. These registers and buffers may individually be referred to as a storage location. In one embodiment, for example, a buffer may store information related to more than one process whereas a register may store information related to a single process. For instance, thestate machine engine14 may include control and status registers154. In addition, a program buffer system (e.g., repair map and program buffers156) may be provided for programming theFSM lattice30 initially. For example, initial (e.g., starting) state vector data may be provided from the program buffer system to the FSM lattice30 (e.g., via the de-compressor138). The de-compressor138 may be used to decompress configuration data (e.g., state vector data, routing switch data,SME34,36 states, Boolean function data, counter data, match MUX data) provided to program theFSM lattice30.
• Similarly, a repair map buffer system (e.g., save and repair map buffers158) may also be provided for storage of data (e.g., save and repair maps) for setup and usage. The data stored by the repair map buffer system may include data that corresponds to repaired hardware elements, such as data identifying whichSMEs34,36 were repaired. The repair map buffer system may receive data via any suitable manner. For example, data may be provided from a “fuse map” memory, which provides the mapping of repairs done on a device during final manufacturing testing, to the repair map buffers158. As another example, the repair map buffer system may include data used to modify (e.g., customize) a standard programming file so that the standard programming file may operate in aFSM lattice30 with a repaired architecture (e.g.,bad SMEs34,36 in aFSM lattice30 may be bypassed so they are not used). Thecompressor140 may be used to compress data provided to the repair map buffers158 from the fuse map memory. As illustrated, thebus interface130 may be used to provide data to the program buffers156 and to provide data from the repair map buffers158. As will be appreciated, the data provided to the program buffers156 and/or provided from the repair map buffers158 may be compressed. In some embodiments, data is provided to thebus interface130 and/or received from thebus interface130 via a device external to the state machine engine14 (e.g., theprocessor12, thememory16, thecompiler20, and so forth). The device external to thestate machine engine14 may be configured to receive data provided from the repair map buffers158, to store the data, to analyze the data, to modify the data, and/or to provide new or modified data to the program buffers156.
• Thestate machine engine14 includes a lattice programming andinstruction control system159 used to configure (e.g., program) theFSM lattice30 as well as provide inserted instructions, as will be described in greater detail below. As illustrated, the lattice programming andinstruction control system159 may receive data (e.g., configuration instructions) from the instruction buffer133. Furthermore, the lattice programming andinstruction control system159 may receive data (e.g., configuration data) from the program buffers156. The lattice programming andinstruction control system159 may use the configuration instructions and the configuration data to configure the FSM lattice30 (e.g., to configure routing switches,SMEs34,36, Boolean cells, counters, match MUX) and may use the inserted instructions to correct errors during the operation of thestate machine engine14. The lattice programming andinstruction control system159 may also use the de-compressor138 to decompress data and thecompressor140 to compress data (e.g., for data exchanged with the program buffers156 and the repair map buffers158).
• Thestate machine engine14 also includes an inter-rank (IR)bus control system160, which may, for example, include a controller. In one embodiment, the IRbus control system160 may also receive commands from the programming andinstruction control system159. Additionally, the IRbus control system160 may, for example, facilitate communication between multiplestate machine engines14. This communication may be accomplished through the use of a common data bus and common write clock signal. Accordingly, the IRbus control system160 may include an output that is coupled to the external IR bus OF interface via the IR bus and process buffer interface136.
• FIG.10 illustrates a block diagram of a plurality ofstate machine engines14 coupled to one another via anIR bus162 made up ofsignal path164 andsignal path166. In one embodiment, thesignal paths164 and166 may interface with thestate machines14 via anIR bus interface168. As previously discussed, thisIR bus interface168 may be coupled to the IRbus control system160 illustrated inFIG.9, for example, via IR bus and process buffer interface136. TheIR bus162 may be a communication bus that allows for transmission of data, timing, control, synchronization, and/or clock signals between thestate machine engines14. Also illustrated inFIG.10 aresignal path170,signal path172, andsignal path174. In some embodiments, signalpaths170,172, and174 may be part ofIR bus162. However, signalpaths170,172, and174 may alternatively be part of a separate bus that allows for data and/or communication signals to be transmitted between thestate machine engines14. In one embodiment,signal path170 may transmit data, such as result data generated by theFSM lattice30, from astate machine engine14.Signal paths172 and174 may transmit information related to the data transmitted onsignal path170, such as indication signals that identify aspects of the data transmitted onpath170, such as when and from whichstate machine engine14 data has been transmitted. In some embodiments, the indication signals onpaths172 and174 may be utilized as timing signals to allow for the transmission of data alongpath170. For example,path172 may operate as a common write clock signal that allows for common writes to occur in each of thestate machine engines14 concurrently (e.g., simultaneously) whilepath174 may transmit an inverse of the clock signal onpath172.
• In one embodiment, at any given time, one state machine engine14 (e.g., state machine engine A) on theIR bus162 may act as a master (e.g., the sender of data), with all remaining state machine engines14 (e.g., state machine engine B, state machine engine C, state machine engine D) acting as slaves (receivers of data). Furthermore, the setup of thestate machine engines14 allows for a data transfer operation request to simultaneously be sent to allstate machine engines14. A subsequent synchronization step is executed, whereby slave state machine engines14 (e.g., state machine engine B, state machine engine C, state machine engine D) inform the master state machine engine14 (e.g., state machine engine A) they are ready for data operations. Read/write operations are then initiated on the common data bus (e.g., IR bus162) and thestate machine engines14 may undertake the read/write operations in parallel based on the common clock provided thereto (e.g., a common write clock). In this way, read/write operations may occur simultaneously for each of thestate machine engines14 on theIR bus162.
• FIG.11 is a timing diagram176 that illustrates the above-described process of synchronizing thestate machine engines14 ofFIG.10.Timing signal178 may represent a synchronization signal transmitted alongsignal path166 from, for example, slave state machine engines14 (e.g., state machine engine B, state machine engine C, state machine engine D) to the master state machine engine14 (e.g., state machine engine A).Timing signal178 may be read by the master state machine engine14 (e.g., state machine engine A) as indicating that the slave state machine engines14 (e.g., state machine engine B, state machine engine C, state machine engine D) are ready for data operations. The master state machine engine14 (e.g., state machine engine A) may then transmit aninitialization signal180 onpath164 to the slave state machine engines14 (e.g., state machine engine B, state machine engine C, state machine engine D). Thisinitialization signal180 onpath164 to the slave state machine engines14 (e.g., state machine engine B, state machine engine C, state machine engine D) may operate to initialize all of thestate machine engines14 to prepare for a read or a write operation. Read/write operations may then be initiated, for example, by the master state machine engine14 (e.g., state machine engine A), whereby pulses as part oftiming signal182 indicate the transmission of a common write clock signal, for example, passed alongpath172 from respectivestate machine engines14, to be utilized for common (e.g., concurrent or simultaneous) writes of the data signal184 to the state machine engines14 (e.g., to IR bus registers in each of thestate machine engines14, as will be discussed in greater detail below). In one embodiment, the data signal184 may represent sequential read/write operations that are commonly undertaken simultaneously (e.g., concurrently) in each of thestate machine engines14.
• As discussed above, in some embodiments, the read/write operations of thestate machine engines14 may be performed utilizing a common clock signal. Moreover, to aid in the read/write operations of the state machine engines14 (e.g., to aid in the timing of the read/write operations), internally to eachstate machine engine14, there may exist a data register (e.g., an IR bus register) dedicated to read/write operation monitoring. In some embodiments, this register may be identically sized in each of thestate machine engines14. As illustrated inFIG.9, this register may be controlled by the IRbus control system160. The register may be physically located, for example in the IR bus and process buffer interface136 or adjacent to or in process buffers134. In one embodiment, this register (e.g., an IR bus register) may be located between an IR bus interface and a process buffer interface of the IR bus and process buffer interface136. TheIR bus control160 system, as previously noted, may include a controller that may operate in conjunction with the IR bus register described. For example, the controller of theIR bus control160 system may be or may include an application specific integrated circuit (ASIC), a processor, or another other piece of control hardware.
• In some embodiments, the IR bus register may operate on the boundary of two separate clock domains. For example, write operations associated with a master state machine engine14 (e.g., state machine engine A) driven by a common write clock, may occur at a frequency that is greater than that of read operations. In one scenario, the common write clock might be a high speed clock configured to operate at DDR3 clock frequencies (e.g., 400 MHz or greater), while the internal read clocks might be at a lower frequency in order to align with typically slower FSM timings (e.g., approximately 67 MHz, 100 MHz, 133 MHz, 150 MHz, 167 MHz, 200 MHz, or another value). Accordingly, data may be written, for example, to IR bus and process buffer interface136, to process buffers134, and/or to additional registers or buffers of thestate machine engines14 much faster than the data may be read out. As a result, it is possible that read operations for a particular location in thestate machine engine14 may not be fully executed by the time subsequent write operations are presented to the same location. As may be appreciated, the size of the locations housing the data, e.g., the number of possible locations in the IR bus and process buffer interface136, and/or process buffers134), determines how quickly and how often such data collisions may occur. The IR bus register may be utilized to alleviate these potential collisions.
• In some embodiments, the IRbus control system160 may, for example, track and measure how many data locations of one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14 contain unread data and/or are empty at any given time. The IR bus andcontrol system160 may determine this information through a connection to the programminginstruction control system159. For example, signals may be received from the programminginstruction control system159 detailing data writes, data reads, and/or specific measurements related to the amount of data locations utilized in, for example, one or more buffers or registers (e.g., storage locations) of thestate machine engine14. In one embodiment, a series of logical flags may be set to indicate whether or not unread data is present at each given location of the one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14. These flags may be present in the IRbus control system160 itself, or in the IR bus register, and may map to (e.g., correspond to) each given location of the one or more buffers or registers of thestate machine engine14.
• Additionally, in some embodiments, the IRbus control system160 may utilize a storage flag related to the number of available (e.g., empty) data locations. Thus, the IRbus control system160 may monitor when available data locations (e.g., in the IR bus register) have been reduced to the point that an overflow condition is imminent. In some embodiments, this storage flag may be dynamically compared to a threshold value to determine if the value of the storage flag meets and/or exceeds the threshold value. If the storage flag meets and/or exceeds this threshold value, an overflow condition may be imminent (e.g., unread data locations to be overwritten). The checking of this storage flag against the threshold may be done at predetermined time intervals or as set occurrences are met (e.g., initialization of read or write commands). Moreover, the number of times that the storage flag is dynamically checked against a threshold value may be a function of the size of the one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14 and/or the difference in read/write clock frequencies that are present in thestate machine engine14. For example, the smaller the size of the one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14 and/or the larger the difference in read/write clock frequencies that are present in thestate machine engine14 may generate a greater number of dynamic checking operations by the IRbus control system160.
• When the IRbus control system160 determines that an overflow condition is imminent, the IRbus control system160 may generate an overflow signal that indicates that overwriting of a data location (e.g., an overflow condition) is to occur. This signal may represent, for example, that write operations should be paused in order to allow read operations to be performed, so as to produce empty data locations available for subsequent writes to, for example, the IR bus register. It should be noted that the terms pausing, ceasing, interrupting, and/or various forms thereof are all intended to be analogous to the term in the present disclosure. Moreover, the overflow signal may be internal to each of thestate machine engines14; however, each of thestate machine engines14 may generate a respective overflow signal concurrently.
• In some embodiments, the overflow signal may be transmitted to the programminginstruction control system159 and/or to an IR bus register in the IR bus and process buffer interface136 to institute a pause of the writing of data to one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14, so that data may be read out of one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14 and not overwritten. This pause of the writing of data may be internal to each of thestate machine engines14; however, each of thestate machine engines14 may pause the writing of data concurrently. In some embodiments, the IR bus andcontrol system160 may also determine the amount of data locations left in the one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14 and may transmit an indication to allow the one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14 to be filled to capacity (i.e. no empty data locations) before instituting the write pause. That is, if available data locations are present after an overflow condition is discovered to be imminent, the IRbus control system160 may allow the remaining free locations to be written before ceasing the write operations to the one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14. Once these remaining locations are filled, write operations are paused until a number of read operations necessary to empty all locations of the one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14. The IRbus control system160 may monitor the reading process and determine when all locations are empty. When this has occurred, the IRbus control system160 may generate a restart signal that allows write operations to restart.
• Because the IRbus control system160 detects an overflow condition and self-corrects by inducing a pause in write operations to allow the data to be read out completely, potential data corruption may be averted. The self-correcting nature of the IRbus control system160 allows all functions to be carried out concurrently (e.g., on both the masterstate machine engine14, e.g., state machine engine A, as well as on each slavestate machine engine14, e.g., state machine engine B, state machine engine C, state machine engine D), without the need to signal separate interrupt conditions and/or recover from additional latencies that might be present if eachstate machine engine14 was restarted due to the overwrite of data in any givenstate machine engine14.
• FIG.12 illustrates a process186 for interrupting and restarting an operation of astate machine engine14. In step188, the IRbus control system160 may receive an indication of an amount of data locations currently being utilized in one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14. In some embodiments, this indication may be saved in the IRbus control system160 as a storage flag. Instep190, the IRbus control system160 may perform a comparison of the indication of an amount of data locations currently being utilized in one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14 with a threshold. For example, this comparison of the indication may include a comparison of the storage flag indicative of the amount of data locations currently being utilized in one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14 with a threshold. Instep192, the IRbus control system160 may determine if the threshold is met and/or exceeded by the indication of an amount of data locations currently being utilized (e.g., the storage flag) in one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14. If the threshold is not met and/or exceeded instep192, the process may return to step188. If, however, the threshold is met and/or exceeded instep192, the IRbus control system160 may executestep194.
• Step194 ofFIG.12 may include generation of an overflow signal by the IRbus control system160. This overflow signal may indicate that an overwrite (e.g., an overflow) is imminent and may represent that, for example, write operations should be paused in order to allow read operations to be performed, so as to empty data locations for subsequent writes. Additionally, instep196, the IRbus control system160 may determine the amount of empty data locations present in the one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14. That is, a recognized overflow condition may be recognized, however, the IR bus andcontrol system160 may allow writes to open data locations to occur, if such writes will not cause overwriting of data present in the data locations. Instep198, the IR bus andcontrol system160 may transmit an indication to allow the one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14 to be filled to capacity (i.e. no empty data locations remain) or to a predetermined level less than capacity before instituting a write pause. That is, when available data locations are present, the IRbus control system160 may allow these locations to be written with data before ceasing the write operations to the one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14.
• Upon allowing the writing of data to the empty locations instep198, the IR bus andcontrol system160, instep200, may transmit a halt signal that pauses further writes (e.g., a write operation) to thestate machine engines14. Thus, a write operation, for example, to the one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14 may be halted until a number of read operations necessary to empty all locations of the one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14 is accomplished. The halting of the write operation may be internal to each of thestate machine engines14; however, each of thestate machine engines14 may generate the halt process concurrently. Instep202, the IRbus control system160 may monitor the reading process and determine when all locations of, for example, the one or more buffers or registers (e.g., the IR bus register) of thestate machine engine14 are empty. Upon determining that all data locations are empty, the IRbus control system160, instep204, may generate a restart signal that allows write operations to restart for thestate machine engines14. However, in some embodiments, instead of determining that all data locations are empty before generating a restart signal, the restart signal may be generated when a threshold number of data locations of, for example, the IR bus register become available. Moreover, the restart signal may be internal to each of thestate machine engines14; however, each of thestate machine engines14 may generate a respective restart signal concurrently.
• Effects of an embodiment of the present application can include dynamically detecting and self-correcting overflow conditions, which may be beneficial in a multi-chip master/slave system where an interrupt in onestate machine engine14 is acknowledged by every otherstate machine engine14 on theIR bus162. Moreover, any overwrite of data in a multi-chip master/slave system entails that all of thestate machine engines14 are re-synchronized and restarted, which may result in additional time delays (latencies) that could hamper overall performance. By aligning write operations of eachstate machine engine14 to a common clock signal on acommon IR bus162, eachstate machine engine14 may sense an overflow condition at the exact same point in time, thus allowing eachstate machine engine14 to sense and self-correct simultaneously. Subsequently, when write operations are re-initiated, allstate machine engines14, e.g., state machine A, state machine engine B, state machine engine C, state machine engine D) will contain empty buffers and/or registers and will concurrently be ready to receive new data. Additionally, by allowing write operations to continue until the data locations of the one or more buffers or registers of thestate machine engine14 is filled to capacity, a maximum amount of data to be transferred to eachstate machine engine14 may be accomplished prior to a pause operation, which may improve overall system throughput.
• While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims. Moreover, it should be noted that terms such as “responsive to,” “based upon,” or “based, at least in part, on” may, in some embodiments, encompass temporal phrases/actions such as when, after, and/or the like.

Claims (20)

What is claimed is:

1. A data analysis system, comprising:

a data buffer configured to receive data to be analyzed;

a state machine lattice comprising a plurality of configurable elements, wherein the configurable elements are configured to analyze at least a portion of the data as an analysis and to output a result of the analysis; and

a buffer interface configured to receive the data from the data buffer and to provide the at least a portion of the data to the state machine lattice for analysis.

2. The data analysis system ofclaim 1, comprising a second plurality of configurable elements configured to receive the result from the plurality of configurable elements.

3. The data analysis system ofclaim 2, wherein the second plurality of configurable elements are configured to analyze at least a portion of the result and to output a second result based upon analysis of the result.

4. The data analysis system ofclaim 3, comprising a second data buffer configured to receive the second result from the second plurality of configurable elements.

5. The data analysis system ofclaim 1, comprising a second data buffer configured to receive the result from the plurality of configurable elements.

6. The data analysis system ofclaim 1, comprising a host processor configured to receive the result from the plurality of configurable elements.

7. The data analysis system ofclaim 1, wherein each configurable element of the plurality of configurable elements comprises a plurality of memory cells.

8. A method, comprising:

receiving, at a buffer interface, data to be analyzed from a data buffer;

providing at least a portion of the data to a state machine lattice via the buffer interface;

analyzing the at least a portion of the data in a first set of configurable elements of the state machine lattice to generate a result; and

outputting the result from the configurable elements of the state machine lattice.

9. The method ofclaim 8, comprising receiving the result from the first set of configurable elements of the state machine lattice at the buffer interface and outputting the result from the buffer interface.

10. The method ofclaim 9, comprising receiving the result from the buffer interface at a second data buffer.

11. The method ofclaim 8, comprising receiving the result at a second set of configurable elements.

12. The method ofclaim 8, comprising receiving the result at a host processor.

13. The method ofclaim 8, comprising utilizing a plurality of memory cells of the first set of configurable elements to generate the result.

14. A system, comprising:

a host processor configured to initiate transmission of data to be analyzed;

a data buffer configured to transmit the data to be analyzed;

a buffer interface configured to receive the data from the data buffer; and

a state machine lattice coupled to the buffer interface to receive the at least a portion of the data, wherein the state machine lattice is configured to analyze the at least a portion of the data and to output a result.

15. The system ofclaim 14, wherein the state machine lattice comprises a plurality of configurable elements.

16. The system ofclaim 15, wherein each configurable element of the plurality of configurable elements comprises a memory cell.

17. The system ofclaim 15, wherein the state machine lattice comprises a second plurality of configurable elements configured to receive the at least a partial analysis result from the plurality of configurable elements, wherein the second plurality of configurable elements is configured to perform an analysis based at least in part on the partial analysis result to generate the result.

18. The system ofclaim 14, comprising a second data buffer configured to receive the result from the state machine lattice.

19. The system ofclaim 14, wherein the host processor is configured to receive the result from the state machine lattice.

20. The system ofclaim 14, wherein the data buffer is configured to receive and store the data to be analyzed.

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