US20230260562A1 - Memory device for reducing row hammer disturbance, and a method of refreshing the same - Google Patents

Abstract

A memory device includes a memory cell array connected to a plurality of wordlines and a plurality of bitlines; a row decoder configured to select a wordline, among the plurality of wordlines, in response to a row address; a column decoder configured to corresponding bitlines, among the plurality of bitlines, in response to a column address; a sense amplification circuit having a plurality of amplifiers connected to the selected corresponding bitlines; a row hammer detector configured to generate a refresh row address when the number of accesses to a row corresponding to the row address is a multiple of a predetermined value; and a refresh controller configured to perform a refresh operation on a row corresponding to the refresh row address. The row corresponding to the refresh row address is disposed adjacent to the row corresponding to the row address.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S)
• This application is a Continuation of U.S. patent application Ser. No. 17/408,454 filed on Aug. 22, 2021, now Allowed, which claims benefit of priority to Korean Patent Application No. 10-2021-0023900 filed on Feb. 23, 2021 in the Korean Intellectual Property Office, the disclosure of each of which is incorporated herein by reference in its entirety.
BACKGROUND
• The present inventive concept relates to a memory device and a method of operating the same.
• In general, a dynamic random access memory (DRAM) may perform a refresh operation to retain stored data. That is, the DRAM may retain data stored in a cell capacitor by the refresh operation. With the development of process technology such as an increase in a degree of integrity, a gap between cells of a DRAM is gradually being reduced. In addition, due to the reduction in the gap between cells, interference from adjacent cells or wordlines is increasingly acting as an important data reliability factor. Even if the above-described interference is concentrated on a specific cell, it may be difficult to restrict access to a specific address in a random access memory such as a DRAM. Accordingly, a disturbance may occur for a specific cell, and a refresh characteristic for such a cell may also be affected.
SUMMARY
• An aspect of the present inventive concept is to provide a memory device for reducing row hammer disturbance, and a method of operating the same.
• According to an aspect of the present inventive concept, a memory device includes a memory cell array having a plurality of memory cells disposed in a plurality of rows and a plurality of columns and connected to a plurality of wordlines and a plurality of bitlines; a row decoder selecting a wordline, among the plurality of wordlines, in response to a row address; a column decoder selecting corresponding bitlines, among the plurality of bitlines, in response to a column address; a sense amplification circuit having a plurality of amplifiers connected to the selected corresponding bitlines; a row hammer detector configured to receive the row address, and output a refresh row address generated from the row address when the number of accesses to a row corresponding to the row address is a multiple of a predetermined value; a refresh controller performing a refresh operation on a row corresponding to the refresh row address. The row corresponding to the refresh row address may be disposed adjacent to the row corresponding to the row address.
• According to an aspect of the present inventive concept, a method of operating a memory device including a plurality of memory cells disposed in a plurality of rows, the method includes receiving a row address; reading the number of row accesses and an overflow flag bit, corresponding to the row address; increasing the number of row accesses by 1; determining whether a modular calculated value for the increased number of row accesses is equal to zero, or the overflow flag bit is ‘1’; determining whether a buffer queue configured to store the row address is full, when the modular calculated value is equal to zero or the overflow flag bit is ‘1’; setting the overflow flag bit to ‘1,’ when the buffer queue is full; updating the increased number of row accesses and the overflow flag bit; and performing a refresh operation on a row corresponding to a refresh row address generated from the row address.
• According to an aspect of the present inventive concept, a method of operating a memory device including a plurality of memory cells disposed in a plurality of rows, the method includes receiving a row address; reading the number of row accesses corresponding to the row address; increasing the number of row accesses by 1; determining whether a modular calculated value for the increased number of row accesses is equal to zero; determining whether a buffer queue configured to store the row address is full, when the modular calculated value is equal to zero; retaining the number of row accesses, when the buffer queue is full; and performing a refresh operation on a row corresponding to a refresh row address generated from the row address.
BRIEF DESCRIPTION OF DRAWINGS
• The above and other aspects, features, and advantages of the present inventive concept will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:
• The accompanying drawings may be provided to aid understanding of this embodiment, and may provide embodiments along with a detailed description.
• FIG.1 is a view illustrating a general row hammer and an extended row hammer.
• FIG.2 is a view illustrating a memory device according to example embodiments.
• FIGS.3A and3B are views illustrating an RCNT storage unit according to example embodiments.
• FIG.4 is a flowchart illustrating a row hammer detection operation of a memory device according to example embodiments.
• FIG.5 is a view illustrating a memory device according to example embodiments.
• FIG.6 is a flowchart illustrating a row hammer detection operation of a memory device according to example embodiments.
• FIG.7 is graphs illustrating a simulation result between memory devices according to the present inventive concept and a conventional memory device.
• FIG.8 is a view illustrating a memory system according to example embodiments.
• FIG.9 is a flowchart illustrating a refresh operation of a memory system according to example embodiments.
• FIG.10 is a view illustrating a memory system according to example embodiments.
• FIG.11 is a view illustrating a mobile system according to example embodiments.
DETAILED DESCRIPTION
• In the following, the present inventive concept will be described clearly and in sufficient detail to be easily implemented by those of ordinary skill in the art referring to the drawings.
• A memory device according to the present inventive concept, and an operating method of the same, may reduce row hammer disturbance by using an overflow flag bit or by adjusting a value of an access count, to manage a missed row, when a row address is not stored due to an overflow of a buffer queue. As a result, the memory device of the present inventive concept may manage the disturbance on a low level, even when the overflow of the queue occurs. In the following embodiments, for convenience of description, the terms of the “row” and “row address” may be used interchangeably.
• FIG.1 is a view illustrating a row hammer RH and an extended row hammer ERH. Referring toFIG.1, memory cells MC may be connected between wordlines WLk-2, WLk-1, and WLk (k is an integer) and bitlines BL1 to BL4. In this case, the memory cell MC may be a volatile memory cell or a nonvolatile memory cell. In the following, for convenience of description, the memory cell MC may be a volatile memory cell having an access transistor and a cell capacitor. For example, a gate terminal of the access transistor of the memory cell MC may be connected to a corresponding wordline, and one terminal thereof may be connected to a bitline BL.
• In general, a selected wordline voltage (e.g., Vpp) may be provided to a selected wordline WLk during a read operation or a write operation. In this case, due to a capacitive coupling effect, a voltage of the adjacent wordlines (e.g., WLk-1 and WLk-2) may increase, even when the selected wordline voltage is not applied to the adjacent wordlines. This capacitive coupling may be illustrated as parasitic capacitances Cc1 and Cc2 between wordlines. When the selected wordline WLk is repeatedly accessed, charge may gradually leak from memory cells corresponding to the adjacent wordlines WLk-1 and WLk-2. A phenomenon for the nearest adjacent wordline WLk-1 may be referred to as the row hammer RH, and a phenomenon for the next adjacent wordline WLk-2 may be referred to as the extended row hammer ERH. A Patent Application of a technology for detecting and refreshing the row hammer was applied by Samsung Electronics, and is described in U.S. Pat. No. 9,087,602, which is incorporated by reference in this application.
• A memory device according to the present inventive concept may add an overflow flag bit OF_FLAG to manage a missed row (i.e., a missed row address), when an overflow occurs in a queue. For example, a row address stored in a queue (e.g., a buffer queue) may have an overflow flag bit OF_FLAG set to ‘0,’ and a row address not stored in a queue may have an overflow flag bit OF_FLAG set to ‘1.’ It should be understood that an overflow situation and values of the overflow flag bit may not be limited thereto.
• FIG.2 is a view illustrating amemory device100 according to example embodiments. Referring toFIG.2, amemory device100 may include anaddress buffer105, amemory cell array110, arow decoder120, acolumn decoder125, asense amplification circuit130, arefresh controller140, and arow hammer detector150.
• Thememory cell array110 may include a plurality of bank arrays. Each of the bank arrays may include a plurality of memory cells MC formed at portions at which a plurality of wordlines WL and a plurality of bitlines BL intersect each other. As illustrated inFIG.2, each of the plurality of memory cells may be implemented with a select transistor and a capacitor.
• Theaddress buffer105 temporarily stores an address ADD inputted from an external device (e.g., a memory controller). Theaddress buffer105 provides a row address R_ADD to therow decoder120 and a column address C_ADD to thecolumn decoder125. The address ADD in an external signaling scheme is converted into one in an internal signaling scheme of thememory device100 through theaddress buffer105.
• Therow decoder120 may be implemented to receive the row address R_ADD, decode the row address R_ADD, output a row address RA (e.g., a decoded row address RA), and activate a wordline corresponding to the row address RA. For example, the activated row decoder may select a wordline corresponding to the row address RA, and apply a wordline voltage to the selected wordline. In a refresh operation, therow decoder120 may receive a refresh row address RF_ADD from therefresh controller140.
• Thecolumn decoder125 may be implemented to receive a column address CA, select bitlines corresponding to the column address CA, and connect sense amplifiers corresponding to the selected bitlines.
• Thesense amplification circuit130 may include a plurality of sense amplifiers connected to a plurality of bitlines. Each of the plurality of sense amplifiers may be implemented to sense data corresponding to a bitline. For example, each of the sense amplifiers may be connected to a bitline and a complementary bitline. Each of the plurality of sense amplifiers may be implemented to write data to a memory cell connected to a selected bitline, or to sense stored data from the memory cell connected to the selected bitline. In addition, each of the plurality of sense amplifiers may be implemented to rewrite the stored data in the memory cell in a refresh operation.
• Therefresh controller140 may be implemented to control the refresh operation of thememory device100 in response to a refresh command. A command corresponding to a general auto refresh operation may be received through a combination of control signals (e.g., /RAS, /CAS, and/WE). A command decoder (not shown) may decode the received control signals to determine the refresh operation, and may transmit the refresh command to therefresh controller140. Therefresh controller140 may control therow decoder120 and thesense amplification circuit130 to perform the refresh operation on a selected region of thememory cell array110.
• In addition, therefresh controller140 may perform the refresh operation internally or in response to an external command, with respect to a refresh row address RF_ADD corresponding to a detection signal.
• In addition, when performing the refresh operation, therefresh controller140 may receive information on whether or not storage capacity is empty, from a rowaddress storage unit153. When storage capacity is empty, therefresh controller140 may refresh row lines (or wordlines) in a predetermined order. In this case, the rowaddress storage unit153 may provide an empty flag bit EMPTY_FLAG as ‘1’. When storage capacity is not empty, therefresh controller140 may receive a refresh row address RF_ADD from the rowaddress storage unit153, and may refresh one or more wordlines corresponding to the refresh row address RF_ADD. In this case, the rowaddress storage unit153 may provide the empty flag bit EMPTY_FLAG as ‘0’.
• In other example embodiments, therefresh controller140 may receive the row address RA from the rowaddress storage unit153 and generate a refresh row address RF_ADD corresponding to the one or more wordlines adjacent to the specific wordline of the row address RA.
• Therow hammer detector150 may be implemented to receive the row address RA and output the refresh row address RF_ADD and the empty flag bit EMPTY_FLAG.
• Therow hammer detector150 may include anRCNT storage unit151, anaccess counter152, the rowaddress storage unit153, an overflowflag storage unit154, and anoverflow controller155.
• TheRCNT storage unit151 may be implemented to store a row access count RCNT (i.e., the number of row accesses) corresponding to the received row address RA. Herein, for convenience of description, the terms of the row access count RCNT and row access count value RCNT may be used interchangeably. In an embodiment, theRCNT storage unit151 may store a row access count RCNT per row. For example, theRCNT storage unit151 may store the number of accesses to a specific row (e.g., a wordline). In another embodiment, theRCNT storage unit151 may store a row access count RCNT per row group. For example, theRCNT storage unit151 may store the number of accesses to a specific cell region (e.g., wordlines).
• Theaccess counter152 may be implemented to read a row access count RCNT corresponding to the row address RA from theRCNT storage unit151, and increase the row access count RCNT for the row address RA. Also, theaccess counter152 may output the increased access count RCNT to be stored in theRCNT storage unit151.
• In an embodiment, theaccess counter152 may receive the number of row accesses (X, i.e., a row access count RCNT) from theRCNT storage unit151, and may increase the number of row accesses by 1 (i.e., X+1). In addition, theaccess counter152 may transmit the increased number of row accesses (X+1) to theRCNT storage unit151. In an embodiment, when the increased number of row accesses (X+1) matches a reference value, theaccess counter152 may transmit a row address RA to the rowaddress storage unit153. Herein, the term “match” may be referred to as “equal to” or “multiple of”.
• In an embodiment, the reference value may vary according to an operation mode. The operation mode may mutually share a buffer queue (e.g., a row address storage unit) storing the row address RA. In another embodiment, the reference value may be constant regardless of the operation mode.
• The rowaddress storage unit153 may be implemented to store the row address RA output from theaccess counter152 or a row address RA output from theoverflow controller155. In an embodiment, the rowaddress storage unit153 may include at least one register. The rowaddress storage unit153 may generate and store a refresh row address RF_ADD corresponding to one or more wordlines adjacent to a specific wordline corresponding to the row address RA and store the generated refresh row address RF_ADD. In this case, the rowaddress storage unit153 may provide the refresh row address RF_ADD to therefresh controller140. In other example embodiments, therefresh controller140 may generate the refresh row address RF_ADD based on the received row address RA from the rowaddress storage unit153.
• In addition, when the row address RA is input, the rowaddress storage unit153 may determine whether storage capacity of the rowaddress storage unit153 is full, and may transmit corresponding information to theoverflow controller155. In this case, the rowaddress storage unit153 may provide the overflow flag bit OF_FLAG as ‘1’ to theoverflow controller155. When storage capacity is not full, the rowaddress storage unit153 may store the received row address RA or a refresh row address RF_ADD corresponding to the received row address RA which the number of accesses matches the reference value. In this case, the rowaddress storage unit153 may provide the overflow flag bit OF_FLAG as ‘0’ to theoverflow controller155.
• In addition, in a refresh operation, the rowaddress storage unit153 may determine whether or not storage capacity is empty, and may transmit corresponding information to therefresh controller140. When storage capacity is not empty (e.g., the EMPTY_FLAG is ‘0’) in a refresh operation, the rowaddress storage unit153 may transmit some or all of the stored row addresses RA or refresh row addresses RF_ADD to therefresh controller140, and may remove the transmitted row addresses RA or refresh row addresses RF_ADD from the rowaddress storage unit153.
• The overflowflag storage unit154 may be implemented to receive the row address RA and store an overflow flag bit OF_FLAG corresponding to the row address RA. For example, the overflowflag storage unit154 may store ‘0’ for rows stored in a queue (e.g., a row address storage unit153), and may store ‘1’ for missed rows not stored in the queue.
• Also, when access to a row occurs, the overflowflag storage unit154 may output a received row address RA and an overflow flag bit OF_FLAG corresponding to the received row address RA, to theoverflow controller155.
• In addition, the overflowflag storage unit154 may receive and store an overflow flag bit OF_FLAG from theoverflow controller155.
• Theoverflow controller155 may receive a row address RA and an overflow flag bit OF_FLAG from the overflowflag storage unit154, and may determine whether or not the row address RA is provided to the rowaddress storage unit153 in response to the overflow flag bit OF_FLAG.
• When the overflow flag bit OF_FLAG is ‘1,’ theoverflow controller155 may transmit the row address RA to the rowaddress storage unit153.
• In an embodiment, after receiving information on whether or not storage capacity is full of the rowaddress storage unit153, when the storage capacity is full, theoverflow controller155 may set the overflow flag bit OF_FLAG as ‘1,’ and the set overflow flag bit OF_FLAG as ‘1’ may be transmitted to the overflowflag storage unit154.
• In an embodiment, after receiving information on whether or not storage capacity is full of the rowaddress storage unit153, when the storage capacity is not full, the rowaddress storage unit153 may set the overflow flag bit OF_FLAG as ‘0,’ and the set overflow flag bit OF_FLAG as ‘0’ may be transmitted to the overflowflag storage unit154.
• In example embodiments thememory device100 may manage a missed row address by indicating an overflow flag bit OF_FLAG without increasing an area, when there is no empty space in the rowaddress storage unit153 to store a row address corresponding to row hammer/extended row hammer such that thememory device100 may reduce row hammer disturbance.
• FIGS.3A and3B are views illustrating anRCNT storage unit151 according to example embodiments. In an embodiment, as illustrated inFIG.3A, anRCNT storage unit151 may include storage units ST1 to ST8 storing a row access count RCNT per wordline corresponding to a row address RA. In this case, each of the storage units ST1 to ST8 may include at least one count cell implemented to have a structure, identical to those of a memory cell MC.
• In another embodiment, as illustrated inFIG.3B, anRCNT storage unit151 may include two groups of storage units GST1 and GST2 storing a row access count RCNT per group of wordlines corresponding to a row address RA.
• FIG.4 is a flowchart illustrating a row hammer detection operation of amemory device100 according to example embodiments. Referring toFIGS.2 to4, a row hammer detection operation of amemory device100 may be performed as follows.
• A row address RA may be received (S110). A row access count RCNT and an overflow flag bit OF_FLAG, corresponding to the row address RA, may be read (S120). Anaccess counter152 may count-up the read row access count RCNT (S130). Thereafter, a modular operation for the row access count RCNT may be performed. For example, in S140, if the row access count RCNT is 200 and a predetermined value PDV as modulus is 100 the remainder is 0. In this case, it may be expressed as (200mod 100=0). It may be determined whether or not the modular calculated value is zero or the read overflow flag bit OF_FLAG is ‘1’ (S140). For example, when the row access count value RCNT is a multiple of the predetermined value PDV the remainder is zero.
• When the modular calculated value is zero or the read overflow flag bit OF_FLAG is 1,′ it may be determined whether or not a buffer queue is full (S150). In this case, the buffer queue may be the rowaddress storage unit153 illustrated inFIG.2. When the buffer queue is full, the overflow flag bit OF_FLAG may become ‘1’ (S160), and S170 may be performed. When the buffer queue is not full, the row address RA RA may be stored and may generate the refresh row address RF_ADD in the buffer queue, the overflow flag bit OF_FLAG may become ‘0,’ and S170 will be performed.
• When the modular calculated value is not zero or the read overflow flag bit OF_FLAG is not ‘1,’ S170 may proceed. For example, in S140, if the row access count RCNT is 210 and a predetermined value PDV as modulus is 100 the remainder is 10 (i.e., not zero). In this case, it may be expressed as (210mod 100=10), and the row access count value RCNT is not a multiple of the predetermined value PDV.
• In S170, the row access count RCNT and the overflow flag bit OF_FLAG may be updated (S170).
• A row hammer detector150 (refer toFIG.2) according to the present inventive concept may express a missed row address not stored in a buffer queue due to occurrence of overflow (i.e., when the rowaddress storage unit153 is full) as an overflow flag bit, and may thus input the row address in the buffer queue when the next access occurs corresponding to the row address. In an embodiment, a row access count value and an overflow flag bit may be stored per row. When accessing a row, the row access count value may be increased by 1. When the overflow flag bit is ‘1’ or the row access count value is a multiple of a specific reference value, a corresponding row address RA may be transmitted to the buffer queue. For example, theaccess counter152 may transmit the row address RA to the rowaddress storage unit153 when the increased number of row accesses (X+1) matches (or is multiple of) the reference value (or, the predetermined value PDV). For example, theoverflow controller155 may transmit the row address RA to the rowaddress storage unit153 when the overflow flag bit OF_FLAG of the row address RA is ‘1’. When there is an empty space in the buffer queue, the row address RA may be stored in the buffer queue, and the overflow flag bit OF_FLAG may be set to ‘0.’ When the buffer queue is full, the row address RA may not be input, and the overflow flag bit OF_FLAG may be set to ‘b1.’
• In example embodiments, a memory device according to the present inventive concept may be implemented by adjusting an access count value without using an overflow flag bit. For example, the memory device may increase an access count value in case of a row address input to theRCNT storage unit151, may retains the access count value in case of a row address not input to the queue, and may transmit a corresponding row address to the queue when accessing a missed row.
• FIG.5 is a view illustrating amemory device100aaccording to example embodiments. Referring toFIG.5, amemory device100amay be implemented to detect RH/ERH without storing an overflow flag bit, as compared to thememory device100 illustrated inFIG.2.
• Arow hammer detector150amay include anRCNT storage unit151a, anaccess counter152a, a rowaddress storage unit153a, and anoverflow controller155a.
• TheRCNT storage unit151amay be implemented to store a row access count RCNT corresponding to a received row address RA.
• Theaccess counter152amay be implemented to read a row access count RCNT corresponding to a row address RA from theRCNT storage unit151a, and increase a row access count RCNT for the row address RA. Also, theaccess counter152amay output the increased row access count RCNT to be stored in theRCNT storage unit151a. Also, theaccess counter152amay transmit the row access count RCNT to theoverflow controller155a, and may receive the row access count RCNT from theoverflow controller155a.
• In addition, theaccess counter152amay receive the number of row accesses (X) from theRCNT storage unit151a, and may increase the number of row accesses (X) by 1 (i.e., X+1). When the increased number of row accesses (X+1) is less than a reference value (or a predetermined value PDV), theaccess counter152amay transmit the increased number of row accesses (X+1) to theRCNT storage unit151a. When the increased number of row accesses (X+1) matches the reference value, theaccess counter152amay transmit the row address RA to the rowaddress storage unit153a. In addition, when the increased number of row accesses (X+1) matches the reference value, theaccess counter152amay transmit the increased number of row accesses (X+1) to theoverflow controller155a. In addition, when the increased number of row accesses (X+1) matches the reference value, theaccess counter152amay receive the number of changed row accesses from theoverflow controller155a, and may store the number of received row accesses in theRCNT storage unit151a.
• The rowaddress storage unit153amay be implemented to store the refresh row address RF_ADD generated from the row address RA received from theaccess counter152a. In other example embodiments, the rowaddress storage unit153amay store the the row address RA received from theaccess counter152a.
• Theoverflow controller155amay receive a row access count RCNT from theaccess counter152a, may receive an overflow flag bit OF_FLAG from the rowaddress storage unit153a, and may output a row access count RCNT to theaccess counter152a.
• In an embodiment, after receiving information on whether or not storage capacity is full of the rowaddress storage unit153a, when the storage capacity is not full, theoverflow controller155amay transmit the number of row accesses (X+1), received from theaccess counter152a, to theaccess counter152a.
• In an embodiment, after receiving information on whether or not storage capacity is full of the rowaddress storage unit153a, when the storage capacity is full, theoverflow controller155amay decrease the number of row accesses (X+1), received from theaccess counter152a, by 1, and may transmit the decreased number of row accesses (X) to theaccess counter152a.
• In example embodiments, thememory device100amay manage a missed row address by adjusting the number of row accesses, when there is no empty space in the rowaddress storage unit153ato store a row address RA or a refresh row address RF_ADD corresponding to row hammer/extended row hammer such that thememory device100amay reduce row hammer disturbance.
• FIG.6 is a flowchart illustrating a row hammer detection operation of amemory device100aexample embodiments. Referring toFIGS.5 and6, a row hammer detection operation of amemory device100amay be performed as follows.
• A row address RA may be received (S210). A row access count RCNT (X) corresponding to the row address RA may be read (S220). Anaccess counter152amay increase the read row access count RCNT (X+1) (S230). Thereafter, it may be determined whether or not the modular calculated value is zero (S240). For example, when the row access count value RCNT is a multiple of the predetermined value PDV the remainder is zero.
• When the modular calculated value for the increased row access count RCNT (X+1) is equal to or multiple of the predetermined value PDV, it may be determined whether or not a buffer queue is full (S250). When the buffer queue is not full, the row address RA may be stored in the buffer queue (S260), and S270 may be performed. When the buffer queue is full, a row accesscount storage unit151amay retain a current row access count RCNT (i.e., X) (S275).
• When the modular calculated value for the increased row access count RCNT is not zero, S270 may be performed. The row access count RCNT increased in S270 may be updated in the row accesscount storage unit151a.
• Arow hammer detector150aof amemory device100aaccording to the present inventive concept may retain a current row access count value (e.g., X), without increasing a row access count RCNT, to a missed row in a buffer queue due to occurrence of overflow, and may thus input the row in the buffer queue when the next access occurs corresponding to the row address RA. In an embodiment, a row access count value may be stored per row. When accessing a row, the row access count value may be increased by 1. When the number of row accesses is a multiple of a specific threshold value, a corresponding row address RA may be transmitted to the buffer queue. When there is an empty space in the buffer queue, the row address RA may be stored in the buffer queue, and a row access count value increased by 1 may be stored in theRCNT storage unit151a. When the buffer queue is full and the row address RA may not be input, the read row access count value may be stored in theRCNT storage unit151a.
• FIG.7 is graphs illustrating a simulation result between memory devices according to the present inventive concept and a conventional memory device. Referring toFIG.7, it can be seen that a problem of large disturbance of rows in a specific number of rows/ACTs may be solved by implementing of the present inventive concepts. For example, in the present inventive concepts, the disturbance may be decreased below 1K. Herein, the disturbance 1K means that a row is not in a refresh state until a specific row is accessed 1K in a predetermined period. In the graphs ofFIG.7, a horizontal axis represents a number of attack rows, a vertical axis represents the maximum row disturbance in a unit K. Referring toFIG.7, the maximum row disturbance may be reduced as shown in a first graph G1 illustrating a simulation result according to the embodiment ofFIG.2 and a second graph G2 illustrating a simulation result according to the embodiment ofFIG.5. Herein, an attack row may mean that the access to a specific row is concentrated during a predetermined period. According to example embodiments, the maximum disturbance may be reduced under 1K from 10K to 150K as shown inFIG.7.
• When access counts are accumulated and managed per row, a memory device according to the present inventive concept may perform a refresh operation in which an address of a row of which access count is a multiple of a specific value is input into a queue, and is managed. As a result, when a missed row not input to the queue occurs due to insufficient space in the queue, a corresponding row may not be managed as a refresh state, and high disturbance may be thus affected. In particular, a reason for not initializing when an access count reaches a threshold value may be that ERH management may be efficient since an address of a row of which access count is a multiple of a specific value is input into a queue. A memory device according to the present inventive concept may manage hammer disturbance at a low level, even when overflow of a queue occurs.
• FIG.8 is a view illustrating amemory system10 according to example embodiments. Referring toFIG.8, amemory system10 may include amemory device100 and amemory controller200.
• Thememory device100 may include arow hammer detector150 detecting the row hammer or the extended row hammer, illustrated inFIGS.1 to7. Thememory device100 may detect whether or not disturbance is concentrated on a specific address in an operation period in which a refresh operation is not performed. Alternatively, thememory device100 may detect whether or not disturbance is concentrated on a specific address in an operation period in which frequency of occurrence of a refresh operation is relatively low. When the number of detected disturbances exceeds a threshold value, thememory device100 may output a warning signal externally. In this case, the warning signal may be a signal output through a specific pin, or may be data output in a data format.
• Thememory device100 may receive a refresh command from thememory controller200, after outputting the warning signal externally. Thememory device100 may perform a refresh operation in response to the refresh command from thememory controller200. For example, the refresh operation may be continuously performed on wordlines adjacent to a wordline on which disturbance is concentrated. Thememory device100 may perform a refresh operation on a corresponding wordline in response to a refresh command from thememory controller200. After thememory device100 outputs the warning signal externally, thememory device100 may perform a refresh operation on its own, without receiving the refresh command from thememory controller200.
• Thememory controller200 may provide an interfacing between a host and thememory device100. Thememory controller200 may communicate data and signals with thememory device100 by control signal lines (e.g., lines for /RAS, /CAS, and /WE), an address line (ADD), data lines (DQ), a warning signal line, and the like. In particular, thememory controller200 may transmit a refresh command with reference to the warning signal provided from thememory device100. For example, when the warning signal output from thememory device100 is activated, thememory controller200 may transmit an auto refresh command set by control signals (e.g., /RAS, /CAS, and /WE) to thememory device100.
• Thememory controller200 may transmit a command set provided to thememory device100 with reference to the control signals (e.g., /RAC, /CAS, /WE). In a typical DRAM, an active command and an auto refresh command may be determined by a combination of the control signals (e.g., /CS, /RAC, /CAS, /WE). In addition, a self refresh command may be identified by a combination of an auto refresh command and a clock enable signal. It should be understood that a refresh command issued by amemory controller200 of the present inventive concept is not limited thereto.
• In a memory system including amemory device100 and amemory controller200 of the present inventive concept, when disturbance is concentrated on a specific memory region, a refresh operation on a memory region on which interference is concentrated may be forcibly performed. To this end, thememory device100 may detect the number or magnitude of the disturbance. When the disturbance reaches a threshold value, thememory device100 may output a warning signal externally. Then, thememory controller200 may determine the warning signal as a refresh request and may provide a refresh command to thememory device100. Thememory device100 may perform a refresh operation on a memory region internally excessively exposed to interference, without providing a refresh command from thememory controller200.
• FIG.9 is a flowchart illustrating a refresh operation of a memory system according to example embodiments. Referring toFIGS.8 and9, a refresh operation may be performed as follows.
• When accessing a row address according to a write operation or a read operation, arow hammer detector150 may read an address count corresponding to the accessed row address, and may perform a modular operation on the read address count (S310). The row hammer detector may detect row hammer or extended row hammer according to a modular calculated value (S320). A refresh operation may be performed on a row address corresponding to the detected row hammer or the detected extended row hammer (S330).
• FIG.10 is a view illustrating amemory system1000 according to an example of example embodiments. Referring toFIG.10, amemory system1000 may include amemory controller1100 and amemory module1200.
• Thememory module1200 may include a register clock driver1210, memory devices1220, and data buffers1230. For example, the register clock driver1210 may be implemented using a system on chip (SoC), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or the like. For example, each of the memory devices1220 may be implemented in the form of a chip or a package.
• The register clock driver1210 may receive a command CMD and an address ADD from thememory controller1100. The register clock driver1210 may transmit an internal command ICMD and an internal address IADD, based on the command CMD and the address ADD, respectively, to the memory devices1220. For example, the register clock driver1210 may transmit the command CMD and the address ADD as an internal command ICMD and an internal address IADD, respectively, as they are to the memory devices1220, or may generate an internal command ICMD and an internal address IADD, based on the command CMD and the address ADD, respectively, and transmit the generated internal command ICMD and the generated internal address IADD to the memory devices1220. For example, the register clock driver1210 may generate an internal command ICMD and an internal address IADD for a row hammer refresh operation, based on the command CMD and the address ADD.
• Each of the memory devices1220 of thememory module1200 may operate based on an internal command ICMD and an internal address IADD. For example, each of the memory devices1220 may correspond to thememory device100 or100adescribed with reference toFIGS.1 and9. When each of the memory devices1220 corresponds to thememory device100 or100adescribed with reference toFIGS.1 to9, and each of the memory devices1220 does not store a row address due to overflow of a buffer queue, missed rows may be managed by using an overflow flag bit or by adjusting an access count value. Also, each of the memory devices1220 may generate a refresh control signal and a row address for a row hammer refresh operation based on the internal command ICMD and the internal address IADD.
• Each of the memory devices1220 may perform a refresh operation based on the generated refresh row address RF_ADD. Each of the memory devices1220 may perform a refresh operation based on an internal command ICMD and an internal address IADD, generated for a row hammer refresh operation.
• The memory devices1220 of thememory module1200 may share a path for receiving an internal command ICMD and an internal address IADD. As another example, first memory devices1220 of the memory module1200 (for example, memory devices disposed on one side based on the register clock driver1210) may share a first path for receiving an internal command ICMD and an internal address IADD. Second memory devices1220 of the memory module1200 (e.g., memory devices disposed on the other side based on the register clock driver1210) may share a second path for receiving an internal command ICMD and an internal address IADD.
• Each of the memory devices1220 may communicate a data signal DQ with thememory controller1100 through each of the data buffers1230. Each of the memory devices1220 may communicate the data signal DQ with thememory controller1100 to exchange data with thememory controller1100. For example, the memory devices1220 may be accessed by thememory controller1100 in parallel. Although nine (9) memory devices1220 are illustrated inFIG.10, it should be understood that the number of memory devices1220 is not limited thereto.
• FIG.11 is a view illustrating amobile system2000 according to example embodiments. Referring toFIG.11, amobile system2000 may include acamera2100, adisplay device2200, anaudio processing device2300, an input/output device2400, amemory device2500, astorage device2600, anantenna2700, and an application processor (AP)2800. In this case, themobile system2000 may be implemented as a laptop computer, a portable terminal, a smartphone, a tablet personal computer (PC), a wearable device, a healthcare device, or an IoT device. In addition, themobile system2000 may be implemented as a server or a personal computer.
• Thecamera2100 may capture an image or a video according to a user's control. Thecamera2100 may communicate with the AP2800 through acamera interface2870.
• Thedisplay device2200 may be implemented in various forms, such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an active-matrix OLED (AM-OLED), a plasma display panel (PDP), and the like. In an embodiment, thedisplay device2200 may be used as an input device of themobile system2000 by receiving an input signal through a user's touch. Thedisplay device2200 may communicate with the AP2800 through adisplay interface2860.
• Theaudio processing device2300 may process audio data included in contents transmitted from thememory device2500 or thestorage device2600. For example, theaudio processing device2300 may perform various types of processing such as encoding/decoding, noise filtering, and the like on audio data.
• The input/output device2400 may include devices providing digital input and output functions such as a device generating input from a user, a universal serial bus (USB), a storage, a digital camera, a secure digital (SD) card, a DVD, a network adapter, and the like. Theaudio processing device2300 and the input/output device2400 may communicate with the AP2800 through aperipheral device interface2850.
• The AP2800 may control an overall operation of themobile system2000 with a central processing unit2810. For example, the AP2800 may control thedisplay device2200 such that a portion of contents stored in thestorage device2600 may be displayed on thedisplay device2200. Also, when a user's input is received by the input/output device2400 or the like, the AP2800 may perform a control operation corresponding to the user's input. In addition, the AP2800 may include abus2890, and various components such as a central processing unit2810, amemory interface2830, astorage interface2840, aperipheral device interface2850, adisplay interface2860, acamera interface2870, and the like may be connected to each other through thebus2890.
• The AP2800 may be implemented as a system-on-chip (SoC) that drives an application program, an operating system (OS) and the like. Alternatively, the AP2800 and other semiconductor components (e.g., thememory device2500 and the storage device2600) may be mounted based on various types of packaging techniques. For example, the AP2800 and other semiconductor components may be mounted using packaging techniques such as a package-on-package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), a system-in-package (SIP), a multi-chip package (MCP), a wafer-level fabricated package (WFP), a wafer-level processed stack package (WSP), and the like.
• In an embodiment, the AP2800 may further include an accelerator2820. The accelerator2820 may be a functional block performing a specific function of the AP2800. For example, the accelerator2820 may include a graphics processing unit (GPU), which may be a functional block for processing graphic data, a neural processing unit (NPU), which may be a function block for performing an AI operation (for example, training and/or inference), or the like.
• In an embodiment, the AP2800 may include amodem2880, or may include a modem chip separately located outside the AP2800. Themodem2880 may transmit and receive wireless data through theantenna2700, may modulate a signal transmitted from theantenna2700, or may demodulate a signal received through theantenna2700.
• In an embodiment, the AP2800 may include amemory interface2830 for communication with thememory device2500. A memory controller for controlling thememory device2500 may be embedded in thememory interface2830. Therefore, thememory device2500 may be directly connected to the AP2800. For example, the memory controller embedded in thememory interface2830 may change read/write memory commands issued from the central processing unit2810, the accelerator2820, themodem2880, or the like to a command for controlling thememory device2500, to control thememory device2500.
• The AP2800 may communicate with thememory device2500 based on a predetermined interface protocol. For example, the AP2800 may communicate with thememory device2500 based on an interface conforming to the JEDEC standards, such as LPDDR4, LPDDR5, and the like. In addition, the AP2800 may communicate with thememory device2500 based on an interface conforming to the high-bandwidth JEDEC standards such as HBM, HMC, and Wide I/O.
• In an embodiment, thememory device2500 may be implemented based on a DRAM. However, the present inventive concept may not be limited thereto, and thememory device2500 may be implemented based on a PRAM, an SRAM, an MRAM, an RRAM, an FRAM, or a hybrid RAM. Thememory device2500 may have a lower latency and a narrower bandwidth, as compared to the input/output device2400 or thestorage device2600. Thememory device2500 may be initialized when themobile system2000 is powered on, and an operating system and application data may be loaded into thememory device2500. Therefore, thememory device2500 may be used as a temporary storage location for the operating system and the application data, or may be used as an execution space for various software codes.
• In an embodiment, thememory device2500 may correspond to thememory device100 or100adescribed with reference toFIGS.1 to9. For example, when a row address may not be stored due to overflow of a buffer queue, thememory device2500 may use an overflow flag bit or adjust an access count value to manage a missed row.
• In an embodiment, the AP2800 may include astorage interface2840 for communication with thestorage device2600. Therefore, thestorage device2600 may be directly connected to the AP2800. For example, thestorage device2600 may be implemented as a separate chip, and the AP2800 and thestorage device2600 may be assembled as a single package. For example, thestorage device2600 may be implemented based on a NAND flash memory, but the present inventive concept is not limited thereto.
• In a memory device according to the present inventive concept, when the number of accesses per row is measured and a number of rows concentratedly accessed exceed row address storage capacity, disturbance of corresponding rows may be reduced to prevent the occurrence of errors. Therefore, reliability of the memory device may be improved.
• In an embodiment, even when a row exceeding a threshold value exceeds row address storage capacity, corresponding rows may be detected and refreshed, to manage disturbance of the corresponding rows. In an embodiment, when the number of rows exceeding the threshold value exceeds row address storage capacity, and a missed row occurs in a row address storage unit, corresponding rows may be managed by a separate logic to manage disturbance on a low level.
• When access to a row occurs, an access count storage unit according to the present inventive concept may output a row access count and a row address to an access counter. In an embodiment, the storage unit may receive and store the row access count from the access counter. In an embodiment, a row access count may be increased (X+1) by receiving a row access count (X) from the access count storage unit. In an embodiment, the increased row access count (X+1) may be transmitted to the access count storage unit. In an embodiment, when the increased row access count matches a threshold value, the row address may be transmitted to the row address storage unit.
• According to the present inventive concept, when a row address is input, a row address storage unit may determine whether or not storage capacity is full, and may transmit corresponding information to an overflow controller. In an embodiment, when storage capacity is not full, the row address storage unit may store a received row address. In an embodiment, the row address storage unit may determine whether or not storage capacity is zero when refreshing, and may transmit corresponding information to a refresh controller. In an embodiment, when storage capacity is not zero when refreshing, the row address storage unit may transmit some or all of stored row addresses to the refresh controller, and the transmitted row addresses may be removed from the storage address.
• A refresh controller according to the present inventive concept may receive from a row address storage unit whether or not storage capacity is zero when refreshing. In an embodiment, when storage capacity of the storage unit is zero, the refresh controller may refresh rows in a predetermined order. In an embodiment, when storage capacity of the storage unit is not zero, the refresh controller may receive a row address from the storage unit, and may refresh corresponding rows.
• An overflow flag storage unit according to the present inventive concept may output an overflow flag bit value and a row address to an overflow controller, when access to a row occurs. In an embodiment, the overflow flag storage unit may receive and store the overflow flag bit from the overflow controller.
• An overflow controller according to the present inventive concept may receive an overflow flag bit and a row address from an overflow flag storage unit and, when the overflow flag bit is 1, may transmit the row address to a row address storage unit. In an embodiment, after receiving an input from the row address storage unit whether or not storage capacity is full, when storage capacity is full, the overflow controller may set the overflow flag bit as 1 and may transmit the same to the overflow flag storage unit. In an embodiment, after receiving an input from the row address storage unit whether or not storage capacity is full, when storage capacity is not full, the overflow controller may set the overflow flag bit as 0 and may transmit the same to the overflow flag storage unit.
• An access counter according to another embodiment of the present inventive concept may receive a row access count (X) from an access count storage unit, and may increase the row access count (X+1). In an embodiment, when the increased row access count is less than a threshold value, the access counter may transmit the increased row access count (X+1) to the access count storage unit. In an embodiment, when the increased row access count matches the threshold value, the access counter may transmit a row address to a row address storage unit. In an embodiment, when the increased row access count matches the threshold value, the access counter may transmit the increased row access count to an overflow controller. In an embodiment, when the increased row access count matches the threshold value, the access counter may receive a changed row access count from the overflow controller, and may transmit the same to the access count storage unit.
• After receiving an input from a row address storage unit whether or not storage capacity is full, when storage capacity is not full, an overflow controller according to another embodiment of the present inventive concept may transmit a row access count received from an access counter to the access counter. In an embodiment, after receiving an input from a row address storage unit whether or not storage capacity is full, when storage capacity is full, the overflow controller may decrease a row access count received from the access counter by 1 and may transmit the same to the access counter.
• In a memory device according to the present inventive concept, and a method of operating the same, row hammer disturbance may be decreased by using an overflow flag bit or by adjusting an access count in a queue overflow situation.
• In addition, a memory device according to the present inventive concept, and a method of operating the same may prevent a row hammer attack to improve reliability of data.
• While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concept as defined by the appended claims.

Claims (20)

What is claimed is:

1. A memory device comprising:

a memory cell array including a plurality of memory cells disposed in a plurality of rows and a plurality of columns and connected to a plurality of wordlines and a plurality of bitlines;

a row decoder configured to receive a row address to activate a wordline corresponding to the row address, among the plurality of wordlines;

a row address storage unit;

an access counter configured to:

obtain an increased access count based on a row access count corresponding to the row address,

in response to the increased access count not reaching a reference value, update the row access count corresponding to the row address with the increased access count,

in response to the increased access count reaching the reference value and the row address storage unit having an empty space for the row address, cause the row address storage unit to store a refresh row address generated from the row address, and

in response to the increased access count reaching the reference value and the row address storage unit having no empty space for the row address, retain the row access count corresponding to the row address; and

a refresh controller configured to perform a refresh operation based on the refresh row address stored in the row address storage unit.

2. The memory device ofclaim 1, wherein the access counter is further configured to obtain the increased access count by increasing the row access count by 1.

3. The memory device ofclaim 1, wherein the reference value includes a multiple of a predetermined value.

4. The memory device ofclaim 1, further comprising:

a row count (RCNT) storage unit including a plurality of storage units, each of the plurality of storage unit configured to store a row access count of at least one corresponding wordline among the plurality of wordlines,

wherein the access counter is further configured to read the row access count corresponding to the row address from the RCNT storage unit.

5. The memory device ofclaim 4, wherein each of the plurality of storage units includes at least one count cell having the same structure as a memory cell of the plurality of memory cells.

6. The memory device ofclaim 1, wherein the refresh controller is further configured to perform the refresh operation on at least one of wordlines adjacent to the wordline corresponding to the row address.

7. The memory device ofclaim 1, wherein the row address storage unit is configured to transfer the refresh row address to the refresh controller for the refresh operation and delete the transferred refresh row address from the row address storage unit.

8. A memory device comprising:

a memory cell array including a plurality of memory cells disposed in a plurality of rows and a plurality of columns and connected to a plurality of wordlines and a plurality of bitlines;

a row decoder configured to receive a row address to activate a wordline corresponding to the row address, among the plurality of wordlines;

a row count (RCNT) storage unit including a plurality of storage units, each of the plurality of storage unit configured to store a row access count of at least one corresponding wordline among the plurality of wordlines;

an access counter configured to:

increase the row access count corresponding to the row address stored in the RCNT storage unit, and

in response to the increased row access count reaching a reference value, output a refresh row address based on the row address;

an overflow controller configured to output the refresh row address in response to an overflow flag bit corresponding to the row address having a predetermined bit value;

a row address storage unit configured to store the refresh row address in response to the row address storage unit having an empty space for the row address; and

a refresh controller configured to perform a refresh operation based on the refresh row address stored in the row address storage unit,

wherein the overflow controller is configured to set the overflow flag bit corresponding to the row address as the predetermined bit value in response to the row address storage unit having no empty space for the row address.

9. The memory device ofclaim 8, wherein the predetermined bit value is 1.

10. The memory device ofclaim 9, wherein the overflow controller is further configured to, in response to the refresh row address being stored in the row address storage unit, set the overflow flag bit corresponding to the row address as 0.

11. The memory device ofclaim 8, wherein each of the plurality of storage units includes at least one count cell having the same structure as a memory cell of the plurality of memory cells.

12. The memory device ofclaim 8, wherein the refresh controller is further configured to perform the refresh operation on at least one of wordlines adjacent to the wordline corresponding to the row address.

13. The memory device ofclaim 8, wherein the row address storage unit is configured to transfer the refresh row address to the refresh controller for the refresh operation and delete the transferred refresh row address from the row address storage unit.

14. A memory device comprising:

a memory cell array including a plurality of memory cells disposed in a plurality of rows and a plurality of columns and connected to a plurality of wordlines and a plurality of bitlines;

a row decoder configured to receive a row address to activate a wordline corresponding to the row address, among the plurality of wordlines;

a row count (RCNT) storage unit including a plurality of storage units, each of the plurality of storage unit configured to store a row access count of at least one corresponding wordline among the plurality of wordlines;

a row address storage unit;

an access counter configured to:

read the row access count corresponding to the row address stored in the RCNT storage unit,

in response to an increased access count obtained from the read row access count not reaching a reference value, update the row access count corresponding to the row address with the increased access count,

in response to the increased access count reaching the reference value and the row address storage unit having an empty space for the row address, cause the row address storage unit to store a refresh row address generated from the row address, and

in response to the increased access count reaching the reference value and the row address storage unit having no empty space for the row address, set the row access count corresponding to the row address to be lower than the reference value; and

a refresh controller configured to perform a refresh operation based on the refresh row address stored in the row address storage unit.

15. The memory device ofclaim 14, wherein the access counter is further configured to, in response to the increased access count reaching the reference value and the row address storage unit having no empty space for the row address, retain the row access count corresponding to the row address.

16. The memory device ofclaim 14, wherein the access counter is further configured to obtain the increased access count by increasing the read row access count by 1.

17. The memory device ofclaim 14, wherein the reference value includes a multiple of a predetermined value.

18. The memory device ofclaim 14, wherein each of the plurality of storage units includes at least one count cell having the same structure as a memory cell of the plurality of memory cells.

19. The memory device ofclaim 14, wherein the refresh controller is further configured to perform the refresh operation on at least one of wordlines adjacent to the wordline corresponding to the row address.

20. The memory device ofclaim 14, wherein the row address storage unit is configured to transfer the refresh row address to the refresh controller for the refresh operation and delete the transferred refresh row address from the row address storage unit.

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