US20230215939A1 - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a group of negatively-charged ions, and a field plate. The gate electrode and the drain electrode disposed above the second nitride-based semiconductor layer to define a drift region therebetween. The group of negatively-charged ions are implanted into the drift region and spaced apart from an area directly beneath the gate and drain electrodes to form at least one high resistivity zone in the second nitride-based semiconductor layer. The field plate is disposed over the gate electrode and extends in a region between the gate electrode and the high resistivity zone.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS
• This application is a continuation application of U.S. application Ser. No. 17/639,910, filed on Mar. 3, 2022, which is a national phase application of PCT/CN2021/143738 filed on Dec. 31, 2021, the disclosure of which are incorporated herein by reference in their entirety.
FIELD OF THE DISCLOSURE
• The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a semiconductor device having negatively-charged ions.
BACKGROUND
• In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT), heterojunction field effect transistor (HFET), and modulation-doped FETs (MODFET).
SUMMARY OF THE DISCLOSURE
• In accordance with one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a gate electrode, and a doped nitride-based semiconductor layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The gate electrode is disposed above the second nitride-based semiconductor layer. The doped nitride-based semiconductor layer is disposed between the second nitride-based semiconductor layer and the gate electrode. The doped nitride-based semiconductor layer has a pair of opposite ledge portions free from coverage of the gate electrode and a central portion therebetween. The second nitride-based semiconductor layer has a first portion beneath the central portion and a second portion beneath the ledge portion, and the second nitride-based semiconductor layer has a doping concentration of a dopant that selected from a highly electronegative group. The doping concentration from the first portion to the second portion increases.
• In accordance with one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes steps as follows. A first nitride-based semiconductor layer is formed. A second nitride-based semiconductor layer is formed on the first nitride-based semiconductor layer. A blanket doped nitride-based semiconductor layer is formed on the second nitride-based semiconductor layer. A blanket gate electrode layer is formed over the blanket doped nitride-based semiconductor layer. A first dielectric layer is formed over the blanket gate electrode layer. The blanket gate electrode layer and the first dielectric layer are patterned to form a gate electrode covered by the patterned first dielectric layer, so as to expose the blanket doped nitride-based semiconductor layer. An ion implantation process is performed, such that at least one portion of the second nitride-based semiconductor layer beneath the exposed blanket doped nitride-based semiconductor layer is doped with a dopant selected from a highly electronegative group. The exposed blanket doped nitride-based semiconductor layer is removed.
• In accordance with one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a gate electrode, and a doped nitride-based semiconductor layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The gate electrode is disposed above the second nitride-based semiconductor layer. The doped nitride-based semiconductor layer is disposed between the second nitride-based semiconductor layer and the gate electrode. The doped nitride-based semiconductor layer has a pair of opposite side surfaces which are spaced apart from each other by a distance greater than a width of the gate electrode. The second nitride-based semiconductor layer has a doping concentration of a dopant that selected from a highly electronegative group, and the doping concentration decreases and then increases between the side surfaces of the second doped nitride-based semiconductor layer.
• In accordance with one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a gate electrode, a source electrode, a drain electrode, and a group of negatively-charged ions. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction therebetween with a two-dimensional electron gas (2DEG) region. The gate electrode is disposed above the second nitride-based semiconductor layer. The source electrode and the drain electrode are disposed above the second nitride-based semiconductor layer. The gate electrode is located between the source and drain electrodes to define a drift region between the gate and drain electrodes. A group of negatively-charged ions are implanted into the drift region and over the 2DEG region and spaced apart from the gate and drain electrodes and spaced apart from an area directly beneath the gate and drain electrodes. The gate electrode is closer to the negatively-charged ions than the drain electrode, such that the negatively-charged ions deplete at least one portion of the 2DEG region which is near the gate electrode.
• In accordance with one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes steps as follows. A first nitride-based semiconductor layer is formed. A second nitride-based semiconductor layer is formed on the first nitride-based semiconductor layer. A blanket doped nitride-based semiconductor layer is formed on the second nitride-based semiconductor layer. A mask is formed with at least one opening on the blanket doped nitride-based semiconductor layer to expose at least one portion of blanket doped nitride-based semiconductor layer. An ion implantation process is performed using negatively-charged ions to distribute the negatively-charged ions in the exposed portion of the blanket doped nitride-based semiconductor layer and a portion of the second nitride-based semiconductor layer beneath the exposed portion of the blanket doped nitride-based semiconductor layer. The mask is removed from the blanket doped nitride-based semiconductor layer. The blanket doped nitride-based semiconductor layer such that the exposed portion of the blanket doped nitride-based semiconductor layer is removed, so as to form a doped nitride-based semiconductor layer. The blanket doped nitride-based semiconductor layer is patterned such that the exposed portion of the blanket doped nitride-based semiconductor layer is removed, so as to form a doped nitride-based semiconductor layer. The mask is removed from the blanket doped nitride-based semiconductor layer. The blanket doped nitride-based semiconductor layer is patterned such that the exposed portion of the blanket doped nitride-based semiconductor layer is removed, so as to form a doped nitride-based semiconductor layer.
• In accordance with one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, at least one high resistivity zone, a gate electrode, and a doped nitride-based semiconductor layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. At least one high resistivity zone is formed by a group of negatively-charged ions and embedded in the second nitride-based semiconductor layer. The source electrode and the drain electrode are disposed above the second nitride-based semiconductor layer and spaced apart from the high resistivity zone. The gate electrode is disposed above the second nitride-based semiconductor layer and between the source and drain electrodes. The gate electrode is vertically and horizontally separated from the high resistivity zone. The doped nitride-based semiconductor layer is disposed between the second nitride-based semiconductor layer and the gate electrode and vertically separated from the high resistivity zone.
• In accordance with one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a group of negatively-charged ions, and a field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction therebetween with a two-dimensional electron gas (2DEG) region. The gate electrode and the drain electrode disposed above the second nitride-based semiconductor layer to define a drift region therebetween. The group of negatively-charged ions are implanted into the drift region and spaced apart from an area directly beneath the gate and drain electrodes to form at least one high resistivity zone in the second nitride-based semiconductor layer. The field plate is disposed over the gate electrode and extends in a region between the gate electrode and the high resistivity zone.
• In accordance with one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes steps as follows. A first nitride-based semiconductor layer is formed. A second nitride-based semiconductor layer is formed on the first nitride-based semiconductor layer. A gate electrode is formed over the second nitride-based semiconductor layer. A first dielectric layer is formed to cover the gate electrode. A mask is formed with an opening over the second nitride-based semiconductor layer and the first dielectric layer, such that at least one portion of the second nitride-based semiconductor layer is exposed from the opening. An ion implantation process is performed such that the exposed portion of the second nitride-based semiconductor layer is doped with a dopant selected from a highly electronegative group, so as to form a high resistivity zone in the second nitride-based semiconductor layer. A field plate is formed over the gate electrode and extends in a region between the gate electrode and the high resistivity zone.
• In accordance with one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, at least one high resistivity zone, a drain electrode, a gate electrode, and a field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. At least one high resistivity zone is formed by a group of negatively-charged ions and doped in the second nitride-based semiconductor layer. The drain electrode is disposed above the second nitride-based semiconductor layer and spaced apart from the high resistivity zone. The gate electrode is disposed above the second nitride-based semiconductor layer and vertically and horizontally separated from the high resistivity zone. The field plate is disposed over the gate electrode. A vertical projection of the field plate on the second nitride-based semiconductor layer at least partially overlaps with the high resistivity zone.
• By the above configuration, with implanting the dopants at least into the second nitride-based semiconductor layer (e.g., barrier layer), the electric field distribution of the semiconductor device can be modified. As such, the semiconductor device can be made without using any field plates or with only a single field plate.
BRIEF DESCRIPTION OF THE DRAWINGS
• Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:
• FIG.1A is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;
• FIG.1B is an enlarged vertical cross-sectional view of a region inFIG.1A;
• FIG.2A,FIG.2B,FIG.2C,FIG.2D,FIG.2E,FIG.2F,FIG.2G andFIG.2H show different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;
• FIG.3 is an enlarged vertical cross-sectional view of a region of a semiconductor device according to some embodiments of the present disclosure;
• FIG.4 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;
• FIG.5A is a top view of a semiconductor device according to some embodiments of the present disclosure;
• FIG.5B is a vertical cross-sectional view of the semiconductor device inFIG.5A;
• FIG.5C is a distribution of the negatively-charged ions in a region of the semiconductor device in theFIG.5B;
• FIG.6A,FIG.6B,FIG.6C, andFIG.6D show different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;
• FIG.7 is a top view of a semiconductor device according to some embodiments of the present disclosure;
• FIG.8 is a top view of a semiconductor device according to some embodiments of the present disclosure;
• FIG.9 is a top view of a semiconductor device according to some embodiments of the present disclosure;
• FIG.10A is a top view of a semiconductor device according to some embodiments of the present disclosure;
• FIG.10B is a vertical cross-sectional view of the semiconductor device inFIG.10A;
• FIG.10C is a distribution of the negatively-charged ions in a region of the semiconductor device in theFIG.10B;
• FIG.11A,FIG.11B,FIG.11C,FIG.11D,FIG.11E,FIG.11F,FIG.11G, andFIG.11H show different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;
• FIG.12 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;
• FIG.13 is a top view of a semiconductor device according to some embodiments of the present disclosure;
• FIG.14 is a top view of a semiconductor device according to some embodiments of the present disclosure;
• FIG.15 is a top view of a semiconductor device according to some embodiments of the present disclosure;
• FIG.16 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure; and
• FIG.17A,FIG.17B,FIG.17C, andFIG.17D show different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.
DETAILED DESCRIPTION
• Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.
• Spatial descriptions, such as “on,” “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component(s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.
• Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.
• In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.
• FIG.1A is a vertical cross-sectional view of asemiconductor device1A according to some embodiments of the present disclosure.FIG.1B is an enlarged vertical cross-sectional view of a region A inFIG.1A. The directions D1 and D2 are labeled in theFIGS.1A and1B, in which the direction D1 is different than the direction D2. In some embodiments, the directions D1 and D2 are perpendicular to each other. For example, the direction D1 is the horizontal direction ofFIGS.1A and1B and the direction D2 is the vertical direction ofFIGS.1A and1B.
• Thesemiconductor device1A includes asubstrate10, abuffer layer12, nitride-basedsemiconductor layers14A and16A,electrodes20 and22, a doped nitride-basedsemiconductor layer32A, agate electrode34, dielectric layers50,52, and54, apassivation layer60, contact vias70 and72, a patternedcircuit layer80.
• Thesubstrate10 may be a semiconductor substrate. The exemplary materials of thesubstrate10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI), or other suitable substrate materials. In some embodiments, thesubstrate10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds). In other embodiments, thesubstrate10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.
• Thebuffer layer12 can be disposed on/over/above thesubstrate10. Thebuffer layer12 can be disposed between thesubstrate10 and the nitride-basedsemiconductor layer14A. Thebuffer layer12 can be configured to reduce lattice and thermal mismatches between thesubstrate10 and the nitride-basedsemiconductor layer14A, thereby curing defects due to the mismatches/difference. Thebuffer layer12 may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of thebuffer layer12 can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof. In some embodiments, thesemiconductor device1A may further include a nucleation layer (not shown). The nucleation layer may be formed between thesubstrate10 and thebuffer layer12. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between thesubstrate10 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.
• The nitride-basedsemiconductor layer14A can be disposed on/over/above thebuffer layer12. The nitride-basedsemiconductor layer16A can be disposed on/over/above the nitride-basedsemiconductor layer14A. The exemplary materials of the nitride-basedsemiconductor layer14A can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In_xAl_yGa_(1−x−y)N where x+y≤1, Al_xGa_(1−x)N where x≤1. The exemplary materials of the nitride-basedsemiconductor layer16A can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In_xAl_yGa_(1−x−y)N where x+y≤1, Al_yGa_(1−y)N where y≤1.
• The exemplary materials of the nitride-basedsemiconductor layers14A and16A are selected, such that the nitride-basedsemiconductor layer16A has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-basedsemiconductor layer14A, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-basedsemiconductor layer14A is selected as an unintentionally-doped GaN layer (or can be referred to as an undoped GaN layer) having a bandgap of approximately 3.4 eV, the nitride-basedsemiconductor layer16A can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-basedsemiconductor layers14A and16A can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, thesemiconductor device1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT).
• Theelectrodes20 and22 can be disposed on/over/above the nitride-basedsemiconductor layer16A. Theelectrodes20 and22 can be in contact with the nitride-basedsemiconductor layer16A. In some embodiments, theelectrode20 can serve as a source electrode. In some embodiments, theelectrode20 can serve as a drain electrode. In some embodiments, theelectrode22 can serve as a source electrode. In some embodiments, theelectrode22 can serve as a drain electrode. The role of theelectrodes20 and22 depends on the device design.
• In some embodiments, theelectrodes20 and22 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of theelectrodes20 and22 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. Each of theelectrodes20 and22 may be a single layer, or plural layers of the same or different composition. Theelectrodes20 and22 form ohmic contacts with the nitride-basedsemiconductor layer16A. Furthermore, the ohmic contacts can be achieved by applying Ti, Al, or other suitable materials to theelectrodes20 and22. In some embodiments, each of theelectrodes20 and22 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.
• The doped nitride-basedsemiconductor layer32A can be disposed on/over/above the nitride-basedsemiconductor layer16A. The doped nitride-basedsemiconductor layer32A can be in contact with the nitride-basedsemiconductor layer16A. The doped nitride-basedsemiconductor layer32A can be disposed/located between theelectrodes20 and22. The doped nitride-basedsemiconductor layer32A can have, for example, a rectangular profile. In some embodiments, the doped nitride-basedsemiconductor layer32A can have, for example, a trapezoid profile.
• Thegate electrode34 can be disposed on/over/above the doped nitride-basedsemiconductor layer32A. Thegate electrode34 can be in contact with the doped nitride-basedsemiconductor layer32A, such that the doped nitride-basedsemiconductor layer32A can be disposed/sandwiched between thegate electrode34 and the nitride-basedsemiconductor layer16A. The doped nitride-basedsemiconductor layer32A has a pair of opposite side surfaces which are spaced apart from each other by a distance greater than a width of thegate electrode34. Thegate electrode34 can be disposed/located between theelectrodes20 and22. A distance between theelectrode22 and thegate electrode34 is greater than a distance between theelectrode20 and thegate electrode20. Thegate electrode34 and the doped nitride-basedsemiconductor layer32A can serve as a gate structure.
• In the exemplary illustration ofFIG.1A, thesemiconductor device1A is an enhancement mode device, which is in a normally-off state when thegate electrode34 is at approximately zero bias. Specifically, the doped nitride-basedsemiconductor layer32A may create at least one p-n junction with the nitride-basedsemiconductor layer16A to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding thegate electrode34 has different characteristics (e.g., different electron concentrations) than the rest of the 2DEG region and thus is blocked.
• Due to such mechanism, thesemiconductor device1A has a normally-off characteristic. In other words, when no voltage is applied to thegate electrode34 or a voltage applied to thegate electrode34 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrode34), the zone of the 2DEG region below thegate electrode34 is kept blocked, and thus no current flows therethrough.
• The exemplary materials of the doped nitride-basedsemiconductor layer32A can be p-type doped. The doped nitride-basedsemiconductor layer32A can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg.
• In some embodiments, thegate electrode34 may include metals or metal compounds. Thegate electrode34 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds. In some embodiments, the exemplary materials of thegate electrode34 may include, for example but are not limited to, nitrides, oxides, silicides, doped semiconductors, or combinations thereof. Theelectrodes20 and22 and thegate electrode34 can constitute a GaN-based HEMT device with the 2DEG region.
• In some embodiments, the nitride-basedsemiconductor layer14A includes undoped GaN and the nitride-basedsemiconductor layer16A includes AlGaN, and the doped nitride-basedsemiconductor layer32A is p-type GaN layer which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region, so as to place thesemiconductor device1A into an off-state condition.
• In order to avoid the breakdown phenomenon induced by a strong peak electric field near the edge of the gate electrode, multi-field plates (i.e., the number of the applied field plates is greater than two) are usually adopted in the semiconductor device to make the electric field distribution more uniform. However, the configuration of the excessive field plates may induce unwanted parasitic/stray capacitances which limits the maximum operating frequency of the device, thereby degrading the electrical properties and the reliability thereof. Moreover, the introduction of the multi-field plates would increase the process complexity of the device. Therefore, there is a need to improve device performance.
• At least for avoiding the aforesaid issues, the present disclosure provides a novel way to suppress the breakdown phenomenon.
• In embodiments of the present disclosure, negatively-charged ions, which are selected from a highly electronegative group, are regionally doped into the nitride-basedsemiconductor layer16A (e.g., barrier layer) to modify the electrical properties thereof, thereby improving the electric field distribution in thesemiconductor device1A. The electronegativity of the selected element in the highly electronegative group is greater than that of nitrogen, such as fluorine (F) or chlorine (Cl). The detail mechanism is described as follows.
• Referring toFIG.1B, the doped nitride-basedsemiconductor layer32A includes acentral portion322A, and a pair ofopposite ledge portions324A and326A. Thecentral portion322A is directly under thegate electrode34. A width of thecentral portion322A can be defined by thegate electrode34. Thecentral portion322A is covered by thegate electrode34. The border of thecentral portion322A coincides with opposite sidewalls of thegate electrode34.
• Thecentral portion322A is located between theledge portions324A and326A. Theledge portions324A and326A are free from coverage of thegate electrode34. The width of theledge portion324A is the same as that of theledge portion326A. In some embodiments, the width of theledge portion324A can be different from that of theledge portion326A. For instance, the width of theledge portion326A can be greater than that of theledge portion326A, such that the width design can match the distance relationship of theelectrodes20,22 and thegate electrode34, thereby improving the electrical properties of thesemiconductor device1A.
• Referring toFIG.1B, the nitride-basedsemiconductor layer16A includesportions162A,164A,166A,168A and169A. Theportion162A is beneath thecentral portion322A. Theportions164A and166A are beneath theportions324A and326A, respectively. The doped nitride-basedsemiconductor layer32A has a left-side surface extending upward from an interface between the portions164A and168A. The doped nitride-basedsemiconductor layer32A has a right-side surface extending upward from an interface between theportions166A and169A. Theportions168A and169A abut against theportions164A and169A, respectively. The portion168A has a top surface in a position lower than theportion324A, such that theportions168A and324A can collectively form a step profile. The similar configuration can be applied to theportions169A and326A.
• During the manufacturing process of thesemiconductor device1A, after forming the doped nitride-basedsemiconductor layer32A and thegate electrode34, an ion implantation process is performed on the resulted structure using thegate electrode34 as a mask, in which the dopant applied to the ion implantation process can be selected from a highly electronegative group. In some embodiments, the highly electronegative group can include fluorine (F) or chlorine (Cl).
• Doping concentration profiles along lines A-A′, B-B′, and C-C′ are shown inFIG.1B as well. Referring to the concentration profile along the line A-A′, since thegate electrode34 can block/hinder the dopants to dope into/enter theportions162A and322A during the ion implantation process, the doping concentration of the dopant in theportions162A and322A is zero or approaches to zero.
• Furthermore, in other regions, the doping depth of the dopant can be well controlled by altering the ion implantation energy, such that most of the dopants can be doped into theportions164A,166A,168A and169A during the ion implantation process.
• Referring to the concentration profile along the line B-B′, the doping concentration of the dopant in the most part ofledge portions324A and326A is zero or approaches to zero. Theledge portion324A and326A has bottom parts near theportions164A and166A, respectively, and such the bottom parts are doped to have a doping concentration of the dopant linearly changing from zero to an non-zero constant along a thickness direction (e.g., the direction D2) thereof.
• The doping concentration of theportions164A and166A of the nitride-basedsemiconductor layer16A remains constant along a thickness direction (e.g., direction D2) thereof. Each of theledge portions324A and326A of the doped nitride-basedsemiconductor layer32A is doped to have a doping concentration of the dopant less than that of theportions164A and166A.
• The nitride-basedsemiconductor layer14A has a top portion beneath the portion164A/166A of the nitride-basedsemiconductor layer16A, and a doping concentration of the dopant of such the top portion linearly changing from an non-zero constant to zero along a thickness direction (e.g., direction D2) thereof.
• As the negatively-charged ions introduced/implanted in the interstitial sites of the layers (e.g., the nitride-basedsemiconductor layer16A), the negatively-charged ion selected from the highly electronegative group can become a negative fixed charge in the nitride-basedsemiconductor layer16A, resulting in increase of the potential of the barrier layer. As such, zones of the 2DEG region directly beneath theportions164A and166A are depleted. Therefore, the density of the electric lines near the edge of thegate electrode34 can be reduced, so as to alleviate the peak intensity of the electric field near thegate electrode34, thereby suppressing the breakdown phenomenon. Hence, thesemiconductor device1A can have good electric properties instead of using field plates.
• Moreover, in order to avoid the influence of negatively-charged ions on the rest of the 2DEG region in thesemiconductor device1A, the dopants in theportions168A and169A should be removed.
• Specifically, after the ion implantation process, adielectric layer52 can be formed to cover theportions324A and326A, and theportions168A,169A are free from coverage of thedielectric layer52. Then, an annealing process is performed to remove some of the dopants in theportions168A and169A of the nitride-basedsemiconductor layer16A.
• In this regard, referring to the concentration profile along the line C-C′, the doping concentration of theportions168A and169A can be zero or approach to zero at top surfaces thereof. Such the concentration profile can be achieved by performing an annealing process.
• It should be noted that thedielectric layer52 can be formed on theportions324A and326A prior to the annealing process, so as to avoid the dopant heat diffusing from theportions324A and326A due to the annealing process. Since the dopants can be removed from theportions168A and169A by performing the annealing process, the corresponding zones of the 2DEG region can be free from obstruction by the dopants.
• After the ion implantation process and the annealing process, the dopants can retain/remain in theportions164A and166A, instead of theportions168A and169A, and most of theportion162A. The doping concentration of theportions168A and169A is zero or approaches to zero due to the annealing process. The doping concentration of the most of theportion162A of the nitride-based semiconductor layer is zero or approaches to zero due to the block of thegate electrode34 during the ion implantation process.
• In some embodiments, theportion162A has a part abutting against the portion164A/166A, the doping concentration of such the part linearly changes along a width direction (e.g., the direction D1) thereof. The doping concentration of the portion168A/169A is less than that of the portion164A/166A due to annealing process. The doping concentration from the portion168A to theportion169A sequentially remains zero, increases to an non-zero constant, remains the non-zero constant, decreases to zero, remains to zero, increases to the non-zero constant, remains the non-zero constant, and then decreases to zero along thedirection D1. In some embodiments, the increase/decrease of the doping concentration of the nitride-basedsemiconductor layer16A is continuous.
• The reason for the distribution of the doping concentration is to shape the depletion region for the 2DEG region. In case the distribution density is too high, the resistivity will get high as well, which is not advantageous on-resistant for devices. In case the distribution density is too low, the normally-off state is hard to keep effective, which will result in leakage current issue.
• Referring toFIGS.1A and1B, thedielectric layer50 can be disposed on/over/above thegate electrode34. Thedielectric layer50 has a pair of opposite side surfaces which connect two opposite side surfaces of thegate electrode34, respectively. The exemplary materials of thedielectric layer50 can include, for example but are not limited to, dielectric materials. For example, thedielectric layer50 can include SiN_x, SiO_x, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX), or combinations thereof.
• Thedielectric layer52 can be disposed on/over/above the doped nitride-basedsemiconductor layer32A. Thedielectric layer52 covers the side surfaces of thegate electrode34 and thedielectric layer50. Thedielectric layer52 covers theledge portions324A and326A of the doped nitride-basedsemiconductor layer32A, and two opposite side surfaces of the doped nitride-basedsemiconductor layer32A are free from coverage by thedielectric layer52. The exemplary materials of thedielectric layer52 can be identical to or similar to that of thedielectric layer50.
• Thedielectric layer54 can be disposed on/over/above the nitride-basedsemiconductor layer16A, and covers thedielectric layer52 so as to form a protruding portion. Thedielectric layer54 has a plurality of through holes TH to expose the nitride-basedsemiconductor layer16A. Theelectrodes20 and22 can extend through the through holes TH (i.e., theelectrodes20 and22 penetrate the dielectric layer54), so as to make contact with the nitride-basedsemiconductor layer16A. The exemplary materials of thedielectric layer54 can be identical to or similar to that of thedielectric layer50.
• Thepassivation layer60 can be disposed on/over/above theelectrodes20,22, and thedielectric layer54. The exemplary material of thepassivation layer60 can be can be identical with or similar with that of thepassivation layer60. Moreover, thepassivation layer60 can serve as a planarization layer which has a level top surface to support other layers/elements. In some embodiments, thepassivation layer60 can be formed as a thicker layer, and a planarization process, such as chemical mechanical polish (CMP) process, is performed on thepassivation layer60 to remove the excess portions, thereby forming a level top surface.
• The contact vias70 are disposed within thepassivation layer60. The contact vias70 can penetrate thepassivation layer60. The contact vias70 can extend longitudinally to connect theelectrodes20 and22. The contact via72 is located directly on/over/above thegate electrode34. The contact via72 penetrates thedielectric layers50,52 and54, and thepassivation layer60, so as to connect thegate electrode34. The upper surfaces of thecontact vias70 and72 are free from coverage of thepassivation layer60. The exemplary materials of thecontact vias70 and72 can include, for example but are not limited to, conductive materials, such as metals or alloys.
• The patternedcircuit layer80 can be disposed on/over/above thepassivation layer60 and theconductive vias70 and72. The patternedcircuit layer80 is in contact with theconductive vias70 and72. The patternedcircuit layer80 may have metal lines, pads, traces, or combinations thereof, such that the patternedcircuit layer80 can form at least one circuit. The exemplary materials of the patternedcircuit layer80 can be identical to or similar with that of thecontact vias70 and72.
• Different stages of a method for manufacturing thesemiconductor device1A are shown inFIG.2A,FIG.2B,FIG.2C,FIG.2D,FIG.2E,FIG.2F,FIG.2G andFIG.2H, as described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic CVD (MOCVD), plasma enhanced CVD (PECVD), low-pressure CVD (LPCVD), plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
• Referring toFIG.2A, abuffer layer12 can be formed on/over/above asubstrate10 by using deposition techniques. A nitride-basedsemiconductor layer14A can be formed on/over/above thebuffer layer12 by using deposition techniques. A nitride-basedsemiconductor layer16A can be formed on/over/above the nitride-basedsemiconductor layer14A by using deposition technique, so that a heterojunction is formed therebetween. A blanket doped nitride-basedsemiconductor layer82 can be formed on/over/above the nitride-basedsemiconductor layer16A. A blanketgate electrode layer84 can be formed on/over/above the blanket doped nitride-basedsemiconductor layer82. The materials of the blanketgate electrode layer84 can be conductive materials; and therefore, the blanketgate electrode layer84 can serve as a blanket conductive layer. Ablanket dielectric layer86 can be formed on/over/above the blanketgate electrode layer84.
• Referring toFIG.2B, a mask layer ML1 can be formed on theblanket dielectric layer86. The formation of the mask layer ML1 may include a pattering process. After the pattering process, some portions of theblanket dielectric layer86 can be exposed.
• Referring toFIG.2C, a patterning process is performed on the blanketgate electrode layer84 and theblanket dielectric layer86, so as to form agate electrode34 and adielectric layer50. Thegate electrode34 is covered by thedielectric layer50. At least a part of the blanket doped nitride-basedsemiconductor layer82 is exposed by thegate electrode34 and thedielectric layer50.
• Referring toFIG.2D, an ion implantation process is performed using thegate electrode34 as a mask, such that at least one portion of the nitride-basedsemiconductor layer16A beneath the exposed blanket doped nitride-basedsemiconductor layer82 is doped with dopants selected from a highly electronegative group, which are depicted as small particle. In some embodiments, at least one portion of the blanket doped nitride-basedsemiconductor layer82 is doped with the dopants. In some embodiments, the highly electronegative group can include fluorine (F) or chlorine (Cl). In this regard, the doping depth of the dopants can be adjusted by altering the ion implantation energy, such that most of the dopants can be doped into the nitride-basedsemiconductor layer16A. In some embodiments, the dopants can be doped into a part of the blanket doped nitride-basedsemiconductor layer82 adjacent to the nitride-basedsemiconductor layer16A. In some embodiments, the dopants can be doped into a part of the nitride-basedsemiconductor layer14A adjacent to the nitride-basedsemiconductor layer16A.
• Referring toFIG.2E, ablanket dielectric layer90 can be formed to cover the resulted structure in theFIG.2D.
• Referring toFIG.2F, a patterning process is performed on theblanket dielectric layer90, so as to form thedielectric layer52 to cover thegate electrode34 and thedielectric layer50, thereby exposing at least a part of the blanket doped nitride-basedsemiconductor layer82.
• Referring toFIG.2G, a patterning process is performed on the blanket doped nitride-basedsemiconductor layer82, so as to remove excess portions of the exposed blanket doped nitride-basedsemiconductor layer82, thereby forming the doped nitride-basedsemiconductor layer32A. At least a part of the nitride-basedsemiconductor layer16A can be exposed thereof. The doped nitride-basedsemiconductor layer32A is formed to be wider than thegate electrode34.
• Then, an annealing process can be performed to remove dopants in the exposed nitride-basedsemiconductor layer16A. The dopants in the portion of the nitride-basedsemiconductor layer16A directly under the doped nitride-basedsemiconductor layer32A can still retain/remain due to the coverage of thedielectric layer52 during the annealing process.
• Referring toFIG.2H, adielectric layer54 can be formed to cover the resulted structure in theFIG.2G, so as to expose at least a part of the nitride-basedsemiconductor layer16A. The formation of thedielectric layer54 includes deposition techniques and a patterning process. In some embodiments, the deposition techniques can be performed for forming a blanket layer, and the patterning process can be performed for removing excess portions thereof. In some embodiments, the patterning process can include photolithography, exposure and development, etching, other suitable processes, or combinations thereof. Thereafter, theelectrodes20 and22, contact vias70 and72, apassivation layer60, and a patternedcircuit layer80 can be formed, obtaining the configuration of thesemiconductor device1A as shown inFIG.1A.
• FIG.3 is an enlarged vertical cross-sectional view of a region of asemiconductor device1B according to some embodiments of the present disclosure. The directions D1 and D2 are illustrated inFIG.3. Thesemiconductor device1B is similar to thesemiconductor device1A as described and illustrated with reference toFIG.1A andFIG.1B. In the present embodiment, the doping concentration profile differs than the previous one.
• In the present embodiment, the doping concentration of thewhole portions324B and326B is zero or approaches to zero. The doping concentration of the whole nitride-basedsemiconductor layer14B is zero or approaches to zero.
• Referring to the concentration profile along the line A-A′, the doping concentration of the portion166B of the nitride-basedsemiconductor layer16B can linearly change along a thickness direction (e.g., direction D2) thereof. Alternatively, the doping concentration of the portion166B of the nitride-basedsemiconductor layer16B can increase first and then decrease along a thickness direction (e.g., direction D2) thereof. The graph of the relationship between the doping concentration and the depth can be curved.
• Referring to the concentration profile along the line C-C′, the doping concentration of theportions168B and169B is greater than zero. That is, the doping concentration of theportions168B and169B can be greater than the portion of the nitride-basedsemiconductor layer16B between theportions164B and166B.
• During the manufacturing process of thesemiconductor device1B, the aforesaid doping profile of the dopants can be controlled by turning the parameters. In some embodiments, the parameters may include ion implantation energy. In some embodiments, the parameters may include profile of reticles, such as a gray-tone mask or a half-tone mask, so as to adjust ion implantation energy during the ion implantation process. In some embodiments, the parameters may include applied time of an annealing process.
• FIG.4 is a vertical cross-sectional view of asemiconductor device1C according to some embodiments of the present disclosure. Thesemiconductor device1C is similar to thesemiconductor device1A as described and illustrated with reference toFIG.1A, except the nitride-basedsemiconductor layer16A is replaced by a nitride-basedsemiconductor layer16C.
• The nitride-basedsemiconductor layer16C includesportions162C,164C, and169C. Theportion162C is directly beneath thegate electrode34. Theportion164C is located between theportions162C and169C. Theportion169C of the nitride-basedsemiconductor layer16C has a top surface in a position lower than theportion164C and thecentral portion162C. Theportions162C,164C and169C can collectively form a step profile.
• During the manufacturing process of thesemiconductor device1C, a patterning process for the doped nitride-basedsemiconductor layer32C can further remove some top portions of the nitride-basedsemiconductor layer16C. The removal of the top portions of the nitride-basedsemiconductor layer16C can form the step profile. Such the profile is advantageous to control the distribution of the dopants.
• FIG.5A is a top view of asemiconductor device1D according to some embodiments of the present disclosure.FIG.5B is a vertical cross-sectional view of thesemiconductor device1D inFIG.5A. Thesemiconductor device1D is similar to thesemiconductor device1A as described and illustrated with reference toFIG.1A, except distribution of negatively-charged ions is varied. The directions D1, D2, and D3 are labeled in theFIGS.5A and5B. The directions D1, D2 and D3 are different from each other. In some embodiments, the directions D1, D2 and D3 are perpendicular to each other.
• Thesemiconductor device1D includes asubstrate10, abuffer layer12, nitride-basedsemiconductor layers14D and16D,electrodes20 and22, a doped nitride-basedsemiconductor layer32D, agate electrode34, adielectric layer54, apassivation layer60, contact vias70, a patternedcircuit layer80, a group of negatively-chargedions92. The descriptions for the identical or similar layers as afore mentioned are omitted.
• A drift region DR is defined between thegate electrode34 and theelectrode22. A group of negatively-chargedions92, which are selected from a highly electronegative group, are implanted/doped into the drift region DR and over the 2DEG region in the nitride-basedsemiconductor layer14D, such that ahigh resistivity zone94D is formed by the group of negatively-chargedions92. Thehigh resistivity zone94D is embedded in the nitride-basedsemiconductor layer16D (e.g., the barrier layer).
• The doped nitride-basedsemiconductor layer32D and thegate electrode34 are vertically spaced apart/separated from the negatively-chargedions92. The doped nitride-basedsemiconductor layer32D and thegate electrode34 are vertically spaced apart/separated from thehigh resistivity zone94D. The negatively-chargedions92 are spaced apart from an area/a region directly beneath thegate electrode32 and theelectrode22. The negatively-chargedions92 are adjacent with an interface formed between the nitride-basedsemiconductor layer16D and thedielectric layer54. Thehigh resistivity zone94D is spaced apart from theelectrodes20 and22. Thegate electrode34 is vertically and horizontally separated from thehigh resistivity zone94D. Thegate electrode34 is closer to the negatively-chargedions92 than theelectrode22, such that the negatively-chargedions92 can deplete at least one portion of the 2DEG region which is near thegate electrode34, thereby rearranging/redistributing the electrical field distribution therein.
• Hence, the density of the electric lines near the edge of thegate electrode34 can be reduced, so as to alleviate the peak intensity of the electric field near thegate electrode34, thereby suppressing the breakdown phenomenon. Thesemiconductor device1D can have good electric properties instead of applying field plate.
• Referring toFIG.5A, from the top view of thesemiconductor device1A, thegate electrode34 and theelectrodes20,22 can extend along the direction D3. The negatively-chargedions92 are distributed along the direction D3 to form a continuous high resistivity strip94 in the drift region DR. Thehigh resistivity zone94D, thegate electrode34, theelectrode20, and theelectrode22 extend along the same direction D3.
• FIG.5C is a distribution of the negatively-charged ions in a region of thesemiconductor device1D in theFIG.5B. The negatively-chargedions92 are distributed from a top surface to a bottom surface of the nitride-basedsemiconductor layer16D. The distributed density of the negatively-chargedions92 changes from the top surface to the bottom surface of the nitride-basedsemiconductor layer16D. The distributed density of the negatively-chargedions92 in the nitride-basedsemiconductor layer16D is non-uniform along the direction D2 pointing from the top surface to the bottom surface of the nitride-basedsemiconductor layer16D (i.e., a direction pointing from thedielectric layer54 toward the nitride-basedsemiconductor layer16D). The distributed density of the negatively-chargedions92 in the nitride-basedsemiconductor layer16D increases first and then decreases along the direction D2. In some embodiments, the distribution of the negatively-chargedions92 along a thickness direction (e.g., the direction D2) of the nitride-basedsemiconductor layer16D can be a normal distribution.
• The reason for such the distributed density is to shape the depletion region for the 2DEG region. In case the distributed density is too high, the resistivity will get high as well, which is not advantageous on-resistant for devices. In case the distributed density is too low, the normally-off state is hard to keep effective so at least one leakage current occurs. With such the distributed density as shown inFIG.5C, thesemiconductor device1D is allowed to become free from any field plate in the structure, thereby avoiding the issues of process complexity caused by the field plate. Accordingly, the structure as shown inFIG.5B does not include any field plate. In the present disclosure, whether to introduce a field plate in the structure of thesemiconductor device1D is not limited.
• In some embodiments, the distribution of the negatively-chargedions92 can be determined by the implantation energy of the ion implantation process. For example, by controlling the implantation energy, the negatively-charged ions can be doped into the nitride-basedsemiconductor layer16D, such that the negatively-chargedions92 can be spaced apart from the top and the bottom surfaces of the nitride-basedsemiconductor layer16D.
• Different stages of a method for manufacturing thesemiconductor device1D are shown inFIG.6A,FIG.6B,FIG.6C, andFIG.6D, as described below.
• Referring toFIG.6A, abuffer layer12 can be formed on/over/above asubstrate10 by using deposition techniques. A nitride-basedsemiconductor layer14D can be formed on/over/above thebuffer layer12 by using deposition techniques. A nitride-basedsemiconductor layer16D can be formed on/over/above the nitride-basedsemiconductor layer14D by using deposition technique, so that a heterojunction is formed therebetween. A blanket doped nitride-basedsemiconductor layer82 can be formed on/over/above the nitride-basedsemiconductor layer16D. A mask layer ML2 with at least one opening OP is formed on the blanket doped nitride-basedsemiconductor layer82. The opening OP of the mask layer ML2 can expose at least one portion EP of the blanket doped nitride-basedsemiconductor layer82, in which the opening OP of the mask layer ML2 is strip-shaped.
• Referring toFIG.6B, an ion implantation process is performed using negatively-chargedions92 to distribute the negatively-chargedions92. The negatively-chargedions92 are distributed in the exposed portion EP of the blanket doped nitride-basedsemiconductor layer82. The negatively-chargedions92 are distributed in a portion P of the nitride-basedsemiconductor layer16D beneath the exposed portion EP of the blanket doped nitride-basedsemiconductor layer82.
• Referring toFIG.6C, the mask layer ML2 is removed from the blanket doped nitride-basedsemiconductor layer82. A blanketgate electrode layer84 is formed on the blanket doped nitride-basedsemiconductor layer82.
• Referring toFIG.6D, a patterning process is performed on the blanket doped nitride-basedsemiconductor layer82, such that the exposed portion EP of the blanket doped nitride-basedsemiconductor layer82 is removed. Thus, a doped nitride-basedsemiconductor layer32D is formed, and the formed doped nitride-basedsemiconductor layer32D is spaced apart from the negatively-chargedions92. A gate electrode34 (e.g., gate electrode layer) is formed on/over/above the doped nitride-basedsemiconductor layer32D, and is spaced apart from the negatively-chargedions92. The formation of thegate electrode34 includes deposition techniques and a patterning process. Thereafter, theelectrodes20 and22, contact vias70 and72, adielectric layer54, apassivation layer60, and a patternedcircuit layer80 can be formed, obtaining the configuration of thesemiconductor device1D as shown inFIG.5B.
• FIG.7 is a top view of a semiconductor device1E according to some embodiments of the present disclosure. The semiconductor device1E is similar to thesemiconductor device1D as described and illustrated with reference toFIG.5A, except thehigh resistivity zone94D is replaced by a plurality of separatedhigh resistivity zones94E.
• In the present embodiment, the negatively-chargedions92 are distributed along the direction D3, which is the same as the extending direction of theelectrodes20 and22. In response to the negatively-chargedions92, thehigh resistivity zones94E are formed in the drift region DR. Thehigh resistivity zones94E are arranged along the direction D3. Each of thehigh resistivity zones94E is in a shape of rectangular from the top view of the semiconductor device1E.
• FIG.8 is a top view of a semiconductor device IF according to some embodiments of the present disclosure. Thesemiconductor device1F is similar to thesemiconductor device1D as described and illustrated with reference toFIG.5A, except thehigh resistivity zone94D is replaced by a plurality of separatedhigh resistivity zones94F.
• In the present embodiment, the negatively-chargedions92 are distributed along the direction D3, which is the same as the extending direction of theelectrodes20 and22. In response to the negatively-chargedions92, thehigh resistivity zones94F are formed in the drift region DR. Thehigh resistivity zones94F are arranged along the direction D3. Each of thehigh resistivity zones94F is in a shape of ellipse from the top view of the semiconductor device IF. In some embodiments, each of thehigh resistivity zones94F is in a shape of circle from the top view of thesemiconductor device1F.
• FIG.9 is a top view of asemiconductor device1G according to some embodiments of the present disclosure. Thesemiconductor device1G is similar to thesemiconductor device1D as described and illustrated with reference toFIG.5A, except thehigh resistivity zone94D is replaced by a plurality of separatedhigh resistivity zones94G.
• In the present embodiment, the negatively-chargedions92 are distributed along the direction D3, which is the same as the extending direction of theelectrodes20 and22. In response to the negatively-chargedions92, thehigh resistivity zones94G are formed in the drift region DR. Thehigh resistivity zones94G are arranged along the direction D3. Each of thehigh resistivity zones94G has a short side and a long side between the short side and theelectrode22. Specifically, each of thehigh resistivity zones94G is in a shape of trapezoid from the top view of thesemiconductor device1G.
• With respect to thesemiconductor devices1E,1F and1G, thehigh resistivity zones94E/94F/94G are formed to be separated from each other, and the overall resistance thereof can be reduced.
• During the manufacturing process of the semiconductor device1E, IF and1G, the mask layer applied in the ion implantation process has a plurality of the separated openings OP to expose the blanket doped nitride-based semiconductor layer thereunder. The shape of the high resistivity zone in the top view of the corresponded semiconductor device can be determined by the shape of the openings OP.
• FIG.10A is a top view of asemiconductor device1H according to some embodiments of the present disclosure.FIG.10B is a vertical cross-sectional view of thesemiconductor device1H inFIG.10A. The directions D1, D2 and D3 are labeled in theFIGS.10A and10B. The directions D1, D2 and D3 are different from each other. In some embodiments, the directions D1, D2 and D3 are perpendicular to each other.
• Thesemiconductor device1H includes asubstrate10, abuffer layer12, nitride-basedsemiconductor layers14H and16H,electrodes20 and22, a doped nitride-basedsemiconductor layer32H, agate electrode34, adielectric layer50,52,54, apassivation layer60, contact vias70, a patternedcircuit layer80, a group of negatively-chargedions92, and afield plate96. The descriptions for the identical or similar layers as afore mentioned are omitted.
• A drift region DR is defined between thegate electrode32 and theelectrode22. A group of negatively-chargedions92, which are selected from a highly electronegative group, are implanted/doped into the drift region DR and over the 2DEG region, such that ahigh resistivity zone94H is formed/embedded in the nitride-basedsemiconductor layer16H (e.g., barrier layer).
• Thegate electrode34 and theelectrode22 extend along a direction D3, and the negatively-chargedions92 are distributed along the direction D3 to form ahigh resistivity zone94H. Thehigh resistivity zone94H can serve as ahigh resistivity strip94H in the drift region DR. The doped nitride-basedsemiconductor layer32H and thegate electrode34 are vertically spaced apart/separated from the negatively-chargedions92/high resistivity zone94H. The doped nitride-basedsemiconductor layer32H is vertically and horizontally separated from thehigh resistivity zone94H. Thegate electrode34 is vertically and horizontally separated from thehigh resistivity zone94H. Thegate electrode34 is closer to thehigh resistivity zone94H than theelectrode22. The negatively-chargedions92 are spaced apart from an area/a region directly beneath thegate electrode32 and theelectrode22.
• The dielectric layers50 and52 can be disposed on/over/above thegate electrode34 and the nitride-basedsemiconductor layer16H. The dielectric layers50 and52 covers thegate electrode34. The nitride-basedsemiconductor layer16H is free from coverage of thedielectric layers50 and52. Thedielectric layer54 can be disposed on/over/above the nitride-basedsemiconductor layer16H and covers thedielectric layers50,52 and thehigh resistivity zone94H.
• Thefield plate96 can be disposed on/over/above thedielectric layer54. Thefield plate96 can be disposed on/over/above thegate electrode34. Thefield plate96 can extend in a region between thegate electrode34 and thehigh resistivity zone94H. Thefield plate96 extends along the direction D1 to span from thegate electrode34 toward thehigh resistivity zone94H. Thefield plate96 forms an interface with thedielectric layer54. Thefield plate96 is conformal with thedielectric layer54.
• Thefield plate96 has two opposite end portions E1 and E2. The end portion E1 is directly above thegate electrode34. The end portion E2 is in a position lower than the end portion E1. The end portion E2 of thefield plate96 vertically overlaps with thehigh resistivity zone94H. Thehigh resistivity zone94H is closer to theelectrode22 than the end portion E2 of thefield plate96. A vertical projection of thefield plate96 on the nitride-basedsemiconductor layer16H at least partially overlaps with thehigh resistivity zone94H. Therefore, the density of the electric lines near the edge of thefield plate96 can be reduced, so as to alleviate the peak intensity of the electric field near thefield plate96, thereby suppressing the breakdown phenomenon.
• The exemplary materials of thefield plate96 can include, for example but are not limited to, conductive materials, such as Ti, Ta, TiN, TaN, or combinations thereof. In some embodiments, other conductive materials such as Al, Cu doped Si, and alloys including these materials may also be used.
• In the present disclosure, by designing the doping location of the negatively-chargedions92 according to the location of thesingle field plate96, thefield plate96 and thehigh resistivity zone94H can collectively modify the electric field distribution of thesemiconductor device1H. Hence, thesemiconductor device1H can have a good electric field distribution without using excessive field plates. The reliability of thesemiconductor device1H can be improved.
• FIG.10C is a distribution of the negatively-charged ions in a region of thesemiconductor device1H in theFIG.10B. The distribution of the negatively-chargedions92 in the nitride-basedsemiconductor layer16H in theFIG.10C can be identical or similar to that of the negatively-chargedions92 in the nitride-basedsemiconductor layer16D in theFIG.5C.
• Different stages of a method for manufacturing thesemiconductor device1H are shown inFIG.11A,FIG.11B,FIG.11C,FIG.11D,FIG.11E,FIG.11F,FIG.11G, andFIG.11H, as described below.
• Referring toFIG.11A, abuffer layer12 can be formed on/over/above asubstrate10 by using deposition techniques. A nitride-basedsemiconductor layer14H can be formed on/over/above thebuffer layer12 by using deposition techniques. A nitride-basedsemiconductor layer16H can be formed on/over/above the nitride-basedsemiconductor layer14H by using deposition technique, so that a heterojunction is formed therebetween. A blanket doped nitride-basedsemiconductor layer82 can be formed on/over/above the nitride-basedsemiconductor layer16H. A blanketgate electrode layer84 is formed on the blanket doped nitride-basedsemiconductor layer82. Ablanket dielectric layer86 can be formed on/over/above the blanketgate electrode layer84.
• Referring toFIG.11B, a mask layer ML3 can be formed on theblanket dielectric layer86. The formation of the mask layer ML3 may include a pattering process. After the pattering process, some portions of theblanket dielectric layer86 can be exposed.
• Referring toFIG.11C, a patterning process is performed on theblanket dielectric layer90 and the blanketgate electrode layer84, so as to form thedielectric layer50 and thegate electrode34. Ablanket dielectric layer90 can be formed to cover thedielectric layer50, thegate electrode34 and the blanket nitride-basedsemiconductor layer82.
• Referring toFIG.11D, a patterning process is performed on theblanket dielectric layer90 and the blanket nitride-basedsemiconductor layer82, so as to form adielectric layer52 and a doped nitride-basedsemiconductor layer32H. Thedielectric layer52 covers thegate electrode34 and the doped nitride-basedsemiconductor layer32H.
• A mask layer ML4 with at least one opening OP is formed on/over/above the nitride-basedsemiconductor layer16H and thedielectric layer52. At least one portion of the nitride-basedsemiconductor layer16H is exposed from the opening OP. The opening OP of the mask layer ML4 is strip-shaped. Then, an ion implantation process is performed such that the exposed portion of the nitride-basedsemiconductor layer16H is doped with a dopant selected from a highly electronegative group, so as to form ahigh resistivity zone94H in the nitride-basedsemiconductor layer16H.
• Referring toFIG.11E, the mask ML4 is removed from the nitride-basedsemiconductor layer16H and thedielectric layer52.
• Referring toFIG.11F, ablanket dielectric layer54′ is formed to cover thedielectric layer52 and the nitride-basedsemiconductor layer16H. A blanket field plate layer98 (i.e., blanket conductive layer) is formed to cover thedielectric layer54′ and over thegate electrode34.
• Referring toFIG.11G, a mask layer ML5 is formed on the blanketfield plate layer98. The mask layer ML5 vertically overlaps with thehigh resistivity zone94H. The right end portion of the mask layer ML5 is directly over thehigh resistivity zone94H. The left end portion of the mask layer ML5 is directly over thegate electrode34.
• Referring toFIG.11H, a patterning process is performed on the blanketfield plate layer98 using the mask layer ML5, so as to form afield plate96. Thefield plate96 is formed to be over thegate electrode34 and extends in a region between thegate electrode34 and thehigh resistivity zone94H. A left end of thefield plate96 vertically overlaps with thegate electrode34. A right end of thefield plate96 vertically overlaps with thehigh resistivity zone94H. Thereafter, theelectrodes20 and22, contact vias70, apassivation layer60, and a patternedcircuit layer80 can be formed, obtaining the configuration of thesemiconductor device1H as shown inFIG.10B .
• FIG.12 is a vertical cross-sectional view of a semiconductor device1I according to some embodiments of the present disclosure. The semiconductor device1I is similar to thesemiconductor device1H as described and illustrated with reference toFIG.10B, except thehigh resistivity zone94H is replaced by ahigh resistivity zone941. Thehigh resistivity zone941 is free from coverage of the field plate961. Borders of thehigh resistivity zone941 and the field plate961 exactly vertically coincide with each other.
• FIG.13 is a top view of asemiconductor device1J according to some embodiments of the present disclosure. Thesemiconductor device1J is similar to thesemiconductor device1H as described and illustrated with reference toFIG.10A, except thehigh resistivity zone94H is replaced by a plurality of separatedhigh resistivity zones94J.
• In the present embodiment, the negatively-chargedions92 are distributed along the direction D3, which is the same as the extending direction of the field plate96J. In response to the negatively-chargedions92, thehigh resistivity zones94J are formed in the drift region. Thehigh resistivity zones94G are arranged along the direction D3. Each of thehigh resistivity zones94D is in a shape of rectangular from the top view of thesemiconductor device1J.
• FIG.14 is a top view of asemiconductor device1K according to some embodiments of the present disclosure. Thesemiconductor device1K is similar to thesemiconductor device1H as described and illustrated with reference toFIG.10A, except thehigh resistivity zone94H is replaced by a plurality of separatedhigh resistivity zones94K.
• In the present embodiment, the negatively-chargedions92 are distributed along the direction D3, which is the same as the extending direction of thefield plate96K. In response to the negatively-chargedions92, thehigh resistivity zones94K are formed in the drift region. Thehigh resistivity zones94J are arranged along the direction D3. Each of thehigh resistivity zones94K is in a shape of ellipse from the top view of thesemiconductor device1K.
• FIG.15 is a top view of asemiconductor device1L according to some embodiments of the present disclosure. Thesemiconductor device1F is similar to thesemiconductor device1H as described and illustrated with reference toFIG.10A, except thehigh resistivity zone94H is replaced by a plurality of separatedhigh resistivity zones94L.
• In the present embodiment, the negatively-chargedions92 are distributed along the direction D3, which is the same as the extending direction of the field plate96L. In response to the negatively-chargedions92, thehigh resistivity zones94L are formed in the drift region. Thehigh resistivity zones94L are arranged along the direction D3. Each of thehigh resistivity zones94L has a short side and a long side between the the doped nitride-basedsemiconductor layer32H and theelectrode22. Specifically, each of thehigh resistivity zones94L is in a shape of trapezoid from the top view of thesemiconductor device1L.
• With respect to thesemiconductor devices1J,1K and1L, thehigh resistivity zones94J/94K/94L are formed to be separated from each other, and the overall resistance thereof can be reduced.
• During the manufacturing process of thesemiconductor devices1J,1K and1L, the mask layer applied in the ion implantation process has a plurality of the separated openings OP to expose a plurality of portions of the nitride-based semiconductor layer (e.g., barrier layer) thereunder. The shape of the high resistivity zone in the top view of the corresponded semiconductor device can be determined by the shape of the opening OP.
• FIG.16 is a vertical cross-sectional view of a semiconductor device1M according to some embodiments of the present disclosure. The semiconductor device1M is similar to thesemiconductor device1H as described and illustrated with reference toFIG.10A, except thedielectric layers50 and52 are omitted.
• Since those dielectric layers are omitted, thedielectric layer54M directly covers the gate electrode. Thedielectric layer54M can form an interface with thegate electrode34. The negatively-chargedions92 are embedded into the nitride-basedsemiconductor layer16M to form ahigh resistivity zone94M. Thehigh resistivity zone94M is over the nitride-basedsemiconductor layer14M.
• Afield plate99 is disposed on thedielectric layer54M. Thefield plate99 is conformal with thedielectric layer54M. Thefield plate99 has a stage-shaped profile. The left end portion E1 of thefield plate99 is directly over thegate electrode34. The right end portion of thefield plate99 is directly over thehigh resistivity zone94M. Since thedielectric layers50 and52 are omitted, the thickness of thesemiconductor device1H can be reduced.
• Referring toFIG.17A, abuffer layer12 and nitride-based semiconductor layers14M and16M are formed over asubstrate10. Ahigh resistivity zone94M is formed in the nitride-basedsemiconductor layer16M. A doped nitride-basedsemiconductor layer32 and agate electrode34 are formed over the nitride-basedsemiconductor layer16M.
• Referring toFIG.17B, adielectric layer54M is formed over the nitride-basedsemiconductor layer16M to cover the doped nitride-basedsemiconductor layer32 and thegate electrode34. Ablanket field plate99′ is formed over thedielectric layer54M.
• Referring toFIG.17C, a mask layer ML5 is formed over theblanket field plate99′. The left end portion of the mask layer ML5 is directly over thegate electrode34. The right end portion of the mask layer ML5 is directly over thehigh resistivity zone94M.
• Referring toFIG.17D, a patterning process is performed on theblanket field plate99′ such that afield plate99 is formed. The patterning process is performed by using the mask layer ML5. After the patterning process, the mask layer ML5 can be removed from thefield plate99.
• Based on the above description, in embodiments of the present disclosure, the doping location of the negatively-charged ions is determined in the barrier layer according to the location of the gate electrode or single field plate; and therefore, the electrical properties of the semiconductor device can be can be further promoted without using any field plate or with only a single field plate. As such, the semiconductor device can have good electrical properties and reliability.
• The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.
• As used herein and not otherwise defined, the terms “substantially,” “substantial,” “approximately” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.
• As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.
• While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims (20)

1. A semiconductor device, comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction therebetween with a two-dimensional electron gas (2DEG) region;

a gate electrode and a drain electrode disposed above the second nitride-based semiconductor layer to define a drift region therebetween; and

a group of negatively-charged ions implanted into the drift region and spaced apart from an area directly beneath the gate and drain electrodes to form at least one high resistivity zone in the second nitride-based semiconductor layer; and

a field plate disposed over the gate electrode and extending in a region between the gate electrode and the high resistivity zone.

2. The semiconductor device ofclaim 1, wherein the field plate has a first end portion directly above the gate electrode and a second end portion in a position lower than the first end portion.

3. The semiconductor device ofclaim 2, wherein the second end portion of the field plate vertically overlaps with the high resistivity zone.

4. The semiconductor device ofclaim 2, wherein the high resistivity zone is closer to the drain electrode than the second end portion of the field plate.

5. The semiconductor device ofclaim 1, wherein the gate electrode is vertically and horizontally separated from the high resistivity zone.

6. The semiconductor device ofclaim 1, wherein the gate electrode is closer to the high resistivity zone than the drain electrode.

7. The semiconductor device ofclaim 1, wherein the gate electrode and the drain electrode extend along a first direction, and the negatively-charged ions are distributed along the first direction to form a high resistivity strip in the drift region.

8. The semiconductor device ofclaim 7, wherein the field plate extends along a second direction different than the first direction to span from the gate electrode toward the high resistivity zone.

9. The semiconductor device ofclaim 1, wherein the negatively-charged ions form a plurality of high resistivity zones in the second nitride-based semiconductor layer, which are separated from each other.

10. The semiconductor device ofclaim 1, further comprising:

a doped nitride-based semiconductor layer disposed between the second nitride-based semiconductor layer and the gate electrode and vertically and horizontally separated from the high resistivity zone.

11. The semiconductor device ofclaim 1, further comprising:

a first dielectric layer disposed above the second nitride-based semiconductor layer and covering the gate electrode, wherein the second nitride-based semiconductor layer is free from coverage of the first dielectric layer.

12. The semiconductor device ofclaim 11, further comprising:

a second dielectric layer disposed above the second nitride-based semiconductor layer and covering the first dielectric layer and the high resistivity zone.

13. The semiconductor device ofclaim 12, wherein the field plate forms an interface with the second dielectric layer and is conformal with the second dielectric layer.

14. The semiconductor device ofclaim 11, wherein the negatively-charged ions are dopants selected from a highly electronegative group.

15. The semiconductor device ofclaim 11, wherein the negatively-charged ions include fluorine.

16. A method for manufacturing a semiconductor device, comprising:

forming a first nitride-based semiconductor layer;

forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer;

forming a gate electrode over the second nitride-based semiconductor layer;

forming a first dielectric layer to cover the gate electrode;

forming a mask with an opening over the second nitride-based semiconductor layer and the first dielectric layer, such that at least one portion of the second nitride-based semiconductor layer is exposed from the opening;

performing an ion implantation process such that the exposed portion of the second nitride-based semiconductor layer is doped with a dopant selected from a highly electronegative group, so as to form a high resistivity zone in the second nitride-based semiconductor layer; and

forming a field plate over the gate electrode and extending in a region between the gate electrode and the high resistivity zone.

17. The method ofclaim 16, further comprising:

forming a blanket conductive layer over the gate electrode;

patterning the blanket conductive layer to form the field plate such that the field plate vertically overlaps with the high resistivity zone.

18. The method ofclaim 16, wherein the mask is formed to make contact with the second nitride-based semiconductor layer

19. The method ofclaim 16, wherein the opening of the mask is strip-shaped.

20. The method ofclaim 16, wherein the mask has a plurality of the openings to expose a plurality of portions of the second nitride-based semiconductor layer.

Images